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`timescale 1ns / 1ps
moduleencoder_4_2(
input [3:0] in,
outputreg [1:0] out
);
always @(*) begincase(in)
4'b0001 : out =2'b00;
4'b0010 : out =2'b01;
4'b0100 : out =2'b10;
4'b1000 : out =2'b11;
default : out =2'bxx;
endcaseendendmodule
4 to 2 Encoder Test Bench:
moduletestbench;
reg [3:0] in;
wire [1:0] out;
encoder_4_2dut(.in(in), .out(out) );
initialbegin
$monitor("in = %b, out = %b", in, out);
in =4'b0001; #10;
in =4'b0010; #10;
in =4'b0100; #10;
in =4'b1000; #10;
in =4'b1111; #10;
endendmodule