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30 Days of Verilog

Repo was not updated daily. I posted consistently on Linkedin

Embark on a journey through 30 days of Verilog exploration! 🌟

Welcome to my personal project: 30 Days of Verilog. Over the next 30 days, I'll be taking a deep dive into the world of digital circuits and Verilog programming. My goal is to create and showcase 30 different digital circuits, each implemented using Verilog HDL.

About the Project

The aim of this project is to:

  • Learn Verilog: Gain a solid understanding of Verilog and its applications.
  • Explore Digital Circuits: Create a variety of digital circuits to explore different concepts.
  • Document Progress: Document my journey, challenges, and solutions for each circuit.
  • Share with the Community: Provide a resource for others interested in Verilog and digital design.

Repository Structure

Each day, I will add a new folder from Day 1 to Day 30, containing:

  • Verilog Code: Implementation of the day's digital circuit in Verilog.
  • README: Explanation of the circuit, its purpose, and my approach.
  • Simulation: Simulation results, waveforms, and test benches (if applicable).
  • Reflections: Insights and lessons learned during the implementation.

Feel free to follow along, offer suggestions, or learn from my progress!

Table of Contents

Let's Connect

I'd love to share my journey with you and connect with fellow Verilog enthusiasts:

Stay Tuned

Join me as I explore the world of Verilog programming and digital circuits over the next 30 days. Let's explore, create, and learn together!

Happy Verilog coding! 💻