From 46787b80c4442899a8fcb437a8e3115dac739fce Mon Sep 17 00:00:00 2001 From: Shubhekshana Matkar Date: Wed, 22 Dec 2021 16:31:14 +0530 Subject: [PATCH] Trademark Updated (#159) * Update README.md * Update README.md Updated Trademarks * Update README.md * Updated trademarks * Trademarks updates Co-authored-by: Shubhekshana <81768495+Shubhekshana@users.noreply.github.com> --- .../01-aie_lenet_tutorial/README.md | 226 +++++++++--------- .../DualStreamSSR/README.md | 2 +- .../MultiKernel/README.md | 2 +- .../02-super_sampling_rate_fir/README.md | 2 +- .../SingleKernel/README.md | 2 +- .../SingleStreamSSR/README.md | 2 +- .../Module_01_Custom_Platform/README.md | 4 +- .../Module_02_AI_Engine_Design/README.md | 4 +- .../Module_03_PL_Design/README.md | 4 +- .../README.md | 4 +- .../README.md | 4 +- .../README.md | 2 +- .../Module_07_Petalinux/README.md | 2 +- .../Module_08_Linux_SW_Application/README.md | 4 +- .../README.md | 4 +- .../Design_Tutorials/03-beamforming/README.md | 2 +- .../04-custom-platform-emulation/README.md | 12 +- .../06-fft2d_AIEvsHLS/README.md | 2 +- .../07-firFilter_AIEvsHLS/README.md | 2 +- .../Module_01_python_sims/README.md | 2 +- .../Module_02_aie/README.md | 2 +- .../Module_03_pl_kernels/README.md | 2 +- .../Module_04_full_system_design/README.md | 2 +- .../Module_06_sd_card_and_hw_run/README.md | 2 +- .../Module_07_results/README.md | 2 +- .../08-n-body-simulator/README.md | 2 +- .../01-custom_base_platform_creation.md | 2 +- .../02-aie_application_creation.md | 2 +- .../03-pl_application_creation.md | 2 +- .../04-ps_application_creation_run_all.md | 2 +- .../01-aie_a_to_z/05-RPU version[optional].md | 2 +- .../Feature_Tutorials/01-aie_a_to_z/README.md | 4 +- .../Feature_Tutorials/02-using-gmio/README.md | 4 +- .../02-using-gmio/perf_profile_aie_gmio.md | 4 +- .../02-using-gmio/single_aie_gmio.md | 4 +- .../03-rtp-reconfiguration/README.md | 4 +- .../step1_sync_scalar.md | 4 +- .../step2_async_scalar.md | 4 +- .../step3_async_array.md | 4 +- .../step4_async_aie_array.md | 4 +- .../step5_async_array_update_read.md | 4 +- .../04-packet-switching/README.md | 4 +- .../pktstream_based_aie_kernel.md | 4 +- .../window_based_aie_kernel.md | 4 +- .../window_based_mix_data_type.md | 4 +- .../05-AI-engine-versal-integration/README.md | 2 +- .../07-AI-Engine-Floating-Point/README.md | 2 +- .../08-dsp-library/README.md | 2 +- .../10-aie-dsp-lib-model-composer/README.md | 2 +- .../README.md | 2 +- .../12-axis-traffic-generator/README.md | 2 +- .../13-aie-performance-analysis/README.md | 4 +- .../aie_execution_measurement.md | 4 +- .../aie_hang_analysis.md | 4 +- .../Part1a/README.md | 4 +- .../Part1b/README.md | 4 +- .../14-implementing-iir-filter/README.md | 4 +- AI_Engine_Development/README.md | 4 +- 58 files changed, 203 insertions(+), 203 deletions(-) diff --git a/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/README.md b/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/README.md index 8279a26a65..1eacf05ea3 100644 --- a/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/README.md +++ b/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com @@ -36,8 +36,8 @@ This tutorial uses the LeNet algorithm to implement a system-level design to per The tutorial takes you through hardware emulation and hardware flow in the context of a complete Versal ACAP system integration. A Makefile is provided that you can modify to suit your own needs in a different context.
- Objectives - + Objectives + ### Objectives After completing the tutorial, you should be able to: @@ -52,8 +52,8 @@ After completing the tutorial, you should be able to:
- Tutorial Overview - + Tutorial Overview + ## Tutorial Overview In this application tutorial, the LeNet algorithm is used to perform image classification on an input image using five AI Engine tiles and PL resources including block RAM. A top level block diagram is shown in the following figure. An image is loaded from DDR memory through the Network on Chip (NoC) to block RAM and then to the AI Engine. The PL input pre-processing unit receives the input image and sends the output to the first AI Engine tile to perform matrix multiplication. The output from the first AI Engine tile goes to a PL unit to perform the first level of max pool and data rearrangement (M1R1). The output is fed to the second AI Engine tile and the output from that tile is sent to the PL to perform the second level max pooling and data rearrangement (M2R2). The output is then sent to a fully connected layer (FC1) implemented in two AI Engine tiles and uses the rectified linear unit layer (ReLu) as an activation function. The outputs from the two AI Engine tiles are then fed into a second fully connected layer implemented in the `core04` AI Engine tile. The output is sent to a data conversion unit in the PL and then to the DDR memory through the NoC. In between the AI Engine and PL units is a datamover module (refer to the Lenet Controller in the following figure) that contains the following kernels: * `mm2s`: a memory mapped to stream kernel to feed data from DDR memory through the NoC to the AI Engine Array @@ -66,8 +66,8 @@ In the design, there are two major PL kernels. The input pre-processing units, M
- Directory Structure - + Directory Structure + ### Directory Structure ``` lenet @@ -87,8 +87,8 @@ lenet Note: This tutorial targets the VCK190 ES board (see https://www.xilinx.com/products/boards-and-kits/vck190.html). This board is currently available via early access. If you have already purchased this board, download the necessary files from the lounge and ensure you have the correct licenses installed. If you do not have a board and ES license please contact your Xilinx sales contact.
- -Documentation: Explore AI Engine Architecture + +Documentation: Explore AI Engine Architecture ### *Documentation*: Explore AI Engine Architecture @@ -99,12 +99,12 @@ Note: This tutorial targets the VCK190 ES board (see https://www.xilinx.com/prod
- -Tools: Installing the Tools - + +Tools: Installing the Tools + ### *Tools*: Installing the Tools -Tools Documentation: +Tools Documentation: * [AI Engine Tools lounge](https://www.xilinx.com/member/versal_ai_engines.html#documentation) @@ -112,7 +112,7 @@ Tools Documentation: To build and run the Lenet tutorial, you will need the following tools downloaded/installed: -* Install the [Vitis Software Platform 2021.2](https://www.xilinx.com/html_docs/xilinx2021_2/vitis_doc/acceleration_installation.html#dhg1543555360045__ae364401) +* Install the [Vitis Software Platform 2021.2](https://www.xilinx.com/html_docs/xilinx2021_2/vitis_doc/acceleration_installation.html#dhg1543555360045__ae364401) * Obtain a license to enable Beta Devices in Xilinx tools (to use the `xilinx_vck190_base_202120_1` platform) @@ -125,20 +125,20 @@ To build and run the Lenet tutorial, you will need the following tools downloade
-Environment: Setting Up the Shell Environment - +Environment: Setting Up the Shell Environment + ## Environment: Setting Up the Shell Environment -When the elements of the Vitis software platform are installed, update the shell environment script. Set the environment variables to your system-specific paths. +When the elements of the Vitis software platform are installed, update the shell environment script. Set the environment variables to your system-specific paths. -Edit `env_setup.sh` script with your file paths: +Edit `env_setup.sh` script with your file paths: ```bash export XILINX_XRT= -export PLATFORM_REPO_PATHS= +export PLATFORM_REPO_PATHS= source /Vitis//settings64.sh source $XILINX_XRT/setup.sh ``` -Then source the environment script: +Then source the environment script: ```bash source env_setup.sh ``` @@ -146,15 +146,15 @@ source env_setup.sh
-Validation: Confirming Tool Installation - +Validation: Confirming Tool Installation + ### Validation: Confirming Tool Installation ```bash which vitis which aiecompiler ``` -Confirm you have the VCK190 Production Base Platform. +Confirm you have the VCK190 Production Base Platform. ```bash platforminfo --list | grep -m 1 -A 9 vck190_base ``` @@ -176,10 +176,10 @@ Output of the above command should be as follows: ## Building the LeNet Design
- LeNet Design Build - + LeNet Design Build + ### LeNet Design Build -In this section, you will build and run the LeNet design. You will compile the AI Engine design and integrate it into a larger system design (including the Programmable Logic (PL) kernels and Processing System (PS) host application). You can review [Integrating the Application Section in the AI Engine Documentation](#ai-engine-documentation) for the general flow. The following image shows the Vitis tool flow with the `make` targets (in blue) and input source files and output file generation (in red) at each step. +In this section, you will build and run the LeNet design. You will compile the AI Engine design and integrate it into a larger system design (including the Programmable Logic (PL) kernels and Processing System (PS) host application). You can review [Integrating the Application Section in the AI Engine Documentation](#ai-engine-documentation) for the general flow. The following image shows the Vitis tool flow with the `make` targets (in blue) and input source files and output file generation (in red) at each step. ![Image of LeNet Vitis Tool Flow](images/Lenet_vitis_toolflow_2021_1.PNG) @@ -187,37 +187,37 @@ At the end of this section, the design flow will generate a new directory (calle
-## Make Steps +## Make Steps To run the following `make` steps (for example, `make kernels`, `make graph`, etc), you must be in the lenet tutorial folder.
Build the Entire Design with a Single Command - + ### Build the Entire Design with a Single Command -If you are an advanced user and are already familiar with the AI Engine and Vitis kernel compilation flows, you can build the entire design with one command: +If you are an advanced user and are already familiar with the AI Engine and Vitis kernel compilation flows, you can build the entire design with one command: ```bash make build TARGET=hw_emu ``` -or +or ```bash make build TARGET=hw EN_TRACE=0 ``` -or +or ```bash make build TARGET=hw EN_TRACE=1 ``` The default value of EN_TRACE is 0. This command runs the `make kernels`, `make graph`, `make xclbin`, `make application`, and `make package` for hardware emulation or for running on hardware (VCK190 board), depending on the `TARGET` you specify. Also, if the `TARGET` specified is hardware `EN_TRACE` can be set to 1 to enable trace to measure throughput. -You can also run the following command to build the entire Lenet tutorial *and* launch hardware emulation: +You can also run the following command to build the entire Lenet tutorial *and* launch hardware emulation: ```bash make run TARGET=hw_emu ```
- make kernels: Compile PL Kernels - + make kernels: Compile PL Kernels + ### make kernels: Compile PL Kernels In this step, the Vitis compiler takes any Vitis compiler kernels (RTL or HLS C) in the PL region of the target platform (`xilinx_vck190_base_202120_1`) and the AI Engine kernels and graph and compiles them into their respective XO files. In this design, the `dma_hls` kernel is compiled as an XO file and the `Lenet_kernel` has already been pre-compiled as an XO file. You can access the source code by unzipping the XO file. @@ -225,7 +225,7 @@ In this step, the Vitis compiler takes any Vitis compiler kernels (RTL or HLS C) The files will be stored under the `ip_repo` folder. -The following commands compiles the kernels (default TARGET=hw_emu). +The following commands compiles the kernels (default TARGET=hw_emu). ``` make kernels @@ -244,9 +244,9 @@ v++ --target hw_emu \ --verbose \ -c ../../design/pl_src/datamover/dma_hls.cpp\ -k dms_hls \ - -o dma_hls.hw_emu.xo - - cd ../../; + -o dma_hls.hw_emu.xo + + cd ../../; ``` |Switch|Description| | --- | --- | @@ -270,22 +270,22 @@ v++ --target hw_emu \
- make graph: Creating the AI Engine ADF Graph for Vitis Compiler Flow - + make graph: Creating the AI Engine ADF Graph for Vitis Compiler Flow + ### make graph: Creating the AI Engine ADF Graph for Vitis Compiler Flow -An ADF graph can be connected to an extensible Vitis platform (the graph I/Os can be connected either to platform ports or to ports on Vitis kernels through Vitis compiler connectivity directives). -* The AI Engine ADF C++ graph of the design contains AI Engine kernels and PL kernels. +An ADF graph can be connected to an extensible Vitis platform (the graph I/Os can be connected either to platform ports or to ports on Vitis kernels through Vitis compiler connectivity directives). +* The AI Engine ADF C++ graph of the design contains AI Engine kernels and PL kernels. * All interconnects between kernels are defined in the C++ graph. -* All interconnections to external I/O are fully specified in the C++ simulation testbench (`graph.cpp`) that instantiates the C++ ADF graph object. All `adf::sim` platform connections from graph to PLIO map onto ports on the AI Engine subsystem graph that are connected using the Vitis compiler connectivity directives. No dangling ports or implicit connections are allowed by the Vitis compiler. - +* All interconnections to external I/O are fully specified in the C++ simulation testbench (`graph.cpp`) that instantiates the C++ ADF graph object. All `adf::sim` platform connections from graph to PLIO map onto ports on the AI Engine subsystem graph that are connected using the Vitis compiler connectivity directives. No dangling ports or implicit connections are allowed by the Vitis compiler. + To compile the graph using the Makefile flow type: ``` make graph ``` -The following AI Engine compiler command compiles the AI Engine design graph: +The following AI Engine compiler command compiles the AI Engine design graph: ``` cd ./build; -aiecompiler --include= ./design/aie_src \ +aiecompiler --include= ./design/aie_src \ --include= ./design/aie_src/data \ --verbose \ --log-level=5 \ @@ -294,8 +294,8 @@ aiecompiler --include= ./design/aie_src \ --heapsize=2048 \ --workdir=Work \ ./design/aie_src/graph.cpp - -cd ../../; + +cd ../../; ``` |Switch|Description| | --- | --- | @@ -318,22 +318,22 @@ The following is a description of the output objects that results from executing
- make xclbin: Use Vitis Tools to Link AI Engine and HLS Kernels with the Platform - + make xclbin: Use Vitis Tools to Link AI Engine and HLS Kernels with the Platform + ### make xclbin: Use Vitis Tools to Link AI Engine and HLS Kernels with the Platform -After the AI Engine kernels and graph and PL HLS kernels have been compiled, you can use the Vitis compiler to link them with the platform to generate both an XCLBIN and a new XSA file. +After the AI Engine kernels and graph and PL HLS kernels have been compiled, you can use the Vitis compiler to link them with the platform to generate both an XCLBIN and a new XSA file. ### Platform The Vitis tools allow you to integrate the AI Engine, HLS, and RTL kernels into an existing extensible platform. This is an automated step from a software developer perspective where the platform chosen is provided by the hardware designer (or you can opt to use one of the many extensible base platforms provided by Xilinx) and the Vitis tools build the hardware design and integrate the AI Engine and PL kernels into the design. - + To test this feature in this tutorial, use the base VCK190 platform to build the design. - + The command to run this step is as follows (default TARGET=hw_emu, default EN_TARCE=0): ``` make xclbin -``` +``` -The expanded command is as follow: +The expanded command is as follow: ``` cd ./build/hw_emu; @@ -349,8 +349,8 @@ v++ -l \ ../../design/pl_src/lenet_kernel/lenet_kernel.xo \ ../build/libadf.a \ -o vck190_aie_lenet.hw_emu.xclbin - -cd ../../; + +cd ../../; ``` If EN_TRACE=1, the command is expanded as follow: @@ -371,8 +371,8 @@ v++ -l \ ../../design/pl_src/lenet_kernel/lenet_kernel.xo \ ../build/libadf.a \ -o vck190_aie_lenet.hw_emu.xclbin - -cd ../../; + +cd ../../; ``` The options to run this step are as follows: @@ -412,15 +412,15 @@ param=compiler.addOutputTypes=hw_export |--connectivity.stream_connect|How the kernels will connect to IPs, platforms, or other kernels. The output of the AI Engine compiler tell you the interfaces that need to be connected. `mm2s_0.s:ai_engine_0.lte_0` means that the Vitis compiler should connect the port `s` of `mm2s` to the port `lte_0` of AI Engine port 0. The name of the AI Engine port is one that has been defined in `graph.cpp` PLIO instantiation.| |param=compiler.addOutputTypes=hw_export| This option tells the Vitis compiler that besides creating an XCLBIN file, it also outputs an XSA file which is needed to create a post-Vivado fixed platform for Vitis software development.| -Note that the Vitis compiler calls Vivado® IP integrator under the hood to build the design. The platform and kernels are input to the Vivado Design Suite, which produces a simulation XSA or an XSA after running place and route on the design. The point at which the XSA is produced from Vivado is dependent on what `-target` option is set on the the Vitis compiler command line. +Note that the Vitis compiler calls Vivado® IP integrator under the hood to build the design. The platform and kernels are input to the Vivado Design Suite, which produces a simulation XSA or an XSA after running place and route on the design. The point at which the XSA is produced from Vivado is dependent on what `-target` option is set on the the Vitis compiler command line. Note that you can now view the Vivado project, which is located in the `build/[hw|hw_emu]/\_x/link/vivado/vpl/prj` directory. -Now you have generated the XCLBIN file that will be used to execute your design on the platform. -
- +Now you have generated the XCLBIN file that will be used to execute your design on the platform. +
+
- make application: Compile the Host Application + make application: Compile the Host Application ### make application: Compile the Host Application You can compile the host application by following the typical cross-compilation flow for the Cortex-A72. To build the application run the following command: @@ -440,7 +440,7 @@ aarch64-linux-gnu-g++ -O \ -I $(PLATFORM_REPO_PATHS)/sw/versal/xilinx-versal-common-v2021.2/sysroots/aarch64-xilinx-linux/usr/lib \ ../build//Work/ps/c_rts/aie_control_xrt.cpp \ -o ../build/app_control.o - + aarch64-linux-gnu-g++ -O \ -c \ -D__linux__ \ @@ -456,15 +456,15 @@ aarch64-linux-gnu-g++ -O \ aarch64-linux-gnu-g++ ./build/app_control.o \ ./build/lenet_app.o \ --sysroot=$(PLATFORM_REPO_PATHS)/sw/versal/xilinx-versal-common-v2021.2/sysroots/aarch64-xilinx-linux \ - -L$(PLATFORM_REPO_PATHS)/sw/versal/xilinx-versal-common-v2021.2/sysroots/aarch64-xilinx-linux/usr/lib\ + -L$(PLATFORM_REPO_PATHS)/sw/versal/xilinx-versal-common-v2021.2/sysroots/aarch64-xilinx-linux/usr/lib\ -L$(XILINX_VITIS_AIETOOLS)/lib/aarch64.o \ -L$(XILINX_VITIS_AIETOOLS)/lib/lnx64.o \ -ladf_api_xrt \ -lxrt_coreutil \ -std=c++14 \ - -o ../build/lenet_xrt.elf - -cd ../../; + -o ../build/lenet_xrt.elf + +cd ../../; ``` |Switch|Description| @@ -476,16 +476,16 @@ cd ../../; |-o \|Place output in file ``. This applies regardless of the output being produced, whether it be an executable file, an object file, an assembler file or preprocessed C code.| |--sysroot=\|Use `dir` as the logical root directory for headers and libraries. For example, if the compiler normally searches for headers in `/usr/include` and libraries in `/usr/lib`, it instead searches in `dir/usr/include` and `dir/usr/lib`.| |-l\|Search the library named `library` when linking. The LeNet tutorial requires `adf_api`, `xrt_coreutil`, `xrt_core`, `aiengine`, `metal`, and `open_amp` libraries.| -|-L \|Add directory `` to the list of directories to be searched for -l.| +|-L \|Add directory `` to the list of directories to be searched for -l.| -The following is a description of the input sources compiled by the AI Engine compiler command. +The following is a description of the input sources compiled by the AI Engine compiler command. |Inputs Sources|Description| | --- | --- | |design/aie_src/main.cpp|Source application file for the `lenet_xrt.elf` that will run on an A72 processor.| |build/Work/ps/c_rts/aie_control_xrt.cpp|This is the AI Engine control code generated implementing the graph APIs for the LeNet graph.| -The following is a description of the output objects that results from executing the AI Engine compiler command with the above inputs and options. +The following is a description of the output objects that results from executing the AI Engine compiler command with the above inputs and options. |Output Objects|Description| | --- | --- | @@ -493,16 +493,16 @@ The following is a description of the output objects that results from executing
- make package: Package the Design - + make package: Package the Design + ### make package: Package the Design With the AI Engine outputs created, as well as the new platform, you can now generate the Programmable Device Image (PDI) and a package to be used on an SD card. The PDI contains all executables, bitstreams, and configurations of the device. The packaged SD card directory contains everything to boot Linux, the generated applications and the XCLBIN file. The command to run this step is as follows (default TARGET=hw_emu): ``` make package -``` -or +``` +or ``` v++ -p \ @@ -519,8 +519,8 @@ v++ -p \ --package.image_format=ext4 \ --package.sd_file ./build/lenet_xrt.elf ./build/hw_emu/vck190_aie_lenet.hw_emu.xclbin ./build/libadf.a \ --package.defer_aie_run - -cd ../../; + +cd ../../; ``` @@ -528,8 +528,8 @@ If TARGET=hw and EN_TRACE=1 ``` make package -``` -or +``` +or ``` v++ -p \ @@ -547,8 +547,8 @@ v++ -p \ --package.sd_file ./build/lenet_xrt.elf ./build/hw_emu/vck190_aie_lenet.hw_emu.xclbin ./build/libadf.a \ --package.defer_aie_run \ --package.sd_file $(MAKEFILES_REPO)/xrt.ini - -cd ../../; + +cd ../../; ``` @@ -573,7 +573,7 @@ cd ../../; |build/hw_emu/vck190_aie_lenet.hw_emu.xclbin|The XCLBIN file created in the `make xclbin` step.| |build/libadf.a|The compiled AI Engine design graph created in the `make graph` step.| -The output of the Package step is the package directory that contains the contents to run hardware emulation. +The output of the Package step is the package directory that contains the contents to run hardware emulation. |Output Objects|Description| | --- | --- | @@ -585,16 +585,16 @@ The output of the Package step is the package directory that contains the conten make run_emu: Run Hardware Emulation ### make run_emu: Run Hardware Emulation -After packaging, everything is set to run emulation on hardware. To run emulation use the following command: +After packaging, everything is set to run emulation on hardware. To run emulation use the following command: ``` make run_emu ``` or ``` cd ./build/hw_emu/package -./launch_hw_emu.sh +./launch_hw_emu.sh ``` -When launched, you will see the QEMU simulator load. Wait for the autoboot countdown to go to zero, and after a few minutes, you will see the root Linux prompt display: +When launched, you will see the QEMU simulator load. Wait for the autoboot countdown to go to zero, and after a few minutes, you will see the root Linux prompt display: ```bash root@versal-rootfs-common-2021_2:~# ``` @@ -618,25 +618,25 @@ export XILINX_XRT=/usr ./lenet_xrt.elf a.xclbin ``` -The `lenet_xrt.elf` should execute, and after a few minutes, you should see the output with *TEST PASSED* on the console. When this is shown, run the following keyboard command to exit the QEMU instance: +The `lenet_xrt.elf` should execute, and after a few minutes, you should see the output with *TEST PASSED* on the console. When this is shown, run the following keyboard command to exit the QEMU instance: ``` #To exit QEMU Simulation -Press CtrlA, let go of the keyboard, and then press x +Press CtrlA, let go of the keyboard, and then press x ```
- TARGET=hw: Run on Hardware - + TARGET=hw: Run on Hardware + ## TARGET=hw: Run on Hardware To run your design on hardware, re-run the following steps with TARGET=hw: ``` make kernels TARGET=hw make xclbin TARGET=hw -make package TARGET=hw +make package TARGET=hw ``` These command create a `build/hw` folder with the kernels, `xclbin`, and `package` for a hardware run. @@ -683,7 +683,7 @@ export XILINX_XRT=/usr ## Hardware Design Details
LeNet Architecture and AI Engine/PL Function Partitioning - + ## LeNet Architecture and AI Engine/PL Function Partitioning The architecture of the LeNet design is shown in the following figure. The details of the individual layers and their implementation will be described in a later section. This design provides an illustration of the functional partitioning between the AI Engine and PL resources, as shown in the block diagram previously. The input rearrange, max pooling, and rearrange are scalar byte operations and interact with read/write memories to ensure sustained throughput. This set of operations are suitable for implementation in PL rather than in the AI Engine array. With appropriate data rearrangement, the computations in the convolutional layers are presented as matrix multiplications and they are optimized to be implemented in the AI Engine array. @@ -693,7 +693,7 @@ The architecture of the LeNet design is shown in the following figure. The detai
Design Platform Details - + ## Design Platform Details In the base platform, the CIPS, NoC, and AI Engine are instantiated and interfaces among them are created. To add the various functions in a system-level design, PL kernels are added to the base platform depending on the application developed, that is, the PL kernels present in each design might vary. An ADF graph is connected to an extensible Vitis platform where the graph I/Os are connected either to the platform ports or to ports on Vitis kernels through the Vitis compiler connectivity directives. For this design, the components are added by the `v++ -l` step (make XCLBIN in the tool flow section above) and include the following: @@ -711,7 +711,7 @@ To see a schematic view of the design with the extended platform (as shown in th
AI Engine and PL Kernel details - + ### AI Engine and PL Kernel Details The design implements the LeNet CNN to perform digital classification on gray scale images. The AI Engine kernels have been covered in the [Tutorial Overview](#tutorial-overview) section and more details will be provided in the [Software Design Details](#software-design-details) section. @@ -721,7 +721,7 @@ The PL kernels perform the following functions: The AI Engine kernels are mainly used to perform matrix multiplication due to their high INT8 MAC performance. -Most of the data processing function is handled in the PL kernel, `lenet_kernel`, which comes pre-compiled and contains the following +Most of the data processing function is handled in the PL kernel, `lenet_kernel`, which comes pre-compiled and contains the following modules. **Input Rearrange (IPR)** @@ -730,14 +730,14 @@ The LeNet algorithm in this design starts with an image of size 28x28 input impo **Max Pool and Data Rearrangement Set 1 (M1R1)** -Pooling is the operation in CNN to enable the detection of the object when presented with different versions of the images by reducing the size of the feature map. Among the types of pooling, the max is chosen to account for distortion. +Pooling is the operation in CNN to enable the detection of the object when presented with different versions of the images by reducing the size of the feature map. Among the types of pooling, the max is chosen to account for distortion. In this design, the output from the first AI Engine tile (core01) is a 576x8 matrix, which is sent to the PL. Each of the columns in the matrix corresponds to a 24x24 dimensional image laid out in the row-major format. The network being implemented has only six output features for the Conv1 layers and hence two of the eight columns do not contain real images. Then a max pool operation is performed and a value is returned from a 2x2 matrix, as seen in the green squares in the following diagram. ![Image of LeNet Maxpool1](images/Lenet_maxpool1.PNG) The resulting 144x8 byte matrix, which is stored in RAMB36 module, then goes through a rearrange operation, where the data is written into six RAMB18s populated with zeros in the appropriate positions and the addresses are generated by the fanout table. Each RAMB18 is configured as 2048x8 (depth x width). The arrays then go through a second stage or rearrange operation where each array is configured in read mode and 512x32. These block RAMS are rearranged to four block RAMS and five register files After the rearrange function, the data is output as six images each of 64x25 dimension. The data for the previous image needs to be sent out to memory mapped AXI4 before the writing of the new image starts. -Also in M1R1 are two instances of the AXI2BRAM module, one at the PL-AI Engine interface and another at the AI Engine-PL interface. At the PL-AI Engine interface, data is coming into the module in AXI4-Stream format from the AI Engine. +Also in M1R1 are two instances of the AXI2BRAM module, one at the PL-AI Engine interface and another at the AI Engine-PL interface. At the PL-AI Engine interface, data is coming into the module in AXI4-Stream format from the AI Engine. The AXI stream supplies a data rate of 128 bits/cycle at 250 MHz and the data is written into four 32-bit RAMB18. A corresponding set of operations is performed at the AI Engine-PL interface. @@ -753,10 +753,10 @@ The PL-based data mover kernel consist of MM2S and S2MM kernels. This module get
Design Implementation - + ### Design Implementation -The following table provides details on the design implementation. It includes image dimensions, weight dimensions, and number of features in each layer. +The following table provides details on the design implementation. It includes image dimensions, weight dimensions, and number of features in each layer. ![Image of Lenet Design Implementation](images/Lenet_implementation.PNG) @@ -773,9 +773,9 @@ The software design in the LeNet tutorial consists of the following sections:
AI Engine Kernels and Graph Representation - + ### AI Engine Kernels and Graph Representation -An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that targets the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each of the AI Engines being used in the design. Review [AI Engine Kernel Programming Section in the AI Engine Documentation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/ciz1611769309578.html) for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine graphs written in C++. +An AI Engine kernel is a C/C++ program written using specialized intrinsic calls that targets the VLIW vector processor. The AI Engine compiler compiles the kernel code to produce an executable ELF file for each of the AI Engines being used in the design. Review [AI Engine Kernel Programming Section in the AI Engine Documentation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/ciz1611769309578.html) for a high-level overview of kernel programming. These kernels can be stitched together to function as AI Engine graphs written in C++. The AI Engine compiler writes a summary of compilation results called `lenet.aiecompile_summary`. You can view the graph by running the following command: `vitis_analyzer build/Work/lenet.aiecompile_summary` @@ -790,16 +790,16 @@ Note: Also defined in the AI Engine graph are the weights (`corelut.h`). The
Data Flow Graph - + ### Data Flow Graph This section describes the overall data-flow graph specification of the LeNet design which is compiled by the AI Engine compiler. Refer to [AI Engine Programming Section in the AI Engine Documentation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/ai_engine_programming.html#mes1509388302139) for information on ADF graphs. The overall graph definition of the design is contained in the `graph.cpp` file. The following steps describe the definition of the graph. -#### Define the Graph Class +#### Define the Graph Class Define the LeNet graph class by using the objects defined in the appropriate name space. It must include the Adaptive Data Flow (ADF) library. All user graphs are derived from the class graph, for example in this design: -`class myGraph : public adf::graph`. +`class myGraph : public adf::graph`. Declare top level ports to the graph: @@ -812,8 +812,8 @@ Use the `kernel::create` function to instantiate the C++ kernel objects, for exa `core01 = adf::kernel::create(core01_top);` -#### Add Connectivity Information -This is done by using the templated connect<> object. The connection can be window<> or stream. If a window connection is used, then window parameters must be specified. +#### Add Connectivity Information +This is done by using the templated connect<> object. The connection can be window<> or stream. If a window connection is used, then window parameters must be specified. In this description, ports are referred to by indices. An example of the connection between the input port of the graph and input of an AI Engine kernel is as follows: ``` @@ -829,7 +829,7 @@ adf::connect<>(core01lut,core01); ``` Based on the datatype of `core01lut`, the API call is inferred as a look up table in the AI Engine tile. -#### Set the Source File and Tile Use +#### Set the Source File and Tile Use Set the source file and tile use for each of the kernels, for example: ``` @@ -865,7 +865,7 @@ The main program is the driver of the graph. It is used to load, execute, and te
PL Kernels - + ### PL Kernels In addition to kernels operating in the AI Engine array, this design specifies two kernels to run on the PL region of the device (written in HLS C++), `lenet_kernel` and `dma_hls`. Note the `dma_hls` kernel is brought into the design during the Vitis kernel compilation whereas the `lenet_kernel` is only brought in later in the Vitis link stage since the kernel is pre-packaged. @@ -880,11 +880,11 @@ The `dma_hls` kernel is an IP which contains `dma_mm2s` and `dma_s2mm`. `dma_mm2
PS Host Application - + ### PS Host Application -The LeNet tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review [Programming the PS Host Application Section in the AI Engine Documentation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/program_ps_host_application.html#ykt1590616160037) to understand the process to create a host application. +The LeNet tutorial uses the embedded processing system (PS) as an external controller to control the AI Engine graph and data mover PL kernels. Review [Programming the PS Host Application Section in the AI Engine Documentation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/program_ps_host_application.html#ykt1590616160037) to understand the process to create a host application. -In addition to the PS host application (`main.cpp`), the AI Engine control code must also be compiled. This control code (`aie_control_xrt.cpp`) is generated by the AI Engine compiler when compiling the AI Engine design graph and kernel code. +In addition to the PS host application (`main.cpp`), the AI Engine control code must also be compiled. This control code (`aie_control_xrt.cpp`) is generated by the AI Engine compiler when compiling the AI Engine design graph and kernel code. The AI Engine control code is used by the PS host application for the following reasons: * Control the initial loading of the AI Engine kernels. * Run the graph for several iterations, update the run time parameters associated with the graph, exit, and reset the AI Engine tiles. @@ -899,7 +899,7 @@ The steps in the tutorial to run the A72 application are described as follows: Include the `graph.cpp` AI Engine application file. This file contains the instantiation of the AI Engine LeNet data flow graph object. ``` #include graph.cpp -``` +``` #### 2. Check Command Line Argument The beginning of the A72 application is represented by the `main` function. It takes in one command line argument, an XCLBIN file. @@ -1017,7 +1017,7 @@ The following are links to Vitis related information referenced in this tutorial * July 2021 - Updated for 2021.1 * Dec 2020 - Initial Release - + © Copyright 2020-2021 Xilinx, Inc. Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/DualStreamSSR/README.md b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/DualStreamSSR/README.md index 4ed0dcf178..be9160ef4a 100644 --- a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/DualStreamSSR/README.md +++ b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/DualStreamSSR/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/MultiKernel/README.md b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/MultiKernel/README.md index 451993ad43..ba2c1ddf6c 100644 --- a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/MultiKernel/README.md +++ b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/MultiKernel/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/README.md b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/README.md index 7674fa714e..a6ea8013c0 100644 --- a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/README.md +++ b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleKernel/README.md b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleKernel/README.md index d3d286f465..69ffd72831 100644 --- a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleKernel/README.md +++ b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleKernel/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleStreamSSR/README.md b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleStreamSSR/README.md index 3744ebc17b..d80f0aedc7 100644 --- a/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleStreamSSR/README.md +++ b/AI_Engine_Development/Design_Tutorials/02-super_sampling_rate_fir/SingleStreamSSR/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md index 3d5d0aa50a..449985aa09 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_01_Custom_Platform/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md index 719200f0d1..85e6ed3282 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_02_AI_Engine_Design/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md index 1121f79c1a..61d8b503a1 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_03_PL_Design/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md index 652cf69c15..69c1aa1cbd 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_04_AI_Engine_and_PL_Integration/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md index a480a410f8..8821fc1168 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_05_Baremetal_Host_Application/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md index acc920861f..6bad0feeb3 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_06_Running_the_Baremetal_System/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md index b10511856e..df51b3627b 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_07_Petalinux/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md index f0dc8dec1e..eef87ccd0d 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_08_Linux_SW_Application/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_09_Running_the_Linux_System/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_09_Running_the_Linux_System/README.md index c03cb1c103..45a887974c 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_09_Running_the_Linux_System/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/Module_09_Running_the_Linux_System/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Design_Tutorials/03-beamforming/README.md b/AI_Engine_Development/Design_Tutorials/03-beamforming/README.md index bc3ac75c89..85b38a4896 100644 --- a/AI_Engine_Development/Design_Tutorials/03-beamforming/README.md +++ b/AI_Engine_Development/Design_Tutorials/03-beamforming/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md index 808b953b37..6540e9839e 100644 --- a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md +++ b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com @@ -41,20 +41,20 @@ After creating the custom platform from the previous tutorial, the next step is * The script creates a Vivado Design Suite project; this is required to create any IP because all source and constraint files need to be local to the IP. * Lines 40 and 41 are used to associate the correct clock pins to the interfaces. This is required for the Vitis compiler which links those interfaces to the platform clocking. - + ```tcl ipx::associate_bus_interfaces -busif in_sample -clock ap_clk [ipx::current_core] ipx::associate_bus_interfaces -busif out_sample -clock ap_clk [ipx::current_core] ``` * On lines 44 and 45 the `FREQ_HZ` bus parameter is removed. This parameter is used in IP integrator, and is to make sure the associated clock of the interface is used correctly. However, the Vitis compiler sets this during the compilation process, and having it set in the IP will cause the compiler to incorrectly link the clocks. - + ```tcl ipx::remove_bus_parameter FREQ_HZ [ipx::get_bus_interfaces in_sample -of_objects [ipx::current_core]] ipx::remove_bus_parameter FREQ_HZ [ipx::get_bus_interfaces out_sample -of_objects [ipx::current_core]] ``` * At the end of the script there is the `package_xo` command. This command analyzes the IP that was created to make sure proper AXI interfaces are used and other rule checks are followed. It then creates the XO file in the same location as the IP repository. A key function used in this command is the `-output_kernel_xml`. The `kernel.xml` file is key to the RTL kernel as it describes to the Vitis tool how the kernel should be controlled. You can find more information on RTL kernels and their requirements [here](https://www.xilinx.com/cgi-bin/docs/rdoc?t=vitis+doc;v=2021.1;d=devrtlkernel.html). - + ```tcl package_xo -kernel_name $kernelName \ -ctrl_protocol ap_ctrl_none \ @@ -239,7 +239,7 @@ After packaging, everything is ready to run emulation or to run on hardware. ```bash cd ./sw - ./launch_hw_emu.sh + ./launch_hw_emu.sh cd .. ``` @@ -293,4 +293,4 @@ You may obtain a copy of the License at Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -

Copyright© 2020–2021 Xilinx
XD012

\ No newline at end of file +

Copyright© 2020–2021 Xilinx
XD012

diff --git a/AI_Engine_Development/Design_Tutorials/06-fft2d_AIEvsHLS/README.md b/AI_Engine_Development/Design_Tutorials/06-fft2d_AIEvsHLS/README.md index 768ef4ed7b..29da8560ad 100755 --- a/AI_Engine_Development/Design_Tutorials/06-fft2d_AIEvsHLS/README.md +++ b/AI_Engine_Development/Design_Tutorials/06-fft2d_AIEvsHLS/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/README.md b/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/README.md index 6102eccfa3..08c0799f14 100644 --- a/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/README.md +++ b/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_01_python_sims/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_01_python_sims/README.md index 001e6646a9..082147ead4 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_01_python_sims/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_01_python_sims/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md index 121c2dd5cd..a6d1e3a96d 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_02_aie/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md index dd61811867..912d444ad1 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_03_pl_kernels/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md index ed307616b4..68a63497be 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_04_full_system_design/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md index 9884015bac..c4007109f1 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_06_sd_card_and_hw_run/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_07_results/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_07_results/README.md index 1037086c9b..beeb2aac7f 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_07_results/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/Module_07_results/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/README.md b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/README.md index c9920eed33..4978170945 100644 --- a/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/README.md +++ b/AI_Engine_Development/Design_Tutorials/08-n-body-simulator/README.md @@ -2,7 +2,7 @@

Versal® ACAP AI Engine Tutorials

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/01-custom_base_platform_creation.md b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/01-custom_base_platform_creation.md index 11f8e36e30..d9b022a81b 100644 --- a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/01-custom_base_platform_creation.md +++ b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/01-custom_base_platform_creation.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/02-aie_application_creation.md b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/02-aie_application_creation.md index 1c3aea1a0f..28d1a7f8e7 100644 --- a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/02-aie_application_creation.md +++ b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/02-aie_application_creation.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/03-pl_application_creation.md b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/03-pl_application_creation.md index 6f5d685c1f..c98085c65b 100644 --- a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/03-pl_application_creation.md +++ b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/03-pl_application_creation.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/04-ps_application_creation_run_all.md b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/04-ps_application_creation_run_all.md index 55d5d7818e..f479cc78c1 100644 --- a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/04-ps_application_creation_run_all.md +++ b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/04-ps_application_creation_run_all.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/05-RPU version[optional].md b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/05-RPU version[optional].md index 4f78e33abf..d037847e4e 100644 --- a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/05-RPU version[optional].md +++ b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/05-RPU version[optional].md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/README.md b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/README.md index 55e3cdb1b3..46d1fd085a 100644 --- a/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/README.md +++ b/AI_Engine_Development/Feature_Tutorials/01-aie_a_to_z/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/02-using-gmio/README.md b/AI_Engine_Development/Feature_Tutorials/02-using-gmio/README.md index 22e9d9bba3..96d91e64c4 100644 --- a/AI_Engine_Development/Feature_Tutorials/02-using-gmio/README.md +++ b/AI_Engine_Development/Feature_Tutorials/02-using-gmio/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/02-using-gmio/perf_profile_aie_gmio.md b/AI_Engine_Development/Feature_Tutorials/02-using-gmio/perf_profile_aie_gmio.md index 0e20351e62..f6f909fed6 100644 --- a/AI_Engine_Development/Feature_Tutorials/02-using-gmio/perf_profile_aie_gmio.md +++ b/AI_Engine_Development/Feature_Tutorials/02-using-gmio/perf_profile_aie_gmio.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/02-using-gmio/single_aie_gmio.md b/AI_Engine_Development/Feature_Tutorials/02-using-gmio/single_aie_gmio.md index e1156a7427..58bfd95175 100644 --- a/AI_Engine_Development/Feature_Tutorials/02-using-gmio/single_aie_gmio.md +++ b/AI_Engine_Development/Feature_Tutorials/02-using-gmio/single_aie_gmio.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/README.md b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/README.md index 16ff066cc5..2adc840ea0 100644 --- a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/README.md +++ b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step1_sync_scalar.md b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step1_sync_scalar.md index 8ecd152a92..583a926822 100644 --- a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step1_sync_scalar.md +++ b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step1_sync_scalar.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step2_async_scalar.md b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step2_async_scalar.md index 3b07fb5f10..210667be45 100644 --- a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step2_async_scalar.md +++ b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step2_async_scalar.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step3_async_array.md b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step3_async_array.md index 49546774b6..c0d4747bed 100644 --- a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step3_async_array.md +++ b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step3_async_array.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step4_async_aie_array.md b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step4_async_aie_array.md index 4a5d40e4fa..b4cdb9a391 100644 --- a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step4_async_aie_array.md +++ b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step4_async_aie_array.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step5_async_array_update_read.md b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step5_async_array_update_read.md index 6e53382b87..df63359e53 100644 --- a/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step5_async_array_update_read.md +++ b/AI_Engine_Development/Feature_Tutorials/03-rtp-reconfiguration/step5_async_array_update_read.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/README.md b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/README.md index 58b9490ba4..1e5c0ac472 100644 --- a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/README.md +++ b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/pktstream_based_aie_kernel.md b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/pktstream_based_aie_kernel.md index 4025102bfd..d451c5a742 100644 --- a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/pktstream_based_aie_kernel.md +++ b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/pktstream_based_aie_kernel.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_aie_kernel.md b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_aie_kernel.md index edac5c6790..5b04927ef2 100644 --- a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_aie_kernel.md +++ b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_aie_kernel.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_mix_data_type.md b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_mix_data_type.md index e7f2b24abd..c0f84b3e03 100644 --- a/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_mix_data_type.md +++ b/AI_Engine_Development/Feature_Tutorials/04-packet-switching/window_based_mix_data_type.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration/README.md b/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration/README.md index fa2e9f1744..1c330a55a6 100644 --- a/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration/README.md +++ b/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md b/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md index 0dfa2f8a12..022ed7b122 100644 --- a/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md +++ b/AI_Engine_Development/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/08-dsp-library/README.md b/AI_Engine_Development/Feature_Tutorials/08-dsp-library/README.md index c9a68ea3fc..49c860ad2e 100644 --- a/AI_Engine_Development/Feature_Tutorials/08-dsp-library/README.md +++ b/AI_Engine_Development/Feature_Tutorials/08-dsp-library/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/10-aie-dsp-lib-model-composer/README.md b/AI_Engine_Development/Feature_Tutorials/10-aie-dsp-lib-model-composer/README.md index 4941f3bd25..21fe205785 100644 --- a/AI_Engine_Development/Feature_Tutorials/10-aie-dsp-lib-model-composer/README.md +++ b/AI_Engine_Development/Feature_Tutorials/10-aie-dsp-lib-model-composer/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README.md b/AI_Engine_Development/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README.md index b502c76962..4ddd0c5ec9 100644 --- a/AI_Engine_Development/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README.md +++ b/AI_Engine_Development/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README.md @@ -2,7 +2,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com diff --git a/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md b/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md index 37e83337c4..ac5dfeb655 100644 --- a/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md +++ b/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md @@ -13,7 +13,7 @@

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com >>>>>>> d8d61191... Updated headers and footers, fixed image references (#33) diff --git a/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/README.md b/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/README.md index e6e48ffed3..707083e2d0 100644 --- a/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/README.md +++ b/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/README.md @@ -1,9 +1,9 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_execution_measurement.md b/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_execution_measurement.md index 2e218dc5b5..9fdad66b31 100644 --- a/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_execution_measurement.md +++ b/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_execution_measurement.md @@ -1,9 +1,9 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_hang_analysis.md b/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_hang_analysis.md index aeafca5f1d..042ec26014 100644 --- a/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_hang_analysis.md +++ b/AI_Engine_Development/Feature_Tutorials/13-aie-performance-analysis/aie_hang_analysis.md @@ -1,9 +1,9 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1a/README.md b/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1a/README.md index 52b12d73e7..c26b5952b6 100644 --- a/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1a/README.md +++ b/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1a/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1b/README.md b/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1b/README.md index b0ef3b876c..354829fc18 100644 --- a/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1b/README.md +++ b/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/Part1b/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/README.md b/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/README.md index 7582979750..8bcf511a12 100644 --- a/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/README.md +++ b/AI_Engine_Development/Feature_Tutorials/14-implementing-iir-filter/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/README.md b/AI_Engine_Development/README.md index 46866b1a14..1e5b4201a0 100755 --- a/AI_Engine_Development/README.md +++ b/AI_Engine_Development/README.md @@ -1,8 +1,8 @@ - +

AI Engine Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis-AI™ Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com