diff --git a/lab6/ece385lab6.qpf b/lab6/ece385lab6.qpf
new file mode 100644
index 0000000..33e5dfb
--- /dev/null
+++ b/lab6/ece385lab6.qpf
@@ -0,0 +1,6 @@
+QUARTUS_VERSION = "18.1"
+DATE = "11:00:00  February 28, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "ece385lab6"
diff --git a/lab6/ece385lab6.sdc b/lab6/ece385lab6.sdc
new file mode 100644
index 0000000..b0df13c
--- /dev/null
+++ b/lab6/ece385lab6.sdc
@@ -0,0 +1,17 @@
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+create_generated_clock -source [get_pins { u0|altpll_0|sd1|pll7|clk[1] }] -name clk_dram_ext [get_ports {DRAM_CLK}]
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_input_delay -max -clock clk_dram_ext 5.9 [get_ports DRAM_DQ*]
+set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*]
+set_multicycle_path -from [get_clocks {clk_dram_ext}] -to [get_clocks { u0|altpll_0|sd1|pll7|clk[0] }] -setup 2
+set_output_delay -max -clock clk_dram_ext 1.6  [get_ports {DRAM_DQ* DRAM_*DQM}]
+set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_DQ* DRAM_*DQM}]
+set_output_delay -max -clock clk_dram_ext 1.6  [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
+set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
+
+set_false_path -from [get_ports {KEY* SW* DRAM* altera*}] -to *
+set_false_path -from * -to [get_ports {LEDR* HEX* DRAM* altera*}]
diff --git a/lab6/ece385lab61.qsf b/lab6/ece385lab61.qsf
new file mode 100644
index 0000000..4f24375
--- /dev/null
+++ b/lab6/ece385lab61.qsf
@@ -0,0 +1,259 @@
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY lab61
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:00  FEBRUARY 28, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name SYSTEMVERILOG_FILE src/lab61.sv
+set_global_assignment -name QIP_FILE lab6_soc/synthesis/lab61_soc.qip
+set_global_assignment -name SDC_FILE lab6.sdc
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+set_location_assignment PIN_A8 -to LEDR[0]
+set_location_assignment PIN_A9 -to LEDR[1]
+set_location_assignment PIN_A10 -to LEDR[2]
+set_location_assignment PIN_B10 -to LEDR[3]
+set_location_assignment PIN_D13 -to LEDR[4]
+set_location_assignment PIN_C13 -to LEDR[5]
+set_location_assignment PIN_E14 -to LEDR[6]
+set_location_assignment PIN_D14 -to LEDR[7]
+set_location_assignment PIN_A11 -to LEDR[8]
+set_location_assignment PIN_B11 -to LEDR[9]
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_A19 -to HEX2[7]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_D22 -to HEX3[7]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_F17 -to HEX4[7]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_location_assignment PIN_L19 -to HEX5[7]
+set_location_assignment PIN_U17 -to DRAM_ADDR[0]
+set_location_assignment PIN_W19 -to DRAM_ADDR[1]
+set_location_assignment PIN_V18 -to DRAM_ADDR[2]
+set_location_assignment PIN_U18 -to DRAM_ADDR[3]
+set_location_assignment PIN_U19 -to DRAM_ADDR[4]
+set_location_assignment PIN_T18 -to DRAM_ADDR[5]
+set_location_assignment PIN_T19 -to DRAM_ADDR[6]
+set_location_assignment PIN_R18 -to DRAM_ADDR[7]
+set_location_assignment PIN_P18 -to DRAM_ADDR[8]
+set_location_assignment PIN_P19 -to DRAM_ADDR[9]
+set_location_assignment PIN_T20 -to DRAM_ADDR[10]
+set_location_assignment PIN_P20 -to DRAM_ADDR[11]
+set_location_assignment PIN_R20 -to DRAM_ADDR[12]
+set_location_assignment PIN_Y21 -to DRAM_DQ[0]
+set_location_assignment PIN_Y20 -to DRAM_DQ[1]
+set_location_assignment PIN_AA22 -to DRAM_DQ[2]
+set_location_assignment PIN_AA21 -to DRAM_DQ[3]
+set_location_assignment PIN_Y22 -to DRAM_DQ[4]
+set_location_assignment PIN_W22 -to DRAM_DQ[5]
+set_location_assignment PIN_W20 -to DRAM_DQ[6]
+set_location_assignment PIN_V21 -to DRAM_DQ[7]
+set_location_assignment PIN_P21 -to DRAM_DQ[8]
+set_location_assignment PIN_J22 -to DRAM_DQ[9]
+set_location_assignment PIN_H21 -to DRAM_DQ[10]
+set_location_assignment PIN_H22 -to DRAM_DQ[11]
+set_location_assignment PIN_G22 -to DRAM_DQ[12]
+set_location_assignment PIN_G20 -to DRAM_DQ[13]
+set_location_assignment PIN_G19 -to DRAM_DQ[14]
+set_location_assignment PIN_F22 -to DRAM_DQ[15]
+set_location_assignment PIN_T21 -to DRAM_BA[0]
+set_location_assignment PIN_T22 -to DRAM_BA[1]
+set_location_assignment PIN_V22 -to DRAM_LDQM
+set_location_assignment PIN_J21 -to DRAM_UDQM
+set_location_assignment PIN_U22 -to DRAM_RAS_N
+set_location_assignment PIN_U21 -to DRAM_CAS_N
+set_location_assignment PIN_N22 -to DRAM_CKE
+set_location_assignment PIN_L14 -to DRAM_CLK
+set_location_assignment PIN_V20 -to DRAM_WE_N
+set_location_assignment PIN_U20 -to DRAM_CS_N
+set_location_assignment PIN_N5 -to ADC_CLK_10
+set_location_assignment PIN_P11 -to MAX10_CLK1_50
+set_location_assignment PIN_N14 -to MAX10_CLK2_50
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/lab6/ece385lab62.qsf b/lab6/ece385lab62.qsf
new file mode 100644
index 0000000..4f87055
--- /dev/null
+++ b/lab6/ece385lab62.qsf
@@ -0,0 +1,326 @@
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY lab62
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:00  FEBRUARY 28, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name SYSTEMVERILOG_FILE src/lab62.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/ball.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/vga.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/utils.sv
+set_global_assignment -name QIP_FILE lab62_soc/synthesis/lab62_soc.qip
+set_global_assignment -name SDC_FILE lab6.sdc
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to ARDUINO_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+set_location_assignment PIN_A8 -to LEDR[0]
+set_location_assignment PIN_A9 -to LEDR[1]
+set_location_assignment PIN_A10 -to LEDR[2]
+set_location_assignment PIN_B10 -to LEDR[3]
+set_location_assignment PIN_D13 -to LEDR[4]
+set_location_assignment PIN_C13 -to LEDR[5]
+set_location_assignment PIN_E14 -to LEDR[6]
+set_location_assignment PIN_D14 -to LEDR[7]
+set_location_assignment PIN_A11 -to LEDR[8]
+set_location_assignment PIN_B11 -to LEDR[9]
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_A19 -to HEX2[7]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_D22 -to HEX3[7]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_F17 -to HEX4[7]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_location_assignment PIN_L19 -to HEX5[7]
+set_location_assignment PIN_U17 -to DRAM_ADDR[0]
+set_location_assignment PIN_W19 -to DRAM_ADDR[1]
+set_location_assignment PIN_V18 -to DRAM_ADDR[2]
+set_location_assignment PIN_U18 -to DRAM_ADDR[3]
+set_location_assignment PIN_U19 -to DRAM_ADDR[4]
+set_location_assignment PIN_T18 -to DRAM_ADDR[5]
+set_location_assignment PIN_T19 -to DRAM_ADDR[6]
+set_location_assignment PIN_R18 -to DRAM_ADDR[7]
+set_location_assignment PIN_P18 -to DRAM_ADDR[8]
+set_location_assignment PIN_P19 -to DRAM_ADDR[9]
+set_location_assignment PIN_T20 -to DRAM_ADDR[10]
+set_location_assignment PIN_P20 -to DRAM_ADDR[11]
+set_location_assignment PIN_R20 -to DRAM_ADDR[12]
+set_location_assignment PIN_Y21 -to DRAM_DQ[0]
+set_location_assignment PIN_Y20 -to DRAM_DQ[1]
+set_location_assignment PIN_AA22 -to DRAM_DQ[2]
+set_location_assignment PIN_AA21 -to DRAM_DQ[3]
+set_location_assignment PIN_Y22 -to DRAM_DQ[4]
+set_location_assignment PIN_W22 -to DRAM_DQ[5]
+set_location_assignment PIN_W20 -to DRAM_DQ[6]
+set_location_assignment PIN_V21 -to DRAM_DQ[7]
+set_location_assignment PIN_P21 -to DRAM_DQ[8]
+set_location_assignment PIN_J22 -to DRAM_DQ[9]
+set_location_assignment PIN_H21 -to DRAM_DQ[10]
+set_location_assignment PIN_H22 -to DRAM_DQ[11]
+set_location_assignment PIN_G22 -to DRAM_DQ[12]
+set_location_assignment PIN_G20 -to DRAM_DQ[13]
+set_location_assignment PIN_G19 -to DRAM_DQ[14]
+set_location_assignment PIN_F22 -to DRAM_DQ[15]
+set_location_assignment PIN_T21 -to DRAM_BA[0]
+set_location_assignment PIN_T22 -to DRAM_BA[1]
+set_location_assignment PIN_V22 -to DRAM_LDQM
+set_location_assignment PIN_J21 -to DRAM_UDQM
+set_location_assignment PIN_U22 -to DRAM_RAS_N
+set_location_assignment PIN_U21 -to DRAM_CAS_N
+set_location_assignment PIN_N22 -to DRAM_CKE
+set_location_assignment PIN_L14 -to DRAM_CLK
+set_location_assignment PIN_V20 -to DRAM_WE_N
+set_location_assignment PIN_U20 -to DRAM_CS_N
+set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
+set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
+set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
+set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
+set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
+set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
+set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
+set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
+set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
+set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
+set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
+set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
+set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
+set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
+set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
+set_location_assignment PIN_F16 -to ARDUINO_RESET_N
+set_location_assignment PIN_AA1 -to VGA_R[0]
+set_location_assignment PIN_V1 -to VGA_R[1]
+set_location_assignment PIN_Y2 -to VGA_R[2]
+set_location_assignment PIN_Y1 -to VGA_R[3]
+set_location_assignment PIN_W1 -to VGA_G[0]
+set_location_assignment PIN_T2 -to VGA_G[1]
+set_location_assignment PIN_R2 -to VGA_G[2]
+set_location_assignment PIN_R1 -to VGA_G[3]
+set_location_assignment PIN_P1 -to VGA_B[0]
+set_location_assignment PIN_T1 -to VGA_B[1]
+set_location_assignment PIN_P4 -to VGA_B[2]
+set_location_assignment PIN_N2 -to VGA_B[3]
+set_location_assignment PIN_N3 -to VGA_HS
+set_location_assignment PIN_N1 -to VGA_VS
+set_location_assignment PIN_N5 -to ADC_CLK_10
+set_location_assignment PIN_P11 -to MAX10_CLK1_50
+set_location_assignment PIN_N14 -to MAX10_CLK2_50
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/lab6/lab61_soc.qsys b/lab6/lab61_soc.qsys
new file mode 100644
index 0000000..ecd7f3c
--- /dev/null
+++ b/lab6/lab61_soc.qsys
@@ -0,0 +1,1260 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element mem_onchip
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element mem_onchip.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element nios2
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element nios2.debug_mem_slave
+   {
+      datum baseAddress
+      {
+         value = "4096";
+         type = "String";
+      }
+   }
+   element pio_hex0
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element pio_hex0.s1
+   {
+      datum baseAddress
+      {
+         value = "256";
+         type = "String";
+      }
+   }
+   element pio_hex1
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element pio_hex1.s1
+   {
+      datum baseAddress
+      {
+         value = "176";
+         type = "String";
+      }
+   }
+   element pio_hex2
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element pio_hex2.s1
+   {
+      datum baseAddress
+      {
+         value = "192";
+         type = "String";
+      }
+   }
+   element pio_hex3
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element pio_hex3.s1
+   {
+      datum baseAddress
+      {
+         value = "208";
+         type = "String";
+      }
+   }
+   element pio_hex4
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element pio_hex4.s1
+   {
+      datum baseAddress
+      {
+         value = "224";
+         type = "String";
+      }
+   }
+   element pio_hex5
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element pio_hex5.s1
+   {
+      datum baseAddress
+      {
+         value = "240";
+         type = "String";
+      }
+   }
+   element pio_key1
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element pio_key1.s1
+   {
+      datum baseAddress
+      {
+         value = "272";
+         type = "String";
+      }
+   }
+   element pio_led
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element pio_led.s1
+   {
+      datum baseAddress
+      {
+         value = "304";
+         type = "String";
+      }
+   }
+   element pio_sw
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element pio_sw.s1
+   {
+      datum baseAddress
+      {
+         value = "288";
+         type = "String";
+      }
+   }
+   element pll
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element pll.pll_slave
+   {
+      datum baseAddress
+      {
+         value = "320";
+         type = "String";
+      }
+   }
+   element sdram
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sdram.s1
+   {
+      datum baseAddress
+      {
+         value = "134217728";
+         type = "String";
+      }
+   }
+   element sysid
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sysid.control_slave
+   {
+      datum baseAddress
+      {
+         value = "344";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C7G" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="ece385lab6.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="hex0_wire"
+   internal="pio_hex0.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hex1_wire"
+   internal="pio_hex1.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hex2_wire"
+   internal="pio_hex2.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hex3_wire"
+   internal="pio_hex3.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hex4_wire"
+   internal="pio_hex4.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="hex5_wire"
+   internal="pio_hex5.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="key1_wire"
+   internal="pio_key1.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="led_wire"
+   internal="pio_led.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
+ <interface name="sdram_clk" internal="pll.c1" type="clock" dir="start" />
+ <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
+ <interface
+   name="sw_wire"
+   internal="pio_sw.external_connection"
+   type="conduit"
+   dir="end" />
+ <module name="clk" kind="clock_source" version="18.1" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   name="mem_onchip"
+   kind="altera_avalon_onchip_memory2"
+   version="18.1"
+   enabled="1">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_mem_onchip</parameter>
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="copyInitFile" value="false" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dataWidth2" value="32" />
+  <parameter name="deviceFamily" value="MAX 10" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dualPort" value="false" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="enPRInitMode" value="false" />
+  <parameter name="enableDiffWidth" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="16" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+ </module>
+ <module name="nios2" kind="altera_nios2_gen2" version="18.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C7G" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave" value="None" />
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="28" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem_onchip.s1' start='0x0' end='0x10' type='altera_avalon_onchip_memory2.s1' /><slave name='pio_hex1.s1' start='0xB0' end='0xC0' type='altera_avalon_pio.s1' /><slave name='pio_hex2.s1' start='0xC0' end='0xD0' type='altera_avalon_pio.s1' /><slave name='pio_hex3.s1' start='0xD0' end='0xE0' type='altera_avalon_pio.s1' /><slave name='pio_hex4.s1' start='0xE0' end='0xF0' type='altera_avalon_pio.s1' /><slave name='pio_hex5.s1' start='0xF0' end='0x100' type='altera_avalon_pio.s1' /><slave name='pio_hex0.s1' start='0x100' end='0x110' type='altera_avalon_pio.s1' /><slave name='pio_key1.s1' start='0x110' end='0x120' type='altera_avalon_pio.s1' /><slave name='pio_sw.s1' start='0x120' end='0x130' type='altera_avalon_pio.s1' /><slave name='pio_led.s1' start='0x130' end='0x140' type='altera_avalon_pio.s1' /><slave name='pll.pll_slave' start='0x140' end='0x150' type='altpll.pll_slave' /><slave name='sysid.control_slave' start='0x158' end='0x160' type='altera_avalon_sysid_qsys.control_slave' /><slave name='nios2.debug_mem_slave' start='0x1000' end='0x1800' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sdram.s1' start='0x8000000' end='0xC000000' type='altera_avalon_new_sdram_controller.s1' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="exceptionSlave" value="sdram.s1" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="4096" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Tiny" />
+  <parameter name="instAddrWidth" value="28" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem_onchip.s1' start='0x0' end='0x10' type='altera_avalon_onchip_memory2.s1' /><slave name='pio_hex1.s1' start='0xB0' end='0xC0' type='altera_avalon_pio.s1' /><slave name='pio_hex2.s1' start='0xC0' end='0xD0' type='altera_avalon_pio.s1' /><slave name='pio_hex3.s1' start='0xD0' end='0xE0' type='altera_avalon_pio.s1' /><slave name='pio_hex4.s1' start='0xE0' end='0xF0' type='altera_avalon_pio.s1' /><slave name='pio_hex5.s1' start='0xF0' end='0x100' type='altera_avalon_pio.s1' /><slave name='pio_hex0.s1' start='0x100' end='0x110' type='altera_avalon_pio.s1' /><slave name='pio_key1.s1' start='0x110' end='0x120' type='altera_avalon_pio.s1' /><slave name='pio_sw.s1' start='0x120' end='0x130' type='altera_avalon_pio.s1' /><slave name='pio_led.s1' start='0x130' end='0x140' type='altera_avalon_pio.s1' /><slave name='pll.pll_slave' start='0x140' end='0x150' type='altpll.pll_slave' /><slave name='sysid.control_slave' start='0x158' end='0x160' type='altera_avalon_sysid_qsys.control_slave' /><slave name='nios2.debug_mem_slave' start='0x1000' end='0x1800' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sdram.s1' start='0x8000000' end='0xC000000' type='altera_avalon_new_sdram_controller.s1' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="0" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_TLBMissExcSlave" value="None" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="2" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="sdram.s1" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="false" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="true" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="true" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="true" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="1" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module name="pio_hex0" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_hex1" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_hex2" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_hex3" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_hex4" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_hex5" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_key1" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+ </module>
+ <module name="pio_led" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_sw" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pll" kind="altpll" version="18.1" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="1" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="1" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="-1000" />
+  <parameter name="CLK2_DIVIDE_BY" value="" />
+  <parameter name="CLK2_DUTY_CYCLE" value="" />
+  <parameter name="CLK2_MULTIPLY_BY" value="" />
+  <parameter name="CLK2_PHASE_SHIFT" value="" />
+  <parameter name="CLK3_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="" />
+  <parameter name="CLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK3_PHASE_SHIFT" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="" />
+  <parameter name="CLK4_DUTY_CYCLE" value="" />
+  <parameter name="CLK4_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_PHASE_SHIFT" value="" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 50.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -1.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1678129893648955.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_UNUSED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="PORT_clk2" value="PORT_UNUSED" />
+  <parameter name="PORT_clk3" value="PORT_UNUSED" />
+  <parameter name="PORT_clk4" value="PORT_UNUSED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module
+   name="sdram"
+   kind="altera_avalon_new_sdram_controller"
+   version="18.1"
+   enabled="1">
+  <parameter name="TAC" value="5.4" />
+  <parameter name="TMRD" value="3" />
+  <parameter name="TRCD" value="20.0" />
+  <parameter name="TRFC" value="70.0" />
+  <parameter name="TRP" value="20.0" />
+  <parameter name="TWR" value="14.0" />
+  <parameter name="casLatency" value="3" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="columnWidth" value="10" />
+  <parameter name="componentName" value="$${FILENAME}_sdram" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="generateSimulationModel" value="false" />
+  <parameter name="initNOPDelay" value="0.0" />
+  <parameter name="initRefreshCommands" value="2" />
+  <parameter name="masteredTristateBridgeSlave" value="0" />
+  <parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
+  <parameter name="numberOfBanks" value="4" />
+  <parameter name="numberOfChipSelects" value="1" />
+  <parameter name="pinsSharedViaTriState" value="false" />
+  <parameter name="powerUpDelay" value="200.0" />
+  <parameter name="refreshPeriod" value="15.625" />
+  <parameter name="registerDataIn" value="true" />
+  <parameter name="rowWidth" value="13" />
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="18.1"
+   enabled="1">
+  <parameter name="id" value="0" />
+ </module>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0158" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="nios2.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pll.pll_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0140" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="mem_onchip.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_led.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0130" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="18.1" start="nios2.data_master" end="sdram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_sw.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0120" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_key1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0110" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0100" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex5.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00f0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex4.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex3.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex2.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00b0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0158" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="nios2.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pll.pll_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0140" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="mem_onchip.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_led.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0130" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="sdram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_sw.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0120" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_key1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0110" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_hex0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0100" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_hex5.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00f0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_hex4.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_hex3.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_hex2.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pio_hex1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00b0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="18.1" start="pll.c0" end="sdram.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="nios2.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_led.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_sw.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_key1.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex0.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex1.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex2.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex3.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex4.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex5.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="sysid.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="mem_onchip.clk1" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pll.inclk_interface" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pll.inclk_interface_reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="nios2.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="pio_led.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="sdram.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="pio_sw.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_key1.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_hex0.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_hex5.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_hex4.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_hex3.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_hex2.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_hex1.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="mem_onchip.reset1" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pll.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="nios2.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_led.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="sdram.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_sw.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_key1.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex0.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex5.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex4.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex3.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex2.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex1.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="mem_onchip.reset1" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/lab6/lab62_soc.qsys b/lab6/lab62_soc.qsys
new file mode 100644
index 0000000..784217c
--- /dev/null
+++ b/lab6/lab62_soc.qsys
@@ -0,0 +1,1217 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element jtag_uart
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element jtag_uart.avalon_jtag_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "112";
+         type = "String";
+      }
+   }
+   element nios2
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element nios2.debug_mem_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "4096";
+         type = "String";
+      }
+   }
+   element pio_hex
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element pio_hex.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "128";
+         type = "String";
+      }
+   }
+   element pio_key
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element pio_key.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "160";
+         type = "String";
+      }
+   }
+   element pio_keycode
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element pio_keycode.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "176";
+         type = "String";
+      }
+   }
+   element pio_led
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element pio_led.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "144";
+         type = "String";
+      }
+   }
+   element pio_usb_gpx
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element pio_usb_gpx.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "208";
+         type = "String";
+      }
+   }
+   element pio_usb_irq
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element pio_usb_irq.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "192";
+         type = "String";
+      }
+   }
+   element pio_usb_rst
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element pio_usb_rst.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "224";
+         type = "String";
+      }
+   }
+   element pll
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element pll.pll_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "96";
+         type = "String";
+      }
+   }
+   element sdram
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sdram.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "134217728";
+         type = "String";
+      }
+   }
+   element spi
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element spi.spi_control_port
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "64";
+         type = "String";
+      }
+   }
+   element sysid
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element sysid.control_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "120";
+         type = "String";
+      }
+   }
+   element timer
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element timer.s1
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M50DAF484C7G" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="ece385lab6.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="hex_digits"
+   internal="pio_hex.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="key_external_connection"
+   internal="pio_key.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="keycode"
+   internal="pio_keycode.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="leds"
+   internal="pio_led.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
+ <interface name="sdram_clk" internal="pll.c1" type="clock" dir="start" />
+ <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
+ <interface name="spi0" internal="spi.external" type="conduit" dir="end" />
+ <interface
+   name="usb_gpx"
+   internal="pio_usb_gpx.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="usb_irq"
+   internal="pio_usb_irq.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="usb_rst"
+   internal="pio_usb_rst.external_connection"
+   type="conduit"
+   dir="end" />
+ <module name="clk" kind="clock_source" version="18.1" enabled="1">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   name="jtag_uart"
+   kind="altera_avalon_jtag_uart"
+   version="18.1"
+   enabled="1">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clkFreq" value="50000000" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module name="nios2" kind="altera_nios2_gen2" version="18.1" enabled="1">
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_DEVICE" value="10M50DAF484C7G" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="breakSlave" value="None" />
+  <parameter name="cdx_enabled" value="false" />
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="cpuArchRev" value="1" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
+  <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
+  <parameter name="dataAddrWidth" value="28" />
+  <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="dataMasterHighPerformanceMapParam" value="" />
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='timer.s1' start='0x0' end='0x40' type='altera_avalon_timer.s1' /><slave name='spi.spi_control_port' start='0x40' end='0x60' type='altera_avalon_spi.spi_control_port' /><slave name='pll.pll_slave' start='0x60' end='0x70' type='altpll.pll_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x70' end='0x78' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sysid.control_slave' start='0x78' end='0x80' type='altera_avalon_sysid_qsys.control_slave' /><slave name='pio_hex.s1' start='0x80' end='0x90' type='altera_avalon_pio.s1' /><slave name='pio_led.s1' start='0x90' end='0xA0' type='altera_avalon_pio.s1' /><slave name='pio_key.s1' start='0xA0' end='0xB0' type='altera_avalon_pio.s1' /><slave name='pio_keycode.s1' start='0xB0' end='0xC0' type='altera_avalon_pio.s1' /><slave name='pio_usb_irq.s1' start='0xC0' end='0xD0' type='altera_avalon_pio.s1' /><slave name='pio_usb_gpx.s1' start='0xD0' end='0xE0' type='altera_avalon_pio.s1' /><slave name='pio_usb_rst.s1' start='0xE0' end='0xF0' type='altera_avalon_pio.s1' /><slave name='nios2.debug_mem_slave' start='0x1000' end='0x1800' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sdram.s1' start='0x8000000' end='0xC000000' type='altera_avalon_new_sdram_controller.s1' /></address-map>]]></parameter>
+  <parameter name="data_master_high_performance_paddr_base" value="0" />
+  <parameter name="data_master_high_performance_paddr_size" value="0" />
+  <parameter name="data_master_paddr_base" value="0" />
+  <parameter name="data_master_paddr_size" value="0" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="debug_datatrigger" value="0" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_enabled" value="true" />
+  <parameter name="debug_hwbreakpoint" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="debug_traceStorage" value="onchip_trace" />
+  <parameter name="debug_traceType" value="none" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="deviceFamilyName" value="MAX 10" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="dividerType" value="no_div" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="exceptionSlave" value="sdram.s1" />
+  <parameter name="faAddrWidth" value="1" />
+  <parameter name="faSlaveMapParam" value="" />
+  <parameter name="fa_cache_line" value="2" />
+  <parameter name="fa_cache_linesize" value="0" />
+  <parameter name="flash_instruction_master_paddr_base" value="0" />
+  <parameter name="flash_instruction_master_paddr_size" value="0" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_size" value="4096" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="impl" value="Tiny" />
+  <parameter name="instAddrWidth" value="28" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='pll.pll_slave' start='0x60' end='0x70' type='altpll.pll_slave' /><slave name='sysid.control_slave' start='0x78' end='0x80' type='altera_avalon_sysid_qsys.control_slave' /><slave name='nios2.debug_mem_slave' start='0x1000' end='0x1800' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sdram.s1' start='0x8000000' end='0xC000000' type='altera_avalon_new_sdram_controller.s1' /></address-map>]]></parameter>
+  <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+  <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+  <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+  <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+  <parameter name="instruction_master_paddr_base" value="0" />
+  <parameter name="instruction_master_paddr_size" value="0" />
+  <parameter name="internalIrqMaskSystemInfo" value="14" />
+  <parameter name="io_regionbase" value="0" />
+  <parameter name="io_regionsize" value="0" />
+  <parameter name="master_addr_map" value="false" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="mmu_TLBMissExcSlave" value="None" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpx_enabled" value="false" />
+  <parameter name="mul_32_impl" value="2" />
+  <parameter name="mul_64_impl" value="0" />
+  <parameter name="mul_shift_choice" value="0" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramInit" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="register_file_por" value="false" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="resetSlave" value="sdram.s1" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateTrace" value="false" />
+  <parameter name="setting_allow_break_inst" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_asic_add_scan_mode_input" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_asic_third_party_synthesis" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_branchpredictiontype" value="Dynamic" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_dc_ecc_present" value="true" />
+  <parameter name="setting_disable_tmr_inj" value="false" />
+  <parameter name="setting_disableocitrace" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="true" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_exportHostDebugPort" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_exportdebuginfo" value="false" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_fast_register_read" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_itcm_ecc_present" value="true" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_oci_version" value="1" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_support31bitdcachebypass" value="true" />
+  <parameter name="setting_tmr_output_disable" value="false" />
+  <parameter name="setting_usedesignware" value="false" />
+  <parameter name="shift_rot_impl" value="1" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+  <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+  <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+  <parameter name="tmr_enabled" value="false" />
+  <parameter name="tracefilename" value="" />
+  <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module name="pio_hex" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="16" />
+ </module>
+ <module name="pio_key" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="2" />
+ </module>
+ <module
+   name="pio_keycode"
+   kind="altera_avalon_pio"
+   version="18.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+ </module>
+ <module name="pio_led" kind="altera_avalon_pio" version="18.1" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="14" />
+ </module>
+ <module
+   name="pio_usb_gpx"
+   kind="altera_avalon_pio"
+   version="18.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+ </module>
+ <module
+   name="pio_usb_irq"
+   kind="altera_avalon_pio"
+   version="18.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+ </module>
+ <module
+   name="pio_usb_rst"
+   kind="altera_avalon_pio"
+   version="18.1"
+   enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+ </module>
+ <module name="pll" kind="altpll" version="18.1" enabled="1">
+  <parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="1" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_DIVIDE_BY" value="1" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_MULTIPLY_BY" value="1" />
+  <parameter name="CLK1_PHASE_SHIFT" value="-1000" />
+  <parameter name="CLK2_DIVIDE_BY" value="" />
+  <parameter name="CLK2_DUTY_CYCLE" value="" />
+  <parameter name="CLK2_MULTIPLY_BY" value="" />
+  <parameter name="CLK2_PHASE_SHIFT" value="" />
+  <parameter name="CLK3_DIVIDE_BY" value="" />
+  <parameter name="CLK3_DUTY_CYCLE" value="" />
+  <parameter name="CLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK3_PHASE_SHIFT" value="" />
+  <parameter name="CLK4_DIVIDE_BY" value="" />
+  <parameter name="CLK4_DUTY_CYCLE" value="" />
+  <parameter name="CLK4_MULTIPLY_BY" value="" />
+  <parameter name="CLK4_PHASE_SHIFT" value="" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED</parameter>
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 50.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -1.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1678129893648955.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_LOCKED" value="PORT_UNUSED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="PORT_clk2" value="PORT_UNUSED" />
+  <parameter name="PORT_clk3" value="PORT_UNUSED" />
+  <parameter name="PORT_clk4" value="PORT_UNUSED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ </module>
+ <module
+   name="sdram"
+   kind="altera_avalon_new_sdram_controller"
+   version="18.1"
+   enabled="1">
+  <parameter name="TAC" value="5.4" />
+  <parameter name="TMRD" value="3" />
+  <parameter name="TRCD" value="20.0" />
+  <parameter name="TRFC" value="70.0" />
+  <parameter name="TRP" value="20.0" />
+  <parameter name="TWR" value="14.0" />
+  <parameter name="casLatency" value="3" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="columnWidth" value="10" />
+  <parameter name="componentName" value="$${FILENAME}_sdram" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="generateSimulationModel" value="false" />
+  <parameter name="initNOPDelay" value="0.0" />
+  <parameter name="initRefreshCommands" value="2" />
+  <parameter name="masteredTristateBridgeSlave" value="0" />
+  <parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
+  <parameter name="numberOfBanks" value="4" />
+  <parameter name="numberOfChipSelects" value="1" />
+  <parameter name="pinsSharedViaTriState" value="false" />
+  <parameter name="powerUpDelay" value="200.0" />
+  <parameter name="refreshPeriod" value="15.625" />
+  <parameter name="registerDataIn" value="true" />
+  <parameter name="rowWidth" value="13" />
+ </module>
+ <module name="spi" kind="altera_avalon_spi" version="18.1" enabled="1">
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="inputClockRate" value="50000000" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="2500000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+ </module>
+ <module
+   name="sysid"
+   kind="altera_avalon_sysid_qsys"
+   version="18.1"
+   enabled="1">
+  <parameter name="id" value="0" />
+ </module>
+ <module name="timer" kind="altera_avalon_timer" version="18.1" enabled="1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="64" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="systemFrequency" value="50000000" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="watchdogPulse" value="2" />
+ </module>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="jtag_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0070" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0078" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="nios2.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pll.pll_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0060" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="18.1" start="nios2.data_master" end="sdram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="18.1" start="nios2.data_master" end="timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_hex.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0080" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_usb_irq.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_led.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0090" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_usb_gpx.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_key.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_usb_rst.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="pio_keycode.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00b0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.data_master"
+   end="spi.spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0040" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0078" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="nios2.debug_mem_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x1000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="pll.pll_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0060" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="18.1"
+   start="nios2.instruction_master"
+   end="sdram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="18.1" start="pll.c0" end="sdram.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="nios2.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="sysid.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="spi.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="timer.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="jtag_uart.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_hex.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_usb_irq.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_led.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_keycode.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_usb_gpx.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_key.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pio_usb_rst.clk" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="pll.inclk_interface" />
+ <connection kind="interrupt" version="18.1" start="nios2.irq" end="spi.irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection kind="interrupt" version="18.1" start="nios2.irq" end="timer.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection kind="interrupt" version="18.1" start="nios2.irq" end="jtag_uart.irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pll.inclk_interface_reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="nios2.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="sysid.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="sdram.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="spi.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="timer.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="jtag_uart.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="pio_hex.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_usb_irq.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="pio_led.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_keycode.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_usb_gpx.reset" />
+ <connection kind="reset" version="18.1" start="clk.clk_reset" end="pio_key.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="pio_usb_rst.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pll.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="nios2.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="sdram.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="spi.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="timer.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="jtag_uart.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_hex.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_usb_irq.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_led.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_keycode.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_usb_gpx.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_key.reset" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="nios2.debug_reset_request"
+   end="pio_usb_rst.reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/lab6/software/lab61_app/main.c b/lab6/software/lab61_app/main.c
new file mode 100644
index 0000000..978ea09
--- /dev/null
+++ b/lab6/software/lab61_app/main.c
@@ -0,0 +1,52 @@
+// #define BLINKING_TEST
+
+int main() {
+
+	volatile unsigned int *LED_PIO  = (unsigned int*)0x130;
+
+#ifdef BLINKING_TEST
+
+	*LED_PIO = 0;
+	while (1) {
+		for (int i = 0; i < 100000; i++);
+		*LED_PIO |= 0x1;
+		for (int i = 0; i < 100000; i++);
+		*LED_PIO &= ~0x1;
+	}
+
+#else
+
+#define IDLE 0
+#define EXEC 1
+#define DONE 2
+
+	volatile unsigned int *SW_PIO   = (unsigned int*)0x120;
+	volatile unsigned int *KEY1_PIO = (unsigned int*)0x110;
+	// volatile unsigned int *HEX0_PIO = (unsigned int*)0x100;
+	// volatile unsigned int *HEX1_PIO = (unsigned int*)0x0B0;
+	// volatile unsigned int *HEX2_PIO = (unsigned int*)0x0C0;
+	// volatile unsigned int *HEX3_PIO = (unsigned int*)0x0D0;
+	// volatile unsigned int *HEX4_PIO = (unsigned int*)0x0E0;
+	// volatile unsigned int *HEX5_PIO = (unsigned int*)0x0F0;
+
+	*LED_PIO = 0;
+	int state = IDLE;
+	while (1) {
+		switch (state) {
+		case IDLE:
+			if (!*KEY1_PIO) state = EXEC;
+			break;
+		case EXEC:
+			*LED_PIO += *SW_PIO;
+			state = DONE;
+			break;
+		case DONE:
+			if (*KEY1_PIO) state = IDLE;
+			break;
+		}
+	}
+	
+#endif
+
+	return 1;
+}
diff --git a/lab6/software/usb_kb/main.c b/lab6/software/usb_kb/main.c
new file mode 100644
index 0000000..3230d99
--- /dev/null
+++ b/lab6/software/usb_kb/main.c
@@ -0,0 +1,230 @@
+//ECE 385 USB Host Shield code
+//based on Circuits-at-home USB Host code 1.x
+//to be used for ECE 385 course materials
+//Revised October 2020 - Zuofu Cheng
+
+#include <stdio.h>
+#include "system.h"
+#include "altera_avalon_spi.h"
+#include "altera_avalon_spi_regs.h"
+#include "altera_avalon_pio_regs.h"
+#include "sys/alt_irq.h"
+#include "usb_kb/GenericMacros.h"
+#include "usb_kb/GenericTypeDefs.h"
+#include "usb_kb/HID.h"
+#include "usb_kb/MAX3421E.h"
+#include "usb_kb/transfer.h"
+#include "usb_kb/usb_ch9.h"
+#include "usb_kb/USB.h"
+
+extern HID_DEVICE hid_device;
+
+static BYTE addr = 1; 				//hard-wired USB address
+const char* const devclasses[] = { " Uninitialized", " HID Keyboard", " HID Mouse", " Mass storage" };
+
+BYTE GetDriverandReport() {
+	BYTE i;
+	BYTE rcode;
+	BYTE device = 0xFF;
+	BYTE tmpbyte;
+
+	DEV_RECORD* tpl_ptr;
+	printf("Reached USB_STATE_RUNNING (0x40)\n");
+	for (i = 1; i < USB_NUMDEVICES; i++) {
+		tpl_ptr = GetDevtable(i);
+		if (tpl_ptr->epinfo != NULL) {
+			printf("Device: %d", i);
+			printf("%s \n", devclasses[tpl_ptr->devclass]);
+			device = tpl_ptr->devclass;
+		}
+	}
+	//Query rate and protocol
+	rcode = XferGetIdle(addr, 0, hid_device.interface, 0, &tmpbyte);
+	if (rcode) {   //error handling
+		printf("GetIdle Error. Error code: ");
+		printf("%x \n", rcode);
+	} else {
+		printf("Update rate: ");
+		printf("%x \n", tmpbyte);
+	}
+	printf("Protocol: ");
+	rcode = XferGetProto(addr, 0, hid_device.interface, &tmpbyte);
+	if (rcode) {   //error handling
+		printf("GetProto Error. Error code ");
+		printf("%x \n", rcode);
+	} else {
+		printf("%d \n", tmpbyte);
+	}
+	return device;
+}
+
+void setLED(int LED) {
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE,
+			(IORD_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE) | (0x001 << LED)));
+}
+
+void clearLED(int LED) {
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE,
+			(IORD_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE) & ~(0x001 << LED)));
+
+}
+
+void printSignedHex0(signed char value) {
+	BYTE tens = 0;
+	BYTE ones = 0;
+	WORD pio_val = IORD_ALTERA_AVALON_PIO_DATA(PIO_HEX_BASE);
+	if (value < 0) {
+		setLED(11);
+		value = -value;
+	} else {
+		clearLED(11);
+	}
+	//handled hundreds
+	if (value / 100)
+		setLED(13);
+	else
+		clearLED(13);
+
+	value = value % 100;
+	tens = value / 10;
+	ones = value % 10;
+
+	pio_val &= 0x00FF;
+	pio_val |= (tens << 12);
+	pio_val |= (ones << 8);
+
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_HEX_BASE, pio_val);
+}
+
+void printSignedHex1(signed char value) {
+	BYTE tens = 0;
+	BYTE ones = 0;
+	DWORD pio_val = IORD_ALTERA_AVALON_PIO_DATA(PIO_HEX_BASE);
+	if (value < 0) {
+		setLED(10);
+		value = -value;
+	} else {
+		clearLED(10);
+	}
+	//handled hundreds
+	if (value / 100)
+		setLED(12);
+	else
+		clearLED(12);
+
+	value = value % 100;
+	tens = value / 10;
+	ones = value % 10;
+	tens = value / 10;
+	ones = value % 10;
+
+	pio_val &= 0xFF00;
+	pio_val |= (tens << 4);
+	pio_val |= (ones << 0);
+
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_HEX_BASE, pio_val);
+}
+
+void setKeycode(WORD keycode)
+{
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_KEYCODE_BASE, keycode);
+}
+int main() {
+	BYTE rcode;
+	BOOT_MOUSE_REPORT buf;		//USB mouse report
+	BOOT_KBD_REPORT kbdbuf;
+
+	BYTE runningdebugflag = 0;//flag to dump out a bunch of information when we first get to USB_STATE_RUNNING
+	BYTE errorflag = 0; //flag once we get an error device so we don't keep dumping out state info
+	BYTE device;
+	WORD keycode;
+
+	printf("initializing MAX3421E...\n");
+	MAX3421E_init();
+	printf("initializing USB...\n");
+	USB_init();
+	while (1) {
+		printf(".");
+		MAX3421E_Task();
+		USB_Task();
+		//usleep (500000);
+		if (GetUsbTaskState() == USB_STATE_RUNNING) {
+			if (!runningdebugflag) {
+				runningdebugflag = 1;
+				setLED(9);
+				device = GetDriverandReport();
+			} else if (device == 1) {
+				//run keyboard debug polling
+				rcode = kbdPoll(&kbdbuf);
+				if (rcode == hrNAK) {
+					continue; //NAK means no new data
+				} else if (rcode) {
+					printf("Rcode: ");
+					printf("%x \n", rcode);
+					continue;
+				}
+				printf("keycodes: ");
+				for (int i = 0; i < 6; i++) {
+					printf("%x ", kbdbuf.keycode[i]);
+				}
+				setKeycode(kbdbuf.keycode[0]);
+				printSignedHex0(kbdbuf.keycode[0]);
+				printSignedHex1(kbdbuf.keycode[1]);
+				printf("\n");
+			}
+
+			else if (device == 2) {
+				rcode = mousePoll(&buf);
+				if (rcode == hrNAK) {
+					//NAK means no new data
+					continue;
+				} else if (rcode) {
+					printf("Rcode: ");
+					printf("%x \n", rcode);
+					continue;
+				}
+				printf("X displacement: ");
+				printf("%d ", (signed char) buf.Xdispl);
+				printSignedHex0((signed char) buf.Xdispl);
+				printf("Y displacement: ");
+				printf("%d ", (signed char) buf.Ydispl);
+				printSignedHex1((signed char) buf.Ydispl);
+				printf("Buttons: ");
+				printf("%x\n", buf.button);
+				if (buf.button & 0x04)
+					setLED(2);
+				else
+					clearLED(2);
+				if (buf.button & 0x02)
+					setLED(1);
+				else
+					clearLED(1);
+				if (buf.button & 0x01)
+					setLED(0);
+				else
+					clearLED(0);
+			}
+		} else if (GetUsbTaskState() == USB_STATE_ERROR) {
+			if (!errorflag) {
+				errorflag = 1;
+				clearLED(9);
+				printf("USB Error State\n");
+				//print out string descriptor here
+			}
+		} else //not in USB running state
+		{
+
+			printf("USB task state: ");
+			printf("%x\n", GetUsbTaskState());
+			if (runningdebugflag) {	//previously running, reset USB hardware just to clear out any funky state, HS/FS etc
+				runningdebugflag = 0;
+				MAX3421E_init();
+				USB_init();
+			}
+			errorflag = 0;
+			clearLED(9);
+		}
+
+	}
+	return 0;
+}
diff --git a/lab6/software/usb_kb/usb_kb/GenericMacros.h b/lab6/software/usb_kb/usb_kb/GenericMacros.h
new file mode 100644
index 0000000..c980123
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/GenericMacros.h
@@ -0,0 +1,9 @@
+/* Generic macros */
+
+/* Word <> two chars. Works both ways */
+#define LOBYTE(x) ((char*)(&(x)))[0]
+#define HIBYTE(x) ((char*)(&(x)))[1]
+
+/* Bit set/clear */
+#define bitset(var, bitno) ((var) |= 1 << (bitno))
+#define bitclr(var, bitno) ((var) &= ~(1 << (bitno)))
diff --git a/lab6/software/usb_kb/usb_kb/GenericTypeDefs.h b/lab6/software/usb_kb/usb_kb/GenericTypeDefs.h
new file mode 100644
index 0000000..32c687c
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/GenericTypeDefs.h
@@ -0,0 +1,200 @@
+//Modified version of Generic Types as included by Microchip C18
+
+#ifndef __GENERIC_TYPE_DEFS_H_
+#define __GENERIC_TYPE_DEFS_H_
+
+typedef enum _BOOL {
+	FALSE = 0, TRUE
+} BOOL;	// Undefined size
+
+#define	ON TRUE
+#define	OFF	FALSE
+
+typedef unsigned char BYTE;				// 8-bit unsigned
+typedef unsigned short int WORD;				// 16-bit unsigned
+typedef unsigned long DWORD;				// 32-bit unsigned
+typedef unsigned long long QWORD;				// 64-bit unsigned
+typedef signed char CHAR;				// 8-bit signed
+typedef signed short int SHORT;				// 16-bit signed
+typedef signed long LONG;				// 32-bit signed
+typedef signed long long LONGLONG;			// 64-bit signed
+
+typedef union _BYTE_VAL {
+	BYTE Val;
+	struct {
+		unsigned char b0 :1;
+		unsigned char b1 :1;
+		unsigned char b2 :1;
+		unsigned char b3 :1;
+		unsigned char b4 :1;
+		unsigned char b5 :1;
+		unsigned char b6 :1;
+		unsigned char b7 :1;
+	} bits;
+} BYTE_VAL;
+
+typedef union _WORD_VAL {
+	WORD Val;
+	BYTE v[2];
+	struct {
+		BYTE LB;
+		BYTE HB;
+	} byte;
+	struct {
+		unsigned char b0 :1;
+		unsigned char b1 :1;
+		unsigned char b2 :1;
+		unsigned char b3 :1;
+		unsigned char b4 :1;
+		unsigned char b5 :1;
+		unsigned char b6 :1;
+		unsigned char b7 :1;
+		unsigned char b8 :1;
+		unsigned char b9 :1;
+		unsigned char b10 :1;
+		unsigned char b11 :1;
+		unsigned char b12 :1;
+		unsigned char b13 :1;
+		unsigned char b14 :1;
+		unsigned char b15 :1;
+	} bits;
+} WORD_VAL;
+
+typedef union _DWORD_VAL {
+	DWORD Val;
+	WORD w[2];
+	BYTE v[4];
+	struct {
+		WORD LW;
+		WORD HW;
+	} word;
+	struct {
+		BYTE LB;
+		BYTE HB;
+		BYTE UB;
+		BYTE MB;
+	} byte;
+	struct {
+		unsigned char b0 :1;
+		unsigned char b1 :1;
+		unsigned char b2 :1;
+		unsigned char b3 :1;
+		unsigned char b4 :1;
+		unsigned char b5 :1;
+		unsigned char b6 :1;
+		unsigned char b7 :1;
+		unsigned char b8 :1;
+		unsigned char b9 :1;
+		unsigned char b10 :1;
+		unsigned char b11 :1;
+		unsigned char b12 :1;
+		unsigned char b13 :1;
+		unsigned char b14 :1;
+		unsigned char b15 :1;
+		unsigned char b16 :1;
+		unsigned char b17 :1;
+		unsigned char b18 :1;
+		unsigned char b19 :1;
+		unsigned char b20 :1;
+		unsigned char b21 :1;
+		unsigned char b22 :1;
+		unsigned char b23 :1;
+		unsigned char b24 :1;
+		unsigned char b25 :1;
+		unsigned char b26 :1;
+		unsigned char b27 :1;
+		unsigned char b28 :1;
+		unsigned char b29 :1;
+		unsigned char b30 :1;
+		unsigned char b31 :1;
+	} bits;
+} DWORD_VAL;
+
+typedef union _QWORD_VAL {
+	QWORD Val;
+	DWORD d[2];
+	WORD w[4];
+	BYTE v[8];
+	struct {
+		WORD LD;
+		WORD HD;
+	} dword;
+	struct {
+		WORD LW;
+		WORD HW;
+		WORD UW;
+		WORD MW;
+	} word;
+	struct {
+		unsigned char b0 :1;
+		unsigned char b1 :1;
+		unsigned char b2 :1;
+		unsigned char b3 :1;
+		unsigned char b4 :1;
+		unsigned char b5 :1;
+		unsigned char b6 :1;
+		unsigned char b7 :1;
+		unsigned char b8 :1;
+		unsigned char b9 :1;
+		unsigned char b10 :1;
+		unsigned char b11 :1;
+		unsigned char b12 :1;
+		unsigned char b13 :1;
+		unsigned char b14 :1;
+		unsigned char b15 :1;
+		unsigned char b16 :1;
+		unsigned char b17 :1;
+		unsigned char b18 :1;
+		unsigned char b19 :1;
+		unsigned char b20 :1;
+		unsigned char b21 :1;
+		unsigned char b22 :1;
+		unsigned char b23 :1;
+		unsigned char b24 :1;
+		unsigned char b25 :1;
+		unsigned char b26 :1;
+		unsigned char b27 :1;
+		unsigned char b28 :1;
+		unsigned char b29 :1;
+		unsigned char b30 :1;
+		unsigned char b31 :1;
+		unsigned char b32 :1;
+		unsigned char b33 :1;
+		unsigned char b34 :1;
+		unsigned char b35 :1;
+		unsigned char b36 :1;
+		unsigned char b37 :1;
+		unsigned char b38 :1;
+		unsigned char b39 :1;
+		unsigned char b40 :1;
+		unsigned char b41 :1;
+		unsigned char b42 :1;
+		unsigned char b43 :1;
+		unsigned char b44 :1;
+		unsigned char b45 :1;
+		unsigned char b46 :1;
+		unsigned char b47 :1;
+		unsigned char b48 :1;
+		unsigned char b49 :1;
+		unsigned char b50 :1;
+		unsigned char b51 :1;
+		unsigned char b52 :1;
+		unsigned char b53 :1;
+		unsigned char b54 :1;
+		unsigned char b55 :1;
+		unsigned char b56 :1;
+		unsigned char b57 :1;
+		unsigned char b58 :1;
+		unsigned char b59 :1;
+		unsigned char b60 :1;
+		unsigned char b61 :1;
+		unsigned char b62 :1;
+		unsigned char b63 :1;
+	} bits;
+} QWORD_VAL;
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#endif //__GENERIC_TYPE_DEFS_H_
diff --git a/lab6/software/usb_kb/usb_kb/HID.c b/lab6/software/usb_kb/usb_kb/HID.c
new file mode 100644
index 0000000..867d252
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/HID.c
@@ -0,0 +1,228 @@
+/* HID class support functions */
+
+#include <stdio.h>
+
+#include "../usb_kb/project_config.h"
+
+BYTE bigbuf[256];   //256 bytes
+extern DEV_RECORD devtable[];
+
+HID_DEVICE hid_device = { { 0 } };
+EP_RECORD hid_ep[2] = { { 0 } }; //HID class endpoints, 1 control, 1 interrupt-IN
+//the third endpoint is not implemented     
+
+/* HID Mouse probe. Called from USB state machine.                          */
+/* assumes configuration length is less than 256 bytes                      */
+/* looks for Class:03, Subclass: 01, Protocol: 02 in interface descriptor   */
+/* sets mouse in boot protocol                                              */
+/* assumes single configuration and interface configuration 0               */
+BOOL HIDMProbe(BYTE addr, DWORD flags) {
+	BYTE tmpbyte;
+	BYTE rcode;
+	BYTE confvalue;
+	WORD total_length;
+	USB_DESCR* data_ptr = (USB_DESCR *) &bigbuf;
+	BYTE* byte_ptr = bigbuf;
+	rcode = XferGetConfDescr(addr, 0, CONF_DESCR_LEN, 0, bigbuf); //get configuration descriptor
+	if (rcode) {   //error handling
+		//printf("unable to get configuration descriptor");
+		return (FALSE);
+	}
+	if (data_ptr->descr.config.wTotalLength > 256) {
+		total_length = 256;
+	} else {
+		total_length = data_ptr->descr.config.wTotalLength;
+	}
+	rcode = XferGetConfDescr(addr, 0, total_length, 0, bigbuf); //get the whole configuration
+	if (rcode) {   //error handling
+		//printf("unable to get configuration");
+		return (FALSE);
+	}
+	confvalue = data_ptr->descr.config.bConfigurationValue;
+	//printf("checking configuration value (length: %d): ",
+	//		data_ptr->descr.config.wTotalLength);
+	//for (int i = 0; i < data_ptr->descr.config.wTotalLength; i++) {
+		//printf("%x ", (unsigned char) (bigbuf[i] & 0xff));
+	//}
+	while (byte_ptr < bigbuf + total_length) {
+		if (data_ptr->descr.config.bDescriptorType != USB_DESCRIPTOR_INTERFACE) {
+			byte_ptr = byte_ptr + data_ptr->descr.config.bLength;
+			data_ptr = (USB_DESCR*) byte_ptr;
+		} // if( data_ptr->descr.config.bDescriptorType != USB_DESCRIPTOR_INTERFACE
+		else {
+			//printf("starting interface parsing at byte location %d\n",
+			//		data_ptr->descr.config.bLength);
+			BYTE class = data_ptr->descr.interface.bInterfaceClass;
+			BYTE subclass = data_ptr->descr.interface.bInterfaceSubClass;
+			BYTE protocol = data_ptr->descr.interface.bInterfaceProtocol;
+			//printf("class %x, subclass %x, protocol %x,\n", class, subclass,
+			//		protocol);
+			//interface descriptor
+			if (class == HID_INTF && subclass == BOOT_INTF_SUBCLASS
+					&& protocol == HID_PROTOCOL_MOUSE) {
+				//detected a mouse
+				devtable[addr].devclass = HID_M;                  //device class
+				tmpbyte = devtable[addr].epinfo->MaxPktSize;
+				HID_init();                         //initialize data structures
+				devtable[addr].epinfo = hid_ep; //switch endpoint information structure
+				devtable[addr].epinfo[0].MaxPktSize = tmpbyte;
+				hid_device.interface =
+						data_ptr->descr.interface.bInterfaceNumber;
+				hid_device.addr = addr;
+				byte_ptr = byte_ptr + data_ptr->descr.config.bLength;
+				data_ptr = (USB_DESCR*) byte_ptr;
+				while (byte_ptr < bigbuf + total_length) {
+					if (data_ptr->descr.config.bDescriptorType
+							!= USB_DESCRIPTOR_ENDPOINT) { //skip to endpoint descriptor
+						byte_ptr = byte_ptr + data_ptr->descr.config.bLength;
+						data_ptr = (USB_DESCR*) byte_ptr;
+					} else {
+						/* fill endpoint information structure */
+						devtable[addr].epinfo[1].epAddr =
+								data_ptr->descr.endpoint.bEndpointAddress;
+						devtable[addr].epinfo[1].Attr =
+								data_ptr->descr.endpoint.bmAttributes;
+						devtable[addr].epinfo[1].MaxPktSize =
+								data_ptr->descr.endpoint.wMaxPacketSize;
+						devtable[addr].epinfo[1].Interval =
+								data_ptr->descr.endpoint.bInterval;
+						// devtable[ addr ].epinfo[ 1 ].rcvToggle = bmRCVTOG0;
+						/* configure device */
+						rcode = XferSetConf(addr, 0, confvalue); //set configuration
+						if (rcode) {   //error handling
+							return (FALSE);
+						}
+						rcode = XferSetProto(addr, 0, hid_device.interface,
+								BOOT_PROTOCOL);
+						if (rcode) {   //error handling
+							return (FALSE);
+						} else {
+							return (TRUE);
+						}
+					}
+				}   //while( byte_ptr....
+			}   //if (Class matches
+			else { //if class don't match; die on first interface. Not really correct
+				return (FALSE);
+			}
+		} //else if( data_ptr->
+	} // while( byte_ptr < &buf + total_length
+	return (FALSE);
+}
+/* HID Keyboard probe. Called from USB state machine.                           */
+/* assumes configuration length is less than 256 bytes                          */
+/* looks for Class:03, Subclass: 01, Protocol: 01 in interface descriptor       */
+/* sets keyboard in boot protocol                                               */
+/* assumes single configuration, single endpoint, and interface configuration 0 */
+BOOL HIDKProbe(BYTE addr, DWORD flags) {
+	BYTE tmpbyte;
+	BYTE rcode;
+	BYTE confvalue;
+	WORD total_length;
+	USB_DESCR* data_ptr = (USB_DESCR *) &bigbuf;
+	BYTE* byte_ptr = bigbuf;
+	rcode = XferGetConfDescr(addr, 0, CONF_DESCR_LEN, 0, bigbuf); //get configuration descriptor
+	if (rcode) {   //error handling           
+		return (FALSE);
+	}
+	if (data_ptr->descr.config.wTotalLength > 256) {
+		total_length = 256;
+	} else {
+		total_length = data_ptr->descr.config.wTotalLength;
+	}
+	rcode = XferGetConfDescr(addr, 0, total_length, 0, bigbuf); //get the whole configuration
+	if (rcode) {   //error handling
+		return (FALSE);
+	}
+	confvalue = data_ptr->descr.config.bConfigurationValue; //save configuration value to use later
+	while (byte_ptr < bigbuf + total_length) {             //parse configuration
+		if (data_ptr->descr.config.bDescriptorType != USB_DESCRIPTOR_INTERFACE) { //skip to the next descriptor
+			byte_ptr = byte_ptr + data_ptr->descr.config.bLength;
+			data_ptr = (USB_DESCR*) byte_ptr;
+		} // if( data_ptr->descr.config.bDescriptorType != USB_DESCRIPTOR_INTERFACE
+		else {
+			//printf("starting interface parsing at byte location %d\n",
+			//		data_ptr->descr.config.bLength);
+			BYTE class = data_ptr->descr.interface.bInterfaceClass;
+			BYTE subclass = data_ptr->descr.interface.bInterfaceSubClass;
+			BYTE protocol = data_ptr->descr.interface.bInterfaceProtocol;
+			//printf("class %x, subclass %x, protocol %x,\n", class, subclass,
+			//		protocol);
+			//interface descriptor
+			if (class == HID_INTF && subclass == BOOT_INTF_SUBCLASS
+					&& protocol == HID_PROTOCOL_KEYBOARD) {
+				//detected a keyboard
+				devtable[addr].devclass = HID_K;             //fill device class
+				tmpbyte = devtable[addr].epinfo->MaxPktSize; //save max.packet size
+				HID_init();                         //initialize data structures
+				devtable[addr].epinfo = hid_ep; //switch endpoint information structure
+				devtable[addr].epinfo[0].MaxPktSize = tmpbyte; //fill in max.packet size
+				hid_device.interface =
+						data_ptr->descr.interface.bInterfaceNumber; //fill in interface number to be used in HID requests
+				hid_device.addr = addr;                        //fill in address
+				byte_ptr = byte_ptr + data_ptr->descr.config.bLength; //skip to the next descriptor
+				data_ptr = (USB_DESCR*) byte_ptr;
+				while (byte_ptr < bigbuf + total_length) {
+					if (data_ptr->descr.config.bDescriptorType
+							!= USB_DESCRIPTOR_ENDPOINT) { //skip to endpoint descriptor
+						byte_ptr = byte_ptr + data_ptr->descr.config.bLength;
+						data_ptr = (USB_DESCR*) byte_ptr;
+					} else {
+						/* fill endpoint information structure */
+						devtable[addr].epinfo[1].epAddr =
+								data_ptr->descr.endpoint.bEndpointAddress;
+						devtable[addr].epinfo[1].Attr =
+								data_ptr->descr.endpoint.bmAttributes;
+						devtable[addr].epinfo[1].MaxPktSize =
+								data_ptr->descr.endpoint.wMaxPacketSize;
+						devtable[addr].epinfo[1].Interval =
+								data_ptr->descr.endpoint.bInterval;
+						/* configure device */
+						rcode = XferSetConf(addr, 0, confvalue); //set configuration
+						if (rcode) {   //error handling
+							return (FALSE);
+						}
+						rcode = XferSetProto(addr, 0, hid_device.interface,
+								BOOT_PROTOCOL);
+						if (rcode) {   //error handling
+							return (FALSE);
+						} else {
+							return (TRUE);
+						}
+					}
+				}   //while( byte_ptr....
+			}   //if (Class matches
+			else { //if class don't match; stop processing after first interface. Not really correct
+				return (FALSE);
+			}
+		} //else if( data_ptr->
+	} // while( byte_ptr < &buf + total_length
+	return (FALSE);
+}
+/* HID data structures initialization */
+void HID_init(void) {
+	hid_ep[1].sndToggle = bmSNDTOG0;
+	hid_ep[1].rcvToggle = bmRCVTOG0;
+}
+/* poll boot mouse */
+BYTE mousePoll(BOOT_MOUSE_REPORT* buf) {
+	BYTE rcode;
+	MAXreg_wr( rPERADDR, hid_device.addr);    //set peripheral address
+	rcode = XferInTransfer(hid_device.addr, 1, 8, (BYTE*) buf,
+			devtable[hid_device.addr].epinfo[1].MaxPktSize);
+	return (rcode);
+}
+/* poll boot keyboard */
+BYTE kbdPoll(BOOT_KBD_REPORT* buf) {
+	BYTE rcode;
+	MAXreg_wr( rPERADDR, hid_device.addr);    //set peripheral address
+	rcode = XferInTransfer(hid_device.addr, 1, 8, (BYTE*) buf,
+			devtable[hid_device.addr].epinfo[1].MaxPktSize);
+	return (rcode);
+}
+BOOL HIDMEventHandler(BYTE address, BYTE event, void *data, DWORD size) {
+	return (FALSE);
+}
+BOOL HIDKEventHandler(BYTE address, BYTE event, void *data, DWORD size) {
+	return (FALSE);
+}
diff --git a/lab6/software/usb_kb/usb_kb/HID.h b/lab6/software/usb_kb/usb_kb/HID.h
new file mode 100644
index 0000000..80e9144
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/HID.h
@@ -0,0 +1,50 @@
+/* HID support header */
+
+#ifndef _HID_h_
+#define _HID_h
+
+/* HID device structure */
+typedef struct {
+	BYTE addr;
+	BYTE interface;
+} HID_DEVICE;
+/* Boot mouse report 8 bytes */
+typedef struct {
+//    struct {
+//        unsigned one:1;
+//        unsigned two:1;
+//        unsigned three:1;
+//        unsigned :5;
+//        } button;
+	BYTE button;
+	BYTE Xdispl;
+	BYTE Ydispl;
+	BYTE bytes3to7[5];   //optional bytes
+} BOOT_MOUSE_REPORT;
+/* boot keyboard report 8 bytes */
+typedef struct {
+	BYTE mod;
+//    struct {
+//        unsigned LCtrl:1;
+//        unsigned LShift:1;
+//        unsigned LAlt:1;
+//        unsigned LWin:1;
+//        /**/
+//        unsigned RCtrl:1;
+//        unsigned RShift:1;
+//        unsigned RAlt:1;
+//        unsigned RWin:1;
+//        } mod;
+	BYTE reserved;
+	BYTE keycode[6];
+} BOOT_KBD_REPORT;
+
+/* Function prototypes */
+BOOL HIDMProbe(BYTE address, DWORD flags);
+BOOL HIDKProbe(BYTE address, DWORD flags);
+void HID_init(void);
+BYTE mousePoll(BOOT_MOUSE_REPORT* buf);
+BYTE kbdPoll(BOOT_KBD_REPORT* buf);
+BOOL HIDMEventHandler(BYTE addr, BYTE event, void *data, DWORD size);
+BOOL HIDKEventHandler(BYTE addr, BYTE event, void *data, DWORD size);
+#endif // _HID_h_
diff --git a/lab6/software/usb_kb/usb_kb/MAX3421E.c b/lab6/software/usb_kb/usb_kb/MAX3421E.c
new file mode 100644
index 0000000..58eb4e0
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/MAX3421E.c
@@ -0,0 +1,198 @@
+#define _MAX3421E_C_
+
+#include "system.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "string.h"
+#include "../usb_kb/project_config.h"
+#include "altera_avalon_spi.h"
+#include "altera_avalon_spi_regs.h"
+#include "altera_avalon_pio_regs.h"
+#include <sys/alt_stdio.h>
+#include <unistd.h>
+
+//variables and data structures
+//External variables
+extern BYTE usb_task_state;
+
+/* Functions    */
+void SPI_init(BYTE sync_mode, BYTE bus_mode, BYTE smp_phase) {
+	//Don't need to initialize SPI port, already ready to go with BSP
+}
+
+//writes single byte to MAX3421E via SPI, simultanously reads status register and returns it
+BYTE SPI_wr(BYTE data) {
+	//This function is never used by the code, so you do not need to fill it in
+}
+
+/* -------------------- LAB 6.2 -------------------- */
+
+// writes register to MAX3421E via SPI
+void MAXreg_wr(BYTE reg, BYTE val) {
+	alt_u8 wbuf[2] = {reg + 2, val};
+	if (alt_avalon_spi_command(SPI_BASE, 0, 2, wbuf, 0, NULL, 0) < 0)
+		printf("SPI write register error\n");
+}
+
+// multiple-byte write; returns a pointer to a memory position after last written
+BYTE* MAXbytes_wr(BYTE reg, BYTE nbytes, BYTE* data) {
+	alt_u8 wbuf[nbytes + 1];
+	wbuf[0] = reg + 2;
+	// memcpy(wbuf + 1, data, nbytes);
+	for (int i = 0; i < nbytes; i++)
+		wbuf[i + 1] = data[i];
+	if (alt_avalon_spi_command(SPI_BASE, 0, nbytes + 1, wbuf, 0, NULL, 0) < 0)
+		printf("SPI write bytes error\n");
+	return data + nbytes;
+}
+
+// reads register from MAX3421E via SPI
+BYTE MAXreg_rd(BYTE reg) {
+	BYTE val = 0;
+	if (alt_avalon_spi_command(SPI_BASE, 0, 1, &reg, 1, &val, 0) < 0)
+		printf("SPI read register error\n");
+	return val;
+}
+
+// multiple-byte read; returns a pointer to a memory position after last written
+BYTE* MAXbytes_rd(BYTE reg, BYTE nbytes, BYTE* data) {
+	if (alt_avalon_spi_command(SPI_BASE, 0, 1, &reg, nbytes, data, 0) < 0)
+		printf("SPI read bytes error\n");
+	return data + nbytes;
+}
+
+/* ------------------ LAB 6.2 END ------------------ */
+
+/* reset MAX3421E using chip reset bit. SPI configuration is not affected   */
+void MAX3421E_reset(void) {
+	//hardware reset, then software reset
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_USB_RST_BASE, 0);
+	usleep(1000000);
+	IOWR_ALTERA_AVALON_PIO_DATA(PIO_USB_RST_BASE, 1);
+	BYTE tmp = 0;
+	MAXreg_wr( rUSBCTL, bmCHIPRES);      //Chip reset. This stops the oscillator
+	MAXreg_wr( rUSBCTL, 0x00);                          //Remove the reset
+	while (!(MAXreg_rd( rUSBIRQ) & bmOSCOKIRQ)) { //wait until the PLL stabilizes
+		tmp++;                                      //timeout after 256 attempts
+		if (tmp == 0) {
+			printf("reset timeout!");
+		}
+	}
+}
+/* turn USB power on/off                                                */
+/* ON pin of VBUS switch (MAX4793 or similar) is connected to GPOUT7    */
+/* OVERLOAD pin of Vbus switch is connected to GPIN7                    */
+/* OVERLOAD state low. NO OVERLOAD or VBUS OFF state high.              */
+BOOL Vbus_power(BOOL action) {
+	// power on/off successful
+	return (1);
+}
+
+/* probe bus to determine device presense and speed */
+void MAX_busprobe(void) {
+	BYTE bus_sample;
+
+//  MAXreg_wr(rHCTL,bmSAMPLEBUS);
+	bus_sample = MAXreg_rd( rHRSL);            //Get J,K status
+	bus_sample &= ( bmJSTATUS | bmKSTATUS);      //zero the rest of the byte
+
+	switch (bus_sample) {                   //start full-speed or low-speed host
+	case ( bmJSTATUS):
+		/*kludgy*/
+		if (usb_task_state != USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE) { //bus reset causes connection detect interrupt
+			if (!(MAXreg_rd( rMODE) & bmLOWSPEED)) {
+				MAXreg_wr( rMODE, MODE_FS_HOST);         //start full-speed host
+				printf("Starting in full speed\n");
+			} else {
+				MAXreg_wr( rMODE, MODE_LS_HOST);    //start low-speed host
+				printf("Starting in low speed\n");
+			}
+			usb_task_state = ( USB_STATE_ATTACHED); //signal usb state machine to start attachment sequence
+		}
+		break;
+	case ( bmKSTATUS):
+		if (usb_task_state != USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE) { //bus reset causes connection detect interrupt
+			if (!(MAXreg_rd( rMODE) & bmLOWSPEED)) {
+				MAXreg_wr( rMODE, MODE_LS_HOST);   //start low-speed host
+				printf("Starting in low speed\n");
+			} else {
+				MAXreg_wr( rMODE, MODE_FS_HOST);         //start full-speed host
+				printf("Starting in full speed\n");
+			}
+			usb_task_state = ( USB_STATE_ATTACHED); //signal usb state machine to start attachment sequence
+		}
+		break;
+	case ( bmSE1):              //illegal state
+		usb_task_state = ( USB_DETACHED_SUBSTATE_ILLEGAL);
+		break;
+	case ( bmSE0):              //disconnected state
+		if (!((usb_task_state & USB_STATE_MASK) == USB_STATE_DETACHED)) //if we came here from other than detached state
+			usb_task_state = ( USB_DETACHED_SUBSTATE_INITIALIZE); //clear device data structures
+		else {
+			MAXreg_wr( rMODE, MODE_FS_HOST); //start full-speed host
+			usb_task_state = ( USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE);
+		}
+		break;
+	} //end switch( bus_sample )
+}
+/* MAX3421E initialization after power-on   */
+void MAX3421E_init(void) {
+	/* Configure full-duplex SPI, interrupt pulse   */
+	MAXreg_wr( rPINCTL, (bmFDUPSPI + bmINTLEVEL + bmGPXB)); //Full-duplex SPI, level interrupt, GPX
+	MAX3421E_reset();                                //stop/start the oscillator
+	/* configure power switch   */
+	Vbus_power( OFF);                                      //turn Vbus power off
+	MAXreg_wr( rGPINIEN, bmGPINIEN7); //enable interrupt on GPIN7 (power switch overload flag)
+	Vbus_power( ON);
+	/* configure host operation */
+	MAXreg_wr( rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST | bmSEPIRQ); // set pull-downs, SOF, Host, Separate GPIN IRQ on GPX
+	//MAXreg_wr( rHIEN, bmFRAMEIE|bmCONDETIE|bmBUSEVENTIE );                      // enable SOF, connection detection, bus event IRQs
+	MAXreg_wr( rHIEN, bmCONDETIE);                        //connection detection
+	/* HXFRDNIRQ is checked in Dispatch packet function */
+	MAXreg_wr(rHCTL, bmSAMPLEBUS);        // update the JSTATUS and KSTATUS bits
+	MAX_busprobe();                             //check if anything is connected
+	MAXreg_wr( rHIRQ, bmCONDETIRQ); //clear connection detect interrupt                 
+	MAXreg_wr( rCPUCTL, 0x01);                            //enable interrupt pin
+}
+
+/* MAX3421 state change task and interrupt handler */
+void MAX3421E_Task(void) {
+	if ( IORD_ALTERA_AVALON_PIO_DATA(PIO_USB_IRQ_BASE) == 0) {
+		printf("MAX interrupt\n\r");
+		MaxIntHandler();
+	}
+	if ( IORD_ALTERA_AVALON_PIO_DATA(PIO_USB_GPX_BASE) == 1) {
+		printf("GPX interrupt\n\r");
+		MaxGpxHandler();
+	}
+}
+
+void MaxIntHandler(void) {
+	BYTE HIRQ;
+	BYTE HIRQ_sendback = 0x00;
+	HIRQ = MAXreg_rd( rHIRQ);                  //determine interrupt source
+	printf("IRQ: %x\n", HIRQ);
+	if (HIRQ & bmFRAMEIRQ) {                   //->1ms SOF interrupt handler
+		HIRQ_sendback |= bmFRAMEIRQ;
+	}                   //end FRAMEIRQ handling
+
+	if (HIRQ & bmCONDETIRQ) {
+		MAX_busprobe();
+		HIRQ_sendback |= bmCONDETIRQ;      //set sendback to 1 to clear register
+	}
+	if (HIRQ & bmSNDBAVIRQ) //if the send buffer is clear (previous transfer completed without issue)
+	{
+		MAXreg_wr(rSNDBC, 0x00);//clear the send buffer (not really necessary, but clears interrupt)
+	}
+	if (HIRQ & bmBUSEVENTIRQ) {           //bus event is either reset or suspend
+		usb_task_state++;                       //advance USB task state machine
+		HIRQ_sendback |= bmBUSEVENTIRQ;
+	}
+	/* End HIRQ interrupts handling, clear serviced IRQs    */
+	MAXreg_wr( rHIRQ, HIRQ_sendback); //write '1' to CONDETIRQ to ack bus state change
+}
+
+void MaxGpxHandler(void) {
+	BYTE GPINIRQ;
+	GPINIRQ = MAXreg_rd( rGPINIRQ);            //read both IRQ registers
+}
diff --git a/lab6/software/usb_kb/usb_kb/MAX3421E.h b/lab6/software/usb_kb/usb_kb/MAX3421E.h
new file mode 100644
index 0000000..2944a6f
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/MAX3421E.h
@@ -0,0 +1,246 @@
+/* MAX3421E support header												*/
+/* Register names and bit masks for MAX3421 in host mode				*/
+/* Function prototypes in MAX3421E.c									*/
+#ifndef _MAX3421E_H_
+#define _MAX3421E_H_
+
+/* SPI interface definitions	*/
+/* SSPSTAT REGISTER */
+
+// Master SPI mode only
+#define   SMPEND        0x80           // Input data sample at end of data out             
+#define   SMPMID        0x00           // Input data sample at middle of data out
+
+#define   MODE_00       0              // Setting for SPI bus Mode 0,0
+//CKE           0x40                   // SSPSTAT register 
+//CKP           0x00                   // SSPCON1 register 
+
+#define   MODE_01       1              // Setting for SPI bus Mode 0,1
+//CKE           0x00                   // SSPSTAT register 
+//CKP           0x00                   // SSPCON1 register
+
+#define   MODE_10       2              // Setting for SPI bus Mode 1,0
+//CKE           0x40                   // SSPSTAT register
+//CKP           0x10                   // SSPCON1 register
+
+#define   MODE_11       3              // Setting for SPI bus Mode 1,1
+//CKE           0x00                   // SSPSTAT register
+//CKP           0x10                   // SSPCON1 register
+
+/* SSPCON1 REGISTER */
+#define   SSPENB        0x20           // Enable serial port and configures SCK, SDO, SDI
+
+#define   SPI_FOSC_4    0              // SPI Master mode, clock = Fosc/4
+#define   SPI_FOSC_16   1              // SPI Master mode, clock = Fosc/16
+#define   SPI_FOSC_64   2              // SPI Master mode, clock = Fosc/64
+#define   SPI_FOSC_TMR2 3              // SPI Master mode, clock = TMR2 output/2
+#define   SLV_SSON      4              // SPI Slave mode, /SS pin control enabled
+#define   SLV_SSOFF     5              // SPI Slave mode, /SS pin control disabled
+
+/* MAX3421E command byte format: rrrrr0wa where 'r' is register number	*/
+//
+// MAX3421E Registers in HOST mode. 
+//
+#define rRCVFIFO	0x08	//1<<3
+#define rSNDFIFO	0x10	//2<<3
+#define rSUDFIFO	0x20	//4<<3
+#define rRCVBC		0x30	//6<<3
+#define rSNDBC		0x38	//7<<3
+
+#define rUSBIRQ		0x68	//13<<3
+/* USBIRQ Bits	*/
+#define bmVBUSIRQ   0x40	//b6
+#define bmNOVBUSIRQ 0x20	//b5
+#define bmOSCOKIRQ  0x01	//b0
+
+#define	rUSBIEN		0x70	//14<<3
+/* USBIEN Bits	*/
+#define bmVBUSIE    0x40	//b6
+#define bmNOVBUSIE  0x20	//b5
+#define bmOSCOKIE   0x01	//b0
+
+#define rUSBCTL 	0x78	//15<<3
+/* USBCTL Bits	*/
+#define bmCHIPRES   0x20	//b5
+#define bmPWRDOWN   0x10	//b4
+
+#define rCPUCTL		0x80	//16<<3
+/* CPUCTL Bits	*/
+#define bmPUSLEWID1	0x80	//b7
+#define bmPULSEWID0 0x40	//b6
+#define bmIE        0x01	//b0
+
+#define rPINCTL 	0x88	//17<<3
+/* PINCTL Bits	*/
+#define bmFDUPSPI   0x10	//b4
+#define bmINTLEVEL  0x08	//b3
+#define bmPOSINT    0x04	//b2
+#define bmGPXB      0x02	//b1
+#define	bmGPXA      0x01	//b0
+// GPX pin selections
+#define GPX_OPERATE	0x00
+#define GPX_VBDET	0x01
+#define GPX_BUSACT	0x02
+#define GPX_SOF		0x03
+
+#define rREVISION 	0x90	//18<<3
+
+#define rIOPINS1 	0xa0	//20<<3
+
+/* IOPINS1 Bits	*/
+#define bmGPOUT0    0x01
+#define bmGPOUT1    0x02
+#define bmGPOUT2    0x04
+#define bmGPOUT3    0x08
+#define bmGPIN0     0x10
+#define bmGPIN1     0x20
+#define bmGPIN2     0x40
+#define bmGPIN3     0x80
+
+#define rIOPINS2 	0xa8	//21<<3
+/* IOPINS2 Bits	*/
+#define bmGPOUT4    0x01
+#define bmGPOUT5    0x02
+#define bmGPOUT6    0x04
+#define bmGPOUT7    0x08
+#define bmGPIN4     0x10
+#define bmGPIN5     0x20
+#define bmGPIN6     0x40
+#define bmGPIN7     0x80
+
+#define rGPINIRQ	0xb0	//22<<3
+/* GPINIRQ Bits */
+#define bmGPINIRQ0 0x01
+#define bmGPINIRQ1 0x02
+#define bmGPINIRQ2 0x04
+#define bmGPINIRQ3 0x08
+#define bmGPINIRQ4 0x10
+#define bmGPINIRQ5 0x20
+#define bmGPINIRQ6 0x40
+#define bmGPINIRQ7 0x80
+
+#define rGPINIEN	0xb8	//23<<3
+/* GPINIEN Bits */
+#define bmGPINIEN0 0x01
+#define bmGPINIEN1 0x02
+#define bmGPINIEN2 0x04
+#define bmGPINIEN3 0x08
+#define bmGPINIEN4 0x10
+#define bmGPINIEN5 0x20
+#define bmGPINIEN6 0x40
+#define bmGPINIEN7 0x80
+
+#define rGPINPOL 	0xc0	//24<<3
+/* GPINPOL Bits */
+#define bmGPINPOL0 0x01
+#define bmGPINPOL1 0x02
+#define bmGPINPOL2 0x04
+#define bmGPINPOL3 0x08
+#define bmGPINPOL4 0x10
+#define bmGPINPOL5 0x20
+#define bmGPINPOL6 0x40
+#define bmGPINPOL7 0x80
+
+#define rHIRQ		0xc8	//25<<3
+/* HIRQ Bits */
+#define bmBUSEVENTIRQ   0x01   // indicates BUS Reset Done or BUS Resume     
+#define bmRWUIRQ        0x02
+#define bmRCVDAVIRQ     0x04
+#define bmSNDBAVIRQ     0x08
+#define bmSUSDNIRQ      0x10
+#define bmCONDETIRQ     0x20
+#define bmFRAMEIRQ      0x40
+#define bmHXFRDNIRQ     0x80
+
+#define rHIEN 		0xd0	//26<<3
+/* HIEN Bits */
+#define bmBUSEVENTIE    0x01
+#define bmRWUIE         0x02
+#define bmRCVDAVIE      0x04
+#define bmSNDBAVIE      0x08
+#define bmSUSDNIE       0x10
+#define bmCONDETIE      0x20
+#define bmFRAMEIE       0x40
+#define bmHXFRDNIE      0x80
+
+#define rMODE		0xd8	//27<<3
+/* MODE Bits */
+#define bmHOST          0x01
+#define bmLOWSPEED      0x02
+#define bmHUBPRE        0x04
+#define bmSOFKAENAB     0x08
+#define bmSEPIRQ        0x10
+#define bmDELAYISO      0x20
+#define bmDMPULLDN      0x40
+#define bmDPPULLDN      0x80
+
+#define rPERADDR	0xe0	//28<<3
+
+#define rHCTL		0xe8	//29<<3
+/* HCTL Bits */
+#define bmBUSRST        0x01
+#define bmFRMRST        0x02
+#define bmSAMPLEBUS     0x04
+#define bmSIGRSM        0x08
+#define bmRCVTOG0       0x10
+#define bmRCVTOG1       0x20
+#define bmSNDTOG0       0x40
+#define bmSNDTOG1       0x80
+
+#define rHXFR		0xf0	//30<<3
+/* Host transfer token values for writing the HXFR register (R30)	*/
+/* OR this bit field with the endpoint number in bits 3:0				*/
+#define tokSETUP  0x10  // HS=0, ISO=0, OUTNIN=0, SETUP=1
+#define tokIN     0x00  // HS=0, ISO=0, OUTNIN=0, SETUP=0
+#define tokOUT    0x20  // HS=0, ISO=0, OUTNIN=1, SETUP=0
+#define tokINHS   0x80  // HS=1, ISO=0, OUTNIN=0, SETUP=0
+#define tokOUTHS  0xA0  // HS=1, ISO=0, OUTNIN=1, SETUP=0 
+#define tokISOIN  0x40  // HS=0, ISO=1, OUTNIN=0, SETUP=0
+#define tokISOOUT 0x60  // HS=0, ISO=1, OUTNIN=1, SETUP=0
+
+#define rHRSL		0xf8	//31<<3
+/* HRSL Bits */
+#define bmRCVTOGRD	0x10
+#define bmSNDTOGRD	0x20
+#define bmKSTATUS	0x40
+#define bmJSTATUS	0x80
+#define bmSE0		0x00	//SE0 - disconnect state
+#define bmSE1		0xc0	//SE1 - illegal state		
+/* Host error result codes, the 4 LSB's in the HRSL register */
+#define hrSUCCESS   0x00
+#define hrBUSY      0x01
+#define hrBADREQ    0x02
+#define hrUNDEF     0x03
+#define hrNAK       0x04
+#define hrSTALL     0x05
+#define hrTOGERR    0x06
+#define hrWRONGPID  0x07
+#define hrBADBC     0x08
+#define hrPIDERR    0x09
+#define hrPKTERR    0x0A
+#define hrCRCERR    0x0B
+#define hrKERR      0x0C
+#define hrJERR      0x0D
+#define hrTIMEOUT   0x0E
+#define hrBABBLE    0x0F
+
+#define MODE_FS_HOST	(bmDPPULLDN|bmDMPULLDN|bmHOST|bmSOFKAENAB)
+#define MODE_LS_HOST	(bmDPPULLDN|bmDMPULLDN|bmHOST|bmLOWSPEED|bmSOFKAENAB)
+
+/* MAX3421E.c function prototypes	*/
+void SPI_init(BYTE sync_mode, BYTE bus_mode, BYTE smp_phase);
+BYTE SPI_wr(BYTE data);
+void MAXreg_wr(BYTE reg, BYTE val);
+BYTE* MAXbytes_wr(BYTE reg, BYTE nbytes, BYTE * data);
+BYTE MAXreg_rd(BYTE reg);
+BYTE* MAXbytes_rd(BYTE reg, BYTE nbytes, BYTE *data);
+void MAX3421E_reset(void);
+BOOL Vbus_power(BOOL action);
+void MAX3421E_init(void);
+void MAX_busprobe(void);
+void MAX3421E_Task(void);
+void MaxIntHandler(void);
+void MaxGpxHandler(void);
+
+#endif //_MAX3421E_H_
+
diff --git a/lab6/software/usb_kb/usb_kb/README b/lab6/software/usb_kb/usb_kb/README
new file mode 100644
index 0000000..b66c227
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/README
@@ -0,0 +1,12 @@
+This is a project directory of Lightweight USB host for Microchip PIC18 and Maxim MAX3421E USB Host controller.
+This is a migration from FreeRTOS implementation, which I decided to stop developing because the end product will not fit into PIC18.
+Therefore, you will find fragments of strange code every now and then. 
+
+The code is compiled using Microchip C18 compiler in MPLAB. MPLAB project file is provided but not guaranteed to work on your system
+due to absolute path issue. You can manually edit the .mcp file or make your own. The project uses standard linker script and headers.
+
+In addition, logic analyzer trace is provided in LPF file. Too see the trace you will need to download Logicport software from Intronix,
+http://www.pctestinstruments.com/downloads.htm
+
+For hardware implementation information go to http://www.circuitsathome.com
+
diff --git a/lab6/software/usb_kb/usb_kb/USB.h b/lab6/software/usb_kb/usb_kb/USB.h
new file mode 100644
index 0000000..3e38a36
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/USB.h
@@ -0,0 +1,277 @@
+/* USB task support header */
+
+#ifndef _USB_h_
+#define _USB_h_
+
+// *****************************************************************************
+// Section: State Machine Constants
+// *****************************************************************************
+
+/* States are defined by 4 high bits
+ Substates are defined by 4 low bits */
+
+#define USB_STATE_MASK                                      0xf0  //
+#define USB_SUBSTATE_MASK                                   0x0f  //
+
+#define SUBSUBSTATE_MASK                                0x000F  //
+
+#define NEXT_STATE                                      0x0100  //
+#define NEXT_SUBSTATE                                   0x0010  //
+#define NEXT_SUBSUBSTATE                                0x0001  //
+
+#define SUBSUBSTATE_ERROR                               0x000F  //
+
+#define NO_STATE                                        0xFFFF  //
+
+/*
+ *******************************************************************************
+ DETACHED state machine values
+
+ This state machine handles the condition when no device is attached.
+ */
+
+#define USB_STATE_DETACHED									0x00
+#define USB_DETACHED_SUBSTATE_INITIALIZE					0x01
+#define USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE				0x03
+#define	USB_DETACHED_SUBSTATE_ILLEGAL						0x04
+
+/*
+ *******************************************************************************
+ ATTACHED state machine values
+
+ This state machine gets the device descriptor of the remote device.  We get the
+ size of the device descriptor, and use that size to get the entire device
+ descriptor.  Then we check the VID and PID and make sure they appear in the TPL.
+ */
+
+#define USB_STATE_ATTACHED										0x10
+#define USB_ATTACHED_SUBSTATE_SETTLE                            0x11
+#define USB_ATTACHED_SUBSTATE_RESET_DEVICE						0x12
+#define USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE				0x13
+#define USB_ATTACHED_SUBSTATE_WAIT_SOF                          0x14
+#define USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE        0x15
+//#define USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR				0x16
+//#define USB_ATTACHED_SUBSTATE_VALIDATE_VID_PID					0x17
+//#define USB_ATTACHED_SUBSTATE_VALIDATE_CLSP                     0x18
+
+/*
+ *******************************************************************************
+ ADDRESSING state machine values
+
+ This state machine sets the address of the remote device.
+ */
+
+#define USB_STATE_ADDRESSING							0x20
+/*
+ *******************************************************************************
+ CONFIGURING state machine values
+
+ This state machine sets the configuration of the remote device, and sets up
+ internal variables to support the device.
+ */
+#define USB_STATE_CONFIGURING							0x30
+
+/*
+ *******************************************************************************
+ RUNNING state machine values
+
+ */
+
+#define USB_STATE_RUNNING									0x40
+//#define RUNNING_SUBSTATE_NORMAL_RUN							0x0000  //
+//#define RUNNING_SUBSTATE_SUSPEND_AND_RESUME					0x0010  //
+//#define RUNNING_SUBSUBSTATE_SUSPEND							0x0000  //
+//#define RUNNING_SUBSUBSTATE_RESUME							0x0001  //
+//#define RUNNING_SUBSUBSTATE_RESUME_WAIT						0x0002  //
+//#define RUNNING_SUBSUBSTATE_RESUME_RECOVERY					0x0003  //
+//#define RUNNING_SUBSUBSTATE_RESUME_RECOVERY_WAIT			0x0004  //
+//#define RUNNING_SUBSUBSTATE_RESUME_COMPLETE					0x0005  //
+
+/*
+ *******************************************************************************
+ HOLDING state machine values
+
+ */
+
+#define STATE_HOLDING                                   0x50  //
+
+#define HOLDING_SUBSTATE_HOLD_INIT                              0x0000  //
+#define HOLDING_SUBSTATE_HOLD                                   0x0001  //
+
+/* Error state machine state. Non-recoverable */
+
+#define USB_STATE_ERROR							0xff								
+
+// *****************************************************************************
+// Section: Token State Machine Constants
+// *****************************************************************************
+
+#define TSTATE_MASK                             0x00F0  //
+#define TSUBSTATE_MASK                          0x000F  //
+
+#define TSUBSTATE_ERROR                         0x000F  //
+
+#define TSTATE_IDLE                             0x0000  //
+
+#define TSTATE_CONTROL_NO_DATA                  0x0010  //
+#define TSUBSTATE_CONTROL_NO_DATA_SETUP         0x0000  //
+#define TSUBSTATE_CONTROL_NO_DATA_ACK           0x0001  //
+#define TSUBSTATE_CONTROL_NO_DATA_COMPLETE      0x0002  //
+
+#define TSTATE_CONTROL_READ                     0x0020  //
+#define TSUBSTATE_CONTROL_READ_SETUP            0x0000  //
+#define TSUBSTATE_CONTROL_READ_DATA             0x0001  //
+#define TSUBSTATE_CONTROL_READ_ACK              0x0002  //
+#define TSUBSTATE_CONTROL_READ_COMPLETE         0x0003  //
+
+#define TSTATE_CONTROL_WRITE                    0x0030  //
+#define TSUBSTATE_CONTROL_WRITE_SETUP           0x0000  //
+#define TSUBSTATE_CONTROL_WRITE_DATA            0x0001  //
+#define TSUBSTATE_CONTROL_WRITE_ACK             0x0002  //
+#define TSUBSTATE_CONTROL_WRITE_COMPLETE        0x0003  //
+
+#define TSTATE_INTERRUPT_READ                   0x0040  //
+#define TSUBSTATE_INTERRUPT_READ_DATA           0x0000  //
+#define TSUBSTATE_INTERRUPT_READ_COMPLETE       0x0001  //
+
+#define TSTATE_INTERRUPT_WRITE                  0x0050  //
+#define TSUBSTATE_INTERRUPT_WRITE_DATA          0x0000  //
+#define TSUBSTATE_INTERRUPT_WRITE_COMPLETE      0x0001  //
+
+#define TSTATE_ISOCHRONOUS_READ                 0x0060  //
+#define TSUBSTATE_ISOCHRONOUS_READ_DATA         0x0000  //
+#define TSUBSTATE_ISOCHRONOUS_READ_COMPLETE     0x0001  //
+
+#define TSTATE_ISOCHRONOUS_WRITE                0x0070  //
+#define TSUBSTATE_ISOCHRONOUS_WRITE_DATA        0x0000  //
+#define TSUBSTATE_ISOCHRONOUS_WRITE_COMPLETE    0x0001  //
+
+#define TSTATE_BULK_READ                        0x0080  //
+#define TSUBSTATE_BULK_READ_DATA                0x0000  //
+#define TSUBSTATE_BULK_READ_COMPLETE            0x0001  //
+
+#define TSTATE_BULK_WRITE                       0x0090  //
+#define TSUBSTATE_BULK_WRITE_DATA               0x0000  //
+#define TSUBSTATE_BULK_WRITE_COMPLETE           0x0001  //
+
+// ************************
+// Standard USB Requests
+#define SR_GET_STATUS			0x00	// Get Status
+#define SR_CLEAR_FEATURE		0x01	// Clear Feature
+#define SR_RESERVED				0x02	// Reserved
+#define SR_SET_FEATURE			0x03	// Set Feature
+#define SR_SET_ADDRESS			0x05	// Set Address
+#define SR_GET_DESCRIPTOR		0x06	// Get Descriptor
+#define SR_SET_DESCRIPTOR		0x07	// Set Descriptor
+#define SR_GET_CONFIGURATION	0x08	// Get Configuration
+#define SR_SET_CONFIGURATION	0x09	// Set Configuration
+#define SR_GET_INTERFACE		0x0a	// Get Interface
+#define SR_SET_INTERFACE		0x0b	// Set Interface
+
+// Get Descriptor codes	
+#define GD_DEVICE			0x01	// Get device descriptor: Device
+#define GD_CONFIGURATION	0x02	// Get device descriptor: Configuration
+#define GD_STRING			0x03	// Get device descriptor: String
+#define GD_HID	            0x21	// Get descriptor: HID
+#define GD_REPORT	        0x22	// Get descriptor: Report
+
+// HID bRequest values
+#define GET_REPORT		1
+#define GET_IDLE		2
+#define GET_PROTOCOL    3
+#define SET_REPORT		9
+#define SET_IDLE		0x0A
+#define SET_PROTOCOL    0x0B
+#define INPUT_REPORT    1
+
+////******************************************************************************
+////******************************************************************************
+//// Section: Macros
+////
+//// These macros are all internal to the host layer.
+////******************************************************************************
+////******************************************************************************
+//
+//#define _USB_InitErrorCounters()        { numCommandTries   = USB_NUM_COMMAND_TRIES; }
+//#define _USB_SetDATA01(x)               { pCurrentEndpoint->status.bfNextDATA01 = x; }
+//#define _USB_SetErrorCode(x)            { usbDeviceInfo.errorCode = x; }
+//#define _USB_SetHoldState()             { usbHostState = STATE_HOLDING; }
+//#define _USB_SetNextState()             { usbHostState = (usbHostState & STATE_MASK) + NEXT_STATE; }
+//#define _host_tasks_SetNextSubState()   { host_tasks_state =( host_tasks_state & (STATE_MASK | SUBSTATE_MASK)) + NEXT_SUBSTATE; }
+//#define _USB_SetNextSubSubState()       { usbHostState =  usbHostState + NEXT_SUBSUBSTATE; }
+//#define _USB_SetNextTransferState()     { pCurrentEndpoint->transferState ++; }
+//#define _USB_SetPreviousSubSubState()   { usbHostState =  usbHostState - NEXT_SUBSUBSTATE; }
+//#define _USB_SetTransferErrorState(x)   { x->transferState = (x->transferState & TSTATE_MASK) | TSUBSTATE_ERROR; }
+//#define freez(x)                        { free(x); x = NULL; }
+
+/* data structures */
+
+// *****************************************************************************
+/* USB Mass Storage Device Information
+
+ This structure is used to hold all the information about an attached Mass Storage device.
+ */
+typedef struct _USB_MSD_DEVICE_INFO {
+	BYTE blockData[31];          // Data buffer for device communication.
+	BYTE deviceAddress;          // Address of the device on the bus.
+	BYTE errorCode;              // Error code of last error.
+	BYTE state;                  // State machine state of the device.
+	BYTE returnState;     // State to return to after performing error handling.
+	union {
+		struct {
+			BYTE bfDirection :1; // Direction of current transfer (0=OUT, 1=IN).
+			BYTE bfReset :1;   // Flag indicating to perform Mass Storage Reset.
+			BYTE bfClearDataIN :1;  // Flag indicating to clear the IN endpoint.
+			BYTE bfClearDataOUT :1; // Flag indicating to clear the OUT endpoint.
+		};
+		BYTE val;
+	} flags;
+	BYTE maxLUN;               // The maximum Logical Unit Number of the device.
+	BYTE interface;              // Interface number we are using.
+	BYTE epin_idx;            // Bulk IN endpoint index in devinfo.epinfo_ptr[].
+	BYTE epout_idx;          // Bulk OUT endpoint index in devinfo.epinfo_ptr[].
+	BYTE endpointDATA;           // Endpoint to use for the current transfer.
+	BYTE *userData;              // Pointer to the user's data buffer.
+	DWORD userDataLength;         // Length of the user's data buffer.
+	DWORD bytesTransferred; // Number of bytes transferred to/from the user's data buffer.
+	DWORD dCBWTag;    // The value of the dCBWTag to verify against the dCSWtag.
+	BYTE attemptsCSW;            // Number of attempts to retrieve the CSW.
+} USB_MSD_DEVICE_INFO;
+
+///* class driver event handler	*/
+//typedef BOOL (* rom CLASS_EVENT_HANDLER) ( BYTE address, BYTE event, void *data, DWORD size );
+//
+///* class driver initialization */
+//typedef BOOL (* rom CLASS_INIT)   ( BYTE address, DWORD flags );
+//
+//// *****************************************************************************
+///* Client Driver Table Structure
+//
+// */
+//
+//typedef struct _CLASS_CALLBACK_TABLE
+//{
+//    CLASS_INIT          Initialize;     // Initialization routine
+//    CLASS_EVENT_HANDLER EventHandler;   // Event routine
+//    DWORD                    flags;          // Initialization flags
+//
+//} CLASS_CALLBACK_TABLE;
+
+//* Functions	*/
+//
+//void vUSBtask_init( void );
+//void vUSB_task( void *pvParameters );
+//void prvUSBdata_init( void );
+//char bUSB_Control_Write_ND( BYTE addr, BYTE ep );
+//char bUSB_Control_Read( BYTE addr, BYTE ep );
+//char bUSB_IN_Transfer( BYTE ep, WORD nbytes, BYTE maxpktsize, BYTE * data );
+//char bUSB_Dispatch_Pkt( BYTE token, BYTE ep );
+//BOOL prvMSDInit( BYTE address, DWORD flags );
+//BOOL prvMSDEventHandler( BYTE address, BYTE event, void *data, DWORD size );
+//BOOL prvCDCProbe( BYTE address, DWORD flags );
+//BOOL prvCDCEventHandler( BYTE address, BYTE event, void *data, DWORD size );
+//BOOL prvDummyProbe( BYTE address , DWORD flags );
+//BOOL prvDummyEventHandler( BYTE address, BYTE event, void *data, DWORD size );
+//BYTE flush_Q( xQueueHandle QueueH );
+
+#endif //_USB_h_
diff --git a/lab6/software/usb_kb/usb_kb/project_config.h b/lab6/software/usb_kb/usb_kb/project_config.h
new file mode 100644
index 0000000..c391cb0
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/project_config.h
@@ -0,0 +1,22 @@
+/* Project name project configuration file	*/
+
+#ifndef _project_config_h_
+#define _project_config_h_
+
+#include "../usb_kb/GenericMacros.h"
+#include "../usb_kb/GenericTypeDefs.h"
+#include "../usb_kb/HID.h"
+#include "../usb_kb/MAX3421E.h"
+#include "../usb_kb/transfer.h"
+#include "../usb_kb/usb_ch9.h"
+#include "../usb_kb/USB.h"
+
+/* USB constants */
+/* time in milliseconds */
+#define USB_SETTLE_TIME 					200         //USB settle after reset
+#define USB_XFER_TIMEOUT					5000        //USB transfer timeout
+
+#define USB_NAK_LIMIT 200
+#define USB_RETRY_LIMIT 3
+
+#endif // _project_config_h
diff --git a/lab6/software/usb_kb/usb_kb/transfer.c b/lab6/software/usb_kb/usb_kb/transfer.c
new file mode 100644
index 0000000..600c016
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/transfer.c
@@ -0,0 +1,442 @@
+
+/* USB transfers    */
+#define _transfer_c_
+
+#include "../usb_kb/project_config.h"
+#include "altera_avalon_timer.h"
+#include "sys/alt_alarm.h"
+
+EP_RECORD dev0ep = {{ 0 }};         //Endpoint data structure for uninitialized device during enumeration
+EP_RECORD msd_ep[ 3 ] = {{ 0 }};    //Mass storage bulk-only transport endpoints: 1 control and 2 bulk, IN and OUT
+//ep records for other classes are defined in class-specific modules
+
+/* macros to aid filling in TPL */
+#define INIT_VID_PID(v,p) 0x##p##v
+#define INIT_CL_SC_P(c,s,p) 0x##00##p##s##c
+
+//const rom USB_TPL_ENTRY TplTable[ USB_NUMTARGETS + 1 ] = {
+//// VID & PID or Client
+//// Class, Subclass & Protocol Config Numep Eprecord Driver
+//{ INIT_VID_PID( 0000, 0000 ), 0, 1, &dev0ep, 0, "Uninitialized" },
+//{ INIT_VID_PID( 0781, 5406 ), 0, 3, msd_ep, MSD_DRIVER, "Mass storage"  },	    //Sandisk U3 Cruzer Micro
+////{ INIT_VID_PID( 0CF2, 6220 ), 0, 0 },	                                        //ENE UB6220
+//{ INIT_CL_SC_P( 03, 01, 02 ), 0, 3, hid_ep, HIDM_DRIVER, "HID Mouse with Boot protocol" },	                //
+//{ INIT_VID_PID( aaaa, 5555 ), 0, 1, NULL, 0, NULL },	                //
+//{ INIT_CL_SC_P( 08, 06, 50 ), 0, 3, msd_ep, MSD_DRIVER, "Mass storage" }	    //Mass storage bulk only class
+//};
+
+/* control transfers function pointers */
+const CTRL_XFER ctrl_xfers[ 2 ] = {
+    XferCtrlND,
+    XferCtrlData
+};
+
+/* device table. Filled during enumeration              */
+/* index corresponds to device address                  */
+/* each entry contains pointer to endpoint structure    */
+/* and device class to use in various places            */
+DEV_RECORD devtable[ USB_NUMDEVICES + 1 ];
+
+/* Client Driver Function Pointer Table	*/
+CLASS_CALLBACK_TABLE ClientDriverTable[ USB_NUMCLASSES ] = {
+    {
+        MSDProbe,				//Mass storage class device init
+        MSDEventHandler,
+        0
+    },
+    {
+    	HIDMProbe,				//HID class device init
+    	HIDMEventHandler,
+    	0
+    },
+    {
+        HIDKProbe,
+        HIDKEventHandler,
+        0
+    },
+    {
+    	DummyProbe,
+    	DummyEventHandler,
+    	0
+    }
+};
+/* Control transfer stages function pointer table */
+
+
+/* USB state machine related variables */
+
+BYTE usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE;
+BYTE usb_error;
+BYTE last_usb_task_state = 0;
+
+/* Control transfer. Sets address, endpoint, fills control packet with necessary data, dispatches control packet, and initiates bulk IN transfer,   */
+/* depending on request. Actual requests are defined as macros                                                                                      */
+/* return codes:                */
+/* 00       =   success         */
+/* 01-0f    =   non-zero HRSLT  */
+BYTE XferCtrlReq( BYTE addr, BYTE ep, BYTE bmReqType, BYTE bRequest, BYTE wValLo, BYTE wValHi, WORD wInd, WORD nbytes, BYTE* dataptr )
+{
+ BOOL direction = FALSE;        //request direction, IN or OUT
+ BYTE datastage = 1; //request data stage present or absent
+ BYTE rcode;
+ SETUP_PKT setup_pkt;
+    if( dataptr == NULL ) {
+        datastage = 0;
+    }
+    MAXreg_wr( rPERADDR, addr );                    //set peripheral address
+    /* fill in setup packet */
+    if( bmReqType & 0x80 ) {
+        direction = TRUE;                   		//determine request direction
+    }
+    /* fill in setup packet */
+    setup_pkt.ReqType_u.bmRequestType = bmReqType;
+    setup_pkt.bRequest = bRequest;
+    setup_pkt.wVal_u.wValueLo = wValLo;
+    setup_pkt.wVal_u.wValueHi = wValHi;
+    setup_pkt.wIndex = wInd;
+    setup_pkt.wLength = nbytes;
+    MAXbytes_wr( rSUDFIFO, 8, (BYTE *)&setup_pkt );     //transfer to setup packet FIFO
+    rcode = XferDispatchPkt( tokSETUP, ep );            //dispatch packet
+    if( rcode ) {                                       //return HRSLT if not zero
+        return( rcode );
+    }
+    rcode = ctrl_xfers[ datastage ]( addr, ep, nbytes, dataptr, direction );    //call data stage or no data stage transfer
+    return( rcode );
+}
+/* Control transfer with data stage */
+BYTE XferCtrlData( BYTE addr, BYTE ep, WORD nbytes, BYTE* dataptr, BOOL direction )
+{
+  BYTE rcode;
+
+    //MAXreg_wr( rHCTL, bmRCVTOG1 );       //set toggle to DATA1
+    if( direction ) {   //IN transfer
+        devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1;
+        rcode = XferInTransfer( addr, ep, nbytes, dataptr, devtable[ addr ].epinfo[ ep ].MaxPktSize );
+        if( rcode ) {
+        return( rcode );
+        }
+        rcode = XferDispatchPkt( tokOUTHS, ep );
+        return( rcode );
+    }
+    else {              //OUT not implemented
+        return( 0xff );
+    }
+}
+/* Control transfer with status stage and no data stage */
+BYTE XferCtrlND( BYTE addr, BYTE ep, WORD nbytes, BYTE* dataptr, BOOL direction )
+{
+  BYTE rcode;
+    if( direction ) { //GET
+        rcode = XferDispatchPkt( tokOUTHS, ep );
+    }
+    else {
+        rcode = XferDispatchPkt( tokINHS, ep );
+    }
+    return( rcode );
+}
+/* Dispatch a packet. Assumes peripheral address is set and, if necessary, sudFIFO-sendFIFO loaded. */
+/* Result code: 0 success, nonzero = error condition                                                */
+/* If NAK, tries to re-send up to USB_NAK_LIMIT times                                               */
+/* If bus timeout, re-sends up to USB_RETRY_LIMIT times                                             */
+/* return codes 0x00-0x0f are HRSLT( 0x00 being success ), 0xff means timeout                       */
+BYTE XferDispatchPkt( BYTE token, BYTE ep )
+{
+ DWORD timeout = (alt_nticks()*1000)/alt_ticks_per_second() + USB_XFER_TIMEOUT;
+ BYTE tmpdata;
+ BYTE rcode;
+ char retry_count = 0;
+ BYTE nak_count = 0;
+
+    while( 1 ) {
+        MAXreg_wr( rHXFR, ( token|ep ));            //launch the transfer
+        rcode = 0xff;
+        while( (alt_nticks()*1000)/alt_ticks_per_second() < timeout ) {
+            tmpdata = MAXreg_rd( rHIRQ );
+            if( tmpdata & bmHXFRDNIRQ ) {
+                MAXreg_wr( rHIRQ, bmHXFRDNIRQ );    //clear the interrupt
+                rcode = 0x00;
+                break;
+            }
+        }
+        if( rcode != 0x00 ) {               //exit if timeout
+            return( rcode );
+        }
+        rcode = ( MAXreg_rd( rHRSL ) & 0x0f );
+        if( rcode == hrNAK ) {
+            nak_count++;
+            if( nak_count == USB_NAK_LIMIT ) {
+                break;
+            }
+            else {
+                continue;
+            }
+        }
+        if( rcode == hrTIMEOUT ) {
+            retry_count++;
+            if( retry_count == USB_RETRY_LIMIT ) {
+                break;
+            }
+            else {
+                continue;
+            }
+        }
+        else break;
+    }//while( 1 )
+    return( rcode );
+}
+/* IN transfer to arbitrary endpoint. Assumes PERADDR is set. Handles multiple packets if necessary. Transfers 'nbytes' bytes.
+    Keep sending INs and writes data to memory area pointed by 'data' */
+/* rcode 0 if no errors. rcode 01-0f is relayed from prvXferDispatchPkt(). Rcode f0 means RCVDAVIRQ error,
+            fe USB xfer timeout */
+BYTE XferInTransfer( BYTE addr/* not sure if it's necessary */, BYTE ep, WORD nbytes, BYTE* data, BYTE maxpktsize )
+{
+ BYTE rcode;
+ BYTE i;
+ BYTE tmpbyte;
+ BYTE pktsize;
+ WORD xfrlen = 0;
+    MAXreg_wr( rHCTL, devtable[ addr ].epinfo[ ep ].rcvToggle );    //set toggle value
+    while( 1 ) { // use a 'return' to exit this loop
+        rcode = XferDispatchPkt( tokIN, ep );           //IN packet to EP-'endpoint'. Function takes care of NAKS.
+        if( rcode ) {
+            return( rcode );                            //should be 0, indicating ACK. Else return error code.
+        }
+        /* check for RCVDAVIRQ and generate error if not present */
+        /* the only case when absence of RCVDAVIRQ makes sense is when toggle error occurred. Need to add handling for that */
+        if(( MAXreg_rd( rHIRQ ) & bmRCVDAVIRQ ) == 0 ) {
+            return ( 0xf0 );                            //receive error
+        }
+        pktsize = MAXreg_rd( rRCVBC );                  //number of received bytes
+        //printf ("pktsize: %d\n", pktsize);
+        data = MAXbytes_rd( rRCVFIFO, pktsize, data );
+        MAXreg_wr( rHIRQ, bmRCVDAVIRQ );                // Clear the IRQ & free the buffer
+        xfrlen += pktsize;                              // add this packet's byte count to total transfer length
+        /* The transfer is complete under two conditions:           */
+        /* 1. The device sent a short packet (L.T. maxPacketSize)   */
+        /* 2. 'nbytes' have been transferred.                       */
+        if (( pktsize < maxpktsize ) || (xfrlen >= nbytes )) {    // have we transferred 'nbytes' bytes?
+            if( MAXreg_rd( rHRSL ) & bmRCVTOGRD ) {                 //save toggle value
+                devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG1;
+            }
+            else {
+                devtable[ addr ].epinfo[ ep ].rcvToggle = bmRCVTOG0;
+            }
+            return( 0 );
+        }
+  }//while( 1 )
+}
+/* initialization of USB data structures */
+void USB_init( void )
+{
+  BYTE i;
+    for( i = 0; i < ( USB_NUMDEVICES + 1 ); i++ ) {
+        devtable[ i ].epinfo = NULL;       //clear device table
+        devtable[ i ].devclass = 0;
+    }
+    devtable[ 0 ].epinfo = &dev0ep;  //set single ep for uninitialized device
+    dev0ep.MaxPktSize = 0;
+    dev0ep.sndToggle = bmSNDTOG0;   //set DATA0/1 toggles to 0
+    dev0ep.rcvToggle = bmRCVTOG0;
+}
+/* USB state machine. Connect/disconnect, enumeration, initialization   */
+/* error codes: 01-0f HRSLT        */
+/* ff - unsupported device         */
+/* fe - no address available       */
+/* fd - no client driver available */
+void USB_Task( void )
+{
+ static DWORD usb_delay = 0;
+ static BYTE tmp_addr;
+ USB_DEVICE_DESCRIPTOR buf;
+
+ BYTE rcode, tmpdata;
+ BYTE i;
+
+    switch( usb_task_state & USB_STATE_MASK ) {
+        /* Detached state - when nothing is connected to ( or just disconnected from) USB bus   */
+        case( USB_STATE_DETACHED ):
+            switch( usb_task_state ) {
+                case( USB_DETACHED_SUBSTATE_INITIALIZE ):
+                    /* cleanup device data structures */
+                    USB_init();
+                    usb_task_state = USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE;
+                    break;
+                case( USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE ):
+                    /* Do nothing */
+                    MAXreg_wr(rHCTL,bmSAMPLEBUS);
+                    break;
+                case( USB_DETACHED_SUBSTATE_ILLEGAL ):
+                    /* don't know what to do yet */
+                    break;
+            }//switch( usb_task_state )
+            break;//( USB_STATE_DETACHED ):
+            /**/
+        case( USB_STATE_ATTACHED ):                     //prepare for enumeration
+            switch( usb_task_state ) {
+                case( USB_STATE_ATTACHED ):
+                    usb_delay = (alt_nticks()*1000)/alt_ticks_per_second() + 200;           //initial settle 200ms
+                    usb_task_state = USB_ATTACHED_SUBSTATE_SETTLE;
+                    break;//case( USB_STATE_ATTACHED )
+                case( USB_ATTACHED_SUBSTATE_SETTLE ):   //waiting for settle timer to expire
+                    if( (alt_nticks()*1000)/alt_ticks_per_second() > usb_delay ) {
+                        usb_task_state = USB_ATTACHED_SUBSTATE_RESET_DEVICE;
+                    }
+                    break;//case( USB_ATTACHED_SUBSTATE_SETTLE )
+                case( USB_ATTACHED_SUBSTATE_RESET_DEVICE ):
+                    MAXreg_wr( rHIRQ, bmBUSEVENTIRQ );                               //clear bus event IRQ
+                    MAXreg_wr( rHCTL, bmBUSRST );                                    //issue bus reset
+                    usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE;
+                    break;//case( USB_ATTACHED_SUBSTATE_RESET_DEVICE )
+                case( USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE ):                  //wait for bus reset and first SOF
+                    if(( MAXreg_rd( rHCTL ) & bmBUSRST ) == 0 ) {
+                        tmpdata = MAXreg_rd( rMODE ) | bmSOFKAENAB;                 //start SOF generation
+                        MAXreg_wr( rMODE, tmpdata );
+                        usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_SOF;
+                    }
+                    break;//case( USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE )
+                case( USB_ATTACHED_SUBSTATE_WAIT_SOF ):
+                    if( MAXreg_rd( rHIRQ ) | bmFRAMEIRQ ) {                     //when first SOF received we can continue
+                        usb_task_state = USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE;
+                    }
+                    break;//case( USB_ATTACHED_SUBSTATE_WAIT_SOF )
+                case( USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE ):   //send request for first 8 bytes of device descriptor
+                    devtable[ 0 ].epinfo->MaxPktSize = 0x0008;             //fill max packet size with minimum allowed
+                	rcode = XferGetDevDescr( 0, 0, 8, (BYTE *)&buf );       //get device descriptor size
+                    if( rcode == 0 ) {
+                        devtable[ 0 ].epinfo->MaxPktSize = buf.bMaxPacketSize0;
+
+                        rcode = XferGetDevDescr( 0, 0, buf.bLength, (BYTE *)&buf );     //get full descriptor
+                        //pull the string descriptor for the product if it exists
+            			//hackish, store this somewhere
+                        if (buf.iManufacturer != 0)
+                		{
+                        	USB_STRING_DESCRIPTOR strDesc;
+                			rcode = XferGetStrDescr( 0, 0, 2, buf.iManufacturer, LANG_EN_US, (BYTE *)&strDesc);
+                			rcode = XferGetStrDescr( 0, 0, strDesc.bLength, buf.iManufacturer, LANG_EN_US, (BYTE *)&strDesc);
+                			printf ("Mfgr string(%i): %s\n", buf.iManufacturer, ConvUTF8ToStr(strDesc.bString, (strDesc.bLength>>1)-1));
+                		}
+                		if (buf.iProduct != 0)
+                		{
+                        	USB_STRING_DESCRIPTOR strDesc;
+                        	rcode = XferGetStrDescr( 0, 0, 2, buf.iProduct, LANG_EN_US, (BYTE *)&strDesc);
+                			rcode = XferGetStrDescr( 0, 0, strDesc.bLength, buf.iProduct, LANG_EN_US, (BYTE *)&strDesc);
+                			printf ("Product string(%i): %s\n", buf.iProduct, ConvUTF8ToStr(strDesc.bString, (strDesc.bLength>>1)-1));
+                		}
+                        usb_task_state = USB_STATE_ADDRESSING;
+
+                    }
+                    else {
+                        usb_error = rcode;
+                        last_usb_task_state = usb_task_state;
+                        usb_task_state = USB_STATE_ERROR;
+                    }
+                    break;//case( USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE ):
+            }//switch( usb_task_state )
+            break;//case ( USB_STATE_ATTACHED )
+        case( USB_STATE_ADDRESSING ):   //give device an address
+            for( i = 1; i < USB_NUMDEVICES; i++ ) {
+                if( devtable[ i ].epinfo == NULL ) {
+                    devtable[ i ].epinfo = devtable[ 0 ].epinfo;        //set correct MaxPktSize
+                    //devtable[ i ].epinfo->MaxPktSize = devtable[ 0 ].epinfo->MaxPktSize;  //copy uninitialized device record to have correct MaxPktSize
+                    rcode = XferSetAddr( 0, 0, i );
+                    if( rcode == 0 ) {
+                        tmp_addr = i;
+                        usb_task_state = USB_STATE_CONFIGURING;
+                    }
+                    else {
+                        usb_error = rcode;          //set address error
+                        last_usb_task_state = usb_task_state;
+                        usb_task_state = USB_STATE_ERROR;
+                    }
+                    break;  //break if address assigned or error occurred during address assignment attempt
+                }
+            }
+            if( usb_task_state == USB_STATE_ADDRESSING ) {
+                usb_error = 0xfe;
+                last_usb_task_state = usb_task_state;
+                usb_task_state = USB_STATE_ERROR;
+            }
+            break;//case ( USB_STATE_ADDRESSING )
+        case( USB_STATE_CONFIGURING ):              //checking for driver
+			//run device class probes until one returns TRUE
+            for( i = 0; i < USB_NUMCLASSES; i++ ) {
+                rcode = ClientDriverTable[ i ].Initialize( tmp_addr, 0 );
+                if( rcode == TRUE ) {
+			        usb_task_state = USB_STATE_RUNNING;
+                    break;
+                }
+            }
+            if( usb_task_state == USB_STATE_CONFIGURING ) {
+                usb_error = 0xfd;
+                last_usb_task_state = usb_task_state;
+                usb_task_state = USB_STATE_ERROR;
+            }
+            break;//( USB_STATE_CONFIGURING )
+        case( USB_STATE_RUNNING ):
+          //vTaskDelay( LED_RATE );
+            break;//( USB_STATE_RUNNING )
+        case( USB_STATE_ERROR ):
+            //vTaskDelay( LED_RATE ); //stay here if error
+            break;//( USB_STATE_ERROR )
+        default:
+            //Should never get here
+            break;
+    }//switch( usb_task_state & STATE_MASK )
+}
+
+//place-holders for MSD (mass-storage device) drivers, we don't have them ported.
+//returns TRUE if device is successfully identified and configured, otherwise returns FALSE
+BOOL MSDProbe( BYTE addr, DWORD flags )
+{
+    return( FALSE );
+}
+
+BOOL MSDEventHandler( BYTE address, BYTE event, void *data, DWORD size )
+{
+
+	return( FALSE );
+
+}
+//CDC (communication device class also not supported)
+BOOL CDCProbe( BYTE address, DWORD flags )
+{
+
+	return( FALSE );
+
+}
+
+BOOL CDCEventHandler( BYTE address, BYTE event, void *data, DWORD size )
+{
+	return( FALSE );
+}
+
+BOOL DummyProbe( BYTE address , DWORD flags )
+{
+	return( FALSE );
+}
+
+BOOL DummyEventHandler( BYTE address, BYTE event, void *data, DWORD size )
+{
+	return( FALSE );
+}
+/* Function to access usb_task_state variable from outside */
+BYTE GetUsbTaskState( void )
+{
+    return( usb_task_state );
+}
+/* Function to access devtable[] from outside */
+DEV_RECORD* GetDevtable( BYTE index )
+{
+    return( &devtable[ index ] );
+}
+
+char* ConvUTF8ToStr(BYTE* utf8, BYTE length)
+{
+	BYTE i;
+	for (i = 0; i < length; i++)
+	{
+		utf8[i] = utf8[2*i];
+	}
+	utf8[length] = 0x00;
+	return (char*)utf8;
+}
diff --git a/lab6/software/usb_kb/usb_kb/transfer.h b/lab6/software/usb_kb/usb_kb/transfer.h
new file mode 100644
index 0000000..0b03f18
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/transfer.h
@@ -0,0 +1,248 @@
+/* USB transfers support header */
+
+#ifndef _transfer_h_
+#define _transfer_h_
+
+/* Targeted peripheral list table */
+#define USB_NUMTARGETS  4       //number of targets in TPL, not counting uninitialized device
+#define USB_NUMDEVICES  8       //number of supported devices
+#define USB_NUMCLASSES  4       //number of device classes in class callback table
+#define UNINIT          0       //uninitialized
+#define HID_K           1       //HID Keyboard boot driver number in DEV_RECORD
+#define HID_M           2       //HID Mouse boot driver number in DEV_RECORD
+#define MSD             3       //Mass storage class driver number in DEV_RECORD
+
+/* Standard Device Requests */
+
+#define USB_REQUEST_GET_STATUS                  0       // Standard Device Request - GET STATUS
+#define USB_REQUEST_CLEAR_FEATURE               1       // Standard Device Request - CLEAR FEATURE
+#define USB_REQUEST_SET_FEATURE                 3       // Standard Device Request - SET FEATURE
+#define USB_REQUEST_SET_ADDRESS                 5       // Standard Device Request - SET ADDRESS
+#define USB_REQUEST_GET_DESCRIPTOR              6       // Standard Device Request - GET DESCRIPTOR
+#define USB_REQUEST_SET_DESCRIPTOR              7       // Standard Device Request - SET DESCRIPTOR
+#define USB_REQUEST_GET_CONFIGURATION           8       // Standard Device Request - GET CONFIGURATION
+#define USB_REQUEST_SET_CONFIGURATION           9       // Standard Device Request - SET CONFIGURATION
+#define USB_REQUEST_GET_INTERFACE               10      // Standard Device Request - GET INTERFACE
+#define USB_REQUEST_SET_INTERFACE               11      // Standard Device Request - SET INTERFACE
+#define USB_REQUEST_SYNCH_FRAME                 12      // Standard Device Request - SYNCH FRAME
+
+#define USB_FEATURE_ENDPOINT_HALT               0       // CLEAR/SET FEATURE - Endpoint Halt
+#define USB_FEATURE_DEVICE_REMOTE_WAKEUP        1       // CLEAR/SET FEATURE - Device remote wake-up
+#define USB_FEATURE_TEST_MODE                   2       // CLEAR/SET FEATURE - Test mode
+
+/* Setup Data Constants */
+
+#define USB_SETUP_HOST_TO_DEVICE                0x00    // Device Request bmRequestType transfer direction - host to device transfer
+#define USB_SETUP_DEVICE_TO_HOST                0x80    // Device Request bmRequestType transfer direction - device to host transfer
+#define USB_SETUP_TYPE_STANDARD                 0x00    // Device Request bmRequestType type - standard
+#define USB_SETUP_TYPE_CLASS                    0x20    // Device Request bmRequestType type - class
+#define USB_SETUP_TYPE_VENDOR                   0x40    // Device Request bmRequestType type - vendor
+#define USB_SETUP_RECIPIENT_DEVICE              0x00    // Device Request bmRequestType recipient - device
+#define USB_SETUP_RECIPIENT_INTERFACE           0x01    // Device Request bmRequestType recipient - interface
+#define USB_SETUP_RECIPIENT_ENDPOINT            0x02    // Device Request bmRequestType recipient - endpoint
+#define USB_SETUP_RECIPIENT_OTHER               0x03    // Device Request bmRequestType recipient - other
+
+/* USB descriptors  */
+
+#define USB_DESCRIPTOR_DEVICE           0x01    // bDescriptorType for a Device Descriptor.
+#define USB_DESCRIPTOR_CONFIGURATION    0x02    // bDescriptorType for a Configuration Descriptor.
+#define USB_DESCRIPTOR_STRING           0x03    // bDescriptorType for a String Descriptor.
+#define USB_DESCRIPTOR_INTERFACE        0x04    // bDescriptorType for an Interface Descriptor.
+#define USB_DESCRIPTOR_ENDPOINT         0x05    // bDescriptorType for an Endpoint Descriptor.
+#define USB_DESCRIPTOR_DEVICE_QUALIFIER 0x06    // bDescriptorType for a Device Qualifier.
+#define USB_DESCRIPTOR_OTHER_SPEED      0x07    // bDescriptorType for a Other Speed Configuration.
+#define USB_DESCRIPTOR_INTERFACE_POWER  0x08    // bDescriptorType for Interface Power.
+#define USB_DESCRIPTOR_OTG              0x09    // bDescriptorType for an OTG Descriptor.
+
+/* OTG SET FEATURE Constants    */
+#define OTG_FEATURE_B_HNP_ENABLE                3       // SET FEATURE OTG - Enable B device to perform HNP
+#define OTG_FEATURE_A_HNP_SUPPORT               4       // SET FEATURE OTG - A device supports HNP
+#define OTG_FEATURE_A_ALT_HNP_SUPPORT           5       // SET FEATURE OTG - Another port on the A device supports HNP
+
+/* USB Endpoint Transfer Types  */
+#define USB_TRANSFER_TYPE_CONTROL               0x00    // Endpoint is a control endpoint.
+#define USB_TRANSFER_TYPE_ISOCHRONOUS           0x01    // Endpoint is an isochronous endpoint.
+#define USB_TRANSFER_TYPE_BULK                  0x02    // Endpoint is a bulk endpoint.
+#define USB_TRANSFER_TYPE_INTERRUPT             0x03    // Endpoint is an interrupt endpoint.
+#define bmUSB_TRANSFER_TYPE                     0x03    // bit mask to separate transfer type from ISO attributes
+
+/* Standard Feature Selectors for CLEAR_FEATURE Requests    */
+#define USB_FEATURE_ENDPOINT_STALL              0       // Endpoint recipient
+#define USB_FEATURE_DEVICE_REMOTE_WAKEUP        1       // Device recipient
+#define USB_FEATURE_TEST_MODE                   2       // Device recipient
+
+/* MSD class requests. Not part of chapter 9    */
+#define USB_MSD_GET_MAX_LUN                 0xFE            // Device Request code to get the maximum LUN.
+#define USB_MSD_RESET                       0xFF            // Device Request code to reset the device.
+
+/* HID constants. Not part of chapter 9 */
+/* Class-Specific Requests */
+#define HID_REQUEST_GET_REPORT      0x01
+#define HID_REQUEST_GET_IDLE        0x02
+#define HID_REQUEST_GET_PROTOCOL    0x03
+#define HID_REQUEST_SET_REPORT      0x09
+#define HID_REQUEST_SET_IDLE        0x0A
+#define HID_REQUEST_SET_PROTOCOL    0x0B
+
+/* Class Descriptor Types */
+#define HID_DESCRIPTOR_HID      0x21
+#define HID_DESCRIPTOR_REPORT   0x22
+#define HID_DESRIPTOR_PHY       0x23
+
+/* Protocol Selection */
+#define BOOT_PROTOCOL   0x00
+#define RPT_PROTOCOL    0x01
+/* HID Interface Class Code */
+#define HID_INTF                    0x03
+/* HID Interface Class SubClass Codes */
+#define BOOT_INTF_SUBCLASS          0x01
+/* HID Interface Class Protocol Codes */
+#define HID_PROTOCOL_NONE           0x00
+#define HID_PROTOCOL_KEYBOARD       0x01
+#define HID_PROTOCOL_MOUSE          0x02
+
+/* USB Setup Packet Structure   */
+typedef struct {
+	union {                          // offset   description
+		BYTE bmRequestType;         //   0      Bit-map of request type
+		struct {
+			BYTE recipient :5;  //          Recipient of the request
+			BYTE type :2;  //          Type of request
+			BYTE direction :1;  //          Direction of data X-fer
+		};
+	} ReqType_u;
+	BYTE bRequest;               //   1      Request
+	union {
+		WORD wValue;             //   2      Depends on bRequest
+		struct {
+			BYTE wValueLo;
+			BYTE wValueHi;
+		};
+	} wVal_u;
+	WORD wIndex;                 //   4      Depends on bRequest
+	WORD wLength;                //   6      Depends on bRequest
+} SETUP_PKT, *PSETUP_PKT;
+
+/* Endpoint information structure               */
+/* bToggle of endpoint 0 initialized to 0xff    */
+/* during enumeration bToggle is set to 00      */
+typedef struct {
+	BYTE epAddr; //copy from endpoint descriptor. Bit 7 indicates direction ( ignored for control endpoints )
+	BYTE Attr;          // Endpoint transfer type.
+	WORD MaxPktSize;    // Maximum packet size.
+	BYTE Interval;      // Polling interval in frames.
+	BYTE sndToggle;     //last toggle value, bitmask for HCTL toggle bits
+	BYTE rcvToggle;     //last toggle value, bitmask for HCTL toggle bits
+	/* not sure if both are necessary */
+} EP_RECORD;
+/* device record structure */
+typedef struct {
+	EP_RECORD* epinfo;      //device endpoint information
+	BYTE devclass;          //device class
+} DEV_RECORD;
+
+//targeted peripheral list element
+//NOTE: this is currently not implemented - typically an embedded host will provide a TPL
+//to enumerate supported devices.
+typedef struct {
+	union {
+		DWORD val;
+		struct {
+			WORD idVendor;
+			WORD idProduct;
+		};
+		struct {
+			BYTE bClass;
+			BYTE bSubClass;
+			BYTE bProtocol;
+		};
+	} dev_u;
+	BYTE bConfig;               //configuration
+	BYTE numep;                 //number of endpoints
+	EP_RECORD* epinfo;          //endpoint information structure
+	BYTE CltDrv;                //client driver
+	const char * desc;      //device description
+} USB_TPL_ENTRY;
+/* control transfer */
+typedef BYTE (*CTRL_XFER)(BYTE addr, BYTE ep, WORD nbytes, BYTE* dataptr,
+		BOOL direction);
+/* class driver initialization */
+typedef BOOL (*CLASS_INIT)(BYTE address, DWORD flags);
+/* class driver event handler	*/
+typedef BOOL (*CLASS_EVENT_HANDLER)(BYTE address, BYTE event, void *data,
+		DWORD size);
+/* Client Driver Table Structure */
+typedef struct {
+	CLASS_INIT Initialize;     // Initialization routine
+	CLASS_EVENT_HANDLER EventHandler;   // Event routine
+	DWORD flags;     // Initialization flags
+} CLASS_CALLBACK_TABLE;
+
+/* Common setup data constant combinations  */
+#define bmREQ_GET_DESCR     USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_DEVICE     //get descriptor request type
+#define bmREQ_SET           USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_DEVICE     //set request type for all but 'set feature' and 'set interface'
+#define bmREQ_CL_GET_INTF   USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE     //get interface request type
+
+#define bmREQ_HIDOUT        USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
+#define bmREQ_HIDIN         USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE 
+
+/* Function macros */
+
+//char XferCtrlReq( BYTE addr, BYTE ep, BYTE bmReqType, BYTE bRequest, BYTE wValLo, BYTE wValHi, WORD wInd, WORD nbytes, char* dataptr )
+/* Set address request macro. Human-readable form of bXferCtrlReq   */
+/* won't necessarily work for device in 'Configured' state          */
+#define XferSetAddr( oldaddr, ep, newaddr ) \
+        XferCtrlReq( oldaddr,  ep, bmREQ_SET, USB_REQUEST_SET_ADDRESS, newaddr, 0x00, 0x0000, 0x0000, NULL )
+/* Set Configuration Request  */
+#define XferSetConf( addr, ep, conf_value )  \
+        XferCtrlReq( addr, ep, bmREQ_SET, USB_REQUEST_SET_CONFIGURATION, conf_value, 0x00, 0x0000, 0x0000, NULL )
+///* Get configuration request  */
+//#define bXferGetConf( addr, ep, urb_ptr ) bXferCtrlReq( addr, ep, 1, ( bmREQ_GET_DESCR ), USB_REQUEST_GET_CONFIGURATION, 0x00, 0x00, 0x00, urb_ptr );
+/* Get device descriptor request macro */
+#define XferGetDevDescr( addr, ep, nbytes, dataptr )    \
+        XferCtrlReq( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, 0x00, USB_DESCRIPTOR_DEVICE, 0x0000, nbytes, dataptr )
+///* Get configuration descriptor request macro */  
+#define XferGetConfDescr( addr, ep, nbytes, conf, dataptr )  \
+        XferCtrlReq( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, conf, USB_DESCRIPTOR_CONFIGURATION, 0x0000, nbytes, dataptr )
+///* Get string descriptor request macro    */ 
+#define XferGetStrDescr( addr, ep, nbytes, index, langid, dataptr ) \
+	XferCtrlReq( addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, index, USB_DESCRIPTOR_STRING, langid, nbytes, dataptr )
+///* Get MAX LUN MSD class request macro */
+//#define bXferGetMaxLUN( addr, intf, urb_ptr ) bXferCtrlReq( addr, 0, 1, ( bmREQ_CL_GET_INTF ), USB_MSD_GET_MAX_LUN, 0, 0, intf, urb_ptr )
+/* class requests */
+#define XferSetProto( addr, ep, interface, protocol ) \
+        XferCtrlReq( addr, ep, bmREQ_HIDOUT, HID_REQUEST_SET_PROTOCOL, protocol, 0x00, interface, 0x0000, NULL )
+#define XferGetProto( addr, ep, interface, dataptr ) \
+        XferCtrlReq( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_PROTOCOL, 0x00, 0x00, interface, 0x0001, dataptr )        
+#define XferGetIdle( addr, ep, interface, reportID, dataptr ) \
+        XferCtrlReq( addr, ep, bmREQ_HIDIN, HID_REQUEST_GET_IDLE, reportID, 0, interface, 0x0001, dataptr )       
+
+/* Function prototypes */
+
+BYTE XferCtrlReq(BYTE addr, BYTE ep, BYTE bmReqType, BYTE bRequest, BYTE wValLo,
+		BYTE wValHi, WORD wInd, WORD nbytes, BYTE* dataptr);
+BYTE XferCtrlData(BYTE addr, BYTE ep, WORD nbytes, BYTE* dataptr,
+		BOOL direction);
+BYTE XferCtrlND(BYTE addr, BYTE ep, WORD nbytes, BYTE* dataptr, BOOL direction);
+//BYTE startCtrlReq( BYTE addr, BYTE ep, BYTE bmReqType, BYTE bRequest, BYTE wValLo, BYTE wValHi, WORD wInd, WORD nbytes, char* dataptr );
+BYTE XferDispatchPkt(BYTE token, BYTE ep);
+BYTE XferInTransfer(BYTE addr, BYTE ep, WORD nbytes, BYTE* data,
+		BYTE maxpktsize);
+//BYTE XferInTransfer_mps( BYTE ep, char* data, BYTE maxpktsize );
+void USB_init(void);
+void USB_Task(void);
+BYTE GetUsbTaskState(void);
+DEV_RECORD* GetDevtable(BYTE index);
+
+/* Client driver routines */
+BOOL MSDProbe(BYTE address, DWORD flags);
+BOOL MSDEventHandler(BYTE address, BYTE event, void *data, DWORD size);
+BOOL CDCProbe(BYTE address, DWORD flags);
+BOOL CDCEventHandler(BYTE address, BYTE event, void *data, DWORD size);
+BOOL DummyProbe(BYTE address, DWORD flags);
+BOOL DummyEventHandler(BYTE address, BYTE event, void *data, DWORD size);
+
+//Function to be able to display string descriptors
+char* ConvUTF8ToStr(BYTE* utf8, BYTE length);
+
+#endif //_transfer_h_ 
diff --git a/lab6/software/usb_kb/usb_kb/usb_ch9.h b/lab6/software/usb_kb/usb_kb/usb_ch9.h
new file mode 100644
index 0000000..6173e50
--- /dev/null
+++ b/lab6/software/usb_kb/usb_kb/usb_ch9.h
@@ -0,0 +1,187 @@
+/*
+
+ USB Chapter 9 Protocol (Header File)
+
+ This file defines data structures, constants, and macros that are used to
+ to support the USB Device Framework protocol described in Chapter 9 of the
+ USB 2.0 specification.
+ 
+ In addition to that, class-specific descriptors are typedef'd here as well to keep descriptors together.
+ They are typedefs anyway and won't take any real code space.
+ */
+
+#ifndef _USB_CH9_H_
+#define _USB_CH9_H_
+
+/* Misc.USB constants */
+#define DEV_DESCR_LEN   18      //device descriptor length
+#define CONF_DESCR_LEN  9       //configuration descriptor length
+#define INTR_DESCR_LEN  9       //interface descriptor length
+#define EP_DESCR_LEN    7       //endpoint descriptor length
+/* Device descriptor structure */
+typedef struct {
+	BYTE bLength;               // Length of this descriptor.
+	BYTE bDescriptorType;     // DEVICE descriptor type (USB_DESCRIPTOR_DEVICE).
+	WORD bcdUSB;                // USB Spec Release Number (BCD).
+	BYTE bDeviceClass; // Class code (assigned by the USB-IF). 0xFF-Vendor specific.
+	BYTE bDeviceSubClass;       // Subclass code (assigned by the USB-IF).
+	BYTE bDeviceProtocol; // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific.
+	BYTE bMaxPacketSize0;       // Maximum packet size for endpoint 0.
+	WORD idVendor;              // Vendor ID (assigned by the USB-IF).
+	WORD idProduct;             // Product ID (assigned by the manufacturer).
+	WORD bcdDevice;             // Device release number (BCD).
+	BYTE iManufacturer; // Index of String Descriptor describing the manufacturer.
+	BYTE iProduct;         // Index of String Descriptor describing the product.
+	BYTE iSerialNumber; // Index of String Descriptor with the device's serial number.
+	BYTE bNumConfigurations;    // Number of possible configurations.
+} USB_DEVICE_DESCRIPTOR;
+/* Configuration Descriptor Structure */
+typedef struct {
+	BYTE bLength;               // Length of this descriptor.
+	BYTE bDescriptorType; // CONFIGURATION descriptor type (USB_DESCRIPTOR_CONFIGURATION).
+	WORD wTotalLength; // Total length of all descriptors for this configuration.
+	BYTE bNumInterfaces;        // Number of interfaces in this configuration.
+	BYTE bConfigurationValue;   // Value of this configuration (1 based).
+	BYTE iConfiguration; // Index of String Descriptor describing the configuration.
+	BYTE bmAttributes;          // Configuration characteristics.
+	BYTE bMaxPower;             // Maximum power consumed by this configuration.
+} USB_CONFIGURATION_DESCRIPTOR;
+/* Conf.descriptor attribute bits */
+#define USB_CFG_DSC_REQUIRED     0x80                           // Required attribute
+//#define USB_CFG_DSC_SELF_PWR    (0x40|USB_CFG_DSC_REQUIRED) // Device is self powered.
+//#define USB_CFG_DSC_REM_WAKE    (0x20|USB_CFG_DSC_REQUIRED) // Device can request remote wakup
+#define USB_CFG_DSC_SELF_PWR    (0x40)                          // Device is self powered.
+#define USB_CFG_DSC_REM_WAKE    (0x20)                          // Device can request remote wakup
+/* USB Interface Descriptor Structure */
+typedef struct {
+	BYTE bLength;               // Length of this descriptor.
+	BYTE bDescriptorType; // INTERFACE descriptor type (USB_DESCRIPTOR_INTERFACE).
+	BYTE bInterfaceNumber;      // Number of this interface (0 based).
+	BYTE bAlternateSetting;     // Value of this alternate interface setting.
+	BYTE bNumEndpoints;         // Number of endpoints in this interface.
+	BYTE bInterfaceClass; // Class code (assigned by the USB-IF).  0xFF-Vendor specific.
+	BYTE bInterfaceSubClass;    // Subclass code (assigned by the USB-IF).
+	BYTE bInterfaceProtocol; // Protocol code (assigned by the USB-IF).  0xFF-Vendor specific.
+	BYTE iInterface;     // Index of String Descriptor describing the interface.
+} USB_INTERFACE_DESCRIPTOR;
+/* USB Endpoint Descriptor Structure */
+typedef struct {
+	BYTE bLength;               // Length of this descriptor.
+	BYTE bDescriptorType; // ENDPOINT descriptor type (USB_DESCRIPTOR_ENDPOINT).
+	BYTE bEndpointAddress; // Endpoint address. Bit 7 indicates direction (0=OUT, 1=IN).
+	BYTE bmAttributes;          // Endpoint transfer type.
+	WORD wMaxPacketSize;        // Maximum packet size.
+	BYTE bInterval;             // Polling interval in frames.
+} USB_ENDPOINT_DESCRIPTOR;
+/*  Endpoint Direction */
+#define EP_DIR_IN           0x80    // Data flows from device to host
+#define EP_DIR_OUT          0x00    // Data flows from host to device
+/* USB Endpoint Attributes */
+// Section: Transfer Types
+#define EP_ATTR_CONTROL     (0<<0)  // Endoint used for control transfers
+#define EP_ATTR_ISOCH       (1<<0)  // Endpoint used for isochronous transfers
+#define EP_ATTR_BULK        (2<<0)  // Endpoint used for bulk transfers
+#define EP_ATTR_INTR        (3<<0)  // Endpoint used for interrupt transfers
+// Section: Synchronization Types (for isochronous enpoints)
+#define EP_ATTR_NO_SYNC     (0<<2)  // No Synchronization
+#define EP_ATTR_ASYNC       (1<<2)  // Asynchronous
+#define EP_ATTR_ADAPT       (2<<2)  // Adaptive synchronization
+#define EP_ATTR_SYNC        (3<<2)  // Synchronous
+// Section: Usage Types (for isochronous endpoints)
+#define EP_ATTR_DATA        (0<<4)  // Data Endpoint
+#define EP_ATTR_FEEDBACK    (1<<4)  // Feedback endpoint
+#define EP_ATTR_IMP_FB      (2<<4)  // Implicit Feedback data EP
+// Section: Max Packet Sizes
+#define EP_MAX_PKT_INTR_LS  8       // Max low-speed interrupt packet
+#define EP_MAX_PKT_INTR_FS  64      // Max full-speed interrupt packet
+#define EP_MAX_PKT_ISOCH_FS 1023    // Max full-speed isochronous packet
+#define EP_MAX_PKT_BULK_FS  64      // Max full-speed bulk packet
+#define EP_LG_PKT_BULK_FS   32      // Large full-speed bulk packet
+#define EP_MED_PKT_BULK_FS  16      // Medium full-speed bulk packet
+#define EP_SM_PKT_BULK_FS   8       // Small full-speed bulk packet
+/* USB OTG Descriptor Structure */
+typedef struct {
+	BYTE bLength;               // Length of this descriptor.
+	BYTE bDescriptorType;       // OTG descriptor type (USB_DESCRIPTOR_OTG).
+	BYTE bmAttributes;          // OTG attributes.
+} USB_OTG_DESCRIPTOR;
+/* USB String Descriptor Structure */
+typedef struct {
+	BYTE bLength;            //size of this descriptor
+	BYTE bDescriptorType;    //type, USB_DSC_STRING
+	BYTE bString[256 - 2];     //buffer for string
+} USB_STRING_DESCRIPTOR;
+/* Section: USB Device Qualifier Descriptor Structure */
+typedef struct {
+	BYTE bLength;               // Size of this descriptor
+	BYTE bDescriptorType;        // Type, always USB_DESCRIPTOR_DEVICE_QUALIFIER
+	WORD bcdUSB;                // USB spec version, in BCD
+	BYTE bDeviceClass;          // Device class code
+	BYTE bDeviceSubClass;       // Device sub-class code
+	BYTE bDeviceProtocol;       // Device protocol
+	BYTE bMaxPacketSize0;       // EP0, max packet size
+	BYTE bNumConfigurations;    // Number of "other-speed" configurations
+	BYTE bReserved;             // Always zero (0)
+} USB_DEVICE_QUALIFIER_DESCRIPTOR;
+/* Section: USB Specification Constants */
+#define PID_OUT                                 0x1     // PID for an OUT token
+#define PID_ACK                                 0x2     // PID for an ACK handshake
+#define PID_DATA0                               0x3     // PID for DATA0 data
+#define PID_PING                                0x4     // Special PID PING
+#define PID_SOF                                 0x5     // PID for a SOF token
+#define PID_NYET                                0x6     // PID for a NYET handshake
+#define PID_DATA2                               0x7     // PID for DATA2 data
+#define PID_SPLIT                               0x8     // Special PID SPLIT
+#define PID_IN                                  0x9     // PID for a IN token
+#define PID_NAK                                 0xA     // PID for a NAK handshake
+#define PID_DATA1                               0xB     // PID for DATA1 data
+#define PID_PRE                                 0xC     // Special PID PRE (Same as PID_ERR)
+#define PID_ERR                                 0xC     // Special PID ERR (Same as PID_PRE)
+#define PID_SETUP                               0xD     // PID for a SETUP token
+#define PID_STALL                               0xE     // PID for a STALL handshake
+#define PID_MDATA                               0xF     // PID for MDATA data
+
+#define PID_MASK_DATA                           0x03    // Data PID mask
+#define PID_MASK_DATA_SHIFTED                  (PID_MASK_DATA << 2) // Data PID shift to proper position
+
+#define LANG_EN_US								0x0409	//US language code, probably the only supported by string descriptors
+
+/* USB Token Types */
+/* defined in MAX3421E.h */
+
+/* Section: OTG Descriptor Constants */
+#define OTG_HNP_SUPPORT                         0x02    // OTG Descriptor bmAttributes - HNP support flag
+#define OTG_SRP_SUPPORT                         0x01    // OTG Descriptor bmAttributes - SRP support flag
+/* Section: USB Class Code Definitions */
+#define USB_HUB_CLASSCODE                       0x09    //  Class code for a hub.
+
+/* HID class-specific defines */
+
+/* USB HID Descriptor header per HID 1.1 spec */
+/* section 6.2.1 */
+/* the header is variable length. Only first class descriptor fields are defined */
+typedef struct {
+	BYTE bLength;
+	BYTE bDescriptorType;
+	WORD bcdHID;
+	BYTE bCountryCode;
+	BYTE bNumDescriptors;
+	BYTE bDescrType;
+	WORD wDescriptorLength;
+} USB_HID_DESCRIPTOR;
+
+/* combined descriptor for easy parsing */
+typedef struct {
+	union {
+		BYTE buf[80];
+		USB_DEVICE_DESCRIPTOR device;
+		USB_CONFIGURATION_DESCRIPTOR config;
+		USB_INTERFACE_DESCRIPTOR interface;
+		USB_ENDPOINT_DESCRIPTOR endpoint;
+		USB_STRING_DESCRIPTOR string;
+		/* class descriptors */
+		USB_HID_DESCRIPTOR HID;
+	} descr;
+} USB_DESCR;
+#endif  // _USB_CH9_H_
+
diff --git a/lab6/src/ball.sv b/lab6/src/ball.sv
new file mode 100644
index 0000000..cd30622
--- /dev/null
+++ b/lab6/src/ball.sv
@@ -0,0 +1,48 @@
+`include "utils.sv"
+
+module Ball (
+	input  logic frame_clk, Reset,
+	input  logic [7:0] keycode,
+	output logic [9:0] BallX, BallY, BallS);
+
+	logic [9:0] BallX_speed, BallY_speed;
+
+	assign BallS = 4;
+
+	always_ff @ (posedge Reset or posedge frame_clk) begin
+
+		if (Reset) begin
+			BallX <= `BALL_CENTER_X;
+			BallY <= `BALL_CENTER_Y;
+			BallX_speed <= 10'd0;
+			BallY_speed <= 10'd0;
+		end else begin
+
+			if (BallY - BallS <= 0)							// bounce at top edge
+				BallY_speed <= `BALL_STEP_Y;
+			else if (BallY + BallS >= `VGA_DISP_Y - 1)		// bounce at bottom edge
+				BallY_speed <= ~ (`BALL_STEP_Y) + 1'b1;
+			else if (BallX - BallS <= 0)					// bounce at left edge
+				BallX_speed <= `BALL_STEP_X;
+			else if (BallX + BallS >= `VGA_DISP_X - 1)		// bounce at right edge
+				BallX_speed <= ~ (`BALL_STEP_X) + 1'b1;
+			else begin
+
+				BallX_speed <= BallX_speed;					// keep moving
+				BallY_speed <= BallY_speed;
+				case (keycode)
+					8'h1A: begin BallX_speed <=  0; BallY_speed <= -1; end	// W
+					8'h16: begin BallX_speed <=  0; BallY_speed <=  1; end	// S
+					8'h04: begin BallX_speed <= -1; BallY_speed <=  0; end	// A
+					8'h07: begin BallX_speed <=  1; BallY_speed <=  0; end	// D
+					default: ;
+				endcase
+			end
+
+			BallX <= BallX + BallX_speed;	// update position
+			BallY <= BallY + BallY_speed;
+
+		end
+	end
+
+endmodule
diff --git a/lab6/src/lab61.sv b/lab6/src/lab61.sv
new file mode 100644
index 0000000..6332647
--- /dev/null
+++ b/lab6/src/lab61.sv
@@ -0,0 +1,38 @@
+module lab61 (
+	input  logic MAX10_CLK1_50,
+	input  logic [1:0]  KEY,
+	input  logic [7:0]  SW,
+	output logic [7:0]  LEDR,
+	output logic [7:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
+	inout  logic [15:0] DRAM_DQ,
+	output logic [12:0] DRAM_ADDR,
+	output logic [1:0]  DRAM_BA,
+	output logic DRAM_LDQM, DRAM_UDQM, DRAM_RAS_N, DRAM_CAS_N,
+	output logic DRAM_CKE, DRAM_CLK, DRAM_WE_N, DRAM_CS_N);
+
+	lab6_soc m_lab61_soc (
+		.clk_clk         (MAX10_CLK1_50),
+		.reset_reset_n   (KEY[0]),
+		.key1_wire_export(KEY[1]),
+		.sw_wire_export  (SW),
+		.led_wire_export (LEDR),
+		.hex0_wire_export(HEX0),
+		.hex1_wire_export(HEX1),
+		.hex2_wire_export(HEX2),
+		.hex3_wire_export(HEX3),
+		.hex4_wire_export(HEX4),
+		.hex5_wire_export(HEX5),
+		.sdram_wire_dq   (DRAM_DQ),
+		.sdram_wire_addr (DRAM_ADDR),
+		.sdram_wire_ba   (DRAM_BA),
+		.sdram_wire_dqm  ({DRAM_UDQM, DRAM_LDQM}),
+		.sdram_wire_ras_n(DRAM_RAS_N),
+		.sdram_wire_cas_n(DRAM_CAS_N),
+		.sdram_wire_cke  (DRAM_CKE),
+		.sdram_clk_clk   (DRAM_CLK),
+		.sdram_wire_we_n (DRAM_WE_N),
+		.sdram_wire_cs_n (DRAM_CS_N));
+
+	// Instantiate additional FPGA fabric modules as needed
+
+endmodule
diff --git a/lab6/src/lab62.sv b/lab6/src/lab62.sv
new file mode 100644
index 0000000..e61881c
--- /dev/null
+++ b/lab6/src/lab62.sv
@@ -0,0 +1,80 @@
+module lab62 (
+	input  logic MAX10_CLK1_50,
+	input  logic [1:0]  KEY,					// Peripheral
+	output logic [7:0]  LEDR,
+	output logic [7:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
+	inout  logic [15:0] DRAM_DQ,				// SDRAM
+	output logic [12:0] DRAM_ADDR,
+	output logic [1:0]  DRAM_BA,
+	output logic DRAM_LDQM, DRAM_UDQM, DRAM_RAS_N, DRAM_CAS_N,
+	output logic DRAM_CKE,  DRAM_CLK,  DRAM_WE_N,  DRAM_CS_N,
+	output logic VGA_HS, VGA_VS,				// VGA
+	output logic [3:0]  VGA_R, VGA_G, VGA_B,
+	inout  logic [15:0] ARDUINO_IO,				// Arduino
+	inout  logic ARDUINO_RESET_N);
+
+	logic VGA_Clk, Reset_h;
+	logic SPI0_CS_N, SPI0_SCLK, SPI0_MISO, SPI0_MOSI, USB_GPX, USB_IRQ, USB_RST;
+	logic [9:0] DrawX, DrawY, BallX, BallY, BallS;
+	logic [7:0] Red, Blue, Green, keycode;
+	logic [1:0] signs, hundreds;
+	logic [15:0] hexnum;
+
+	// assignments are specific to Circuits At Home UHS_20
+	// [8] is GPX (set to input); USB_GPX is not needed for standard USB host, set to 0 to prevent interrupt
+	// [6] is uSD CS, set to 1 to prevent uSD card from interfering with USB Host (if uSD card is plugged in)
+	assign ARDUINO_IO[13:6] = {SPI0_SCLK, 1'bZ, SPI0_MOSI, SPI0_CS_N, 1'bZ, 1'bZ, USB_RST, 1'b1};
+	assign ARDUINO_RESET_N = USB_RST;
+	assign SPI0_MISO = ARDUINO_IO[12];
+	assign USB_IRQ = ARDUINO_IO[9];
+	assign USB_GPX = 1'b0;
+
+	HexDriver hexdriver[4] (hexnum, {HEX4[6:0], HEX3[6:0], HEX1[6:0], HEX0[6:0]});
+	assign {HEX4[7], HEX3[7], HEX1[7], HEX0[7]} = 4'b1111;
+	assign HEX5 = {1'b1, ~signs[1], 3'b111, ~hundreds[1], ~hundreds[1], 1'b1};
+	assign HEX2 = {1'b1, ~signs[0], 3'b111, ~hundreds[0], ~hundreds[0], 1'b1};
+	assign {VGA_R, VGA_G, VGA_B} = {Red[7:4], Green[7:4], Blue[7:4]};	// 12-bit A/D converter
+	assign Reset_h = ~KEY[0];
+
+	lab62_soc m_lab62_soc (
+		.clk_clk(MAX10_CLK1_50),
+		.reset_reset_n(1'b1),
+		.altpll_0_locked_conduit_export(),
+		.altpll_0_phasedone_conduit_export(),
+		.altpll_0_areset_conduit_export(),
+		.hex_digits_export(hexnum),				// Peripheral
+		.leds_export({hundreds, signs, LEDR}),
+		.key_external_connection_export(KEY),
+		.sdram_clk_clk   (DRAM_CLK),			// SDRAM
+		.sdram_wire_dq   (DRAM_DQ),
+		.sdram_wire_addr (DRAM_ADDR),
+		.sdram_wire_ba   (DRAM_BA),
+		.sdram_wire_dqm  ({DRAM_UDQM, DRAM_LDQM}),
+		.sdram_wire_ras_n(DRAM_RAS_N),
+		.sdram_wire_cas_n(DRAM_CAS_N),
+		.sdram_wire_cke  (DRAM_CKE),
+		.sdram_wire_we_n (DRAM_WE_N),
+		.sdram_wire_cs_n (DRAM_CS_N),
+		.spi0_SS_n(SPI0_CS_N),					// USB SPI
+		.spi0_SCLK(SPI0_SCLK),
+		.spi0_MOSI(SPI0_MOSI),
+		.spi0_MISO(SPI0_MISO),
+		.keycode_export(keycode),				// USB GPIO
+		.usb_irq_export(USB_IRQ),
+		.usb_gpx_export(USB_GPX),
+		.usb_rst_export(USB_RST));
+
+	assign VGA_Clk = MAX10_CLK1_50;
+
+	Ball ball (
+		.frame_clk(VGA_VS), .Reset(Reset_h),
+		.keycode, .BallX, .BallY, .BallS);
+	VGAController vga_controller (
+		.Clk(VGA_Clk), .Reset(Reset_h),
+		.pixel_clk(), .blank(), .sync(),
+		.hs(VGA_HS), .vs(VGA_VS), .DrawX, .DrawY);
+	ColorMapper color_mapper (
+		.DrawX, .DrawY, .BallX, .BallY, .BallS,
+		.Red, .Green, .Blue);
+
+endmodule
diff --git a/lab6/src/utils.sv b/lab6/src/utils.sv
new file mode 100644
index 0000000..d3b7f68
--- /dev/null
+++ b/lab6/src/utils.sv
@@ -0,0 +1,67 @@
+`ifndef UTILS_SV
+`define UTILS_SV
+
+
+`define VGA_MAX_X		10'd800
+`define VGA_MAX_Y		10'd525
+`define VGA_DISP_X		10'd640
+`define VGA_DISP_Y		10'd480
+`define VGA_HSYNC_START	10'd656
+`define VGA_HSYNC_END	10'd752
+`define VGA_VSYNC_START	10'd490
+`define VGA_VSYNC_END	10'd492
+
+`define BALL_CENTER_X	10'd320
+`define BALL_CENTER_Y	10'd240
+`define BALL_STEP_X		10'd1
+`define BALL_STEP_Y		10'd1
+
+
+module ColorMapper (
+	input  logic [9:0] DrawX, DrawY, BallX, BallY, BallS,
+	output logic [7:0] Red, Green, Blue);
+
+	int DistX, DistY;
+	assign DistX = DrawX - BallX;
+	assign DistY = DrawY - BallY;
+
+	always_comb begin
+		if ( DistX * DistX + DistY * DistY <= BallS * BallS )
+			{Red, Green, Blue} = 24'hFF5500;
+		else
+			{Red, Green, Blue} = {16'h0000, 8'h7F - DrawX[9:3]};
+	 end
+
+endmodule
+
+
+module HexDriver (
+	input  logic [3:0] in,
+	output logic [6:0] out);
+
+	always_comb begin
+		unique case (in)
+			4'b0000: out = 7'b1000000;
+			4'b0001: out = 7'b1111001;
+			4'b0010: out = 7'b0100100;
+			4'b0011: out = 7'b0110000;
+			4'b0100: out = 7'b0011001;
+			4'b0101: out = 7'b0010010;
+			4'b0110: out = 7'b0000010;
+			4'b0111: out = 7'b1111000;
+			4'b1000: out = 7'b0000000;
+			4'b1001: out = 7'b0010000;
+			4'b1010: out = 7'b0001000;
+			4'b1011: out = 7'b0000011;
+			4'b1100: out = 7'b1000110;
+			4'b1101: out = 7'b0100001;
+			4'b1110: out = 7'b0000110;
+			4'b1111: out = 7'b0001110;
+			default: out = 7'bX;
+		endcase
+	end
+
+endmodule
+
+
+`endif
diff --git a/lab6/src/vga.sv b/lab6/src/vga.sv
new file mode 100644
index 0000000..65cb71c
--- /dev/null
+++ b/lab6/src/vga.sv
@@ -0,0 +1,47 @@
+`include "utils.sv"
+
+module VGAController (
+	input  logic Clk, Reset,			// 50 MHz
+	output logic pixel_clk,				// 25 MHz
+	output logic hs, vs, blank,			// AL sync pulse, blanking interval
+	output logic sync,					// Composite Sync, unused but required by DE2 video DAC
+	output logic [9:0] DrawX, DrawY);	// line counters, coords on 800x525 display
+
+	assign sync = 0;	// disable Composite Sync
+
+	always_ff @ (posedge Clk or posedge Reset) begin
+		if (Reset) pixel_clk <= 0;
+		else pixel_clk <= ~pixel_clk;	// cut Clk in half
+	end
+
+	// "hs", "vs" are registered to ensure clean output waveform
+	// "blank" is registered within the DAC chip and written as combinational logic here
+
+	always_ff @ (posedge pixel_clk or posedge Reset) begin
+
+		if (Reset) begin
+			DrawX <= 0;
+			DrawY <= 0;
+		end else if (DrawX == `VGA_MAX_X - 1) begin	// DrawX reached end of pixel count
+			DrawX <= 0;
+			if (DrawY == `VGA_MAX_Y - 1)			// DrawY reached end of line count
+				DrawY <= 0;
+			else DrawY <= DrawY + 1;
+		end else DrawX <= DrawX + 1;				// implied DrawY <= DrawY
+
+		if (Reset) hs <= 0;
+		else if ((DrawX + 1 >= `VGA_HSYNC_START & DrawX + 1 < `VGA_HSYNC_END)) hs <= 0;
+		else hs <= 1;
+		
+		if (Reset) vs <= 0;
+		else if ((DrawY + 1 >= `VGA_VSYNC_START & DrawY + 1 < `VGA_VSYNC_END)) vs <= 0;
+		else vs <= 1;
+
+	end
+
+	always_comb begin
+		if ((DrawX >= `VGA_DISP_X) | (DrawY >= `VGA_DISP_Y)) blank = 0;
+		else blank = 1;
+	end
+
+endmodule