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vivado.log
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#-----------------------------------------------------------
# Vivado v2019.1.1 (64-bit)
# SW Build 2580384 on Sat Jun 29 08:04:45 MDT 2019
# IP Build 2579722 on Sat Jun 29 11:35:40 MDT 2019
# Start of session at: Thu Nov 28 13:15:14 2019
# Process ID: 16080
# Current directory: /home/hwkim/work/pynq-bnn/BNN-PYNQ
# Command line: vivado
# Log file: /home/hwkim/work/pynq-bnn/BNN-PYNQ/vivado.log
# Journal file: /home/hwkim/work/pynq-bnn/BNN-PYNQ/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'design_1_BlackBoxJam_0_0' generated file not found '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_BlackBoxJam_0_0' generated file not found '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_BlackBoxJam_0_0' generated file not found '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_BlackBoxJam_0_0' generated file not found '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_BlackBoxJam_0_0' generated file not found '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0_sim_netlist.vhdl'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:13 . Memory (MB): peak = 6632.156 ; gain = 239.422 ; free physical = 5090 ; free virtual = 6529
update_compile_order -fileset sources_1
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xczu7ev-ffvc1156-2-e
INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0.dcp' for cell 'design_1_i/BlackBoxJam_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0.dcp' for cell 'design_1_i/axi_smc'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.dcp' for cell 'design_1_i/rst_ps8_0_100M'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.dcp' for cell 'design_1_i/zynq_ultra_ps_e_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.dcp' for cell 'design_1_i/ps8_0_axi_periph/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.dcp' for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.dcp' for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_pc'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1.dcp' for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/design_1_auto_pc_1.dcp' for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_pc'
INFO: [Netlist 29-17] Analyzing 10100 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/constrs_1/new/design_1_consts.xdc]
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/constrs_1/new/design_1_consts.xdc]
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl:2]
all_registers: Time (s): cpu = 00:00:18 ; elapsed = 00:00:10 . Memory (MB): peak = 8488.219 ; gain = 563.480 ; free physical = 10367 ; free virtual = 11957
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 8488.219 ; gain = 0.000 ; free physical = 10551 ; free virtual = 12141
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 4625 instances were transformed.
CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 276 instances
DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 24 instances
RAM16X1S => RAM32X1S (RAMS32): 4032 instances
RAM32M16 => RAM32M16 (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 69 instances
RAM32X1S => RAM32X1S (RAMS32): 224 instances
open_run: Time (s): cpu = 00:01:21 ; elapsed = 00:01:00 . Memory (MB): peak = 8624.879 ; gain = 1736.598 ; free physical = 10191 ; free virtual = 11788
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
connect_debug_port u_ila_0/clk [get_nets [list design_1_i/zynq_ultra_ps_e_0/inst/pl_clk0 ]]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 61 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/out_V_offset[60]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 264 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout[16]} 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create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 24 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout[23]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWVALID ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WVALID ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWVALID ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WVALID ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_write ]]
save_constraints
launch_runs impl_1 -to_step write_bitstream -jobs 12
Netlist sorting complete. Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.10 . Memory (MB): peak = 8727.520 ; gain = 0.000 ; free physical = 9968 ; free virtual = 11595
INFO: [Timing 38-480] Writing timing data to binary archive.
[Thu Nov 28 13:31:40 2019] Launched impl_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 8727.520 ; gain = 0.000 ; free physical = 9922 ; free virtual = 11576
close_design
open_run impl_1
INFO: [Netlist 29-17] Analyzing 11108 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 8861.859 ; gain = 134.340 ; free physical = 9268 ; free virtual = 11422
Restored from archive | CPU: 10.350000 secs | Memory: 135.124596 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 8861.859 ; gain = 134.340 ; free physical = 9268 ; free virtual = 11422
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 8861.859 ; gain = 0.000 ; free physical = 9290 ; free virtual = 11444
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 5206 instances were transformed.
CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 932 instances
DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 24 instances
RAM16X1S => RAM32X1S (RAMS32): 3968 instances
RAM32M16 => RAM32M16 (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 58 instances
RAM32X1S => RAM32X1S (RAMS32): 224 instances
open_run: Time (s): cpu = 00:00:49 ; elapsed = 00:00:43 . Memory (MB): peak = 9135.684 ; gain = 408.164 ; free physical = 9059 ; free virtual = 11213
open_report: Time (s): cpu = 00:00:26 ; elapsed = 00:00:08 . Memory (MB): peak = 9197.297 ; gain = 54.609 ; free physical = 8712 ; free virtual = 10868
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
file copy -force /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.sysdef /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk/design_1_wrapper.hdf
launch_sdk -workspace /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk -hwspec /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk -hwspec /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
open_hw
connect_hw_server -url 121.155.128.106:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:121.155.128.106:3121
current_hw_target [get_hw_targets */xilinx_tcf/Xilinx/88281A]
set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Xilinx/88281A]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target 121.155.128.106:3121/xilinx_tcf/Xilinx/88281A
open_hw_target: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 11444.738 ; gain = 836.035 ; free physical = 5098 ; free virtual = 7614
set_property PROGRAM.FILE {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xczu7_0]
set_property PROBES.FILE {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xczu7_0]
set_property FULL_PROBES.FILE {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xczu7_0]
current_hw_device [get_hw_devices xczu7_0]
refresh_hw_device [lindex [get_hw_devices xczu7_0] 0]
INFO: [Labtools 27-2302] Device xczu7 (JTAG device index = 0) is programmed with a design that has 2 ILA core(s).
refresh_hw_device: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 11511.211 ; gain = 52.270 ; free physical = 5061 ; free virtual = 7578
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
Processed interface BlackBoxJam_0_m_axi_hostmem_ila1_slot0
display_hw_ila_data [ get_hw_ila_data hw_ila_data_2 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
WARNING: Simulation object design_1_i/BlackBoxJam_0_interrupt was not found in the design.
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu7_0]
add_wave -into {hw_ila_data_2.wcfg} -radix hex { {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/infer_category_U0/out_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U0/out_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Matrix_Vector_Activa_2_U1_1/out_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWADDR} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_AWVALID} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WDATA} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_1_U0/m_axi_out_V_WVALID} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWADDR} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_AWVALID} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WDATA} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/m_axi_in_V_WVALID} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/Stream2Mem_Batch_U0/memOutStrm_V_V_i_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/StreamingDataWidthCo_13_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_5_U0/out_V_V_write} {u_ila_0_out_V_offset} {u_ila_0_out_V_offset[0]_1} {u_ila_0_out_V_offset[0]_2} {u_ila_0_out_V_offset[0]_3} {u_ila_0_out_V_offset[0]_4} {u_ila_0_out_V_offset[0]_5} {u_ila_0_out_V_offset[0]_6} {u_ila_0_out_V_offset[0]_7} {u_ila_0_out_V_offset[0]_8} {u_ila_0_out_V_offset[0]_9} {u_ila_0_out_V_offset[0]_10} {u_ila_0_out_V_offset[0]_11} {u_ila_0_out_V_offset[0]_12} {u_ila_0_out_V_offset[0]_13} {u_ila_0_out_V_offset[0]_14} {u_ila_0_out_V_offset[0]_15} {u_ila_0_out_V_offset[0]_16} {u_ila_0_out_V_offset[0]_17} {u_ila_0_out_V_offset[0]_18} {u_ila_0_out_V_offset[0]_19} {u_ila_0_out_V_offset[0]_20} {u_ila_0_out_V_offset[0]_21} {u_ila_0_out_V_offset[0]_22} {u_ila_0_out_V_offset[0]_23} {u_ila_0_out_V_offset[0]_24} {u_ila_0_out_V_offset[0]_25} {u_ila_0_out_V_offset[0]_26} {u_ila_0_out_V_offset[0]_27} {u_ila_0_out_V_offset[0]_28} {u_ila_0_out_V_offset[0]_29} {u_ila_0_out_V_offset[0]_30} {u_ila_0_out_V_offset[0]_31} {u_ila_0_out_V_offset[0]_32} {u_ila_0_out_V_offset[0]_33} {u_ila_0_out_V_offset[0]_34} {u_ila_0_out_V_offset[0]_35} {u_ila_0_out_V_offset[0]_36} {u_ila_0_out_V_offset[0]_37} {u_ila_0_out_V_offset[0]_38} {u_ila_0_out_V_offset[0]_39} {u_ila_0_out_V_offset[0]_40} {u_ila_0_out_V_offset[0]_41} {u_ila_0_out_V_offset[0]_42} {u_ila_0_out_V_offset[0]_43} {u_ila_0_out_V_offset[0]_44} {u_ila_0_out_V_offset[0]_45} {u_ila_0_out_V_offset[0]_46} {u_ila_0_out_V_offset[0]_47} {u_ila_0_out_V_offset[0]_48} {u_ila_0_out_V_offset[0]_49} {u_ila_0_out_V_offset[0]_50} {u_ila_0_out_V_offset[0]_51} {u_ila_0_out_V_offset[0]_52} {u_ila_0_out_V_offset[0]_53} {u_ila_0_out_V_offset[0]_54} {u_ila_0_out_V_offset[0]_55} {u_ila_0_out_V_offset[0]_56} {u_ila_0_out_V_offset[0]_57} {u_ila_0_out_V_offset[0]_58} {u_ila_0_out_V_offset[0]_59} {u_ila_0_out_V_offset[0]_60} }
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_2' trigger was armed at 2019-Nov-28 14:04:53
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_2' triggered at 2019-Nov-28 14:04:53
INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.hw/backup/hw_ila_data_2.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
add_wave -into {hw_ila_data_2.wcfg} -radix hex { {u_ila_0_out_V_offset} {u_ila_0_out_V_offset[0]_1} {u_ila_0_out_V_offset[0]_2} {u_ila_0_out_V_offset[0]_3} {u_ila_0_out_V_offset[0]_4} {u_ila_0_out_V_offset[0]_5} {u_ila_0_out_V_offset[0]_6} {u_ila_0_out_V_offset[0]_7} {u_ila_0_out_V_offset[0]_8} {u_ila_0_out_V_offset[0]_9} {u_ila_0_out_V_offset[0]_10} {u_ila_0_out_V_offset[0]_11} {u_ila_0_out_V_offset[0]_12} {u_ila_0_out_V_offset[0]_13} {u_ila_0_out_V_offset[0]_14} {u_ila_0_out_V_offset[0]_15} {u_ila_0_out_V_offset[0]_16} {u_ila_0_out_V_offset[0]_17} {u_ila_0_out_V_offset[0]_18} {u_ila_0_out_V_offset[0]_19} {u_ila_0_out_V_offset[0]_20} {u_ila_0_out_V_offset[0]_21} {u_ila_0_out_V_offset[0]_22} {u_ila_0_out_V_offset[0]_23} {u_ila_0_out_V_offset[0]_24} {u_ila_0_out_V_offset[0]_25} {u_ila_0_out_V_offset[0]_26} {u_ila_0_out_V_offset[0]_27} {u_ila_0_out_V_offset[0]_28} {u_ila_0_out_V_offset[0]_29} {u_ila_0_out_V_offset[0]_30} {u_ila_0_out_V_offset[0]_31} {u_ila_0_out_V_offset[0]_32} {u_ila_0_out_V_offset[0]_33} {u_ila_0_out_V_offset[0]_34} {u_ila_0_out_V_offset[0]_35} {u_ila_0_out_V_offset[0]_36} {u_ila_0_out_V_offset[0]_37} {u_ila_0_out_V_offset[0]_38} {u_ila_0_out_V_offset[0]_39} {u_ila_0_out_V_offset[0]_40} {u_ila_0_out_V_offset[0]_41} {u_ila_0_out_V_offset[0]_42} {u_ila_0_out_V_offset[0]_43} {u_ila_0_out_V_offset[0]_44} {u_ila_0_out_V_offset[0]_45} {u_ila_0_out_V_offset[0]_46} {u_ila_0_out_V_offset[0]_47} {u_ila_0_out_V_offset[0]_48} {u_ila_0_out_V_offset[0]_49} {u_ila_0_out_V_offset[0]_50} {u_ila_0_out_V_offset[0]_51} {u_ila_0_out_V_offset[0]_52} {u_ila_0_out_V_offset[0]_53} {u_ila_0_out_V_offset[0]_54} {u_ila_0_out_V_offset[0]_55} {u_ila_0_out_V_offset[0]_56} {u_ila_0_out_V_offset[0]_57} {u_ila_0_out_V_offset[0]_58} {u_ila_0_out_V_offset[0]_59} {u_ila_0_out_V_offset[0]_60} }
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: 121.155.128.106:3121/xilinx_tcf/Xilinx/88281A
INFO: [Labtoolstcl 44-466] Opening hw_target 121.155.128.106:3121/xilinx_tcf/Xilinx/88281A
INFO: [Labtools 27-1435] Device xczu7 (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
refresh_hw_device [lindex [get_hw_devices xczu7_0] 0]
INFO: [Labtools 27-2302] Device xczu7 (JTAG device index = 0) is programmed with a design that has 2 ILA core(s).
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
Processed interface BlackBoxJam_0_m_axi_hostmem_ila1_slot0
display_hw_ila_data [ get_hw_ila_data hw_ila_data_2 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_2' trigger was armed at 2019-Nov-28 14:11:00
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_2' triggered at 2019-Nov-28 14:11:00
INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.hw/backup/hw_ila_data_2.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
open_bd_design {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd}
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - zynq_ultra_ps_e_0
WARNING: [BD 41-176] The physical port 'M_AXI_HPM0_FPD_aximm_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'M_AXI_HPM0_FPD_aximm_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'M_AXI_HPM1_FPD_aximm_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'M_AXI_HPM1_FPD_aximm_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_HP0_FPD_aximm_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_HP0_FPD_aximm_rd_socket' specified in the portmap, is not found on the block!
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - ps8_0_axi_periph
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_0
Adding component instance block -- xilinx.com:hls:BlackBoxJam:1.0 - BlackBoxJam_0
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> from </BlackBoxJam_0/Data_m_axi_hostmem>
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> from </BlackBoxJam_0/Data_m_axi_hostmem>
Successfully read diagram <design_1> from BD file </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd>
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_2' trigger was armed at 2019-Nov-28 14:12:16
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_2' triggered at 2019-Nov-28 14:12:16
INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.hw/backup/hw_ila_data_2.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
add_wave -into {hw_ila_data_1.wcfg} -radix hex { {design_1_i/system_ila_0/inst/probe0_1} }
set_property NAME.CUSTOM BlackBoxJam_0_interrupt [get_hw_probes design_1_i/system_ila_0/inst/probe0_1]
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Nov-28 14:12:53
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2019-Nov-28 14:12:53
Processed interface BlackBoxJam_0_m_axi_hostmem_ila1_slot0
INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes design_1_i/system_ila_0/inst/net_slot_0_axi_wvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
set_property TRIGGER_COMPARE_VALUE eq1'bR [get_hw_probes design_1_i/system_ila_0/inst/probe0_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2019-Nov-28 14:14:45
wait_on_hw_ila -timeout 0 [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]
INFO: [Labtools 27-1965] The ILA core 'hw_ila_1' trigger was stopped by user at 2019-Nov-28 14:15:17
WARNING: [Labtools 27-157] hw_ila [hw_ila_1] stopped. No data to upload.
open_bd_design {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd}
ipx::edit_ip_in_project -upgrade true -name BlackBoxJam_v1_0_project -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_hostmem_m_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_32_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_53_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_94_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_164_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_185_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_325_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_727_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs0_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs1_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs2_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs3_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs4_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights0_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights1_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights2_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights4_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights10_m_weights_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_1_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_3_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/DoMemInit.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w16_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w16_d2_A_x.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w24_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w32_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w32_d7_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w61_d7_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w61_d41_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w64_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w64_d2_A_x.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w128_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w192_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w256_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/fifo_w264_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/infer_category.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Mem2Stream.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Mem2Stream_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Mem2Stream_Batch3392.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_ConvolutionInputGene_1_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_ConvolutionInputGene_3_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_ConvolutionInputGene_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_ConvolutionInputGene_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_infer_category_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_Stream2Mem_Batch_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_1_1_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_1_1_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_1_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_2_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_3_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_3_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_4_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_5_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_5_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_6_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_6_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_7_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_8_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_9_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_10_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_11_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_11_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_12_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_12_U1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_12_U2_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_StreamingDataWidthCo_12_U3_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_TConvolutionInputGen_1_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/start_for_TConvolutionInputGen_U0.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Stream2Mem.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Stream2Mem_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Stream2Mem_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Stream2Mem_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Stream2Mem_Batch.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/Stream2Mem_Batch_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/StreamingDataWidthCo_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_no_log_test_1127/sol1/impl/ip/hdl/verilog/StreamingDataWidthCo_1_1.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
ipx::edit_ip_in_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 11714.289 ; gain = 0.000 ; free physical = 4849 ; free virtual = 7455
update_compile_order -fileset sources_1
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: 121.155.128.106:3121/xilinx_tcf/Xilinx/88281A
INFO: [Labtoolstcl 44-466] Opening hw_target 121.155.128.106:3121/xilinx_tcf/Xilinx/88281A
INFO: [Labtools 27-1435] Device xczu7 (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
close_project
****** Webtalk v2019.1.1 (64-bit)
**** SW Build 2580384 on Sat Jun 29 08:04:45 MDT 2019
**** IP Build 2579722 on Sat Jun 29 11:35:40 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project/BlackBoxJam_v1_0_project.hw/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project/BlackBoxJam_v1_0_project.hw/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Thu Nov 28 16:43:17 2019. For additional details about this file, please refer to the WebTalk help file at /home/hwkim/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Thu Nov 28 16:43:17 2019...
close_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 11857.129 ; gain = 0.000 ; free physical = 3619 ; free virtual = 7065
exit
INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:43:25 2019...