Created by: Angelo Jacobo
Date: August 14,2021
- asyn_fifo.v -> Asynchronous fifo module. Specs are given below.
- asyn_fifo_TB.v -> Testbench for asyn_fifo module. Test cases are:
- write data until full
- read data until empty
- read data while simultaneously writing data
This project implemented a FIFO with separate clock domains for read and write(i.e. Asynchronous FIFO).
Specs are:
- Reconfigurable memory width and depth
- Infers block ram resource of the FPGA
- Provides data count of the words available for reading. Sync to either read/write clock domains
- Read mode is First-Word Fall-Through
- Reset type is asynchronous
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