Pipeline Registers Missing Connections

[varshinipshetty]

The ID/EX, EX/MEM, and MEM/WB pipeline registers in riscv_core.v have incomplete connections. Many signals are hardcoded to zero instead of being connected to actual module outputs. This prevents proper data flow through the pipeline.
Tags: RTL, bug, pipeline
Files to fix: rtl/top/riscv_core.v