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Fix: ac101 as master, ac108 pll source from ac101 bclk
1 parent 2354856 commit 22f4954

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4 files changed

+63
-35
lines changed

4 files changed

+63
-35
lines changed

‎ac101.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
/*
22
* ac101.c
3+
*
34
* (C) Copyright 2017-2018
45
* Seeed Technology Co., Ltd. <www.seeedstudio.com>
56
*
@@ -554,10 +555,8 @@ int ac101_aif_mute(struct snd_soc_dai *codec_dai, int mute)
554555
ac101_headphone_event(codec, SND_SOC_DAPM_PRE_PMD);
555556
late_enable_dac(codec, SND_SOC_DAPM_POST_PMD);
556557

557-
#if _MASTER_MULTI_CODEC != _MASTER_AC101
558558
ac10x->aif1_clken = 1;
559559
ac101_aif1clk(codec, SND_SOC_DAPM_POST_PMD);
560-
#endif
561560
}
562561
return 0;
563562
}
@@ -847,8 +846,10 @@ static int ac101_set_clock(int y_start_n_stop) {
847846
/* enable global clock */
848847
ac101_aif1clk(static_ac10x->codec, SND_SOC_DAPM_PRE_PMU);
849848
} else {
849+
#if 0
850850
static_ac10x->aif1_clken = 1;
851851
ac101_aif1clk(static_ac10x->codec, SND_SOC_DAPM_POST_PMD);
852+
#endif
852853
}
853854
return 0;
854855
}

‎ac101_regs.h

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,12 @@
11
/*
2-
* sound\soc\sunxi\virtual_audio\ac100.h
3-
* (C) Copyright 2010-2016
2+
* ac101_regs.h
3+
*
4+
* (C) Copyright 2017-2018
5+
* Seeed Technology Co., Ltd. <www.seeedstudio.com>
6+
*
7+
* PeterYang <linsheng.yang@seeed.cc>
8+
*
9+
* (C) Copyright 2010-2017
410
* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
511
* huangxin <huangxin@reuuimllatech.com>
612
*

‎ac108.c

Lines changed: 43 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -94,17 +94,17 @@ static const struct pll_div ac108_pll_div_list[] = {
9494
{ 800000, _FREQ_24_576K, 0, 0, 614, 9, 1 },
9595
{ 1024000, _FREQ_24_576K, 0, 0, 480, 9, 1 }, //_FREQ_24_576K/24
9696
{ 1600000, _FREQ_24_576K, 0, 0, 307, 9, 1 },
97-
{ 2048000, _FREQ_24_576K, 0, 0, 240, 9, 1 }, //_FREQ_24_576K/12
98-
{ 3072000, _FREQ_24_576K, 0, 0, 160, 9, 1 }, //_FREQ_24_576K/8
99-
{ 4096000, _FREQ_24_576K, 2, 0, 360, 9, 1 }, //_FREQ_24_576K/6
97+
{ 2048000, _FREQ_24_576K, 0, 0, 240, 9, 1 }, /* accurate, 8000 * 256 */
98+
{ 3072000, _FREQ_24_576K, 0, 0, 160, 9, 1 }, /* accurate, 12000 * 256 */
99+
{ 4096000, _FREQ_24_576K, 2, 0, 360, 9, 1 }, /* accurate, 16000 * 256 */
100100
{ 6000000, _FREQ_24_576K, 4, 0, 410, 9, 1 },
101101
{ 12000000, _FREQ_24_576K, 9, 0, 410, 9, 1 },
102102
{ 13000000, _FREQ_24_576K, 8, 0, 340, 9, 1 },
103103
{ 15360000, _FREQ_24_576K, 12, 0, 415, 9, 1 },
104104
{ 16000000, _FREQ_24_576K, 12, 0, 400, 9, 1 },
105105
{ 19200000, _FREQ_24_576K, 15, 0, 410, 9, 1 },
106106
{ 19680000, _FREQ_24_576K, 15, 0, 400, 9, 1 },
107-
{ 24000000, _FREQ_24_576K, 4, 0, 128,24, 0 }, //accurate
107+
{ 24000000, _FREQ_24_576K, 4, 0, 128,24, 0 }, // accurate, 24M -> 24.576M */
108108

109109
{ 400000, _FREQ_22_579K, 0, 0, 566, 4, 1 },
110110
{ 512000, _FREQ_22_579K, 0, 0, 880, 9, 1 },
@@ -122,13 +122,12 @@ static const struct pll_div ac108_pll_div_list[] = {
122122
{ 16000000, _FREQ_22_579K, 11, 0, 340, 9, 1 },
123123
{ 19200000, _FREQ_22_579K, 13, 0, 330, 9, 1 },
124124
{ 19680000, _FREQ_22_579K, 14, 0, 345, 9, 1 },
125-
{ 24000000, _FREQ_22_579K, 24, 0, 588,24, 0 }, // accurate
125+
{ 24000000, _FREQ_22_579K, 24, 0, 588,24, 0 }, // accurate, 24M -> 22.5792M */
126126

127-
{ 12288000, _FREQ_24_576K, 9, 0, 400, 9, 1 }, //_FREQ_24_576K/2
128-
{ 11289600, _FREQ_22_579K, 9, 0, 400, 9, 1 }, //_FREQ_22_579K/2
129127

130128
{ _FREQ_24_576K / 1, _FREQ_24_576K, 9, 0, 200, 9, 1 }, //_FREQ_24_576K
131-
{ _FREQ_24_576K / 4, _FREQ_24_576K, 4, 0, 400, 9, 1 }, //6144000
129+
{ _FREQ_24_576K / 2, _FREQ_24_576K, 9, 0, 400, 9, 1 }, /*12288000,accurate, 48000 * 256 */
130+
{ _FREQ_24_576K / 4, _FREQ_24_576K, 4, 0, 400, 9, 1 }, /*6144000, accurate, 24000 * 256 */
132131
{ _FREQ_24_576K / 16, _FREQ_24_576K, 0, 0, 320, 9, 1 }, //1536000
133132
{ _FREQ_24_576K / 64, _FREQ_24_576K, 0, 0, 640, 4, 1 }, //384000
134133
{ _FREQ_24_576K / 96, _FREQ_24_576K, 0, 0, 960, 4, 1 }, //256000
@@ -137,7 +136,8 @@ static const struct pll_div ac108_pll_div_list[] = {
137136
{ _FREQ_24_576K / 192, _FREQ_24_576K, 0, 0, 960, 4, 0 }, //128000
138137

139138
{ _FREQ_22_579K / 1, _FREQ_22_579K, 9, 0, 200, 9, 1 }, //_FREQ_22_579K
140-
{ _FREQ_22_579K / 4, _FREQ_22_579K, 4, 0, 400, 9, 1 }, //5644800
139+
{ _FREQ_22_579K / 2, _FREQ_22_579K, 9, 0, 400, 9, 1 }, /*11289600,accurate, 44100 * 256 */
140+
{ _FREQ_22_579K / 4, _FREQ_22_579K, 4, 0, 400, 9, 1 }, /*5644800, accurate, 22050 * 256 */
141141
{ _FREQ_22_579K / 16, _FREQ_22_579K, 0, 0, 320, 9, 1 }, //1411200
142142
{ _FREQ_22_579K / 64, _FREQ_22_579K, 0, 0, 640, 4, 1 }, //352800
143143
{ _FREQ_22_579K / 96, _FREQ_22_579K, 0, 0, 960, 4, 1 }, //235200
@@ -146,7 +146,7 @@ static const struct pll_div ac108_pll_div_list[] = {
146146
{ _FREQ_22_579K / 192, _FREQ_22_579K, 0, 0, 960, 4, 0 }, //117600
147147

148148
{ _FREQ_22_579K / 6, _FREQ_22_579K, 2, 0, 360, 9, 1 }, //3763200
149-
{ _FREQ_22_579K / 8, _FREQ_22_579K, 0, 0, 160, 9, 1 }, //2822400
149+
{ _FREQ_22_579K / 8, _FREQ_22_579K, 0, 0, 160, 9, 1 }, /*2822400, accurate, 11025 * 256 */
150150
{ _FREQ_22_579K / 12, _FREQ_22_579K, 0, 0, 240, 9, 1 }, //1881600
151151
{ _FREQ_22_579K / 24, _FREQ_22_579K, 0, 0, 480, 9, 1 }, //940800
152152
{ _FREQ_22_579K / 32, _FREQ_22_579K, 0, 0, 640, 9, 1 }, //705600
@@ -510,14 +510,26 @@ static void ac108_configure_power(struct ac10x_priv *ac10x) {
510510
*
511511
* @return int : fail or success
512512
*/
513-
static int ac108_configure_clocking(struct ac10x_priv *ac10x, unsigned int rate) {
513+
static int ac108_config_pll(struct ac10x_priv *ac10x, unsigned rate, unsigned lrck_ratio) {
514514
unsigned int i = 0;
515515
struct pll_div ac108_pll_div = { 0 };
516516

517517
if (ac10x->clk_id == SYSCLK_SRC_PLL) {
518+
unsigned pll_src, pll_freq_in;
519+
520+
if (lrck_ratio == 0) {
521+
/* PLL clock source from MCLK */
522+
pll_freq_in = ac10x->sysclk;
523+
pll_src = 0x0;
524+
} else {
525+
/* PLL clock source from BCLK */
526+
pll_freq_in = rate * lrck_ratio;
527+
pll_src = 0x1;
528+
}
529+
518530
/* FOUT =(FIN * N) / [(M1+1) * (M2+1)*(K1+1)*(K2+1)] */
519531
for (i = 0; i < ARRAY_SIZE(ac108_pll_div_list); i++) {
520-
if (ac108_pll_div_list[i].freq_in == ac10x->sysclk && ac108_pll_div_list[i].freq_out % rate == 0) {
532+
if (ac108_pll_div_list[i].freq_in == pll_freq_in && ac108_pll_div_list[i].freq_out % rate == 0) {
521533
ac108_pll_div = ac108_pll_div_list[i];
522534
dev_dbg(&ac10x->i2c[_MASTER_INDEX]->dev, "AC108 PLL freq_in match:%u, freq_out:%u\n\n",
523535
ac108_pll_div.freq_in, ac108_pll_div.freq_out);
@@ -534,21 +546,21 @@ static int ac108_configure_clocking(struct ac10x_priv *ac10x, unsigned int rate)
534546

535547
/*0x18: PLL clk lock enable*/
536548
ac108_multi_update_bits(PLL_LOCK_CTRL, 0x1 << PLL_LOCK_EN, 0x1 << PLL_LOCK_EN, ac10x);
549+
537550
/*0x10: PLL Common voltage Enable, PLL Enable,PLL loop divider factor detection enable*/
538551
ac108_multi_update_bits(PLL_CTRL1, 0x01 << PLL_EN | 0x01 << PLL_COM_EN | 0x01 << PLL_NDET,
539552
0x01 << PLL_EN | 0x01 << PLL_COM_EN | 0x01 << PLL_NDET, ac10x);
540553

541554
/**
542-
* 0x20: enable pll,pll source from mclk, sysclk source from
543-
* pll,enable sysclk
555+
* 0x20: enable pll, pll source from mclk/bclk, sysclk source from pll, enable sysclk
544556
*/
545-
ac108_multi_update_bits(SYSCLK_CTRL, 0x01 << PLLCLK_EN | 0x03 << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN,
546-
0x01 << PLLCLK_EN | 0x00 << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
557+
ac108_multi_update_bits(SYSCLK_CTRL, 0x01 << PLLCLK_EN | 0x03 << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN,
558+
0x01 << PLLCLK_EN |pll_src<< PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
547559
ac10x->mclk = ac108_pll_div.freq_out;
548560
}
549561
if (ac10x->clk_id == SYSCLK_SRC_MCLK) {
550562
/**
551-
*0x20: sysclk source from mclk,enable sysclk
563+
*0x20: sysclk source from mclk, enable sysclk
552564
*/
553565
ac108_multi_update_bits(SYSCLK_CTRL, 0x01 << PLLCLK_EN | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN,
554566
0x00 << PLLCLK_EN | 0x00 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
@@ -688,7 +700,7 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
688700
return -EINVAL;
689701
}
690702

691-
if (channels == 8 && ac108_sample_rate[rate].real_val == 96000) {
703+
if (channels == 8 && ac108_sample_rate[rate].real_val == 96000) {
692704
/* 24.576M bit clock is not support by ac108 */
693705
return -EINVAL;
694706
}
@@ -749,8 +761,13 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
749761
* ADC Sample Rate synchronised with I2S1 clock zone
750762
*/
751763
ac108_multi_update_bits(ADC_SPRC, 0x0f << ADC_FS_I2S1, ac108_sample_rate[rate].reg_val << ADC_FS_I2S1, ac10x);
752-
ac108_multi_write(HPF_EN,0x0f,ac10x);
753-
ac108_configure_clocking(ac10x, ac108_sample_rate[rate].real_val);
764+
ac108_multi_write(HPF_EN, 0x0F, ac10x);
765+
766+
if (ac10x->i2c101 && _MASTER_MULTI_CODEC == _MASTER_AC101) {
767+
ac108_config_pll(ac10x, ac108_sample_rate[rate].real_val, ac108_samp_res[samp_res].real_val * channels);
768+
} else {
769+
ac108_config_pll(ac10x, ac108_sample_rate[rate].real_val, 0);
770+
}
754771

755772
/*
756773
* master mode only
@@ -761,7 +778,7 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
761778
break;
762779
}
763780
}
764-
ac108_multi_update_bits(I2S_BCLK_CTRL, 0x0F << BCLKDIV, i << BCLKDIV, ac10x);
781+
ac108_multi_update_bits(I2S_BCLK_CTRL, 0x0F << BCLKDIV, i << BCLKDIV, ac10x);
765782

766783
/*
767784
* slots allocation for each chip
@@ -818,7 +835,7 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
818835

819836
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
820837
case SND_SOC_DAIFMT_CBM_CFM: /*AC108 Master*/
821-
if (ac10x->tdm_chips_cnt < 2 || _MASTER_MULTI_CODEC == _MASTER_AC108) {
838+
if (! ac10x->i2c101 || _MASTER_MULTI_CODEC == _MASTER_AC108) {
822839
dev_dbg(dai->dev, "AC108 set to work as Master\n");
823840
/**
824841
* 0x30:chip is master mode ,BCLK & LRCK output
@@ -961,7 +978,6 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
961978
/*
962979
* due to miss channels order in cpu_dai, we meed defer the clock starting.
963980
*/
964-
#if _MASTER_MULTI_CODEC == _MASTER_AC108
965981
static int ac108_set_clock(int y_start_n_stop) {
966982
u8 r;
967983

@@ -988,7 +1004,6 @@ static int ac108_set_clock(int y_start_n_stop) {
9881004

9891005
return 0;
9901006
}
991-
#endif
9921007

9931008
static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
9941009
struct snd_soc_dai *dai)
@@ -1375,12 +1390,12 @@ static int ac108_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *i
13751390
}
13761391

13771392
__ret:
1378-
/* when all i2c prepared, we bind codec to i2c[_MASTER_INDEX] */
1393+
/* It's time to bind codec to i2c[_MASTER_INDEX] when all i2c are ready */
13791394
if ((ac10x->codec_cnt != 0 && ac10x->tdm_chips_cnt < 2)
13801395
|| (ac10x->i2c[0] && ac10x->i2c[1] && ac10x->i2c101)) {
1381-
#if _MASTER_MULTI_CODEC == _MASTER_AC108
1382-
asoc_simple_card_register_set_clock(ac108_set_clock);
1383-
#endif
1396+
if (! ac10x->i2c101 || _MASTER_MULTI_CODEC == _MASTER_AC108) {
1397+
asoc_simple_card_register_set_clock(ac108_set_clock);
1398+
}
13841399
/* no playback stream */
13851400
if (! ac10x->i2c101) {
13861401
memset(&ac108_dai[_MASTER_INDEX]->playback, '\0', sizeof ac108_dai[_MASTER_INDEX]->playback);

‎ac10x.h

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,12 @@
11
/*
2-
* sound\soc\sunxi\virtual_audio\ac100.h
3-
* (C) Copyright 2010-2016
2+
* ac10x.h
3+
*
4+
* (C) Copyright 2017-2018
5+
* Seeed Technology Co., Ltd. <www.seeedstudio.com>
6+
*
7+
* PeterYang <linsheng.yang@seeed.cc>
8+
*
9+
* (C) Copyright 2010-2017
410
* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
511
* huangxin <huangxin@reuuimllatech.com>
612
*
@@ -18,7 +24,7 @@
1824
#define AC101_I2C_ID 4
1925
#define _MASTER_AC108 0
2026
#define _MASTER_AC101 1
21-
#define _MASTER_MULTI_CODEC _MASTER_AC108
27+
#define _MASTER_MULTI_CODEC _MASTER_AC101
2228

2329
#ifdef AC101_DEBG
2430
#define AC101_DBG(format,args...) printk("[AC101] "format,##args)

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