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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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- #undef DEBUG
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+
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+ /* #undef DEBUG
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+ * use 'make DEBUG=1' to enable debugging
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+ */
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
@@ -547,10 +550,6 @@ static int ac108_config_pll(struct ac10x_priv *ac10x, unsigned rate, unsigned lr
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/*0x18: PLL clk lock enable*/
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ac108_multi_update_bits (PLL_LOCK_CTRL , 0x1 << PLL_LOCK_EN , 0x1 << PLL_LOCK_EN , ac10x );
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- /*0x10: PLL Common voltage Enable, PLL Enable,PLL loop divider factor detection enable*/
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- ac108_multi_update_bits (PLL_CTRL1 , 0x01 << PLL_EN | 0x01 << PLL_COM_EN | 0x01 << PLL_NDET ,
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- 0x01 << PLL_EN | 0x01 << PLL_COM_EN | 0x01 << PLL_NDET , ac10x );
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-
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/**
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* 0x20: enable pll, pll source from mclk/bclk, sysclk source from pll, enable sysclk
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*/
@@ -670,8 +669,8 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
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/* Master mode, to clear cpu_dai fifos, output bclk without lrck */
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ac10x_read (I2S_CTRL , & v , ac10x -> i2cmap [_MASTER_INDEX ]);
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- if (v & (0x02 << LRCK_IOEN )) {
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- ac10x_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN , 0x02 << LRCK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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+ if (v & (0x01 << BCLK_IOEN )) {
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+ ac10x_update_bits (I2S_CTRL , 0x1 << LRCK_IOEN , 0x0 << LRCK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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}
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switch (params_format (params )) {
@@ -792,6 +791,11 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
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*/
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ac108_multi_chips_slots (ac10x , channels );
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+ /*0x21: Module clock enable<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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+ ac108_multi_write (MOD_CLK_EN , 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG , ac10x );
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+ /*0x22: Module reset de-asserted<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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+ ac108_multi_write (MOD_RST_CTRL , 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG , ac10x );
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+
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dev_dbg (dai -> dev , "%s() stream=%s ---\n" , __func__ ,
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snd_pcm_stream_str (substream ));
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@@ -851,7 +855,7 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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ac108_multi_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN ,
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0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN , ac10x );
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/* multi_chips: only one chip set as Master, and the others also need to set as Slave */
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- ac10x_update_bits (I2S_CTRL , 0x3 << LRCK_IOEN , 0x2 << LRCK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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+ ac10x_update_bits (I2S_CTRL , 0x3 << LRCK_IOEN , 0x01 << BCLK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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break ;
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} else {
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/* TODO: Both cpu_dai and codec_dai(AC108) be set as slave in DTS */
@@ -863,8 +867,8 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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* 0x30:chip is slave mode, BCLK & LRCK input,enable SDO1_EN and
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* SDO2_EN, Transmitter Block Enable, Globe Enable
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*/
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- ac108_multi_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN ,
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- 0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN , ac10x );
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+ ac108_multi_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x0 << TXEN | 0x0 << GEN ,
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+ 0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x0 << TXEN | 0x0 << GEN , ac10x );
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break ;
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default :
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pr_err ("AC108 Master/Slave mode config error:%u\n\n" , (fmt & SND_SOC_DAIFMT_MASTER_MASK ) >> 12 );
@@ -930,13 +934,6 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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return - EINVAL ;
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}
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- #if 0
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- /* revert LRCK polarity if it's single chip (master mode) */
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- if (ac10x -> tdm_chips_cnt < 2 ) {
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- lrck_polarity = (lrck_polarity == LRCK_LEFT_HIGH_RIGHT_LOW )?
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- LRCK_LEFT_LOW_RIGHT_HIGH : LRCK_LEFT_HIGH_RIGHT_LOW ;
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- }
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- #endif
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ac108_configure_power (ac10x );
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/**
@@ -987,14 +984,16 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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* due to miss channels order in cpu_dai, we meed defer the clock starting.
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*/
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static int ac108_set_clock (int y_start_n_stop ) {
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+ unsigned long flags ;
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u8 r ;
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dev_dbg (ac10x -> codec -> dev , "%s() L%d start:%d\n" , __func__ , __LINE__ , y_start_n_stop );
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+ spin_lock_irqsave (& ac10x -> lock , flags );
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if (y_start_n_stop ) {
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/* enable lrck clock */
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ac10x_read (I2S_CTRL , & r , ac10x -> i2cmap [_MASTER_INDEX ]);
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- if (r & (0x02 << LRCK_IOEN )) {
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+ if (r & (0x01 << BCLK_IOEN )) {
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ac10x_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN , 0x03 << LRCK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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}
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@@ -1005,10 +1004,11 @@ static int ac108_set_clock(int y_start_n_stop) {
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ac10x_read (I2S_CTRL , & r , ac10x -> i2cmap [_MASTER_INDEX ]);
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if (r & (0x01 << LRCK_IOEN )) {
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ac108_multi_update_bits (I2S_CTRL , 0x1 << TXEN | 0x1 << GEN , 0x1 << TXEN | 0x0 << GEN , ac10x );
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- ac10x_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN , 0x02 << LRCK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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+ ac10x_update_bits (I2S_CTRL , 0x03 << LRCK_IOEN , 0x01 << BCLK_IOEN , ac10x -> i2cmap [_MASTER_INDEX ]);
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ac108_multi_update_bits (I2S_CTRL , 0x1 << TXEN | 0x1 << GEN , 0x1 << TXEN | 0x1 << GEN , ac10x );
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}
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}
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+ spin_unlock_irqrestore (& ac10x -> lock , flags );
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return 0 ;
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}
@@ -1028,6 +1028,7 @@ static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
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{
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struct snd_soc_codec * codec = dai -> codec ;
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struct ac10x_priv * ac10x = snd_soc_codec_get_drvdata (codec );
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+ unsigned long flags ;
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int ret = 0 ;
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u8 r ;
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@@ -1036,10 +1037,12 @@ static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
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snd_pcm_stream_str (substream ),
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cmd );
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+ spin_lock_irqsave (& ac10x -> lock , flags );
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+
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if (ac10x -> i2c101 && _MASTER_MULTI_CODEC == _MASTER_AC101 ) {
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ac101_trigger (substream , cmd , dai );
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if (substream -> stream == SNDRV_PCM_STREAM_PLAYBACK ) {
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- return 0 ;
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+ goto __ret ;
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}
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}
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@@ -1049,27 +1052,39 @@ static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE :
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/* disable global clock if lrck disabled */
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ac10x_read (I2S_CTRL , & r , ac10x -> i2cmap [_MASTER_INDEX ]);
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- if ((r & (0x02 << LRCK_IOEN )) && (r & (0x01 << LRCK_IOEN )) == 0 ) {
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+ if ((r & (0x01 << BCLK_IOEN )) && (r & (0x01 << LRCK_IOEN )) == 0 ) {
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/* disable global clock */
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ac108_multi_update_bits (I2S_CTRL , 0x1 << TXEN | 0x1 << GEN , 0x1 << TXEN | 0x0 << GEN , ac10x );
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}
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- /*0x21: Module clock enable<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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- ac108_multi_write (MOD_CLK_EN , 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG , ac10x );
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-
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- /*0x22: Module reset de-asserted<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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- ac108_multi_write (MOD_RST_CTRL , 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG , ac10x );
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+ /*0x10: PLL Common voltage enable, PLL enable */
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+ ac108_multi_update_bits (PLL_CTRL1 , 0x01 << PLL_EN | 0x01 << PLL_COM_EN ,
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+ 0x01 << PLL_EN | 0x01 << PLL_COM_EN , ac10x );
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+ if (ac10x -> i2c101 && _MASTER_MULTI_CODEC == _MASTER_AC101 ) {
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+ /* enable global clock */
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+ ac108_multi_update_bits (I2S_CTRL , 0x1 << TXEN | 0x1 << GEN , 0x1 << TXEN | 0x1 << GEN , ac10x );
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+ }
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/* delayed clock starting, move to simple_card_trigger() */
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break ;
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case SNDRV_PCM_TRIGGER_STOP :
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case SNDRV_PCM_TRIGGER_SUSPEND :
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH :
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+ /*0x10: PLL Common voltage disable, PLL disable */
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+ ac108_multi_update_bits (PLL_CTRL1 , 0x01 << PLL_EN | 0x01 << PLL_COM_EN ,
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+ 0x00 << PLL_EN | 0x00 << PLL_COM_EN , ac10x );
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+ if (ac10x -> i2c101 && _MASTER_MULTI_CODEC == _MASTER_AC101 ) {
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+ /* disable global clock */
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+ ac108_multi_update_bits (I2S_CTRL , 0x1 << TXEN | 0x1 << GEN , 0x0 << TXEN | 0x0 << GEN , ac10x );
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+ }
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break ;
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default :
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ret = - EINVAL ;
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}
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+ __ret :
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+ spin_unlock_irqrestore (& ac10x -> lock , flags );
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+
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return ret ;
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}
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@@ -1378,6 +1393,9 @@ static int ac108_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *i
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ac10x -> i2c101 = i2c ;
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i2c_set_clientdata (i2c , ac10x );
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ret = ac101_probe (i2c , i2c_id );
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+ if (ret ) {
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+ return ret ;
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+ }
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goto __ret ;
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}
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