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Changelog.md

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2.6.3

  • Added Features
    • None
  • Bugfixes
    • In psi_common_axi_slave_ipif: fixed behavior when writing to memory address if memory is disabled

2.6.2

  • Added Features
    • None
  • Bugfixes
    • In psi_common_i2c_master: replace ranged integers by unsigned numbers and added attribute because of Vivado synthesis error

2.6.1

  • Added Features
    • None
  • Bugfixes
    • In psi_common_i2c_master: Pull CmdRdy low when bus is busy
    • In psi_common_i2c_master: Make sure SDA is always high for at least half an SCL clock cycle

2.6.0

  • Added Features
    • Added psi_common_i2c_master: Multi-master capable I2C master
    • Added psi_common_tdp_ram_be: True dual port RAM with byte enables
  • Bugfixes
    • Fixed bug in psi_common_axi_master_simple that led to errors in simulations (no problen in HW)
  • Others
    • Changed AXI record names in psi_common_axi_pkg to be clear for master and slave ports

2.5.1

  • Added Features
    • None
  • Bugfixes
    • Disable psi_commonaxi_slave_ipif_tb for vivado simulator because it uses constructs not supported by the Vivado simulator

2.5.0

  • Added Features
    • Added functions to psi_common_math_pkg: log2ceil() for real, isLog2()
    • Added dependency resolution script
    • Added psi_common_axi_slave_ipif: Full AXI slave interface for IP-Cores
  • Bugfixes
    • Fixed modelsim call in continuous integration script

2.4.1

  • Added Features
    • None
  • Bugfixes
    • Update PDF Documentation
    • Made compatible with Vivado simulator

2.4.0

  • Added Features
    • Added integer to std_logic converstion to psi_common_logic_pkg
    • Added Last handling to psi_common_wconv_... entities
    • Added full AXI master (incl. unaligned transfers) psi_common_axi_master_full
  • Bugfixes
    • Made All Testbenches compatible with GHDL

2.3.0

  • Added Features
    • Added generator scripts for wrappers to ease usage of psi_common_par_tdm, psi_common_tdm_par, psi_common_simple_cc and psi_common_status_cc
    • Added psi_common_axi_master_simple (AXI-Master, supporting aligned transfers only)
  • Bugfixes
    • None

2.2.0

  • Added Features
    • Added generic to control Rdy-behavior during reset
  • Bugfixes
    • None

2.1.0

  • Added Features
    • Added psi_common_spi_master
    • Added FrequencyVld signals to psi_common_clk_meas
  • Bugfixes
    • Fixed bug for psi_common_strobe_divider Ratio_g=1
  • Documentation
    • Added power point presentation about the library

2.0.0

  • First open-source version (older versions not kept in history)
  • Added Features
    • Added psi_common_bit_cc (double-stage synchronizer including all attributes required)
    • Support GHDL as simulator for regression tests
  • Bugfixes
    • Arbitters (psi_common_arb_priority and psi_common_arb_round_robin) are now also working for size=0
  • Changes that are not reverse compatible
    • Syntax changes for consistency in the following entities
      • psi_common_strobe_divider
      • psi_common_strobe_generator
      • psi_common_tdm_mux
    • Changed RAMs for implementing either read-before-write or write-before-read

1.11.1

  • Added Features
    • None
  • Bugfixes
    • psi_common_tdm_mux did not work correctly if input Vld was not kept asserted during a whole TDM run (i.e. all samples of a TDM run had to arrive back-to-back for the mux to work)
    • psi_common_async_fifo timing optimization (from 1.11.0) did not work for OutRdy asserted when a single input sample arrives

1.11.0

  • Added Features
    • Added clock measurement logic (psi_common_clk_meas)
    • Added pulse shaper (create fixed duration pulse with limited frequency) (psi_common_pulse_shaper)
  • Bugfixes
    • Fixed timing issue in psi_common_async_fifo (Timing was often not met for fast clock speeds)
    • psi_common_multi_pl_stage now also supports the case of 0 pipeline stages

1.10.1

  • Added Features
    • None
  • Bugfixes
    • Fixed bug in simulation script that led to an error message with new PsiSim

1.10.0

  • Added Features
    • Priority Arbieter (psi_common_arb_priority)
    • Round Robin Arbiter (psi_common_arb_round_robin)
    • TDM Mux (psi_common_tdm_mux)
  • Bugfixes
    • None

1.9.0

  • Added Features
    • Added parallel to TDM conversion (psi_common_par_tdm)
    • Added TDM to parallel conversion (psi_common_tdm_par)
  • Bugfixes
    • None

1.8.0

  • Added Features
    • Added psi_common_multi_pl_stage (multiple psi_common_pl_stage in one entity)
    • The ready-path (Rdy-handling) can now optionally be disabled for the pipelilne stages
    • The implementation style of RAMs (block or distributed) is now accessible via Generic
  • Changes
    • FIFOs are now using psi_common_sdp_ram_rbw (instead of psi_common_tdp_ram_rbw) to allow using distributed RAM for memory.
  • Bugfixes
    • None

1.7.0

  • Added Features
    • Added psi_common_wconv_n2xn: width converter N->x*N
    • Added psi_common_wconv_xn2n: width converter x*N->N
    • Added psi_common_sync_cc_n2xn: Clock crossing between synchronous clocks (from N MHz to x*N MHz)
    • Added psi_common_sync_cc_xn2n: Clock crossing between synchronous clocks (from xN MHz to N MHz)
    • Added psi_common_pl_stage: Pipelinestage with handshaking (incl. Back-Pressure handling) that registers all signals in both directions (incl. handshaking signals)
  • Bugfixes
  • None

1.6.0

  • Added Features
    • Added more std_logic_vector array types to psi_common_array_pkg
    • Added bool and string arrays to psi_common_array_pkg
    • Added choose() for string and real to psi_common_math_pkg
  • Bugfixes
    • None

1.5.0

  • Added Features
    • Added psi_common_strobe_generator (configurable frequency pulse generator)
    • Added psi_common_strobe_divider (divide pulse rate)
    • Added psi_common_delay (timing optimal delay using SRLs or BRAMs)
  • Bugfixes
    • Added init values to two-process records in psi_common_fifo_async to prevent Modelsim Warnings

1.4.0

  • Added Features
    • Added single port RAM with byte enables
  • Bugfixes
    • None

1.3.1

  • Added Features
    • None
  • Bugfixes
  • Added missing signals to reset in psi_common_async_fifo.vhd

1.3.0

  • Added Features
    • Added Tick Generator
  • Bugfixes
    • None

1.2.0

  • Added Features
    • Added choose function for integers
  • Bugfixes
    • None

V1.01

  • Added Features
    • Added synchronous FIFO
    • Added separate package for logic functions
    • Added Gray <-> Binary conversions
    • Added asynchronous FIFO
  • Bugfixes
    • Added correct attributes for all double-stage-synchronizers in clock crossings

V1.00

  • First release