deploy: 42ecede

Author: lbnl-atg

_downloads/154749296992c7b81e8456297654299c/block.pdf

@@ -165,8 +165,6 @@ <h2>Marble1<a class="headerlink" href="#marble1" title="Permalink to this headin
 </div>
 <p>Also see <a class="reference external" href="testcase.py">testcase.py</a> for other I2C feature support,
 some of which is specific to either Marble or Marble-Mini.</p>
-<section id="extras">
-<h3>Extras<a class="headerlink" href="#extras" title="Permalink to this heading"></a></h3>
 <p>Two <a class="reference external" href="https://en.wikipedia.org/wiki/Easter%20egg%20%28media%29">Easter eggs</a>:</p>
 <ol class="arabic">
 <li><p>Connect up a user terminal to the third FTDI USB UART port, typically /dev/ttyUSB2,
@@ -193,7 +191,7 @@ <h3>Extras<a class="headerlink" href="#extras" title="Permalink to this heading"
 read out <a class="reference external" href="https://en.wikipedia.org/wiki/NMEA_0183">NMEA</a> position and time,
 use the pps signal to calibrate the on-board crystals,
 and even phase-lock the on-board 125 MHz source to GPS time
-with an additive jitter as little as 10 ns rms.
+with a jitter of under 100 ns.
 Supporting python:</p></li>
 </ol>
 <ul class="simple">
@@ -202,7 +200,6 @@ <h3>Extras<a class="headerlink" href="#extras" title="Permalink to this heading"
 <li><p><a class="reference external" href="lock_vcxo.py">lock_vcxo.py</a></p></li>
 </ul>
 </section>
-</section>
 </section>
 
 

_downloads/40e329b5490cebba08fcd11cb34fbeb7/tuning_dsp4.pdf

@@ -187,7 +187,6 @@ <h2>Description<a class="headerlink" href="#description" title="Permalink to thi
 <div class="line">Evaluating gain at f_s*7/33 using python3:</div>
 <div class="line">from numpy import exp, pi; cut=4; N=2**cut; p=(N-1)/N</div>
 <div class="line">z=exp(2j*pi*7/33); gain=(z-1)/z/(z-p); print(abs(gain))</div>
-<div class="line">1.031390721958454</div>
 </div>
 </div>
 </section>

_downloads/cfdab7f028ba73f6ed1e8eeab0acdc59/physics.pdf

@@ -179,6 +179,17 @@
 <h2>Description<a class="headerlink" href="#description" title="Permalink to this heading"></a></h2>
 <div class="line-block">
 <div class="line"><br /></div>
+<div class="line-block">
+<div class="line">TL;DR</div>
+<div class="line">accumulated += ((constant * signal) &gt;&gt;&gt; downscale) + correction</div>
+<div class="line"><br /></div>
+<div class="line">Multiply a <cite>constant</cite> K to input <cite>signal</cite> and accumulate the result on <cite>enable</cite>.</div>
+<div class="line"><br /></div>
+<div class="line">Notice <cite>downscale</cite>, this is meant to downscale the input into the accumulator</div>
+<div class="line">Useful in times of high “natural” integration gain: like running with a superconducting cavity</div>
+<div class="line"><br /></div>
+<div class="line"><cite>correction</cite> comes from some externally-supplied feedforward, maybe derived from the previous pulse</div>
+</div>
 </div>
 </section>
 <section id="pinout">

_downloads/f3c6280cee31f082c3bf980468c0c3b8/block_mode.pdf

@@ -164,34 +164,36 @@
 <span class="linenos"> 81</span><span class="w">     </span><span class="n">valid4</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="n">valid3</span><span class="p">;</span>
 <span class="linenos"> 82</span><span class="k">end</span>
 <span class="linenos"> 83</span>
-<span class="linenos"> 84</span><span class="c1">// Instantiate half-band filter .. or not</span>
-<span class="linenos"> 85</span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="n">outw</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">d5</span><span class="p">;</span>
-<span class="linenos"> 86</span><span class="kt">wire</span><span class="w"> </span><span class="n">valid5</span><span class="p">;</span>
-<span class="linenos"> 87</span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">delay_v45</span><span class="o">=</span><span class="mh">0</span><span class="p">;</span><span class="w">   </span><span class="c1">// seems half_filter take 4 cycles?</span>
-<span class="linenos"> 88</span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="n">outw</span><span class="o">*</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">delay_d45</span><span class="o">=</span><span class="mh">0</span><span class="p">;</span>
-<span class="linenos"> 89</span><span class="k">generate</span>
-<span class="linenos"> 90</span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">use_hb</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span><span class="o">:</span><span class="w"> </span><span class="n">g_use_hb</span>
-<span class="linenos"> 91</span><span class="w">     </span><span class="n">half_filt</span><span class="w"> </span><span class="p">#(.</span><span class="n">len</span><span class="p">(</span><span class="n">dsr_len</span><span class="p">))</span>
-<span class="linenos"> 92</span><span class="w">             </span><span class="n">hb</span><span class="p">(.</span><span class="n">clk</span><span class="p">(</span><span class="n">clk</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">ind</span><span class="p">(</span><span class="n">d4</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">ing</span><span class="p">(</span><span class="n">valid4</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">outd</span><span class="p">(</span><span class="n">d5</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">outg</span><span class="p">(</span><span class="n">valid5</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">reset</span><span class="p">(</span><span class="n">reset</span><span class="p">));</span>
-<span class="linenos"> 93</span><span class="k">end</span>
-<span class="linenos"> 94</span><span class="k">else</span><span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">use_delay</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span><span class="o">:</span><span class="w"> </span><span class="n">g_use_delay</span>
-<span class="linenos"> 95</span><span class="w">     </span><span class="k">always</span><span class="p">@(</span><span class="k">posedge</span><span class="w"> </span><span class="n">clk</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span>
-<span class="linenos"> 96</span><span class="w">             </span><span class="n">delay_v45</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="p">{</span><span class="n">delay_v45</span><span class="p">[</span><span class="mh">4</span><span class="o">-</span><span class="mh">2</span><span class="o">:</span><span class="mh">0</span><span class="p">],</span><span class="n">valid4</span><span class="p">};</span>
-<span class="linenos"> 97</span><span class="w">             </span><span class="n">delay_d45</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="p">{</span><span class="n">delay_d45</span><span class="p">[</span><span class="n">outw</span><span class="o">*</span><span class="p">(</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="p">)</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">],</span><span class="n">d4</span><span class="p">};</span>
-<span class="linenos"> 98</span>
-<span class="linenos"> 99</span><span class="w">     </span><span class="k">end</span>
-<span class="linenos">100</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">d5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">delay_d45</span><span class="p">[</span><span class="n">outw</span><span class="o">*</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="n">outw</span><span class="o">*</span><span class="p">(</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="p">)];</span>
-<span class="linenos">101</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">valid5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">delay_v45</span><span class="p">[</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="p">];</span>
-<span class="linenos">102</span><span class="k">end</span>
-<span class="linenos">103</span><span class="k">else</span><span class="w"> </span><span class="k">begin</span><span class="o">:</span><span class="w"> </span><span class="n">g_use_short</span>
-<span class="linenos">104</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">d5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">d4</span><span class="p">;</span>
-<span class="linenos">105</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">valid5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">valid4</span><span class="p">;</span>
-<span class="linenos">106</span><span class="k">end</span>
-<span class="linenos">107</span><span class="k">endgenerate</span>
-<span class="linenos">108</span>
-<span class="linenos">109</span><span class="k">assign</span><span class="w"> </span><span class="n">strobe</span><span class="o">=</span><span class="n">valid5</span><span class="p">;</span>
-<span class="linenos">110</span><span class="k">assign</span><span class="w"> </span><span class="n">result</span><span class="o">=</span><span class="n">d5</span><span class="p">;</span>
-<span class="linenos">111</span><span class="k">endmodule</span>
+<span class="linenos"> 84</span><span class="no">`undef</span><span class="w"> </span><span class="n">SAT</span>
+<span class="linenos"> 85</span>
+<span class="linenos"> 86</span><span class="c1">// Instantiate half-band filter .. or not</span>
+<span class="linenos"> 87</span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="n">outw</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">d5</span><span class="p">;</span>
+<span class="linenos"> 88</span><span class="kt">wire</span><span class="w"> </span><span class="n">valid5</span><span class="p">;</span>
+<span class="linenos"> 89</span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">delay_v45</span><span class="o">=</span><span class="mh">0</span><span class="p">;</span><span class="w">   </span><span class="c1">// seems half_filter take 4 cycles?</span>
+<span class="linenos"> 90</span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="n">outw</span><span class="o">*</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">delay_d45</span><span class="o">=</span><span class="mh">0</span><span class="p">;</span>
+<span class="linenos"> 91</span><span class="k">generate</span>
+<span class="linenos"> 92</span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">use_hb</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span><span class="o">:</span><span class="w"> </span><span class="n">g_use_hb</span>
+<span class="linenos"> 93</span><span class="w">     </span><span class="n">half_filt</span><span class="w"> </span><span class="p">#(.</span><span class="n">len</span><span class="p">(</span><span class="n">dsr_len</span><span class="p">))</span>
+<span class="linenos"> 94</span><span class="w">             </span><span class="n">hb</span><span class="p">(.</span><span class="n">clk</span><span class="p">(</span><span class="n">clk</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">ind</span><span class="p">(</span><span class="n">d4</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">ing</span><span class="p">(</span><span class="n">valid4</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">outd</span><span class="p">(</span><span class="n">d5</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">outg</span><span class="p">(</span><span class="n">valid5</span><span class="p">),</span><span class="w"> </span><span class="p">.</span><span class="n">reset</span><span class="p">(</span><span class="n">reset</span><span class="p">));</span>
+<span class="linenos"> 95</span><span class="k">end</span>
+<span class="linenos"> 96</span><span class="k">else</span><span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">use_delay</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span><span class="o">:</span><span class="w"> </span><span class="n">g_use_delay</span>
+<span class="linenos"> 97</span><span class="w">     </span><span class="k">always</span><span class="p">@(</span><span class="k">posedge</span><span class="w"> </span><span class="n">clk</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span>
+<span class="linenos"> 98</span><span class="w">             </span><span class="n">delay_v45</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="p">{</span><span class="n">delay_v45</span><span class="p">[</span><span class="mh">4</span><span class="o">-</span><span class="mh">2</span><span class="o">:</span><span class="mh">0</span><span class="p">],</span><span class="n">valid4</span><span class="p">};</span>
+<span class="linenos"> 99</span><span class="w">             </span><span class="n">delay_d45</span><span class="w"> </span><span class="o">&lt;=</span><span class="w"> </span><span class="p">{</span><span class="n">delay_d45</span><span class="p">[</span><span class="n">outw</span><span class="o">*</span><span class="p">(</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="p">)</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="mh">0</span><span class="p">],</span><span class="n">d4</span><span class="p">};</span>
+<span class="linenos">100</span>
+<span class="linenos">101</span><span class="w">     </span><span class="k">end</span>
+<span class="linenos">102</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">d5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">delay_d45</span><span class="p">[</span><span class="n">outw</span><span class="o">*</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="o">:</span><span class="n">outw</span><span class="o">*</span><span class="p">(</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="p">)];</span>
+<span class="linenos">103</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">valid5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">delay_v45</span><span class="p">[</span><span class="mh">4</span><span class="o">-</span><span class="mh">1</span><span class="p">];</span>
+<span class="linenos">104</span><span class="k">end</span>
+<span class="linenos">105</span><span class="k">else</span><span class="w"> </span><span class="k">begin</span><span class="o">:</span><span class="w"> </span><span class="n">g_use_short</span>
+<span class="linenos">106</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">d5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">d4</span><span class="p">;</span>
+<span class="linenos">107</span><span class="w">     </span><span class="k">assign</span><span class="w"> </span><span class="n">valid5</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">valid4</span><span class="p">;</span>
+<span class="linenos">108</span><span class="k">end</span>
+<span class="linenos">109</span><span class="k">endgenerate</span>
+<span class="linenos">110</span>
+<span class="linenos">111</span><span class="k">assign</span><span class="w"> </span><span class="n">strobe</span><span class="o">=</span><span class="n">valid5</span><span class="p">;</span>
+<span class="linenos">112</span><span class="k">assign</span><span class="w"> </span><span class="n">result</span><span class="o">=</span><span class="n">d5</span><span class="p">;</span>
+<span class="linenos">113</span><span class="k">endmodule</span>
 </pre></div>
 </div>
 </section>