From a667fe7a5d6d5468f177c7ca7221519a13a83550 Mon Sep 17 00:00:00 2001
From: sdmurthy <sdmurthy@lbl.gov>
Date: Mon, 9 Dec 2024 20:29:47 -0800
Subject: [PATCH] gige_top.v: Minor clean-up

---
 projects/comms_top/gige_eth/Makefile   | 2 +-
 projects/comms_top/gige_eth/gige_top.v | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/projects/comms_top/gige_eth/Makefile b/projects/comms_top/gige_eth/Makefile
index f49bab27c..472c28ab5 100644
--- a/projects/comms_top/gige_eth/Makefile
+++ b/projects/comms_top/gige_eth/Makefile
@@ -17,7 +17,7 @@ VERILOG_DEFINE_FLAGS =
 include $(COMMS_TOP_DIR)/rules.mk
 include $(BUILD_DIR)/top_rules.mk
 
-all: gen $(APP_NAME).bit
+all: $(APP_NAME).bit
 
 $(APP_NAME).bit: $(IP_TCL)
 
diff --git a/projects/comms_top/gige_eth/gige_top.v b/projects/comms_top/gige_eth/gige_top.v
index d6d68ab45..aa8f676e8 100644
--- a/projects/comms_top/gige_eth/gige_top.v
+++ b/projects/comms_top/gige_eth/gige_top.v
@@ -59,6 +59,7 @@ module gige_top (
    gtp_sys_clk_mmcm i_gtp_sys_clk_mmcm (
       .clk_in  (sys_clk_fast),
       .sys_clk (sys_clk), // Buffered 50 MHz
+      .reset   (1'b0),
       .locked  ()
    );
 `else