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sdmurthysdmurthy
committed
Merge branch 'master' into cmoc_updates
2 parents c5f6b66 + 06b84d9 commit e110116

37 files changed

+263
-115
lines changed

‎badger/tests/sp605/spartan6_clocks.v

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,7 @@ PLL_ADV #(
9393
.CLKOUT2_DIVIDE(plladv_mult), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE( 0.0), // 200 MHz
9494
.REF_JITTER(0.005),
9595
.COMPENSATION("SYSTEM_SYNCHRONOUS")
96-
)
97-
PLL_ADV_inst (
96+
) PLL_ADV_inst (
9897
.CLKINSEL(1'b1),
9998
.CLKIN1(sysclk_buf),
10099
.CLKOUT0(clk_1x_buf), // 62.5 MHz, 90 degree

‎badger/tests/spi_test.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -428,12 +428,14 @@ def remote_program(s, file_name, ad, size):
428428
f = open(file_name, 'rb')
429429
# assume that '.bin' file size is always less than whole pages
430430
for ba in reversed(range(start_p, stop_p)):
431-
print("block %d" % ba)
431+
print("block %d\r" % ba, end='', flush=True)
432432
f.seek((ba << 8) - ad)
433433
bd = f.read(PAGE)
434434
while not (write_enable(s, True)):
435435
time.sleep(WAIT)
436436
page_program(s, ba << 8, bd)
437+
else:
438+
print('')
437439
f.close()
438440
return
439441

‎board_support/ac701/base.xdc

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,5 @@ set_property -dict "PACKAGE_PIN T24 IOSTANDARD LVCMOS33" [get_ports {LED[1]}]
1515
set_property -dict "PACKAGE_PIN T25 IOSTANDARD LVCMOS33" [get_ports {LED[2]}]
1616
set_property -dict "PACKAGE_PIN R26 IOSTANDARD LVCMOS33" [get_ports {LED[3]}]
1717

18-
set_property -dict "PACKAGE_PIN U4 IOSTANDARD LVCMOS15" [get_ports {RESET}]
19-
2018
# UG471 page 50
21-
set_property INTERNAL_VREF 0.90 [get_banks BANK13]
19+
set_property INTERNAL_VREF 0.90 [get_iobanks 13]

‎dsp/chirp/ramps.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,8 @@ always @(posedge clk) begin
5252
amp_nonzero <= |amp_r;
5353
if (gate) amp_r <= amp_railed ? amp_flat : amp_step;
5454
// amplitude needs to be back to zero when next reset hits
55-
// for robustness to incorrect parameters, force it low
56-
if (reset) amp_r <= 0;
55+
// for robustness to incorrect parameters, force it low
56+
if (reset) amp_r <= 0;
5757
a_warning_r <= reset & amp_nonzero;
5858
end
5959
assign amp = amp_r;

‎dsp/cic_wave_recorder_tb.v

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -184,9 +184,7 @@ module cic_wave_recorder_tb;
184184
.lsb_mask (1),
185185
.buf_stat_w (16),
186186
.buf_auto_flip (1)
187-
)
188-
dut
189-
(
187+
) dut (
190188
.iclk (iclk),
191189
.reset (reset),
192190
.stb_in (ext_trig),

‎dsp/demand_gpt.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ reg gate_check=0;
1515
reg [8:0] count=0; // XXX generous, but not general
1616

1717
always @(posedge clk) begin
18-
gate_check <= gate;
18+
gate_check <= gate;
1919
count <= count + gate;
2020
if (trig && gate_check) begin
2121
time_err_r <= (count+gate) != gpt;

‎dsp/digaree/user_tb.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ always @(posedge sf_clk) begin
9494

9595
if (trig_done && conveyor_cnt < data_len) begin
9696
meas <= conveyor[conveyor_cnt];
97-
conveyor_cnt <= conveyor_cnt + 1;
97+
conveyor_cnt <= conveyor_cnt + 1;
9898
end
9999
end
100100

‎dsp/fchan_subset.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ generate
3131
for (ix=0; ix<len; ix=ix+1) begin
3232
assign keep_use[ix] = keep[len-1-ix];
3333
end
34-
end
34+
end
3535
else begin : G_NKEEP_OLD
3636
for (ix=0; ix<len; ix=ix+1) begin
3737
assign keep_use[ix] = keep[ix];

‎dsp/hosted/phs_avg.v

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@
2828
// real when iq==1 and imaginary when iq==0.
2929

3030
module phs_avg #(
31-
parameter dwi = 17
31+
parameter dwi = 17
3232
) (
3333
input clk, // timespec 6.66 ns
3434
input reset,
@@ -50,11 +50,11 @@ assign ky_addr = iq;
5050
reg signed [dwj-1:0] kx1 = 0, ky1 = 0;
5151
reg signed [(dwi+dwj)-1:0] prod_x = 0, prod_y = 0;
5252
always @(posedge clk) begin
53-
// Delay gains, to multiply I*R
54-
kx1 <= kx;
55-
ky1 <= ky;
56-
prod_x <= x * kx1;
57-
prod_y <= y * ky1;
53+
// Delay gains, to multiply I*R
54+
kx1 <= kx;
55+
ky1 <= ky;
56+
prod_x <= x * kx1;
57+
prod_y <= y * ky1;
5858
end
5959

6060
wire signed [dwi+5:0] xmr = prod_x[(dwi+dwj)-2:dwj-7];
@@ -64,11 +64,11 @@ reg signed [dwi+6:0] sum = 0, sum1 = 0;
6464
reg signed [dwi+7:0] sum_f = 0;
6565
reg signed [dwi+intg_scale:0] intg = 0;
6666
always @(posedge clk) begin
67-
sum <= xmr + ymr;
68-
sum1 <= sum;
69-
sum_f <= sum1 + sum; // 2-tap filter [1, 1]
70-
if (reset) intg <= 0;
71-
else intg <= (sum_f >>> 1) + intg; // Integrator
67+
sum <= xmr + ymr;
68+
sum1 <= sum;
69+
sum_f <= sum1 + sum; // 2-tap filter [1, 1]
70+
if (reset) intg <= 0;
71+
else intg <= (sum_f >>> 1) + intg; // Integrator
7272
end
7373
assign sum_filt = sum_f;
7474
assign z = intg[dwi+intg_scale:intg_scale-1];

‎dsp/iq_deinterleaver_multichannel.v

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,7 @@ module iq_deinterleaver_multichannel #(
2929
.scale_wi (SCALE_WI),
3030
.dwi (DWI),
3131
.davr (DAVR)
32-
)
33-
i_iq_deinterleaver
34-
(
32+
) i_iq_deinterleaver (
3533
.clk (clk),
3634
.scale_in (scale_in),
3735
.iq_data_in (iq_data_in[(ch_id+1)*DWI-1:ch_id*DWI]),

‎dsp/iq_mixer_multichannel.v

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,7 @@ module iq_mixer_multichannel #(
3030
.dwi (DWI),
3131
.davr (DAVR),
3232
.dwlo (DWLO)
33-
)
34-
i_mixer_cos
35-
(
33+
) i_mixer_cos (
3634
.clk (clk),
3735
.adcf (adc[(ch_id+1)*DWI-1: ch_id*DWI]),
3836
.mult (cos),
@@ -44,9 +42,7 @@ module iq_mixer_multichannel #(
4442
.dwi (DWI),
4543
.davr (DAVR),
4644
.dwlo (DWLO)
47-
)
48-
i_mixer_sin
49-
(
45+
) i_mixer_sin (
5046
.clk (clk),
5147
.adcf (adc[(ch_id+1)*DWI-1: ch_id*DWI]),
5248
.mult (sin),

‎fpga_family/mgt/gtp_common_2_50.tcl

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
set cfg_dict {
2+
CONFIG.identical_val_tx_line_rate {2.50}
3+
CONFIG.gt0_val {true}
4+
CONFIG.gt0_val_drp_clock {50}
5+
CONFIG.gt0_val_rx_refclk {REFCLK0_Q0}
6+
CONFIG.gt0_val_tx_refclk {REFCLK0_Q0}
7+
CONFIG.gt0_val_txbuf_en {true}
8+
CONFIG.gt0_val_rxbuf_en {true}
9+
CONFIG.gt0_val_port_rxslide {false}
10+
CONFIG.gt0_usesharedlogic {0}
11+
CONFIG.identical_val_rx_line_rate {2.50}
12+
CONFIG.gt_val_tx_pll {PLL0}
13+
CONFIG.gt_val_rx_pll {PLL1}
14+
CONFIG.identical_val_tx_reference_clock {125.000}
15+
CONFIG.identical_val_rx_reference_clock {125.000}
16+
CONFIG.gt0_val_tx_line_rate {2.50}
17+
CONFIG.gt0_val_tx_data_width {20}
18+
CONFIG.gt0_val_tx_int_datawidth {20}
19+
CONFIG.gt0_val_tx_reference_clock {125.000}
20+
CONFIG.gt0_val_rx_line_rate {2.50}
21+
CONFIG.gt0_val_rx_data_width {20}
22+
CONFIG.gt0_val_rx_int_datawidth {20}
23+
CONFIG.gt0_val_rx_reference_clock {125.000}
24+
CONFIG.gt0_val_cpll_fbdiv {4}
25+
CONFIG.gt0_val_cpll_rxout_div {4}
26+
CONFIG.gt0_val_cpll_txout_div {4}
27+
CONFIG.gt0_val_tx_buffer_bypass_mode {Auto}
28+
CONFIG.gt0_val_txoutclk_source {false}
29+
CONFIG.gt0_val_rx_buffer_bypass_mode {Auto}
30+
CONFIG.gt0_val_rxusrclk {RXOUTCLK}
31+
CONFIG.gt0_val_rxslide_mode {OFF}
32+
CONFIG.gt0_val_port_txbufstatus {true}
33+
CONFIG.gt0_val_port_rxbufstatus {true}
34+
CONFIG.gt0_val_port_rxpmareset {true}
35+
CONFIG.gt0_val_align_mcomma_det {true}
36+
CONFIG.gt0_val_align_pcomma_det {true}
37+
CONFIG.gt0_val_comma_preset {User_defined}
38+
CONFIG.gt0_val_align_pcomma_value {1111110000}
39+
CONFIG.gt0_val_align_mcomma_value {0011001111}
40+
CONFIG.gt0_val_align_comma_enable {1111111111}
41+
CONFIG.gt0_val_align_comma_double {true}
42+
CONFIG.gt0_val_align_comma_word {Two_Byte_Boundaries}
43+
CONFIG.gt0_val_port_rxpcommaalignen {false}
44+
CONFIG.gt0_val_port_rxmcommaalignen {false}
45+
CONFIG.gt0_val_dfe_mode {LPM-Auto}
46+
CONFIG.gt0_val_rx_termination_voltage {Programmable}
47+
CONFIG.gt0_val_rx_cm_trim {800}
48+
CONFIG.gt0_val_port_rxdfereset {true}
49+
CONFIG.gt0_val_pd_trans_time_to_p2 {100}
50+
CONFIG.gt0_val_pd_trans_time_from_p2 {60}
51+
CONFIG.gt0_val_pd_trans_time_non_p2 {25}
52+
}

‎fpga_family/mgt/gtp_ethernet_2_50.tcl

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
set cfg_dict {
2+
CONFIG.identical_val_tx_line_rate {2.50}
3+
CONFIG.gt0_val {true}
4+
CONFIG.gt0_val_drp_clock {50}
5+
CONFIG.gt0_val_rx_refclk {REFCLK0_Q0}
6+
CONFIG.gt0_val_tx_refclk {REFCLK0_Q0}
7+
CONFIG.gt0_val_txbuf_en {true}
8+
CONFIG.gt0_val_rxbuf_en {true}
9+
CONFIG.gt0_val_port_rxslide {false}
10+
CONFIG.gt0_usesharedlogic {0}
11+
CONFIG.identical_val_rx_line_rate {2.50}
12+
CONFIG.gt_val_tx_pll {PLL0}
13+
CONFIG.gt_val_rx_pll {PLL0}
14+
CONFIG.identical_val_tx_reference_clock {125.000}
15+
CONFIG.identical_val_rx_reference_clock {125.000}
16+
CONFIG.gt0_val_tx_line_rate {2.50}
17+
CONFIG.gt0_val_tx_data_width {20}
18+
CONFIG.gt0_val_tx_int_datawidth {20}
19+
CONFIG.gt0_val_tx_reference_clock {125.000}
20+
CONFIG.gt0_val_rx_line_rate {2.50}
21+
CONFIG.gt0_val_rx_data_width {20}
22+
CONFIG.gt0_val_rx_int_datawidth {20}
23+
CONFIG.gt0_val_rx_reference_clock {125.000}
24+
CONFIG.gt0_val_cpll_fbdiv {4}
25+
CONFIG.gt0_val_cpll_rxout_div {4}
26+
CONFIG.gt0_val_cpll_txout_div {4}
27+
CONFIG.gt0_val_tx_buffer_bypass_mode {Auto}
28+
CONFIG.gt0_val_txoutclk_source {false}
29+
CONFIG.gt0_val_rx_buffer_bypass_mode {Auto}
30+
CONFIG.gt0_val_rxusrclk {RXOUTCLK}
31+
CONFIG.gt0_val_rxslide_mode {OFF}
32+
CONFIG.gt0_val_port_txbufstatus {true}
33+
CONFIG.gt0_val_port_rxbufstatus {true}
34+
CONFIG.gt0_val_port_rxpmareset {true}
35+
CONFIG.gt0_val_align_mcomma_det {true}
36+
CONFIG.gt0_val_align_pcomma_det {true}
37+
CONFIG.gt0_val_comma_preset {User_defined}
38+
CONFIG.gt0_val_align_pcomma_value {1111110000}
39+
CONFIG.gt0_val_align_mcomma_value {0011001111}
40+
CONFIG.gt0_val_align_comma_enable {1111111111}
41+
CONFIG.gt0_val_align_comma_double {true}
42+
CONFIG.gt0_val_align_comma_word {Two_Byte_Boundaries}
43+
CONFIG.gt0_val_port_rxpcommaalignen {false}
44+
CONFIG.gt0_val_port_rxmcommaalignen {false}
45+
CONFIG.gt0_val_dfe_mode {LPM-Auto}
46+
CONFIG.gt0_val_rx_termination_voltage {Programmable}
47+
CONFIG.gt0_val_rx_cm_trim {800}
48+
CONFIG.gt0_val_port_rxdfereset {true}
49+
CONFIG.gt0_val_pd_trans_time_to_p2 {100}
50+
CONFIG.gt0_val_pd_trans_time_from_p2 {60}
51+
CONFIG.gt0_val_pd_trans_time_non_p2 {25}
52+
}

‎fpga_family/spartan6/spartan6_clocks.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,7 @@ DCM_SP #(
8282
BUFG bufg125_tx(.I(xclk125_buf), .O(clk_eth));
8383

8484
PLL_ADV #(
85+
.SIM_DEVICE("SPARTAN6"),
8586
.BANDWIDTH("OPTIMIZED"),
8687
.CLKIN1_PERIOD(clkin_period),
8788
.CLKFBOUT_MULT(plladv_mult), // 200x5=1000
@@ -92,8 +93,7 @@ PLL_ADV #(
9293
.CLKOUT2_DIVIDE(plladv_mult), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE( 0.0), // 200 MHz
9394
.REF_JITTER(0.005),
9495
.COMPENSATION("SYSTEM_SYNCHRONOUS")
95-
)
96-
PLL_ADV_inst (
96+
) PLL_ADV_inst (
9797
.CLKINSEL(1'b1),
9898
.CLKIN1(sysclk_buf),
9999
.CLKOUT0(clk_1x_buf), // 62.5 MHz, 90 degree

‎fpga_family/xilinx/xadc_tempvoltmon.v

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -168,8 +168,7 @@ module xadc_tempvoltmon #(
168168
// Simulation attributes: Set for proper simulation behavior
169169
.SIM_DEVICE("7SERIES"), // Select target device (values)
170170
.SIM_MONITOR_FILE("design.txt") // Analog simulation data file name
171-
)
172-
XADC_inst (
171+
) XADC_inst (
173172
// ALARMS: 8-bit (each) output: ALM, OT
174173
.ALM(alm), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
175174
.OT(otemp), // 1-bit output: Over-Temperature alarm

‎localbus/jit_rad_gateway_tb.v

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,14 +6,14 @@ reg lb_clk=0;
66
integer cc;
77
reg fail=0;
88
initial begin
9-
if ($test$plusargs("vcd")) begin
10-
$dumpfile("jit_rad_gateway.vcd");
11-
$dumpvars(5, jit_rad_gateway_tb);
12-
end
13-
for (cc=0; cc<2000; cc=cc+1) begin
14-
#10; lb_clk=1;
15-
#10; lb_clk=0;
16-
end
9+
if ($test$plusargs("vcd")) begin
10+
$dumpfile("jit_rad_gateway.vcd");
11+
$dumpvars(5, jit_rad_gateway_tb);
12+
end
13+
for (cc=0; cc<2000; cc=cc+1) begin
14+
#10; lb_clk=1;
15+
#10; lb_clk=0;
16+
end
1717
$display("%s", fail ? "FAIL" : "PASS");
1818
if (fail) $stop(0);
1919
$finish(0);

‎peripheral_drivers/strobe_gen.v

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,10 @@
22

33
module strobe_gen #(
44
parameter TYPE="RISE_EDGE"
5-
)
6-
(
7-
input I_clk,
8-
input I_signal,
9-
output O_strobe
5+
) (
6+
input I_clk,
7+
input I_signal,
8+
output O_strobe
109
);
1110
reg [1:0] sig_r;
1211
generate
@@ -19,7 +18,7 @@ else
1918
endgenerate
2019

2120
always @(posedge I_clk) begin
22-
sig_r<={sig_r[0],I_signal};
21+
sig_r<={sig_r[0],I_signal};
2322
end
2423
assign O_strobe=(sig_r==2'b01);
2524

‎projects/cmoc_top/bmb7_cu/clocks.v

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,7 @@ PLLE2_BASE #(
4242
.CLKOUT1_DIVIDE(pll_div), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(90.0), // 125 MHz
4343
.REF_JITTER1(0.0),
4444
.STARTUP_WAIT("FALSE")
45-
)
46-
PLLE2_BASE_inst (
45+
) PLLE2_BASE_inst (
4746
.CLKIN1(sysclk_buf),
4847
.CLKOUT0(pll_clk_0), // 125 MHz, 0 degree
4948
.CLKOUT1(pll_clk_90), // 125 MHz, 90 degree

‎projects/comms_top/gige_eth/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ VERILOG_DEFINE_FLAGS =
1717
include $(COMMS_TOP_DIR)/rules.mk
1818
include $(BUILD_DIR)/top_rules.mk
1919

20-
all: gen $(APP_NAME).bit
20+
all: $(APP_NAME).bit
2121

2222
$(APP_NAME).bit: $(IP_TCL)
2323

@@ -35,5 +35,5 @@ ifneq (,$(findstring bit,$(MAKECMDGOALS)))
3535
endif
3636
endif
3737

38-
CLEAN += *.bit ../test/*.dat
38+
CLEAN += *.bit *.bin ../test/*.dat
3939
include $(BUILD_DIR)/bottom_rules.mk

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