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Scattered trivial clean-up, including spelling
No change to function Reduced warnings when processing code with yosys and verilator
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6 files changed

+12
-7
lines changed

6 files changed

+12
-7
lines changed

board_support/zest/zest_if.sv

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,8 @@ interface zest_if (
3535
assign {U2_D1NA, U2_D1NB, U2_D1NC, U2_D1ND} = {U2[14], U2[4], U2[26], U2[11]};
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assign {U2_D1PA, U2_D1PB, U2_D1PC, U2_D1PD} = {U2[17], U2[8], U2[5], U2[12]};
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assign {U2_DCON, U2_DCOP, U2_FCON, U2_FCOP} = {U2[9], U2[15], U2[10], U2[6]};
38-
assign {U3[10], U2[22], U4[26]} = {U2_PDWN, U2_CSB, U2_SCLK};
38+
assign {U2[22], U4[26]} = {U2_CSB, U2_SCLK};
39+
// don't set U3[10] to U2_PDWN, since it's set to U3_PDWN below
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wire U3_D0NA, U3_D0NB, U3_D0NC, U3_D0ND, U3_D0PA, U3_D0PB, U3_D0PC, U3_D0PD,
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U3_D1NA, U3_D1NB, U3_D1NC, U3_D1ND, U3_D1PA, U3_D1PB, U3_D1PC, U3_D1PD,
@@ -77,9 +78,9 @@ interface zest_if (
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wire U18_DOUT_RDY = U18[1];
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assign {U18[0], U18[2], U18[3], U18[4]} = {U18_CLK, U18_CS, U18_DIN, U18_SCLK};
7980

80-
// NOTE: Semantics of PMOD and HDMI connectors are application-dependent and
81+
// NOTE: Semantics of Pmod and HDMI connectors are application-dependent and
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// thus not handled here
82-
// PMOD - J18, J17
83+
// Pmod - J18, J17
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// J19: HDMI
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// U33U1: TPS62110 DC-DC converter

board_support/zest_soc/vita_57.1_pinout.txt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
#from https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html
2-
# compactible with KC705 UG810 Appendix B
3-
# compactible with FMC116_112_user_manual.pdf Table 8.
1+
# from https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html
2+
# compatible with KC705 UG810 Appendix B
3+
# compatible with FMC116_112_user_manual.pdf Table 8
44

55
CLK0_M2C_N H5
66
CLK0_M2C_P H4

fpga_family/xilinx/MMCME2_BASE.v

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,7 @@ module MMCME2_BASE #(
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assign CLKOUT0 = CLKIN1;
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assign CLKOUT1 = CLKIN1;
59+
assign LOCKED = 1;
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// verilator lint_restore
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6162
endmodule // MMCME2_BASE

projects/test_marble_family/first_readout.sh

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ echo "Reading kintex 7 internal temperature for $IP using XADC"
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python3 -m xadctemp -a $IP -p 803
1010
echo "Reading kintex 7 DNA for $IP"
1111
python3 -m leep.cli leep://$IP:803 reg dna_high dna_low
12-
echo "Connect Digilent 8 LED board to PMOD J12 and check if all them blink at different rate"
12+
echo "Connect Digilent 8 LED board to Pmod J12 and check if all them blink at different rate"
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python3 -m leep.cli leep://$IP:803 reg led_user_mode=2
1414
tt=$(mktemp /tmp/quick_XXXXXX)
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python3 -m spi_test --ip $IP --udp 804 --otp --pages=1 --dump $tt

selfclean.sh

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,3 +27,4 @@ make -C serial_io/chitchat clean
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make -C serial_io/EVG_EVR clean
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make -C soc/picorv32/test clean
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make -C fpga_family/xilinx clean
30+
rm -r $(find * -name "__pycache__")

soc/picorv32/gateware/uart_fifo_pack.v

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,9 @@ always @(posedge clk) begin
137137
if (|mem_wstrb && (mem_short_addr==UART_BAUDRATE)) begin
138138
if (mem_wstrb[0]) uprescale[ 7:0] <= mem_wdata[ 7:0];
139139
if (mem_wstrb[1]) uprescale[15:8] <= mem_wdata[15:8];
140+
`ifndef YOSYS
140141
$display("new UART prescale value = 0x%04x", mem_wdata);
142+
`endif
141143
end
142144
// -------------
143145
// --- Reads ---

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