From f5f6bc497ac994df2631d6b3c8d3631b123f671b Mon Sep 17 00:00:00 2001
From: sdmurthy <sdmurthy@lbl.gov>
Date: Mon, 9 Dec 2024 20:51:29 -0800
Subject: [PATCH] Add new tcl script for 2.5 GHz (might not be right), enable
 DOUBLEBIT

---
 fpga_family/mgt/gtp_ethernet_2_50.tcl        | 52 ++++++++++++++++++++
 projects/comms_top/gige_eth/Makefile         |  2 +-
 projects/comms_top/gige_eth/gige_top.v       |  2 +-
 projects/comms_top/gige_eth/gtp_gige_top.tcl |  5 +-
 4 files changed, 58 insertions(+), 3 deletions(-)
 create mode 100644 fpga_family/mgt/gtp_ethernet_2_50.tcl

diff --git a/fpga_family/mgt/gtp_ethernet_2_50.tcl b/fpga_family/mgt/gtp_ethernet_2_50.tcl
new file mode 100644
index 000000000..a44f0dcab
--- /dev/null
+++ b/fpga_family/mgt/gtp_ethernet_2_50.tcl
@@ -0,0 +1,52 @@
+set cfg_dict {
+   CONFIG.identical_val_tx_line_rate       {2.50}
+   CONFIG.gt0_val                          {true}
+   CONFIG.gt0_val_drp_clock                {50}
+   CONFIG.gt0_val_rx_refclk                {REFCLK0_Q0}
+   CONFIG.gt0_val_tx_refclk                {REFCLK0_Q0}
+   CONFIG.gt0_val_txbuf_en                 {true}
+   CONFIG.gt0_val_rxbuf_en                 {true}
+   CONFIG.gt0_val_port_rxslide             {false}
+   CONFIG.gt0_usesharedlogic               {0}
+   CONFIG.identical_val_rx_line_rate       {2.50}
+   CONFIG.gt_val_tx_pll                    {PLL0}
+   CONFIG.gt_val_rx_pll                    {PLL0}
+   CONFIG.identical_val_tx_reference_clock {125.000}
+   CONFIG.identical_val_rx_reference_clock {125.000}
+   CONFIG.gt0_val_tx_line_rate             {2.50}
+   CONFIG.gt0_val_tx_data_width            {20}
+   CONFIG.gt0_val_tx_int_datawidth         {20}
+   CONFIG.gt0_val_tx_reference_clock       {125.000}
+   CONFIG.gt0_val_rx_line_rate             {2.50}
+   CONFIG.gt0_val_rx_data_width            {20}
+   CONFIG.gt0_val_rx_int_datawidth         {20}
+   CONFIG.gt0_val_rx_reference_clock       {125.000}
+   CONFIG.gt0_val_cpll_fbdiv               {4}
+   CONFIG.gt0_val_cpll_rxout_div           {4}
+   CONFIG.gt0_val_cpll_txout_div           {4}
+   CONFIG.gt0_val_tx_buffer_bypass_mode    {Auto}
+   CONFIG.gt0_val_txoutclk_source          {false}
+   CONFIG.gt0_val_rx_buffer_bypass_mode    {Auto}
+   CONFIG.gt0_val_rxusrclk                 {RXOUTCLK}
+   CONFIG.gt0_val_rxslide_mode             {OFF}
+   CONFIG.gt0_val_port_txbufstatus         {true}
+   CONFIG.gt0_val_port_rxbufstatus         {true}
+   CONFIG.gt0_val_port_rxpmareset          {true}
+   CONFIG.gt0_val_align_mcomma_det         {true}
+   CONFIG.gt0_val_align_pcomma_det         {true}
+   CONFIG.gt0_val_comma_preset             {User_defined}
+   CONFIG.gt0_val_align_pcomma_value       {1111110000}
+   CONFIG.gt0_val_align_mcomma_value       {0011001111}
+   CONFIG.gt0_val_align_comma_enable       {1111111111}
+   CONFIG.gt0_val_align_comma_double       {true}
+   CONFIG.gt0_val_align_comma_word         {Two_Byte_Boundaries}
+   CONFIG.gt0_val_port_rxpcommaalignen     {false}
+   CONFIG.gt0_val_port_rxmcommaalignen     {false}
+   CONFIG.gt0_val_dfe_mode                 {LPM-Auto}
+   CONFIG.gt0_val_rx_termination_voltage   {Programmable}
+   CONFIG.gt0_val_rx_cm_trim               {800}
+   CONFIG.gt0_val_port_rxdfereset          {true}
+   CONFIG.gt0_val_pd_trans_time_to_p2      {100}
+   CONFIG.gt0_val_pd_trans_time_from_p2    {60}
+   CONFIG.gt0_val_pd_trans_time_non_p2     {25}
+}
diff --git a/projects/comms_top/gige_eth/Makefile b/projects/comms_top/gige_eth/Makefile
index 472c28ab5..bd8c5a312 100644
--- a/projects/comms_top/gige_eth/Makefile
+++ b/projects/comms_top/gige_eth/Makefile
@@ -35,5 +35,5 @@ ifneq (,$(findstring bit,$(MAKECMDGOALS)))
     endif
 endif
 
-CLEAN += *.bit ../test/*.dat
+CLEAN += *.bit *.bin ../test/*.dat
 include $(BUILD_DIR)/bottom_rules.mk
diff --git a/projects/comms_top/gige_eth/gige_top.v b/projects/comms_top/gige_eth/gige_top.v
index aa8f676e8..7694c8032 100644
--- a/projects/comms_top/gige_eth/gige_top.v
+++ b/projects/comms_top/gige_eth/gige_top.v
@@ -29,7 +29,7 @@ module gige_top (
 
    localparam IPADDR   = {8'd192, 8'd168, 8'd1, 8'd179};
    localparam MACADDR  = 48'h00105ad155b5;
-   localparam DOUBLEBIT = 0;  // DOUBLEBIT = 1 fails hardware test
+   localparam DOUBLEBIT = 1;  // XXX DOUBLEBIT = 1 fails hardware test
 
 `define AC701
 `ifdef AC701
diff --git a/projects/comms_top/gige_eth/gtp_gige_top.tcl b/projects/comms_top/gige_eth/gtp_gige_top.tcl
index 555566e00..d3fba338a 100644
--- a/projects/comms_top/gige_eth/gtp_gige_top.tcl
+++ b/projects/comms_top/gige_eth/gtp_gige_top.tcl
@@ -31,7 +31,10 @@ set gt 0
 set en8b10b 0
 set endrp 0
 set pll_type "PLL0"
-add_gt_protocol $gt_type $MGT_CONFIG_DIR/gtp_ethernet.tcl $quad $gt $en8b10b $endrp $pll_type
+# Stupid but working with 62.5 MHz clk:
+# add_gt_protocol $gt_type $MGT_CONFIG_DIR/gtp_ethernet.tcl $quad $gt $en8b10b $endrp $pll_type
+# for DOUBLEBIT experiments:
+add_gt_protocol $gt_type $MGT_CONFIG_DIR/gtp_ethernet_2_50.tcl $quad $gt $en8b10b $endrp $pll_type
 
 # proc add_aux_ip {ipname config_file module_name}
 add_aux_ip clk_wiz $MGT_CONFIG_DIR/mgt_eth_clk.tcl mgt_eth_mmcm