From fd9c45ec0257c4c809712e394a00f705b08de101 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Thu, 3 Oct 2024 13:47:16 -0700 Subject: [PATCH] Fuss with localbus/README.md Explain write-side CDC, and give a bit more info about tgen --- localbus/README.md | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/localbus/README.md b/localbus/README.md index 15b2102f67..35c44a3a2e 100644 --- a/localbus/README.md +++ b/localbus/README.md @@ -17,13 +17,29 @@ Our use case covers real-time on-chip communication, where cycle counts are well-defined and set at configuration/synthesis time, _not_ run-time. -The key component held here is -Just In Time Readout Across Domains - [jit_rad](jit_rad.md) for short. - -Also +Components held here are +- Just In Time Readout Across Domains - [jit_rad](jit_rad.md) for short. - localbus.vh, a helper for cycle-accurate bus simulations - gen_regmap.py -- the much-maligned tgen +- the much-maligned tgen, a general-purpose real-time write sequencer, + constructed as a localbus interposer; + has support in leep as assemble_tgen() and tgen_reg_sequence() + +As the jit_rad documentation explains, it's easy to shift the *write* +side of a localbus to a different clock domain. Throughput is not affected, +and the additional latency and jitter are typically irrelevant +compared to what goes on in the software and LASS host computer. +Here are the typical few lines of Verilog we use to accomplish this +clock domain shift (extracted from cmoc/cryomodule.v): +``` +wire [31:0] clk1x_data; +wire [16:0] clk1x_addr; +wire clk1x_write; +// Transfer local bus to clk1x domain +data_xdomain #(.size(32+17)) lb_to_1x( +.clk_in(lb_clk), .gate_in(lb_write), .data_in({lb_addr,lb_data}), +.clk_out(clk1x), .gate_out(clk1x_write), .data_out({clk1x_addr,clk1x_data})); +``` Also see - [Memory gateway timing](../badger/doc/mem_gateway.svg)