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\section{Abstract}
Recent breakthroughs in machine learning, especially in the field of multi layer convolutional networks(CNNs) have
led to major improvements in the accuracy, speed and versatility of non-trivial image recognition. However the
execution time on regular CPU architectures has proven to be a major roadblock for the wide adoption of CNN technology. 
We believe that a combination of a energy efficient RISC-V processor and our GEMM
acceleration cores could yield a speed increase of multiple magnitudes while preserving a low energy budget which 
would even allow energy constrained applications like embedded devices to profit of state-of-the-art machine
learning. The RISC-V processor would interface with the acceleration cores through our proposed RISC-V extension.
This would enable hardware manufacturers to change the implementation of their accelerators while keeping compatibility
with older software.

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\section{Background}

\begin{figure*}[b]
    \centering
    \includegraphics[width=\textwidth]{Typical_cnn.png}
    \caption{Fig.1: Example of a CNN for image classification. Image source: \cite{CNN_example}}
\end{figure*}
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\bibitem{CNN_example}
By Aphex34 - Own work, CC BY-SA 4.0, \texttt{https://commons.wikimedia.org/w/index.php?curid=45679374}

\end{thebibliography}