-
Notifications
You must be signed in to change notification settings - Fork 0
/
forth-gem5.patch
4396 lines (4165 loc) · 172 KB
/
forth-gem5.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
diff --git a/SConstruct b/SConstruct
index 39e7ccc065..30149a2c6d 100755
--- a/SConstruct
+++ b/SConstruct
@@ -387,10 +387,23 @@ if main['GCC'] or main['CLANG']:
# Treat warnings as errors but white list some warnings that we
# want to allow (e.g., deprecation warnings).
+
main.Append(CCFLAGS=['-Werror',
'-Wno-error=deprecated-declarations',
'-Wno-error=deprecated',
- ])
+ '-Wno-error=cpp',
+ #'-march=native',
+ #'-O3',
+ ])
+
+ #main.Append(CXXFLAGS=['-Werror',
+ # '-Wno-error=deprecated-declarations',
+ # '-Wno-error=deprecated',
+ # '-Wno-error=cpp',
+ # '-march=native',
+ # '-O3',
+ # ])
+
else:
print(termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal, end=' ')
print("Don't know what compiler options to use for your compiler.")
@@ -633,6 +646,7 @@ else:
'Warning: pkg-config could not get protobuf flags.' +
termcap.Normal)
+main['PROTOC'] = False
# Check for 'timeout' from GNU coreutils. If present, regressions will
# be run with a time limit. We require version 8.13 since we rely on
diff --git a/configs/boot/hack_back_ckpt.rcS b/configs/boot/hack_back_ckpt.rcS
index 4c38a4d325..a7bc6cfe26 100644
--- a/configs/boot/hack_back_ckpt.rcS
+++ b/configs/boot/hack_back_ckpt.rcS
@@ -31,6 +31,7 @@ else
/sbin/m5 exit
fi
+sleep 5
# Checkpoint the first execution
echo "Checkpointing simulation..."
/sbin/m5 checkpoint
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index f705ab09a5..f44d9ab250 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -77,6 +77,24 @@ def config_cache(options, system):
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache
+ elif options.cpu_type == "ARM_Cortex_A76":
+ try:
+ import cores.arm.ARM_Cortex_A76 as core
+ except:
+ print("ARM_Cortex_A76 is unavailable")
+ sys.exit(1)
+ print("Selected A76")
+ dcache_class, icache_class, l2_cache_class, walk_cache_class = \
+ core.A76_L1D, core.A76_L1I, core.A76_L2, core.A76_WalkCache
+ elif options.cpu_type == "R_CPU":
+ try:
+ import cores.arm.R_CPU as core
+ except:
+ print("R_CPU is unavailable.")
+ sys.exit(1)
+ print("Selected R_CPU core")
+ dcache_class, icache_class, l2_cache_class, walk_cache_class = \
+ core.R_CPU_L1D, core.R_CPU_L1I, core.R_CPU_L2, core.R_CPU_WalkCache
else:
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 831287ddcd..2c8d30ab50 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -44,6 +44,9 @@ import inspect
import sys
from textwrap import TextWrapper
+# Import to enable the use of ARM cores with fs.py / se.py
+from common.cores.arm import *
+
# Dictionary of mapping names of real CPU models to classes.
_cpu_classes = {}
@@ -78,9 +81,12 @@ def get(name):
try:
cpu_class = _cpu_classes[name]
+ print("Selected CPU class = ", cpu_class)
return cpu_class
except KeyError:
print("%s is not a valid CPU model." % (name,))
+ #Print CPU list in case of error
+ print_cpu_list()
sys.exit(1)
def print_cpu_list():
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 2c90922625..adf36509fe 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -345,6 +345,12 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
self.boot_osflags = fillInCmdline(mdesc, cmdline)
+ # ppetrak: The following is required to successfully boot more than 8 cores
+ # Link:
+ # https://gem5-users.gem5.narkive.com/zLCRsMdq/arm-with-64-cores-fs-hanges
+ #
+ self.realview.gic.gem5_extensions = True
+
if external_memory:
# I/O traffic enters iobus
self.external_io = ExternalMaster(port_data="external_io",
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 3910cacbd1..03c38897dd 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -167,6 +167,8 @@ def config_mem(options, system):
opt_mem_ranks = getattr(options, "mem_ranks", None)
opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
+ # ppetrak: adjust mem type in heterogeneous systems
+ #
if opt_mem_type == "HMC_2500_1x32":
HMChost = HMC.config_hmc_host_ctrl(options, system)
HMC.config_hmc_dev(options, system, HMChost.hmc_host)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index f6fa0d0319..4ca8bccd3e 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -121,8 +121,8 @@ def addNoISAOptions(parser):
parser.add_option("--num-l2caches", type="int", default=1)
parser.add_option("--num-l3caches", type="int", default=1)
parser.add_option("--l1d_size", type="string", default="64kB")
- parser.add_option("--l1i_size", type="string", default="32kB")
- parser.add_option("--l2_size", type="string", default="2MB")
+ parser.add_option("--l1i_size", type="string", default="64kB")
+ parser.add_option("--l2_size", type="string", default="256kB")
parser.add_option("--l3_size", type="string", default="16MB")
parser.add_option("--l1d_assoc", type="int", default=2)
parser.add_option("--l1i_assoc", type="int", default=2)
diff --git a/configs/common/cores/arm/ARM_Cortex_A76.py b/configs/common/cores/arm/ARM_Cortex_A76.py
new file mode 100644
index 0000000000..a9a7a12b01
--- /dev/null
+++ b/configs/common/cores/arm/ARM_Cortex_A76.py
@@ -0,0 +1,223 @@
+# Copyright (c) 2012 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: ICS-FORTH, Polydoros Petrakis <ppetrak@ics.forth.gr>
+# Authors: ICS-FORTH, Vassilis Papaefstathiou <papaef@ics.forth.gr>
+# https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a76
+# https://www.anandtech.com/show/12785/\
+# arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2
+# https://www.anandtech.com/show/12785/\
+# arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from m5.objects import *
+import m5
+m5.util.addToPath('../../')
+from common.Caches import *
+
+#from common import CpuConfig
+#from common import MemConfig
+
+# Simple ALU Instructions have a latency of 1
+class ARM_Cortex_A76_Simple_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
+ count = 3
+
+# Complex ALU instructions have a variable latencies
+class ARM_Cortex_A76_Complex_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
+ OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
+ OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
+ count = 2
+
+# Floating point and SIMD instructions
+class ARM_Cortex_A76_FP(FUDesc):
+ opList = [ OpDesc(opClass='SimdAdd', opLat=4),
+ OpDesc(opClass='SimdAddAcc', opLat=4),
+ OpDesc(opClass='SimdAlu', opLat=4),
+ OpDesc(opClass='SimdCmp', opLat=4),
+ OpDesc(opClass='SimdCvt', opLat=3),
+ OpDesc(opClass='SimdMisc', opLat=3),
+ OpDesc(opClass='SimdMult',opLat=5),
+ OpDesc(opClass='SimdMultAcc',opLat=5),
+ OpDesc(opClass='SimdShift',opLat=3),
+ OpDesc(opClass='SimdShiftAcc', opLat=3),
+ OpDesc(opClass='SimdDiv', opLat=9, pipelined=False),
+ OpDesc(opClass='SimdSqrt', opLat=9),
+ OpDesc(opClass='SimdFloatAdd',opLat=5),
+ OpDesc(opClass='SimdFloatAlu',opLat=5),
+ OpDesc(opClass='SimdFloatCmp', opLat=3),
+ OpDesc(opClass='SimdFloatCvt', opLat=3),
+ OpDesc(opClass='SimdFloatDiv', opLat=3),
+ OpDesc(opClass='SimdFloatMisc', opLat=3),
+ OpDesc(opClass='SimdFloatMult', opLat=3),
+ OpDesc(opClass='SimdFloatMultAcc',opLat=5),
+ OpDesc(opClass='SimdFloatSqrt', opLat=9),
+ OpDesc(opClass='SimdReduceAdd'),
+ OpDesc(opClass='SimdReduceAlu'),
+ OpDesc(opClass='SimdReduceCmp'),
+ OpDesc(opClass='SimdFloatReduceAdd'),
+ OpDesc(opClass='SimdFloatReduceCmp'),
+ OpDesc(opClass='FloatAdd', opLat=5),
+ OpDesc(opClass='FloatCmp', opLat=5),
+ OpDesc(opClass='FloatCvt', opLat=5),
+ OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
+ OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
+ OpDesc(opClass='FloatMult', opLat=4),
+ OpDesc(opClass='FloatMultAcc', opLat=5),
+ OpDesc(opClass='FloatMisc', opLat=3) ]
+ count = 2
+
+# Load/Store Units
+class ARM_Cortex_A76_Load(FUDesc):
+ opList = [ OpDesc(opClass='MemRead'),
+ OpDesc(opClass='FloatMemRead') ]
+ count = 2
+
+class ARM_Cortex_A76_Store(FUDesc):
+ opList = [ OpDesc(opClass='MemWrite'),
+ OpDesc(opClass='FloatMemWrite') ]
+ count = 1
+
+class ARM_Cortex_A76_PredALU(FUDesc):
+ opList = [ OpDesc(opClass='SimdPredAlu') ]
+ count = 1
+
+# Functional Units for this CPU
+class ARM_Cortex_A76_FUP(FUPool):
+ FUList = [ARM_Cortex_A76_Simple_Int(),
+ ARM_Cortex_A76_Complex_Int(),
+ ARM_Cortex_A76_Load(),
+ ARM_Cortex_A76_Store(),
+ ARM_Cortex_A76_PredALU(),
+ ARM_Cortex_A76_FP()]
+
+# Bi-Mode Branch Predictor
+class ARM_Cortex_A76_BP(BiModeBP):
+ globalPredictorSize = 8192
+ globalCtrBits = 2
+ choicePredictorSize = 8192
+ choiceCtrBits = 2
+ BTBEntries = 4096
+ BTBTagSize = 16
+ RASSize = 16
+ instShiftAmt = 2
+
+class ARM_Cortex_A76(DerivO3CPU):
+ LSQDepCheckShift = 0
+ LFSTSize = 1024
+ SSITSize = 1024
+ decodeToFetchDelay = 1
+ renameToFetchDelay = 1
+ iewToFetchDelay = 1
+ commitToFetchDelay = 1
+ renameToDecodeDelay = 1
+ iewToDecodeDelay = 1
+ commitToDecodeDelay = 1
+ iewToRenameDelay = 1
+ commitToRenameDelay = 1
+ commitToIEWDelay = 1
+ fetchWidth = 4
+ fetchBufferSize = 16
+ fetchToDecodeDelay = 1
+ decodeWidth = 4
+ decodeToRenameDelay = 1
+ renameWidth = 4
+ renameToIEWDelay = 1
+ issueToExecuteDelay = 1
+ dispatchWidth = 8
+ issueWidth = 8
+ wbWidth = 8
+ fuPool = ARM_Cortex_A76_FUP()
+ iewToCommitDelay = 1
+ renameToROBDelay = 1
+ commitWidth = 8
+ squashWidth = 8
+ trapLatency = 13
+ backComSize = 5
+ forwardComSize = 5
+ numROBEntries = 192
+ # the default value for numPhysVecPredRegs is 32 in O3 config
+ numPhysVecPredRegs = 64
+ LQEntries = 68
+ SQEntries = 72
+ numIQEntries = 120
+
+ switched_out = False
+ #branchPred = ARM_Cortex_A76_BP()
+ branchPred = Param.BranchPredictor(TournamentBP(
+ numThreads = Parent.numThreads), "Branch Predictor")
+
+# The following lines were copied from file devices.py
+# provided by BSC (and adjusted by FORTH to match A76)
+
+class A76_L1I(L1_ICache):
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 8
+ tgts_per_mshr = 8
+ size = '64kB'
+ assoc = 4
+
+class A76_L1D(L1_DCache):
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 1
+ mshrs = 24
+ tgts_per_mshr = 16
+ size = '64kB'
+ assoc = 4
+ write_buffers = 24
+
+class A76_WalkCache(PageTableWalkerCache):
+ tag_latency = 4
+ data_latency = 4
+ response_latency = 4
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '1kB'
+ assoc = 8
+ write_buffers = 16
+
+class A76_L2(L2Cache):
+ tag_latency = 9
+ data_latency = 9
+ response_latency = 5
+ mshrs = 24
+ tgts_per_mshr = 16
+ write_buffers = 24
+ size = '256kB'
+ assoc = 8
+ clusivity='mostly_incl' #if not LLC
+ prefetch_on_access = True
+ # Simple next line prefetcher
+ # prefetcher = StridePrefetcher(degree=8, latency = 1)
+ prefetcher = TaggedPrefetcher(degree=8, latency = 1, queue_size = 64)
+ #tags = LRU() ## ppetrak: this needs extra imports to work.
+
diff --git a/configs/common/cores/arm/R_CPU.py b/configs/common/cores/arm/R_CPU.py
new file mode 100644
index 0000000000..d09ce5f313
--- /dev/null
+++ b/configs/common/cores/arm/R_CPU.py
@@ -0,0 +1,215 @@
+# Copyright (c) 2012 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: ICS-FORTH, Polydoros Petrakis <ppetrak@ics.forth.gr>
+# Authors: ICS-FORTH, Vassilis Papaefstathiou <papaef@ics.forth.gr>
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from m5.objects import *
+import m5
+m5.util.addToPath('../../')
+from common.Caches import *
+###
+#from common import CpuConfig
+#from common import MemConfig
+
+# Simple ALU Instructions have a latency of 1
+class R_CPU_Simple_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
+ count = 3
+
+# Complex ALU instructions have a variable latencies
+class R_CPU_Complex_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
+ OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
+ OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
+ count = 2
+
+# Floating point and SIMD instructions
+class R_CPU_FP(FUDesc):
+ opList = [ OpDesc(opClass='SimdAdd', opLat=4),
+ OpDesc(opClass='SimdAddAcc', opLat=4),
+ OpDesc(opClass='SimdAlu', opLat=4),
+ OpDesc(opClass='SimdCmp', opLat=4),
+ OpDesc(opClass='SimdCvt', opLat=3),
+ OpDesc(opClass='SimdMisc', opLat=3),
+ OpDesc(opClass='SimdMult',opLat=5),
+ OpDesc(opClass='SimdMultAcc',opLat=5),
+ OpDesc(opClass='SimdShift',opLat=3),
+ OpDesc(opClass='SimdShiftAcc', opLat=3),
+ OpDesc(opClass='SimdDiv', opLat=9, pipelined=False),
+ OpDesc(opClass='SimdSqrt', opLat=9),
+ OpDesc(opClass='SimdFloatAdd',opLat=5),
+ OpDesc(opClass='SimdFloatAlu',opLat=5),
+ OpDesc(opClass='SimdFloatCmp', opLat=3),
+ OpDesc(opClass='SimdFloatCvt', opLat=3),
+ OpDesc(opClass='SimdFloatDiv', opLat=3),
+ OpDesc(opClass='SimdFloatMisc', opLat=3),
+ OpDesc(opClass='SimdFloatMult', opLat=3),
+ OpDesc(opClass='SimdFloatMultAcc',opLat=5),
+ OpDesc(opClass='SimdFloatSqrt', opLat=9),
+ OpDesc(opClass='SimdReduceAdd'),
+ OpDesc(opClass='SimdReduceAlu'),
+ OpDesc(opClass='SimdReduceCmp'),
+ OpDesc(opClass='SimdFloatReduceAdd'),
+ OpDesc(opClass='SimdFloatReduceCmp'),
+ OpDesc(opClass='FloatAdd', opLat=5),
+ OpDesc(opClass='FloatCmp', opLat=5),
+ OpDesc(opClass='FloatCvt', opLat=5),
+ OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
+ OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
+ OpDesc(opClass='FloatMult', opLat=4),
+ OpDesc(opClass='FloatMultAcc', opLat=5),
+ OpDesc(opClass='FloatMisc', opLat=3) ]
+ count = 2
+
+# Load/Store Units
+class R_CPU_Load(FUDesc):
+ opList = [ OpDesc(opClass='MemRead'),
+ OpDesc(opClass='FloatMemRead') ]
+ count = 2
+
+class R_CPU_Store(FUDesc):
+ opList = [ OpDesc(opClass='MemWrite'),
+ OpDesc(opClass='FloatMemWrite') ]
+ count = 1
+
+class R_CPU_PredALU(FUDesc):
+ opList = [ OpDesc(opClass='SimdPredAlu') ]
+ count = 1
+
+# Functional Units for this CPU
+class R_CPU_FUP(FUPool):
+ FUList = [R_CPU_Simple_Int(),
+ R_CPU_Complex_Int(),
+ R_CPU_Load(),
+ R_CPU_Store(),
+ R_CPU_PredALU(),
+ R_CPU_FP()]
+
+# Bi-Mode Branch Predictor
+class R_CPU_BP(BiModeBP):
+ globalPredictorSize = 8192
+ globalCtrBits = 2
+ choicePredictorSize = 8192
+ choiceCtrBits = 2
+ BTBEntries = 4096
+ BTBTagSize = 16
+ RASSize = 16
+ instShiftAmt = 2
+
+class R_CPU(DerivO3CPU):
+ #type='R_CPU'
+ LSQDepCheckShift = 0
+ LFSTSize = 1024
+ SSITSize = 1024
+ decodeToFetchDelay = 1
+ renameToFetchDelay = 1
+ iewToFetchDelay = 1
+ commitToFetchDelay = 1
+ renameToDecodeDelay = 1
+ iewToDecodeDelay = 1
+ commitToDecodeDelay = 1
+ iewToRenameDelay = 1
+ commitToRenameDelay = 1
+ commitToIEWDelay = 1
+ fetchToDecodeDelay = 1
+ decodeToRenameDelay = 1
+ renameWidth = 4
+ renameToIEWDelay = 1
+ issueToExecuteDelay = 1
+ dispatchWidth = 8
+ wbWidth = 8
+ fuPool = R_CPU_FUP()
+ iewToCommitDelay = 1
+ renameToROBDelay = 1
+ commitWidth = 8
+ squashWidth = 8
+ trapLatency = 13
+ backComSize = 5
+ forwardComSize = 5
+ fetchWidth = 4
+ decodeWidth = 4
+ issueWidth = 8
+ numPhysVecPredRegs = 64
+ numPhysVecRegs = 364
+ numIQEntries = 120
+ LQEntries = 96
+ SQEntries = 96
+ fetchBufferSize = 64
+ #fetchQueueSize = 64
+ numROBEntries = 224
+ switched_out = False
+ #branchPred = R_CPU_BP()
+ branchPred = Param.BranchPredictor(TournamentBP(
+ numThreads = Parent.numThreads), "Branch Predictor")
+
+class R_CPU_L1I(L1_ICache):
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 8
+ tgts_per_mshr = 8
+ size = '64kB'
+ assoc = 4
+
+class R_CPU_L1D(L1_DCache):
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 1
+ mshrs = 24
+ tgts_per_mshr = 16
+ size = '64kB'
+ assoc = 4
+ write_buffers = 24
+
+class R_CPU_WalkCache(PageTableWalkerCache):
+ tag_latency = 4
+ data_latency = 4
+ response_latency = 4
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '1kB'
+ assoc = 8
+ write_buffers = 16
+
+class R_CPU_L2(L2Cache):
+ tag_latency = 9
+ data_latency = 9
+ response_latency = 5
+ mshrs = 24
+ tgts_per_mshr = 16
+ write_buffers = 24
+ size = '256kB'
+ assoc = 8
+ clusivity='mostly_incl' #if not LLC
+ prefetch_on_access = True
+ # Simple next line prefetcher
+ # prefetcher = StridePrefetcher(degree=8, latency = 1)
+ prefetcher = TaggedPrefetcher(degree=8, latency = 1, queue_size = 64)
+ #tags = LRU() ## ppetrak: this needs extra imports to work.
diff --git a/configs/example/garnet_synth_traffic.py b/configs/example/garnet_synth_traffic.py
index 9878c23f1c..4e3efe4c3d 100644
--- a/configs/example/garnet_synth_traffic.py
+++ b/configs/example/garnet_synth_traffic.py
@@ -145,7 +145,7 @@ root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')
+m5.ticks.setGlobalFrequency('0.5ns')
# instantiate configuration
m5.instantiate()
diff --git a/configs/example/se.py b/configs/example/se.py
index f43206ad2b..24f7c9b3db 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -110,10 +110,12 @@ def get_processes(options):
process.errout = errouts[idx]
multiprocesses.append(process)
+ #print("Info: Appending workload[%d]: %s" % (idx, wrkld))
idx += 1
if options.smt:
- assert(options.cpu_type == "DerivO3CPU")
+ assert(options.cpu_type == "DerivO3CPU" or \
+ options.cpu_type == "ARM_Cortex_A76" )
return multiprocesses, idx
else:
return multiprocesses, 1
diff --git a/configs/network/Network.py b/configs/network/Network.py
index c1e55bcdc1..2dce885185 100644
--- a/configs/network/Network.py
+++ b/configs/network/Network.py
@@ -25,6 +25,8 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Tushar Krishna
+# Authors: ICS-FORTH, Polydoros Petrakis <ppetrak@ics.forth.gr>
+# Extensions in order to support multiple NoC layers
from __future__ import print_function
from __future__ import absolute_import
@@ -76,6 +78,9 @@ def define_options(parser):
parser.add_option("--garnet-deadlock-threshold", action="store",
type="int", default=50000,
help="network-level deadlock threshold.")
+ parser.add_option("--noc_layers", action="store", type=int,
+ default=6,
+ help="""Number of NoCs (or NoC layers)""")
def create_network(options, ruby):
@@ -114,9 +119,61 @@ def init_network(options, network, InterfaceClass):
if options.network == "simple":
network.setup_buffers()
+ # Define the number of NoC layers
+ # This parameter will be used by the NI class
+ max_layers = options.noc_layers
+
+ print("Info: Number of Ext_links = %d" % len(network.ext_links))
+ print("Info: NoC layers = %d" % max_layers)
+
+ # ppetrak: Adjust the way that the NIs are generated. Generate a single NI
+ # for ext_links/noc_layers instead of one NI for every ext_link
+
+ # ppetrak:
+ # By using offset vnet traffic incoming from a specific vnet (e.g. VNET-0)
+ # can be split into 2 different VNETS ((1) incoming vnet and incoming_vnet + (2) vnet_offset )
+ # Set vnet_offset to a value equal to the number of vnets that each specific CC protocol uses.
+ # offset_vnet = 3 for MOESI_CMP_directory. Set use_offset_vnets = False for disabling this feature.
+
+ MOESI_CMP_directory_offset_vnet = 3
+ use_offset_vnets = False
+
if InterfaceClass != None:
- netifs = [InterfaceClass(id=i) \
- for (i,n) in enumerate(network.ext_links)]
+ netifs = []
+ # In m_id >=32 are given to remaining nodes for Quadrant Topologies with 16 cores / 16 SLC / 8 Dirs
+ if ( use_offset_vnets and
+ (max_layers > MOESI_CMP_directory_offset_vnet ) and
+ (network.topology == "Mesh_EPI_quadrant"
+ or network.topology == "Mesh_EPI_quadrant_p1"
+ or network.topology == "Mesh_EPI_quadrant_p2"
+ or network.topology == "Mesh_EPI_quadrant_p3"
+ or network.topology == "Mesh_EPI_quadrant_p4" )):
+ assert( options.num_dirs == 8 and (options.num_cpus == options.num_l2caches))
+ assert ( max_layers == 2 * MOESI_CMP_directory_offset_vnet )
+
+ for i in range(len(network.ext_links)/max_layers):
+ if(i < options.num_cpus + options.num_l2caches + options.num_dirs ):
+ # Do not offset the first 8 cores, first 8 SLCs, and the 4 even dirs
+ if ( (i < options.num_cpus/2 )
+ or (i >= options.num_cpus and i < options.num_cpus + options.num_l2caches/2)
+ or (i >= options.num_cpus + options.num_l2caches and i%2 == 0) ):
+ t_offset_vnet = 0
+ else:
+ t_offset_vnet = MOESI_CMP_directory_offset_vnet
+ netifs.append(InterfaceClass(id=i, noc_layers = max_layers, offset_vnet = t_offset_vnet))
+ # Extra nodes (io/DMAs etcs)
+ else:
+ t_offset_vnet = 0
+ netifs.append(InterfaceClass(id=i, noc_layers = max_layers, offset_vnet = t_offset_vnet))
+ print('NI[%d], vnet_offset = %d' % (i, t_offset_vnet))
+ else:
+ for i in range(len(network.ext_links)/max_layers):
+ netifs.append(InterfaceClass(id=i, noc_layers = max_layers, offset_vnet = 0))
+
+ #netifs = [InterfaceClass(id=i, noc_layers = max_layers) \
+ # for i in range(len(network.ext_links)/max_layers) ]
+ #[print("Info: NI[%d] (netifs @ Network.py)" % i) \
+ # for i in range(len(network.ext_links)/max_layers) ]
network.netifs = netifs
if options.network_fault_model:
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 18e9ef6c84..1c009f1822 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -138,8 +138,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
-
# Create the L2s interleaved addr ranges
+ # ppetrak: L2 interleaving code
+ #
l2_addr_ranges = []
l2_bits = int(math.log(options.num_l2caches, 2))
numa_bit = block_size_bits + l2_bits - 1
@@ -148,6 +149,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for i in range(options.num_l2caches):
ranges = []
for r in sysranges:
+
addr_range = AddrRange(r.start, size = r.size(),
intlvHighBit = numa_bit,
intlvBits = l2_bits,
@@ -267,6 +269,11 @@ def create_system(options, full_system, system, dma_ports, bootmem,
all_cntrls = all_cntrls + [io_controller]
- ruby_system.network.number_of_virtual_networks = 3
+ if (options.noc_layers > 1):
+ ruby_system.network.number_of_virtual_networks = options.noc_layers
+ else:
+ ruby_system.network.number_of_virtual_networks = 3
+
+
topology = create_topology(all_cntrls, options)
return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 9ec7124df2..85f3ffa5e5 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -40,6 +40,12 @@ from common import FileSystemConfig
#
class L1Cache(RubyCache): pass
class L2Cache(RubyCache): pass
+
+# class L1Cache(RubyCache): #ppetrak
+# dataArrayBanks = 16 #Param.Int(1, "Number of banks for the data array")
+# tagArrayBanks = 16 # Param.Int(1, "Number of banks for the tag array")
+# dataAccessLatency = 1 #Param.Cycles(1, "cycles for a data array access")
+# tagAccessLatency = 1 #Param.Cycles(1, "cycles for a tag array access")
#
# Probe filter is a cache
#
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index c9ae251d91..6fa9ecea1d 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -97,9 +97,11 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
if options.numa_high_bit:
dir_bits = int(math.log(options.num_dirs, 2))
intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
+ # ppetrak: Mem Interleaving step is defined here (num_high_bit)
else:
# if the numa_bit is not specified, set the directory bits as the
# lowest bits above the block offset bits
+ # ppetrak: Mem Interleaving step is defined here (num_high_bit)
intlv_size = options.cacheline_size
# Sets bits to be used for interleaving. Creates memory controllers
diff --git a/configs/topologies/Mesh_EPI_quadrant_p1.py b/configs/topologies/Mesh_EPI_quadrant_p1.py
new file mode 100644
index 0000000000..01fd4d8203
--- /dev/null
+++ b/configs/topologies/Mesh_EPI_quadrant_p1.py
@@ -0,0 +1,332 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# 2016 Georgia Institute of Technology
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+# Tushar Krishna
+# Authors: ICS-FORTH, Polydoros Petrakis <ppetrak@ics.forth.gr>
+# Based on Mesh_XY.py topology file and adjusted
+# in order to support multi-layered NoC
+# Describes a Quadrant Topology
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from m5.params import *
+from m5.objects import *
+
+from common import FileSystemConfig
+
+from .BaseTopology import SimpleTopology
+
+# Creates a generic Mesh
+# and directory controllers.
+# XY routing is enforced (using link weights)
+# to guarantee deadlock freedom.
+
+class Mesh_EPI_quadrant_p1(SimpleTopology):
+ description='Mesh_EPI_quadrant_p1'
+ def __init__(self, controllers):
+ self.nodes = controllers
+
+ # Makes a generic mesh
+ # assuming an equal number of cache and directory cntrls
+
+ def makeTopology(self, options, network, IntLink, ExtLink, Router):
+ nodes = self.nodes
+
+ #ppetrak. The following limitation could be adjusted
+ #num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+ num_routers = num_rows * num_rows
+
+ assert(num_rows == 4)
+
+ # default values for link latency and router latency.
+ # Can be over-ridden on a per link/router basis
+ link_latency = options.link_latency # used by simple and garnet
+ router_latency = options.router_latency # only used by garnet
+
+ print_extra_info = True
+
+ # There must be an evenly divisible number of cntrls to routers
+ # Also, obviously the number or rows must be <= the number of routers
+ cntrls_per_router, remainder = divmod(len(nodes), num_routers)
+ assert(num_rows > 0 and num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+
+ if print_extra_info:
+ print("Info: num_routers (per layer): %d" % (num_routers))
+ #[print("Info: %s" % node) for node in nodes]
+ print("Info: Controllers per router: %d, rows = %d, columns = %d,"
+ " remainder = %d" \
+ % (cntrls_per_router, num_rows, num_columns, remainder))
+
+ # Create the routers in the mesh
+ max_layers = options.noc_layers
+
+ #ppetrak: Adjust (or remove) this if you need to try other CC protocols
+ assert(max_layers == 6 or max_layers == 1 or max_layers == 3)
+
+ routers = [Router(router_id=i, latency = router_latency) \
+ for i in range(num_routers*max_layers)]
+
+ network.routers = routers
+
+ # link counter to set unique link ids
+ link_count = 0
+
+ # Add all but the remainder nodes to the list of nodes to be uniformly
+ # distributed across the network.
+ network_nodes = []
+ remainder_nodes = []
+ l1_nodes = []
+ l2_nodes = []
+ dir_nodes = []
+ for node_index in range(len(nodes)):
+ if print_extra_info:
+ print('Node[%d]: %s' % (node_index, nodes[node_index]))
+
+ if 'dir_cntr' in str(nodes[node_index]):
+ dir_nodes.append(nodes[node_index])
+ elif 'l1_cntrl' in str(nodes[node_index]):
+ l1_nodes.append(nodes[node_index])
+ elif 'l2_cntrl' in str(nodes[node_index]):
+ l2_nodes.append(nodes[node_index])
+ else:
+ if node_index < (len(nodes) - remainder):
+ network_nodes.append(nodes[node_index])
+ else:
+ remainder_nodes.append(nodes[node_index])
+
+ assert(len(l1_nodes) == 8 or len(l1_nodes) == 16)
+ # Comment the l2 assert in case you want to test with
+ # garnet synthetic traffic
+ #
+ #assert(len(l2_nodes) == 8 or len(l2_nodes) == 16)
+ if print_extra_info:
+ print('Net nodes size = %d, remainder nodes = %d'
+ % (len(network_nodes), len(remainder_nodes)))
+ # Connect each node to the appropriate router
+ ext_links = []
+
+ for layer in range(max_layers):
+ for (i, n) in enumerate(network_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+
+ assert(cntrl_level < cntrls_per_router)
+ if print_extra_info:
+ print("Ext_link[%d], ext_node=%s, int_node(router)=%d" \
+ % (link_count, n, (layer*num_routers)+router_id))
+
+ ext_links.append(ExtLink(link_id=link_count, ext_node=n,
+ int_node=routers[(layer*num_routers)+router_id],
+ latency = link_latency))
+ link_count += 1
+
+ # The following setup is for modeling Config_1
+ #
+ dir_router_id_list = [0, 4, 8, 12]
+ cpu_router_list = [6, 7, 9, 10, 11, 13, 14, 15]
+ slc_router_list = [6, 7, 9, 10, 11, 13, 14, 15]
+
+ assert(len(dir_nodes) % len(dir_router_id_list) == 0)
+ dir_controllers_per_router = len(dir_nodes) / len(dir_router_id_list)
+
+ # Handle directory nodes
+ # Adjust the way we attach dir controllers so that consecutive memory ranges
+ # are kept close
+ for (i, node) in enumerate(dir_nodes):
+ #Connect the dir nodes to NI
+ for layer in range(max_layers):
+ if print_extra_info:
+ print("Info: <Dir node>: i = %d, layer = %d, Ext_link[%d], ext_node=%s, "
+ "Int_node(router)=%d" \
+ % (i, layer, link_count, node, (layer*num_routers) + dir_router_id_list[(i%len(dir_nodes))/dir_controllers_per_router] ))
+
+ ext_links.append(ExtLink(link_id=link_count, ext_node=node,
+ int_node=routers[(layer*num_routers)+
+ dir_router_id_list[ (i%len(dir_nodes))/dir_controllers_per_router ]],
+ latency = link_latency))
+ link_count += 1
+
+ # Handle l1 cache nodes
+ for (i, node) in enumerate(l1_nodes):
+ #Connect the dir nodes to NI
+ for layer in range(max_layers):
+ if print_extra_info:
+ print("Info: <l1 node>: i = %d, layer = %d, Ext_link[%d], ext_node=%s, "
+ "Int_node(router)=%d" \
+ % (i, layer, link_count, node, (layer*num_routers) +
+ cpu_router_list[i%len(cpu_router_list)]))
+
+ ext_links.append(ExtLink(link_id=link_count, ext_node=node,
+ int_node=routers[(layer*num_routers)+cpu_router_list[i%len(cpu_router_list)]],
+ latency = link_latency))
+ link_count += 1
+
+ # Handle l2 cache nodes, which acts as SLC in our case
+ for (i, node) in enumerate(l2_nodes):
+ #Connect the dir nodes to NI
+ for layer in range(max_layers):
+ if print_extra_info:
+ print("Info: <l2 node>: i = %d, layer = %d, Ext_link[%d], ext_node=%s, "
+ "Int_node(router)=%d" \
+ % (i, layer, link_count, node, (layer*num_routers) + slc_router_list[i%len(slc_router_list)]))
+
+ ext_links.append(ExtLink(link_id=link_count, ext_node=node,
+ int_node=routers[(layer*num_routers)+
+ slc_router_list[i%len(slc_router_list)]],
+ latency = link_latency))
+ link_count += 1
+
+ if print_extra_info: