diff --git a/webpage/docs/09_projects/05_project-stm32/05_oscillator.md b/webpage/docs/09_projects/05_project-stm32/05_oscillator.md
index 9633d8a5..fac2acc0 100644
--- a/webpage/docs/09_projects/05_project-stm32/05_oscillator.md
+++ b/webpage/docs/09_projects/05_project-stm32/05_oscillator.md
@@ -18,9 +18,9 @@ The STM32 WB55CEU microcontroller utilizes a High-Speed External Oscillator (HSE
 
   The internal load capacitance of the HSE is dynamically adjustable through the RCC_CR register to match the crystal's specified $C_L$. The effective load capacitance is determined by the equation:
 
-  \[
+  $$
   C_{\text{load}} = \frac{C_{L1} \cdot C_{L2}}{C_{L1} + C_{L2}} + C_{\text{stray}}
-  \]
+  $$
 
   where $C_{\text{stray}} \approx 2 \text{ pF}$ accounts for the parasitic capacitance inherent in PCB traces and pad geometries. This configurability allows for precise tuning of the oscillator's frequency response, ensuring optimal performance.
 
@@ -48,15 +48,15 @@ The Low-Speed External Oscillator (LSE) operates at 32.768 kHz and serves as the
 
   To compensate for the crystal's load capacitance and account for stray capacitances ($C_{\text{stray}} \approx 3 \text{ pF}$) from PCB traces and package parasitics, the external load capacitor ($C_{\text{ext}}$) is calculated using the formula:
 
-  \[
+  $$
   C_{\text{ext}} = 2 \cdot (C_L - C_{\text{stray}})
-  \]
+  $$
 
   For instance, with $C_L = 10 \text{ pF}$ and $C_{\text{stray}} = 3 \text{ pF}$, the external load capacitor required is:
 
-  \[
+  $$
   C_{\text{ext}} = 2 \times (10 - 3) = 14 \text{ pF}
-  \]
+  $$
 
   Given standard component values, a 12 pF capacitor is selected to approximate the calculated value, ensuring reliable oscillation without necessitating non-standard components.
 
diff --git a/webpage/docs/09_projects/05_project-stm32/06_programming_debugging.md b/webpage/docs/09_projects/05_project-stm32/06_programming_debugging.md
index 706a2ba5..4df00425 100644
--- a/webpage/docs/09_projects/05_project-stm32/06_programming_debugging.md
+++ b/webpage/docs/09_projects/05_project-stm32/06_programming_debugging.md
@@ -61,9 +61,9 @@ Configuring the boot mode of the STM32 WB55CEU microcontroller is essential for
   
   - **Debounce Filter:** A 100 nF capacitor (C_BOOT) is placed in parallel with the pull-down resistor to create a debounce filter with a time constant of:
   
-    \[
+    $$
     t_{\text{debounce}} = R \cdot C = 5.1 \, \text{kΩ} \cdot 100 \, \text{nF} = 510 \, \mu\text{s}
-    \]
+    $$
     
     This filter prevents mechanical switch bounce from causing false triggers, ensuring that only deliberate button presses alter the boot mode.
 
diff --git a/webpage/docs/09_projects/05_project-stm32/08_peripherials.md b/webpage/docs/09_projects/05_project-stm32/08_peripherials.md
index b04f3201..d0c5eb57 100644
--- a/webpage/docs/09_projects/05_project-stm32/08_peripherials.md
+++ b/webpage/docs/09_projects/05_project-stm32/08_peripherials.md
@@ -31,9 +31,9 @@ The Universal Asynchronous Receiver/Transmitter (UART) interface serves as a fun
 
     The power dissipation ($P$) across each resistor is calculated using Ohm’s law:
 
-    \[
+    $$
     P = \frac{V^2}{R} = \frac{(3.3 \, \text{V})^2}{220 \, \Omega} = 49.5 \, \text{mW} \quad (\text{per resistor})
-    \]
+    $$
 
     This level of power dissipation is well within the safe operating limits of standard 220Ω resistors, ensuring reliable performance without thermal issues.
 
diff --git a/webpage/docs/09_projects/05_project-stm32/10_net_classes.md b/webpage/docs/09_projects/05_project-stm32/10_net_classes.md
index 62830245..5fac49fb 100644
--- a/webpage/docs/09_projects/05_project-stm32/10_net_classes.md
+++ b/webpage/docs/09_projects/05_project-stm32/10_net_classes.md
@@ -153,7 +153,7 @@ Ensuring that the BOM is accurate and compliant with design specifications is cr
 
 - **Sourcing:**  
   - Components are vetted for lifecycle status, distinguishing between Not Recommended for New Designs (NRND) and active components.  
-  - Lead times are verified to be within acceptable ranges (e.g., <12 weeks) to prevent procurement delays.
+  - Lead times are verified to be within acceptable ranges (e.g., < 12 weeks) to prevent procurement delays.
 
 - **Standards Compliance:**  
   - **IPC-7351 Land Pattern Compliance:**