From 1dd9696dde3cfa8679c3f40e3114eaaea4d0b0fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Costa?= Date: Fri, 29 Nov 2024 15:07:13 +0100 Subject: [PATCH] SailBugfix: Bit 11 of medeleg is read-only zero In the official specification, the bit at position 11 is a read-only zero, which is currently not the case in Miralis. --- src/virt/csr.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/virt/csr.rs b/src/virt/csr.rs index 11561866..7ab8b7ac 100644 --- a/src/virt/csr.rs +++ b/src/virt/csr.rs @@ -450,8 +450,8 @@ impl HwRegisterContextSetter for VirtContext { mctx.hw.extensions.is_sstc_enabled = self.csr.menvcfg & menvcfg::STCE_FILTER != 0; } Csr::Mseccfg => self.csr.mseccfg = value, - Csr::Mconfigptr => (), // Read-only - Csr::Medeleg => self.csr.medeleg = value, //TODO : some values need to be read-only 0 + Csr::Mconfigptr => (), // Read-only + Csr::Medeleg => self.csr.medeleg = value & !(1 << 11), Csr::Mideleg => { self.csr.mideleg = (value & hw.interrupts & !mie::MIDELEG_READ_ONLY_ZERO) | mie::MIDELEG_READ_ONLY_ONE;