diff --git a/src/virt/csr.rs b/src/virt/csr.rs
index f8e646c8..a33ed608 100644
--- a/src/virt/csr.rs
+++ b/src/virt/csr.rs
@@ -4,6 +4,7 @@
 //! specification.
 
 use super::{VirtContext, VirtCsr};
+use crate::arch::mie::{LCOFIE_FILTER, SEIE_FILTER, SSIE_FILTER, STIE_FILTER};
 use crate::arch::mstatus::{MBE_FILTER, SBE_FILTER, UBE_FILTER};
 use crate::arch::pmp::pmpcfg;
 use crate::arch::{hstatus, menvcfg, mie, misa, mstatus, Arch, Architecture, Csr, Register};
@@ -540,10 +541,18 @@ impl HwRegisterContextSetter<Csr> for VirtContext {
                 );
             }
             Csr::Sie => {
-                // Clear S bits
-                let mie = self.get(Csr::Mie) & !mie::SIE_FILTER;
-                // Set S bits to new value
-                self.set_csr(Csr::Mie, mie | (value & mie::SIE_FILTER), mctx);
+                if SEIE_FILTER & self.get(Csr::Mideleg) != 0 {
+                    self.csr.mie = (self.csr.mie & !SEIE_FILTER) | (SEIE_FILTER & value);
+                }
+                if STIE_FILTER & self.get(Csr::Mideleg) != 0 {
+                    self.csr.mie = (self.csr.mie & !STIE_FILTER) | (STIE_FILTER & value);
+                }
+                if SSIE_FILTER & self.get(Csr::Mideleg) != 0 {
+                    self.csr.mie = (self.csr.mie & !SSIE_FILTER) | (SSIE_FILTER & value);
+                }
+                if LCOFIE_FILTER & self.get(Csr::Mideleg) != 0 {
+                    self.csr.mie = (self.csr.mie & !LCOFIE_FILTER) | (LCOFIE_FILTER & value);
+                }
             }
             Csr::Stvec => {
                 match value & 0b11 {