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fpoussinfpoussin
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Merge pull request #410 from dexter93/sn32_flexible_usb
SN32 USB LLD: flexibility updates
2 parents 6daa08b + 1b165fc commit bbf5966

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4 files changed

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-84
lines changed

4 files changed

+92
-84
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‎os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c

Lines changed: 33 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ static const USBEndpointConfig ep0config = {
8686
/*===========================================================================*/
8787
/* Driver local variables and types. */
8888
/*===========================================================================*/
89-
89+
uint32_t msk_EP_NAK, msk_EP_ACK;
9090
/*===========================================================================*/
9191
/* Driver local functions. */
9292
/*===========================================================================*/
@@ -137,6 +137,11 @@ static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) {
137137
if (off + chunk > sz)
138138
chunk = sz - off;
139139

140+
#if (SN32_USB_DIRECT_SRAM == TRUE)
141+
volatile uint32_t *sram;
142+
sram = (volatile uint32_t *)(SN32_USBRAM_BASE + off + ep_offset);
143+
data = *sram;
144+
#else
140145
if(intr) {
141146
SN32_USB->RWADDR = off + ep_offset;
142147
SN32_USB->RWSTATUS = 0x02;
@@ -149,7 +154,7 @@ static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) {
149154
while (SN32_USB->RWSTATUS2 & 0x02);
150155
data = SN32_USB->RWDATA2;
151156
}
152-
157+
#endif
153158
//dest, src, size
154159
memcpy(buf, &data, chunk);
155160

@@ -180,6 +185,11 @@ static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool
180185
//dest, src, size
181186
memcpy(&data, buf, chunk);
182187

188+
#if (SN32_USB_DIRECT_SRAM == TRUE)
189+
volatile uint32_t *sram;
190+
sram = (volatile uint32_t *)(SN32_USBRAM_BASE + off + ep_offset);
191+
*sram = data;
192+
#else
183193
if(intr) {
184194
SN32_USB->RWADDR = off + ep_offset;
185195
SN32_USB->RWDATA = data;
@@ -192,7 +202,7 @@ static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool
192202
SN32_USB->RWSTATUS2 = 0x01;
193203
while (SN32_USB->RWSTATUS2 & 0x01);
194204
}
195-
205+
#endif
196206
off += chunk;
197207
buf += chunk;
198208
}
@@ -306,7 +316,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
306316
/////////////////////////////////////////////////
307317
/* Device Status Interrupt (EPnACK) */
308318
/////////////////////////////////////////////////
309-
if (iwIntFlag & (mskEP6_ACK|mskEP5_ACK|mskEP4_ACK|mskEP3_ACK|mskEP2_ACK|mskEP1_ACK)) {
319+
if (iwIntFlag & msk_EP_ACK) {
310320
// Determine the interrupting endpoint, direction, and clear the interrupt flag
311321
for(usbep_t ep = 1; ep <= USB_MAX_ENDPOINTS; ep++) {
312322
if (iwIntFlag & mskEPn_ACK(ep)){
@@ -315,9 +325,8 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
315325
}
316326
}
317327
}
318-
if (iwIntFlag & (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK)) {
319-
SN32_USB->INSTSC = (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK);
320-
328+
if (iwIntFlag & msk_EP_NAK) {
329+
SN32_USB->INSTSC = msk_EP_NAK;
321330
}
322331

323332
}
@@ -451,6 +460,9 @@ void usb_lld_start(USBDriver *usbp) {
451460
/* Powers up the transceiver while holding the USB in reset state.*/
452461
SN32_USB->SGCTL = (mskBUS_DRVEN|mskBUS_J_STATE);
453462
SN32_USB->CFG = (mskVREG33_EN|mskPHY_EN|mskDPPU_EN|mskSIE_EN|mskESD_EN);
463+
# if defined(SN32F240)
464+
SN32_USB->CFG |= (mskUSBRAM_EN|mskVREG33DIS_EN);
465+
# endif
454466
/* Set up hardware configuration.*/
455467
SN32_USB->PHYPRM = 0x80000000;
456468
SN32_USB->PHYPRM2 = 0x00004004;
@@ -470,10 +482,18 @@ void usb_lld_start(USBDriver *usbp) {
470482
if (usbp->config->sof_cb != NULL) {
471483
SN32_USB->INTEN |= mskUSB_SOF_IE;
472484
}
473-
//SN32_USB->INTEN |= (mskEP1_NAK_EN|mskEP2_NAK_EN|mskEP3_NAK_EN|mskEP4_NAK_EN);
474-
#if (USB_ENDPOINTS_NUMBER > 4)
475-
//SN32_USB->INTEN |= (mskEP5_NAK_EN|mskEP6_NAK_EN);
476-
#endif /* (USB_ENDPOINTS_NUMBER > 4) */
485+
/* Calculate EP ACK, NAK, NAK_EN flags.*/
486+
msk_EP_NAK = 0;
487+
msk_EP_ACK = 0;
488+
//uint32_t msk_EP_NAK_EN = 0;
489+
for(usbep_t ep = 1; ep <= USB_MAX_ENDPOINTS; ep++) {
490+
msk_EP_NAK |= mskEPn_NAK(ep);
491+
msk_EP_ACK |= mskEPn_ACK(ep);
492+
// msk_EP_NAK_EN |= mskEPn_NAK_EN(ep);
493+
}
494+
/* Enable NAK EP interrupts.*/
495+
// Disabled for now.
496+
// SN32_USB->INTEN |= msk_EP_NAK_EN;
477497
}
478498
}
479499

@@ -506,7 +526,7 @@ void usb_lld_stop(USBDriver *usbp) {
506526
*/
507527
void usb_lld_reset(USBDriver *usbp) {
508528
/* Post reset initialization.*/
509-
SN32_USB->INSTSC = (0xFFFFFFFF);
529+
SN32_USB->INSTSC = (UINT32_MAX);
510530

511531
/* Set the address to zero during enumeration.*/
512532
usbp->address = 0;
@@ -529,7 +549,7 @@ void usb_lld_reset(USBDriver *usbp) {
529549
*/
530550
void usb_lld_set_address(USBDriver *usbp) {
531551

532-
SN32_USB->ADDR = usbp->address & 0x7F;
552+
SN32_USB->ADDR = usbp->address & mskUADDR;
533553
}
534554

535555
/**

‎os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,13 @@
8383
#if !defined(SN32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
8484
#define SN32_USB_HOST_WAKEUP_DURATION 2
8585
#endif
86+
87+
/**
88+
* @brief USB driver using SRAM direct.
89+
*/
90+
#if !defined(SN32_USB_DIRECT_SRAM) || defined(__DOXYGEN__)
91+
#define SN32_USB_DIRECT_SRAM FALSE
92+
#endif
8693
/** @} */
8794

8895
/*===========================================================================*/

‎os/hal/ports/SN32/LLD/SN32F2xx/USB/sn32_usb.h

Lines changed: 50 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -32,45 +32,51 @@
3232
* @brief Number of the available endpoints.
3333
* @details This value does not include the endpoint 0 which is always present.
3434
*/
35-
#define HAL_MAX_ENDPOINTS 6
35+
#define HAL_MAX_ENDPOINTS 7
3636
#if (defined(SN32F240B) || defined(SN32F260))
37-
#define USB_ENDPOINTS_NUMBER 4
38-
#define SN32_USB_PMA_SIZE 256
39-
#elif (defined(SN32F280) || defined(SN32F290))
40-
#define USB_ENDPOINTS_NUMBER HAL_MAX_ENDPOINTS
41-
#define SN32_USB_PMA_SIZE 512
37+
# define USB_ENDPOINTS_NUMBER 4
38+
# define SN32_USB_PMA_SIZE 256
39+
#elif defined(SN32F240C)
40+
# define USB_ENDPOINTS_NUMBER HAL_MAX_ENDPOINTS
41+
# define SN32_USB_PMA_SIZE 512
42+
#elif (defined(SN32F240) || defined(SN32F280) || defined(SN32F290))
43+
# define USB_ENDPOINTS_NUMBER 6
44+
# define SN32_USB_PMA_SIZE 512
4245
#else
43-
#error "USB driver not supported in the selected device"
46+
# error "USB driver not supported in the selected device"
4447
#endif
4548

4649
/**
4750
* @brief USB registers block.
4851
*/
4952
typedef struct {
50-
volatile uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */
51-
volatile uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */
52-
volatile uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear Register */
53-
volatile uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */
54-
volatile uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */
55-
volatile uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */
56-
volatile uint32_t EPCTL[HAL_MAX_ENDPOINTS +1]; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0-6 Control Registers */
57-
volatile uint32_t RESERVED[2];
58-
volatile uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */
59-
volatile uint32_t RESERVED1[2];
60-
volatile uint32_t EPBUFOS[HAL_MAX_ENDPOINTS]; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1-6 Buffer Offset Registers */
61-
volatile uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */
62-
volatile uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */
63-
volatile uint32_t RESERVED3;
64-
volatile uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter 2 Register */
65-
volatile uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */
66-
volatile uint32_t RESERVED4;
67-
volatile uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */
68-
volatile uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */
69-
volatile uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */
70-
volatile uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */
71-
volatile uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */
72-
volatile uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */
73-
} sn32_usb_t; /*!< Size = 144 (0x90) */
53+
volatile uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */
54+
volatile const uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */
55+
volatile uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear Register */
56+
volatile uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */
57+
volatile uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */
58+
volatile uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */
59+
volatile uint32_t EPCTL[USB_ENDPOINTS_NUMBER +1]; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0-7 Control Registers */
60+
volatile const uint32_t RESERVED[HAL_MAX_ENDPOINTS - USB_ENDPOINTS_NUMBER + 1];
61+
volatile uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */
62+
volatile const uint32_t RESERVED1[2];
63+
volatile uint32_t EPBUFOS[USB_ENDPOINTS_NUMBER]; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1-7 Buffer Offset Registers */
64+
#if (USB_ENDPOINTS_NUMBER != HAL_MAX_ENDPOINTS)
65+
volatile uint32_t RESERVED2[HAL_MAX_ENDPOINTS - USB_ENDPOINTS_NUMBER - 1];
66+
#endif
67+
volatile const uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */
68+
volatile uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */
69+
volatile const uint32_t RESERVED3;
70+
volatile uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter 2 Register */
71+
volatile uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */
72+
volatile const uint32_t RESERVED4;
73+
volatile uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */
74+
volatile uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */
75+
volatile uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */
76+
volatile uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */
77+
volatile uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */
78+
volatile uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */
79+
} sn32_usb_t; /*!< Size = 144 (0x90) */
7480

7581
/** @} */
7682

@@ -93,10 +99,19 @@
9399
* @brief Pointer to the USB RAM.
94100
*/
95101
#define SN32_USBRAM ((sn32_usb_pma_t *)SN32_USBRAM_BASE)
96-
#define mskEPn_NAK(ep) (0x1<<(ep -1))
97-
#define mskEPn_ACK(ep) (0x1<<(8+(ep-1)))
98-
#define mskEPn_DIR(ep) (0x1<<(ep-1))
99-
#define mskEPn_DATA_TOGGLE(ep) (0x1<<(ep-1))
102+
/**
103+
* @brief USB EP handling.
104+
*/
105+
/* USB Interrupt Event Status Bit Definitions <USB_INSTS/USB_INSTSC> */
106+
#define mskEPn_NAK(ep) (0x1<<(ep -1))
107+
#define mskEPn_ACK(ep) (0x1<<(8+(ep-1)))
108+
/* USB Configuration Bit Definitions <USB_CFG> */
109+
#define mskEPn_DIR(ep) (0x1<<(ep-1))
110+
/* USB Endpoint Data Toggle Bit Definitions <USB_EPTOGGLE> */
111+
#define mskEPn_DATA_TOGGLE(ep) (0x1<<(ep-1))
112+
/* USB Interrupt Enable Bit Definitions <USB_INTEN> */
113+
#define mskEPn_NAK_EN(ep) mskEPn_NAK(ep)
114+
#define mskEPnACK_EN (0x1<<USB_ENDPOINTS_NUMBER)
100115

101116
#define EPCTL_SET_STAT_ACK(ep, bBytecnt) \
102117
SN32_USB->EPCTL[ep] = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_ACK|bBytecnt)

‎os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h

Lines changed: 2 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -5,35 +5,12 @@
55
#define __USBHW_H__
66

77
/* USB Interrupt Enable Bit Definitions <USB_INTEN> */
8-
#define mskEP1_NAK_EN (0x1<<0)
9-
#define mskEP2_NAK_EN (0x1<<1)
10-
#define mskEP3_NAK_EN (0x1<<2)
11-
#define mskEP4_NAK_EN (0x1<<3)
12-
#define mskEP5_NAK_EN (0x1<<4)
13-
#define mskEP6_NAK_EN (0x1<<5)
14-
#define mskEPnACK_EN (0x1<<6)
15-
168
#define mskBUSWK_IE (0x1<<28)
179
#define mskUSB_IE (0x1<<29)
1810
#define mskUSB_SOF_IE (0x1<<30)
1911
#define mskBUS_IE (0x1U<<31)
2012

2113
/* USB Interrupt Event Status Bit Definitions <USB_INSTS/USB_INSTSC> */
22-
#define mskEP1_NAK (0x1<<0)
23-
#define mskEP2_NAK (0x1<<1)
24-
#define mskEP3_NAK (0x1<<2)
25-
#define mskEP4_NAK (0x1<<3)
26-
#define mskEP5_NAK (0x1<<4)
27-
#define mskEP6_NAK (0x1<<5)
28-
29-
#define mskEP1_ACK (0x1<<8)
30-
#define mskEP2_ACK (0x1<<9)
31-
#define mskEP3_ACK (0x1<<10)
32-
#define mskEP4_ACK (0x1<<11)
33-
#define mskEP5_ACK (0x1<<12)
34-
#define mskEP6_ACK (0x1<<13)
35-
36-
3714
#define mskERR_TIMEOUT (0x1<<17)
3815
#define mskERR_SETUP (0x1<<18)
3916
#define mskEP0_OUT_STALL (0x1<<19)
@@ -52,13 +29,8 @@
5229
#define mskUADDR (0x7F<<0)
5330

5431
/* USB Configuration Bit Definitions <USB_CFG> */
55-
#define mskEP1_DIR (0x1<<0)
56-
#define mskEP2_DIR (0x1<<1)
57-
#define mskEP3_DIR (0x1<<2)
58-
#define mskEP4_DIR (0x1<<3)
59-
#define mskEP5_DIR (0x1<<4)
60-
#define mskEP6_DIR (0x1<<5)
61-
32+
#define mskVREG33DIS_EN (0x1<<24)
33+
#define mskUSBRAM_EN (0x1<<25)
6234
#define mskDIS_PDEN (0x1<<26)
6335
#define mskESD_EN (0x1<<27)
6436
#define mskSIE_EN (0x1<<28)
@@ -85,12 +57,6 @@
8557
#define mskEPn_ENDP_STATE_STALL (0x3<<29)
8658
#define mskEPn_ENDP_EN (0x1U<<31)
8759

88-
/* USB Endpoint Data Toggle Bit Definitions <USB_EPTOGGLE> */
89-
#define mskEP1_CLEAR_DATA0 (0x1<<0)
90-
#define mskEP2_CLEAR_DATA0 (0x1<<1)
91-
#define mskEP3_CLEAR_DATA0 (0x1<<2)
92-
#define mskEP4_CLEAR_DATA0 (0x1<<3)
93-
9460
/* USB Endpoint n Buffer Offset Bit Definitions <USB_EPnBUFOS> */
9561
#define mskEPn_OFFSET (0x1FF<<0)
9662

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