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TODO
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Friday, 3rd February:
DONE * Finish the implementation of execute'
DONE * Define an instance for the RiscvProgram typeclass
DONE * Split the code between several files, requirements :
- One non scary file
- automatically generated code within one file not pushed on the repo.
- Create Makefile for the generation
X - typeclasses and instances in different file(s).
- miscellaneous plumbing functions in different file.
DONE * Look for more polymorphism in the instruction type. (Some reading required)
Friday, 17 february:
* Change memory : addresses in the processor are in bytes. Now there are in words.
* elf library in haskell or elf2hex + custom parsing Tcl/Tk.
* Add State monad to avoid dependency with mtl
* MonadPlus would allow us to define execute functions specific to each
extensions (in different files) with execute _ = mzero. Then our step function
would cascade those different functions (with mplus).
* For the different modules of RISCV, reuse the naming convention of riscv.
Monday, 27 february:
* Decode stage : Change Int to Integer wherever it is needed.
* avoid the use of functions for infix operators.
* elf library in haskell or elf2hex + custom parsing Tcl/Tk.
* For the different modules of RISCV, reuse the naming convention of riscv.
* testing with riscv toolchain.
Monday, 20th March:
* Build regression test harness (integration with spike?)
* Implement CSRs for machine mode (exceptions, interrupts)
* Supervisor mode
Monday, 3rd April:
* Look into: Torture Tests, The Essence of Functional Programming (paper)
* Memory-mapped IO for printing characters (test via looking at output rather than state)
- New instance of RiscvProgram with alternate impl. of storeWord
* Implement CSRs (packing, look at prior implementation)
Monday, 17th April:
* CSRs, IO-monad based MMIO, Newlib, Spike testing harness.
Monday, May 1st:
* Search for CSR structure info, otherwise file bug report
* Finish basic CSR implementation (write tests).
* Spike testing harness (Run spike to find correct output, compare against Run.hs).
* (Fix jimm20. -> Working mandelbrot!)
Eventually: lots of testing, memory typeclass, faster memory implementation.
Monday, May 15th:
* Make fromIntegral prettier. (infix?)
* Memory typeclass, faster implementation
* Agreed to resume next Fall, low-priority thread to keep info fresh
* (Finish Spike harness.)
Thursday, September 14th
* Boot Linux in Spike
* Haskell FFI / Spike step function
* 64-bit implementation (alongside 32-bit)
* Continue work on CSRs, supervisor mode
Friday, September 22nd
* Basic interrupts via polling (interrupt CSRs).
Monday, October 2nd
* Virtual memory (check spec).
* Attempt to test it?
* Spike/Linux-saga continues
* Haskell FFI / Spike step function
Friday, October 6th
* Implement CSR that holds virtual memory mode, base address.
* SATP, MIP
Friday, October 13th
* 64-bit SATP, implement Sv39
* Check out riscv-tests
* loadField/storeField
* Timer interrupts
* Initial floating-point support using Haskell semantics?
* Replace Int/Integer with MachineInt (= Int64 for now). Set Register = Int8.
Friday, October 19th
* instret, cycle (= instret in this case).
* ECALL, MRET, EBREAK (approx. = ECALL in this case).
* Timer interrupts
* medeleg, mideleg need not exist yet (except for spike compat)
* MPIE, MIE, most things hardwired to 0
* Timer and time compare register are memory-mapped
* Taking an interrupt should disable interrupts (trap handler is responsible for re-enabling)
Friday, November 3rd
* mtime, mtimecmp (memory-mapped registers, use Spike addresses)
* debug logging typeclass to wrap existing instances
* misaligned fetch (exception caused by instruction before misaligned instruction); can raise an exception in jump/branch insts
* ditto for misaligned accesses
* add extra param to decode for machine width, generate huge if structure instead of huge table
* refactor Maybe out of RiscvProgram and into Execute
Friday, November 17th
Infrastructure:
* riscv-tests
* continuous integration via Travis
* 32-bit/64-bit builds in build system
Code:
* Virtual memory once again (Sv39)
* Refactor Maybe out of MMIO64. Sub-executes will require MonadPlus instead of RiscvProgram.
* s/fromIntegral/some other name/g, remove all '$' from execute files
* Hierarchy of implementation (build MMIO64 using Minimal64).
Friday, December 8th
Infrastructure:
* CI for riscv-tests (so we don't have to deal with installing riscv-gcc in Travis).
* Update mmio32.ld to use 0x80000000 for consistency.
* Update elf2hex to deal with large addresses nicely.
Code:
* Virtual memory. calculateAddress helper (virtual -> physical), not in typeclass.
* Haskell implementation of elf2hex to avoid extra dependency.
Tuesday, February 13th
* Virtual memory. Helper outside typeclass, but in the monad.
* Run riscv-tests in Travis (pending pre-built binaries going up).
Tuesday, Feburary 27th
* Travis: download riscv-gcc, build riscv-tests, and run them.
* Change RISCV-V exceptions control-flow via Haskell exceptions.
* Use translation for execution in supervisor mode.
Tuesday, March 6th
* Travis: build isa, run rv64ui tests.
* Rename step -> commit, helper -> something reasonable.
* Add some type variables and an interrupt callback to helper, and stop copying it everywhere.
* Add processor mode to typeclass.
Friday, March 16th
(Abridged meeting.)
Tuesday, March 20th
* Add processor mode outside typeclass
* Virtual memory when fetching instructions
* Update Travis
Tuesday, April 3rd
* Add processor mode *inside* typeclass
* Update calculateAddress to check current privilege mode, relevant CSRs
* Add permission checks for page accesses
* Update CSRSpec to deal with privileges
* Update raiseException to modify mstatus priv. stack
* Add Sret, Update Mret
Tuesday, April 17th
* Debug rv64mi-* tests.
* Debug rv64ui-v-* tests.
* Get some level of tandem debugging with Spike working.
Tuesday, May 1st
* Implement "A" extension using GADTs
* Implement "F" extension?
* Attempt to boot Linux!
Tuesday, September 11th
* Implement F extension
Tuesday, October 2nd
* Boot bbl.
* Tandem verification stuff?
Tuesday, October 16th
* Get dummy_payload printing: include device tree, initialize registers, memory map UART.
* Add another device for user mode?
* Investigate GDB remote debugging protocol (consult spike src, maybe gdb).
For building bbl without compressed instructions:
../configure --prefix=$RISCV --host=riscv64-unknown-linux-gnu CFLAGS=-march=rv64imafd
CFLAGS=-march=rv64imafd make
Tuesday, November 20th
* Investigate memory leak. Profiling, test programs, try making everything strict, etc.
* Try adding 'size' to Memory; requests above size are out-of-bounds.
* Tandem verification stuff
Tuesday, January 22nd
* Documentation, debugging.