forked from rombaby/Mi2-2s-aries--CM_EX-Patch
-
Notifications
You must be signed in to change notification settings - Fork 0
/
cm11-ex.patch
3020 lines (2866 loc) · 95.7 KB
/
cm11-ex.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
arch/arm/Kconfig | 6 +
arch/arm/include/asm/xor.h | 73 +++
arch/arm/lib/Makefile | 6 +
arch/arm/mach-msm/Kconfig | 18 +
arch/arm/mach-msm/Makefile | 2 +
arch/arm/mach-msm/acpuclock-8064.c | 337 +++++++------
arch/arm/mach-msm/acpuclock-krait.c | 49 ++
arch/arm/mach-msm/board-8064-regulator.c | 10 +-
arch/arm/mach-msm/clock-8960.c | 81 ++-
arch/arm/mach-msm/clock-pll.c | 37 ++
arch/arm/mach-msm/cpufreq.c | 79 +++
arch/arm/mach-msm/include/mach/kgsl.h | 2 +
arch/arm/mach-msm/xiaomi/aries/board-aries-gpu.c | 24 +-
.../mach-msm/xiaomi/aries/board-aries-regulator.c | 10 +-
arch/arm/vfp/vfphw.S | 5 +
arch/arm/vfp/vfpmodule.c | 81 ++-
crypto/Kconfig | 33 ++
drivers/cpufreq/Kconfig | 26 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq.c | 320 +++++++++---
drivers/cpufreq/cpufreq_stats.c | 4 +-
drivers/gpu/msm/Kconfig | 7 +
drivers/gpu/msm/kgsl_pwrctrl.c | 69 ++-
drivers/gpu/msm/kgsl_pwrscale_trustzone.c | 76 +++
drivers/input/touchscreen/Kconfig | 6 +
drivers/input/touchscreen/atmel_mxt_ts.c | 544 ++++++++++++++++++++-
drivers/power/pm8921-charger.c | 2 +-
drivers/usb/gadget/f_qdss.c | 4 +-
drivers/video/msm/mipi_hitachi.c | 4 +-
fs/namespace.c | 4 +-
include/linux/cpufreq.h | 11 +-
kernel/power/process.c | 27 +-
net/bluetooth/hci_conn.c | 2 +-
33 files changed, 1669 insertions(+), 291 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1afb325..59794fa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2441,6 +2441,12 @@ config NEON
Say Y to include support code for NEON, the ARMv7 Advanced SIMD
Extension.
+config KERNEL_MODE_NEON
+ bool "Support for NEON in kernel mode"
+ depends on NEON && AEABI
+ help
+ Say Y to include support for NEON in kernel mode.
+
endmenu
menu "Userspace binary formats"
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h
index 7604673..4ffb26d 100644
--- a/arch/arm/include/asm/xor.h
+++ b/arch/arm/include/asm/xor.h
@@ -7,7 +7,10 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+#include <linux/hardirq.h>
#include <asm-generic/xor.h>
+#include <asm/hwcap.h>
+#include <asm/neon.h>
#define __XOR(a1, a2) a1 ^= a2
@@ -138,4 +141,74 @@ static struct xor_block_template xor_block_arm4regs = {
xor_speed(&xor_block_arm4regs); \
xor_speed(&xor_block_8regs); \
xor_speed(&xor_block_32regs); \
+ NEON_TEMPLATES; \
} while (0)
+
+#ifdef CONFIG_KERNEL_MODE_NEON
+
+extern struct xor_block_template const xor_block_neon_inner;
+
+static void
+xor_neon_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
+{
+ if (in_interrupt()) {
+ xor_arm4regs_2(bytes, p1, p2);
+ } else {
+ kernel_neon_begin();
+ xor_block_neon_inner.do_2(bytes, p1, p2);
+ kernel_neon_end();
+ }
+}
+
+static void
+xor_neon_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+ unsigned long *p3)
+{
+ if (in_interrupt()) {
+ xor_arm4regs_3(bytes, p1, p2, p3);
+ } else {
+ kernel_neon_begin();
+ xor_block_neon_inner.do_3(bytes, p1, p2, p3);
+ kernel_neon_end();
+ }
+}
+
+static void
+xor_neon_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+ unsigned long *p3, unsigned long *p4)
+{
+ if (in_interrupt()) {
+ xor_arm4regs_4(bytes, p1, p2, p3, p4);
+ } else {
+ kernel_neon_begin();
+ xor_block_neon_inner.do_4(bytes, p1, p2, p3, p4);
+ kernel_neon_end();
+ }
+}
+
+static void
+xor_neon_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+ unsigned long *p3, unsigned long *p4, unsigned long *p5)
+{
+ if (in_interrupt()) {
+ xor_arm4regs_5(bytes, p1, p2, p3, p4, p5);
+ } else {
+ kernel_neon_begin();
+ xor_block_neon_inner.do_5(bytes, p1, p2, p3, p4, p5);
+ kernel_neon_end();
+ }
+}
+
+static struct xor_block_template xor_block_neon = {
+ .name = "neon",
+ .do_2 = xor_neon_2,
+ .do_3 = xor_neon_3,
+ .do_4 = xor_neon_4,
+ .do_5 = xor_neon_5
+};
+
+#define NEON_TEMPLATES \
+ do { if (cpu_has_neon()) xor_speed(&xor_block_neon); } while (0)
+#else
+#define NEON_TEMPLATES
+#endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8ade75d..be2a316 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -46,3 +46,9 @@ lib-$(CONFIG_ARCH_SHARK) += io-shark.o
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
+
+ifeq ($(CONFIG_KERNEL_MODE_NEON),y)
+ NEON_FLAGS := -mcpu=cortex-a15 -mfloat-abi=hard -mfpu=neon-vfpv4
+ CFLAGS_xor-neon.o += $(NEON_FLAGS)
+ obj-$(CONFIG_XOR_BLOCKS) += xor-neon.o
+endif
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a7464c1..e48bc7c 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1634,6 +1634,24 @@ config MSM_CPU_FREQ_MIN
endif # CPU_FREQ_MSM
+config GPU_VOLTAGE_TABLE
+ bool "Enable GPU Voltage Table via sysfs for adjustments"
+ default n
+ help
+ Adreno User Voltage Control
+
+config MSM_SLEEPER
+ bool "Limit max frequency and shut off cores while screen is off"
+ default n
+ help
+ Limit max frequency and shut off cores while screen is off
+
+config CPU_VOLTAGE_TABLE
+ bool "Enable CPU Voltage Table via sysfs for adjustements"
+ default n
+ help
+ Krait User Votlage Control
+
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
default n
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index debe164..7e9c125 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -404,3 +404,5 @@ obj-$(CONFIG_MSM_CPU_PWRCTL) += msm_cpu_pwrctl.o
obj-$(CONFIG_CPU_FREQ_MSM) += cpufreq.o
obj-$(CONFIG_ARCH_RANDOM) += early_random.o
+
+obj-$(CONFIG_MSM_SLEEPER) += msm-sleeper.o
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 8262946..231df89 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -98,6 +98,7 @@ static struct scalable scalable[] __initdata = {
/*
* The correct maximum rate for 8064ab in 600 MHZ.
* We rely on the RPM rounding requests up here.
+ * bus(前端总线)频率
*/
static struct msm_bus_paths bw_level_tbl[] __initdata = {
[0] = BW_MBPS(640), /* At least 80 MHz on bus. */
@@ -115,6 +116,7 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
.name = "acpuclk-8064",
};
+/* l2(二级缓存)频率 */
static struct l2_level l2_freq_tbl[] __initdata = {
[0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
[1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
@@ -134,33 +136,8 @@ static struct l2_level l2_freq_tbl[] __initdata = {
{ }
};
+/* 8064各体质频率 */
static struct acpu_level tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_nom[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
@@ -183,45 +160,21 @@ static struct acpu_level tbl_nom[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1225000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
{ 0, { 0 } }
};
-static struct acpu_level tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1100000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_faster[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
+static struct acpu_level tbl_nom[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 850000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 850000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 950000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 950000 },
{ 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
{ 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 },
@@ -235,6 +188,64 @@ static struct acpu_level tbl_faster[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1150000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1175000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_fast[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 825000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 825000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 850000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 850000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 925000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1000000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1025000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1050000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1050000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1062500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1062500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1075000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1100000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_faster[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 825000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 825000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 850000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 850000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 887500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 975000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1000000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1000000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1025000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1025000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1037500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1050000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1075000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
{ 0, { 0 } }
};
@@ -350,132 +361,141 @@ static struct acpu_level tbl_PVS6_1512MHz[] __initdata = {
{ 0, { 0 } }
};
+/* 8064T各体质频率 */
static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1087500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1150000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1175000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1225000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 912500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 950000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 987500 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1037500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1075000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1125000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1250000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1037500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1050000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1087500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1150000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1187500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1162500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 887500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 937500 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 962500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 975000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1012500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1062500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1112500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1220000 },
{ 0, { 0 } }
};
-static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 837500 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 850000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1037500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1075000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 987500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1025000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1050000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1087500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1112500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1162500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 800000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 850000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 875000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 900000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 912500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 925000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 962500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 987500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1125000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 812500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 825000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 850000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 875000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 887000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 900000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 925000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 962500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1000000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1025000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1075000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 812500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 825000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 850000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 862500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 875000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 887500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 912500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 937500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 975000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1000000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1075000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 812500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 825000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 850000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 862500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 875000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 887500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 900000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 925000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 950000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 975000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1050000 },
{ 0, { 0 } }
};
+/* 8064AB各体质频率 */
static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
@@ -609,6 +629,7 @@ static struct acpu_level tbl_PVS6_2000MHz[] __initdata = {
{ 0, { 0 } }
};
+/* 跟据speed_bin和pvs来选择频率表，最后一个值为boost_uv(动态浮动电压) */
static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
[0][PVS_SLOW] = {tbl_slow, sizeof(tbl_slow), 0 },
[0][PVS_NOMINAL] = {tbl_nom, sizeof(tbl_nom), 25000 },
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index e3a3f54..0397f0d 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -912,6 +912,55 @@ static void __init bus_init(const struct l2_level *l2_level)
dev_err(drv.dev, "initial bandwidth req failed (%d)\n", ret);
}
+/* cpu电压控制 */
+#ifdef CONFIG_CPU_VOLTAGE_TABLE
+
+#define HFPLL_MIN_VDD 800000
+#define HFPLL_MAX_VDD 1300000
+
+ssize_t acpuclk_get_vdd_levels_str(char *buf) {
+
+ int i, len = 0;
+
+ if (buf) {
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ /* updated to use uv required by 8x60 architecture - faux123 */
+ len += sprintf(buf + len, "%8lu: %8d\n", drv.acpu_freq_tbl[i].speed.khz,
+ drv.acpu_freq_tbl[i].vdd_core );
+ }
+
+ mutex_unlock(&driver_lock);
+ }
+ return len;
+}
+
+/* updated to use uv required by 8x60 architecture - faux123 */
+void acpuclk_set_vdd(unsigned int khz, int vdd_uv) {
+
+ int i;
+ unsigned int new_vdd_uv;
+
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ if (khz == 0)
+ new_vdd_uv = min(max((unsigned int)(drv.acpu_freq_tbl[i].vdd_core + vdd_uv),
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else if ( drv.acpu_freq_tbl[i].speed.khz == khz)
+ new_vdd_uv = min(max((unsigned int)vdd_uv,
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else
+ continue;
+
+ drv.acpu_freq_tbl[i].vdd_core = new_vdd_uv;
+ }
+ pr_warn("faux123: user voltage table modified!\n");
+ mutex_unlock(&driver_lock);
+}
+#endif /* CONFIG_CPU_VOTALGE_TABLE */
+
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
diff --git a/arch/arm/mach-msm/board-8064-regulator.c b/arch/arm/mach-msm/board-8064-regulator.c
index b06599c..b1737116 100644
--- a/arch/arm/mach-msm/board-8064-regulator.c
+++ b/arch/arm/mach-msm/board-8064-regulator.c
@@ -571,18 +571,18 @@ mpq8064_gpio_regulator_pdata[] __devinitdata = {
SX150X_GPIO(4, 15), "avc_5v"),
};
-/* SAW regulator constraints */
+/* SAW regulator constraints 主板CPU接口电压 */
struct regulator_init_data msm8064_saw_regulator_pdata_8921_s5 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8921_s5", 850000, 1300000);
+ SAW_VREG_INIT(S5, "8921_s5", 775000, 1300000);
struct regulator_init_data msm8064_saw_regulator_pdata_8921_s6 =
- SAW_VREG_INIT(S6, "8921_s6", 850000, 1300000);
+ SAW_VREG_INIT(S6, "8921_s6", 775000, 1300000);
struct regulator_init_data msm8064_saw_regulator_pdata_8821_s0 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(8821_S0, "8821_s0", 850000, 1300000);
+ SAW_VREG_INIT(8821_S0, "8821_s0", 775000, 1300000);
struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1 =
- SAW_VREG_INIT(8821_S1, "8821_s1", 850000, 1300000);
+ SAW_VREG_INIT(8821_S1, "8821_s1", 775000, 1300000);
/* PM8921 regulator constraints */
struct pm8xxx_regulator_platform_data
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 7b20003..4896eb5 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -380,8 +380,53 @@ enum vdd_dig_levels {
VDD_DIG_NUM
};
+
+/* GPU电压控制 */
+#ifdef CONFIG_GPU_VOLTAGE_TABLE
+#define GPU_MIN_VDD 900
+#define GPU_MAX_VDD 1200
+
+/* low=128mhz nominal=320mhz high=450mhz
+详见fmax_gfx3d_8064[VDD_DIG_NUM] */
+static int vdd_uv[] = {
+ [VDD_DIG_NONE] = 0,
+ [VDD_DIG_LOW] = 900000,
+ [VDD_DIG_NOMINAL] = 1000000,
+ [VDD_DIG_HIGH] = 1150000
+};
+
+ssize_t get_gpu_vdd_levels_str(char *buf)
+{
+ int i, len = 0;
+
+ if (buf) {
+ for (i = 1; i <= 3; i++) {
+ len += sprintf(buf + len, "%i\n", vdd_uv[i]/1000);
+ }
+ }
+ return len;
+}
+
+void set_gpu_vdd_levels(int uv_tbl[])
+{
+ int i;
+ for (i = 1; i <= 3; i++)
+ {
+ vdd_uv[i] = (min(max(uv_tbl[i - 1],
+ GPU_MIN_VDD), GPU_MAX_VDD))*1000;
+ }
+}
+#endif
+
static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
{
+#ifdef CONFIG_GPU_VOLTAGE_TABLE
+ int ret;
+ ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
+ vdd_uv[level], vdd_uv[VDD_DIG_HIGH], 1);
+ //pr_alert("GPU VOLTAGE - %d - %d", vdd_uv[level], ret);
+ return ret;
+#else
static const int vdd_uv[] = {
[VDD_DIG_NONE] = 0,
[VDD_DIG_LOW] = 945000,
@@ -390,6 +435,7 @@ static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
};
return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
vdd_uv[level], 1150000, 1);
+#endif
}
static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960, VDD_DIG_NUM);
@@ -3532,7 +3578,14 @@ static struct clk_freq_tbl clk_tbl_gfx3d[] = {
F_GFX3D(266667000, pll2, 1, 3),
F_GFX3D(320000000, pll2, 2, 5),
F_GFX3D(400000000, pll2, 1, 2),
+ F_GFX3D(409500000, pll15, 1, 2),
F_GFX3D(450000000, pll15, 1, 2),
+ F_GFX3D(477000000, pll15, 1, 2),
+ F_GFX3D(490500000, pll15, 1, 2),
+ F_GFX3D(504000000, pll15, 1, 2),
+ F_GFX3D(531000000, pll15, 1, 2),
+ F_GFX3D(558000000, pll15, 1, 2),
+ F_GFX3D(585000000, pll15, 1, 2),
F_END
};
@@ -3587,8 +3640,8 @@ static unsigned long fmax_gfx3d_8064ab[VDD_DIG_NUM] = {
static unsigned long fmax_gfx3d_8064[VDD_DIG_NUM] = {
[VDD_DIG_LOW] = 128000000,
- [VDD_DIG_NOMINAL] = 325000000,
- [VDD_DIG_HIGH] = 400000000
+ [VDD_DIG_NOMINAL] = 320000000,
+ [VDD_DIG_HIGH] = 450000000
};
static unsigned long fmax_gfx3d_8930[VDD_DIG_NUM] = {
@@ -6336,7 +6389,9 @@ static struct pll_config pll4_config_393 __initdata = {
.main_output_mask = BIT(23),
};
-static struct pll_config_regs pll15_regs __initdata = {
+
+/* 修改pll15结构名称 */
+static struct pll_config_regs pll15_regs = {
.l_reg = MM_PLL3_L_VAL_REG,
.m_reg = MM_PLL3_M_VAL_REG,
.n_reg = MM_PLL3_N_VAL_REG,
@@ -6344,10 +6399,11 @@ static struct pll_config_regs pll15_regs __initdata = {
.mode_reg = MM_PLL3_MODE_REG,
};
-static struct pll_config pll15_config __initdata = {
- .l = (0x24 | BVAL(31, 7, 0x620)),
+/* 修改pll15结构名称&n值 */
+static struct pll_config pll15_config = {
+ .l = (0x21 | BVAL(31, 7, 0x620)),
.m = 0x1,
- .n = 0x9,
+ .n = 0x3,
.vco_val = BVAL(17, 16, 0x2),
.vco_mask = BM(17, 16),
.pre_div_val = 0x0,
@@ -6601,6 +6657,19 @@ static void __init reg_init(void)
}
}
+//GPU_OC
+/* 创建pll超频方法 */
+extern void configure_pllOC(struct pll_config *config, struct pll_config_regs *regs, u32 ena_fsm_mode);
+
+void __ref SetGPUpll_config(u32 loc, unsigned long freq)
+{
+ pll15_config.l = (loc | BVAL(31, 7, 0x620));
+ pll15_config.m = 0x1;
+ pll15_config.n = 0x3;
+ configure_pllOC(&pll15_config, &pll15_regs, 0);
+ printk("ElementalX: set GPU OC %ld", freq / 1000000);
+}
+
struct clock_init_data msm8960_clock_init_data __initdata;
static void __init msm8960_clock_pre_init(void)
{
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index aeb1c5e..e6eb1f3 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -501,6 +501,43 @@ void __init __configure_pll(struct pll_config *config,
writel_relaxed(regval, PLL_CONFIG_REG(regs));
}
+//GPU_OC
+/* 设置pll值 */
+void configure_pllOC(struct pll_config *config,
+ struct pll_config_regs *regs, u32 ena_fsm_mode)
+{
+ u32 regval;
+
+ writel_relaxed(config->l, PLL_L_REG(regs));
+ writel_relaxed(config->m, PLL_M_REG(regs));
+ writel_relaxed(config->n, PLL_N_REG(regs));
+
+ regval = readl_relaxed(PLL_CONFIG_REG(regs));
+
+ /* Enable the MN accumulator */
+ if (config->mn_ena_mask) {
+ regval &= ~config->mn_ena_mask;
+ regval |= config->mn_ena_val;
+ }
+
+ /* Enable the main output */
+ if (config->main_output_mask) {
+ regval &= ~config->main_output_mask;
+ regval |= config->main_output_val;
+ }
+
+ /* Set pre-divider and post-divider values */
+ regval &= ~config->pre_div_mask;
+ regval |= config->pre_div_val;
+ regval &= ~config->post_div_mask;
+ regval |= config->post_div_val;
+
+ /* Select VCO setting */
+ regval &= ~config->vco_mask;
+ regval |= config->vco_val;
+ writel_relaxed(regval, PLL_CONFIG_REG(regs));
+}
+
void __init configure_sr_pll(struct pll_config *config,
struct pll_config_regs *regs, u32 ena_fsm_mode)
{
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 72ed4f0..cbcf6d1 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -36,6 +36,10 @@
#include "acpuclock.h"
+/* maxscroff */
+uint32_t maxscroff_freq = 702000;
+uint32_t maxscroff = 0;
+
static DEFINE_MUTEX(l2bw_lock);
static struct clk *cpu_clk[NR_CPUS];
@@ -458,8 +462,83 @@ static int msm_cpufreq_resume(struct cpufreq_policy *policy)
return 0;
}
+/** maxscreen off sysfs interface **/
+
+static ssize_t show_max_screen_off_khz(struct cpufreq_policy *policy, char *buf)
+{
+ return sprintf(buf, "%u\n", maxscroff_freq);
+}
+
+static ssize_t store_max_screen_off_khz(struct cpufreq_policy *policy,
+ const char *buf, size_t count)
+{
+ unsigned int freq = 0;
+ int ret;
+ int index;
+ struct cpufreq_frequency_table *freq_table = cpufreq_frequency_get_table(policy->cpu);
+
+ if (!freq_table)
+ return -EINVAL;
+
+ ret = sscanf(buf, "%u", &freq);
+ if (ret != 1)
+ return -EINVAL;
+
+ mutex_lock(&per_cpu(cpufreq_suspend, policy->cpu).suspend_mutex);
+
+ ret = cpufreq_frequency_table_target(policy, freq_table, freq,
+ CPUFREQ_RELATION_H, &index);
+ if (ret)
+ goto out;
+
+ maxscroff_freq = freq_table[index].frequency;
+
+ ret = count;
+
+out:
+ mutex_unlock(&per_cpu(cpufreq_suspend, policy->cpu).suspend_mutex);
+ return ret;
+}
+
+struct freq_attr msm_cpufreq_attr_max_screen_off_khz = {
+ .attr = { .name = "screen_off_max_freq",
+ .mode = 0666,
+ },
+ .show = show_max_screen_off_khz,
+ .store = store_max_screen_off_khz,
+};
+
+static ssize_t show_max_screen_off(struct cpufreq_policy *policy, char *buf)
+{
+ return sprintf(buf, "%u\n", maxscroff);
+}
+
+static ssize_t store_max_screen_off(struct cpufreq_policy *policy,
+ const char *buf, size_t count)
+{
+ if (buf[0] >= '0' && buf[0] <= '1' && buf[1] == '\n')
+ if (maxscroff != buf[0] - '0')
+ maxscroff = buf[0] - '0';
+
+ return count;
+}
+
+struct freq_attr msm_cpufreq_attr_max_screen_off = {
+ .attr = { .name = "screen_off_max",
+ .mode = 0666,
+ },
+ .show = show_max_screen_off,
+ .store = store_max_screen_off,
+};
+
+/** end maxscreen off sysfs interface **/
+
+
static struct freq_attr *msm_freq_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
+/** maxscreen off sysfs interface **/
+ &msm_cpufreq_attr_max_screen_off_khz,
+ &msm_cpufreq_attr_max_screen_off,
NULL,
};
diff --git a/arch/arm/mach-msm/include/mach/kgsl.h b/arch/arm/mach-msm/include/mach/kgsl.h
index 2d7e8df..fc9ab5e 100644
--- a/arch/arm/mach-msm/include/mach/kgsl.h
+++ b/arch/arm/mach-msm/include/mach/kgsl.h
@@ -41,6 +41,8 @@
(((_mi) & 0xFF) << 8) | \
((_pa) & 0xFF))