DE1_TOP.merge.rpt

Partition Merge report for DE1_TOP
Tue Feb 06 18:59:13 2018
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Partition Merge Summary
  3. Partition Merge Netlist Types Used
  4. Connections to In-System Debugging Instance "auto_signaltap_0"
  5. Partition Merge Partition Statistics
  6. Partition Merge Resource Usage Summary
  7. Partition Merge RAM Summary
  8. Partition Merge DSP Block Usage Summary
  9. Partition Merge Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; Partition Merge Summary                                                              ;
+------------------------------------+-------------------------------------------------+
; Partition Merge Status             ; Successful - Tue Feb 06 18:59:13 2018           ;
; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name                      ; DE1_TOP                                         ;
; Top-level Entity Name              ; DE1_TOP                                         ;
; Family                             ; Cyclone II                                      ;
; Total logic elements               ; 18,144                                          ;
;     Total combinational functions  ; 10,837                                          ;
;     Dedicated logic registers      ; 10,404                                          ;
; Total registers                    ; 10404                                           ;
; Total pins                         ; 283                                             ;
; Total virtual pins                 ; 0                                               ;
; Total memory bits                  ; 116,992                                         ;
; Embedded Multiplier 9-bit elements ; 8                                               ;
; Total PLLs                         ; 1                                               ;
+------------------------------------+-------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Netlist Types Used                                                                                            ;
+--------------------------------+----------------+-------------------+------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Netlist Type Requested ; Partition Contents             ;
+--------------------------------+----------------+-------------------+------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; Post-Fit               ;                                ;
; sld_hub:auto_hub               ; Auto-generated ; Post-Synthesis    ; Post-Synthesis         ; sld_hub:auto_hub               ;
; sld_signaltap:auto_signaltap_0 ; Auto-generated ; Post-Synthesis    ; Post-Synthesis         ; sld_signaltap:auto_signaltap_0 ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; Source File            ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+------------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0"                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------------------------------------------------------------+---------------+-----------+----------------+-------------------+---------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                                                                          ; Type          ; Status    ; Partition Name ; Netlist Type Used ; Actual Connection                                                                                       ; Details                                                                                                                                                        ;
+-----------------------------------------------------------------------------------------------+---------------+-----------+----------------+-------------------+---------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A0[0]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[0]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[0]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[0]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[0]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[0]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[1]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[1]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[1]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[1]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[1]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[1]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[2]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[2]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[2]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[2]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[2]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[2]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[3]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[3]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[3]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[3]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[3]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[3]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[4]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[4]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[4]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[4]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[4]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[4]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[5]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[5]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[5]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[5]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[5]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[5]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[6]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[6]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[6]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[6]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[6]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[6]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[7]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[7]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[7]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[7]                                                                                                   ; N/A                                                                                                                                                            ;
; A0[7]                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; A0[7]                                                                                                   ; N/A                                                                                                                                                            ;
; BANK1_CS                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BANK1_CS                                                                                                ; N/A                                                                                                                                                            ;
; BANK1_CS                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BANK1_CS                                                                                                ; N/A                                                                                                                                                            ;
; BANK1_CS                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BANK1_CS                                                                                                ; N/A                                                                                                                                                            ;
; BIOS_CS                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BIOS_CS                                                                                                 ; N/A                                                                                                                                                            ;
; BIOS_CS                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BIOS_CS                                                                                                 ; N/A                                                                                                                                                            ;
; BIOS_CS                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BIOS_CS                                                                                                 ; N/A                                                                                                                                                            ;
; BYTE_ADDR[0]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[0]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[0]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[0]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[0]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[0]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[10]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[10]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[10]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[10]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[10]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[10]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[11]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[11]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[11]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[11]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[11]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[11]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[12]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[12]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[12]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[12]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[12]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[12]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[13]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[13]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[13]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[13]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[13]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[13]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[14]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[14]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[14]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[14]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[14]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[14]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[15]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[15]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[15]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[15]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[15]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[15]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[16]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[16]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[16]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[16]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[16]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[16]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[17]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[17]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[17]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[17]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[17]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[17]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[18]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[18]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[18]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[18]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[18]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[18]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[19]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[19]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[19]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[19]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[19]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[19]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[1]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[1]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[1]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[1]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[1]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[1]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[20]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[20]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[20]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[20]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[20]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[20]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[21]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[21]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[21]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[21]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[21]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[21]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[22]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[22]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[22]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[22]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[22]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[22]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[23]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[23]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[23]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[23]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[23]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[23]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[24]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[24]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[24]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[24]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[24]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[24]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[25]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[25]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[25]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[25]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[25]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[25]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[26]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[26]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[26]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[26]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[26]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[26]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[27]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[27]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[27]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[27]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[27]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[27]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[28]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[28]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[28]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[28]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[28]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[28]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[29]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[29]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[29]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[29]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[29]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[29]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[2]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[2]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[2]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[2]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[2]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[2]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[30]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[30]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[30]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[30]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[30]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[30]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[31]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[31]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[31]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[31]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[31]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[31]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_ADDR[3]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[3]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[3]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[3]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[3]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[3]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[4]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[4]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[4]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[4]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[4]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[4]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[5]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[5]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[5]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[5]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[5]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[5]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[6]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[6]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[6]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[6]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[6]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[6]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[7]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[7]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[7]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[7]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[7]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[7]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[8]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[8]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[8]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[8]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[8]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[8]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[9]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[9]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[9]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[9]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_ADDR[9]                                                                                  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_ADDR[9]                                                                                            ; N/A                                                                                                                                                            ;
; BYTE_COUNT[0]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[0]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[0]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[0]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[0]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[0]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[1]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[1]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[1]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[1]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[1]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[1]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[2]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[2]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[2]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[2]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[2]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[2]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[3]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[3]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[3]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[3]                                                                                           ; N/A                                                                                                                                                            ;
; BYTE_COUNT[3]                                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; BYTE_COUNT[3]                                                                                           ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[0]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[0]~89                                                                                     ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[0]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[0]~89                                                                                     ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[0]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[0]~89                                                                                     ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[10]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[10]~157                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[10]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[10]~157                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[10]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[10]~157                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[11]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[11]~194                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[11]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[11]~194                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[11]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[11]~194                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[12]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[12]~226                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[12]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[12]~226                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[12]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[12]~226                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[13]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[13]~258                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[13]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[13]~258                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[13]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[13]~258                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[14]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[14]~291                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[14]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[14]~291                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[14]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[14]~291                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[15]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[15]~323                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[15]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[15]~323                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[15]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[15]~323                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[16]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[16]~355                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[16]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[16]~355                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[16]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[16]~355                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[17]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[17]~387                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[17]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[17]~387                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[17]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[17]~387                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[18]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[18]~420                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[18]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[18]~420                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[18]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[18]~420                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[19]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[19]~452                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[19]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[19]~452                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[19]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[19]~452                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[1]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[1]~456                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[1]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[1]~456                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[1]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[1]~456                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[20]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[20]~488                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[20]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[20]~488                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[20]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[20]~488                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[21]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[21]~520                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[21]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[21]~520                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[21]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[21]~520                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[22]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[22]~553                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[22]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[22]~553                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[22]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[22]~553                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[23]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[23]~585                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[23]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[23]~585                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[23]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[23]~585                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[24]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[24]~617                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[24]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[24]~617                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[24]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[24]~617                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[25]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[25]~649                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[25]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[25]~649                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[25]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[25]~649                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[26]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[26]~681                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[26]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[26]~681                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[26]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[26]~681                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[27]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[27]~712                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[27]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[27]~712                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[27]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[27]~712                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[28]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[28]~743                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[28]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[28]~743                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[28]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[28]~743                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[29]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[29]~774                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[29]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[29]~774                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[29]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[29]~774                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[2]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[2]~776                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[2]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[2]~776                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[2]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[2]~776                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[30]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[30]~809                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[30]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[30]~809                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[30]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[30]~809                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[31]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[31]~840                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[31]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[31]~840                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[31]                                                                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[31]~840                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[3]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[3]~879                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[3]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[3]~879                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[3]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[3]~879                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[4]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[4]~912                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[4]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[4]~912                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[4]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[4]~912                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[5]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[5]~945                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[5]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[5]~945                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[5]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[5]~945                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[6]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[6]~977                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[6]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[6]~977                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[6]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[6]~977                                                                                    ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[7]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[7]~1008                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[7]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[7]~1008                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[7]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[7]~1008                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[8]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[8]~1039                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[8]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[8]~1039                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[8]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[8]~1039                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[9]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[9]~1070                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[9]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[9]~1070                                                                                   ; N/A                                                                                                                                                            ;
; DATA_READ_MUX[9]                                                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DATA_READ_MUX[9]~1070                                                                                   ; N/A                                                                                                                                                            ;
; DS1386_CS                                                                                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DS1386_CS                                                                                               ; N/A                                                                                                                                                            ;
; DS1386_CS                                                                                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DS1386_CS                                                                                               ; N/A                                                                                                                                                            ;
; DS1386_CS                                                                                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; DS1386_CS                                                                                               ; N/A                                                                                                                                                            ;
; HACK_CS                                                                                       ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; HACK_CS                                                                                       ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; HACK_CS                                                                                       ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; HAL2_CS                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; HAL2_CS                                                                                                 ; N/A                                                                                                                                                            ;
; HAL2_CS                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; HAL2_CS                                                                                                 ; N/A                                                                                                                                                            ;
; HAL2_CS                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; HAL2_CS                                                                                                 ; N/A                                                                                                                                                            ;
; HD0_CS                                                                                        ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; HD0_CS                                                                                        ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; HD0_CS                                                                                        ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; HD_ENET_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; HD_ENET_CS                                                                                              ; N/A                                                                                                                                                            ;
; HD_ENET_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; HD_ENET_CS                                                                                              ; N/A                                                                                                                                                            ;
; HD_ENET_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; HD_ENET_CS                                                                                              ; N/A                                                                                                                                                            ;
; IOC_CS                                                                                        ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; IOC_CS                                                                                        ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; IOC_CS                                                                                        ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; KEY[0]                                                                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[0]                                                                                                  ; N/A                                                                                                                                                            ;
; KEY[0]                                                                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[0]                                                                                                  ; N/A                                                                                                                                                            ;
; KEY[0]                                                                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; KEY[0]                                                                                                  ; N/A                                                                                                                                                            ;
; MAINRAM2_CS                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MAINRAM2_CS                                                                                             ; N/A                                                                                                                                                            ;
; MAINRAM2_CS                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MAINRAM2_CS                                                                                             ; N/A                                                                                                                                                            ;
; MAINRAM2_CS                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MAINRAM2_CS                                                                                             ; N/A                                                                                                                                                            ;
; MAINRAM_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MAINRAM_CS                                                                                              ; N/A                                                                                                                                                            ;
; MAINRAM_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MAINRAM_CS                                                                                              ; N/A                                                                                                                                                            ;
; MAINRAM_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MAINRAM_CS                                                                                              ; N/A                                                                                                                                                            ;
; MC_CS                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MC_CS                                                                                                   ; N/A                                                                                                                                                            ;
; MC_CS                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MC_CS                                                                                                   ; N/A                                                                                                                                                            ;
; MC_CS                                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; MC_CS                                                                                                   ; N/A                                                                                                                                                            ;
; MIPS_INT                                                                                      ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; MIPS_INT                                                                                      ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; MIPS_INT                                                                                      ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; NEWPORT_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; NEWPORT_CS                                                                                              ; N/A                                                                                                                                                            ;
; NEWPORT_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; NEWPORT_CS                                                                                              ; N/A                                                                                                                                                            ;
; NEWPORT_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; NEWPORT_CS                                                                                              ; N/A                                                                                                                                                            ;
; PBUS4_CS                                                                                      ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; PBUS4_CS                                                                                      ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; PBUS4_CS                                                                                      ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; PBUSDMA_CS                                                                                    ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; PBUSDMA_CS                                                                                    ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; PBUSDMA_CS                                                                                    ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; PUTCHAR                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; PUTCHAR                                                                                                 ; N/A                                                                                                                                                            ;
; PUTCHAR                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; PUTCHAR                                                                                                 ; N/A                                                                                                                                                            ;
; PUTCHAR                                                                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; PUTCHAR                                                                                                 ; N/A                                                                                                                                                            ;
; READ_STATE                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; always2~0                                                                                               ; N/A                                                                                                                                                            ;
; READ_STATE                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; always2~0                                                                                               ; N/A                                                                                                                                                            ;
; READ_STATE                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; always2~0                                                                                               ; N/A                                                                                                                                                            ;
; SCRATCH_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; SCRATCH_CS                                                                                              ; N/A                                                                                                                                                            ;
; SCRATCH_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; SCRATCH_CS                                                                                              ; N/A                                                                                                                                                            ;
; SCRATCH_CS                                                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; SCRATCH_CS                                                                                              ; N/A                                                                                                                                                            ;
; SMALLRAM_CS                                                                                   ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; SMALLRAM_CS                                                                                   ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; SMALLRAM_CS                                                                                   ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; UNKBUS0_CS                                                                                    ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; UNKBUS0_CS                                                                                    ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; UNKBUS0_CS                                                                                    ; pre-synthesis ; missing   ; Top            ; post-synthesis    ; GND                                                                                                     ; The name does not exist in your design or refers to an invalid hierarchy or bus element.  You may have modified your design after creating the debug instance. ;
; WRITE_DATA_BACKUP[0]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[0]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[0]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[0]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[0]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[0]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[10]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[10]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[10]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[10]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[10]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[10]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[11]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[11]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[11]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[11]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[11]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[11]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[12]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[12]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[12]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[12]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[12]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[12]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[13]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[13]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[13]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[13]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[13]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[13]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[14]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[14]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[14]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[14]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[14]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[14]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[15]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[15]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[15]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[15]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[15]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[15]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[16]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[16]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[16]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[16]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[16]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[16]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[17]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[17]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[17]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[17]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[17]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[17]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[18]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[18]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[18]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[18]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[18]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[18]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[19]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[19]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[19]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[19]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[19]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[19]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[1]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[1]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[1]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[1]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[1]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[1]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[20]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[20]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[20]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[20]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[20]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[20]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[21]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[21]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[21]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[21]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[21]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[21]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[22]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[22]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[22]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[22]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[22]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[22]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[23]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[23]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[23]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[23]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[23]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[23]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[24]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[24]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[24]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[24]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[24]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[24]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[25]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[25]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[25]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[25]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[25]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[25]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[26]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[26]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[26]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[26]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[26]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[26]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[27]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[27]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[27]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[27]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[27]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[27]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[28]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[28]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[28]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[28]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[28]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[28]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[29]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[29]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[29]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[29]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[29]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[29]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[2]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[2]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[2]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[2]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[2]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[2]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[30]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[30]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[30]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[30]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[30]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[30]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[31]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[31]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[31]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[31]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[31]                                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[31]                                                                                   ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[3]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[3]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[3]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[3]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[3]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[3]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[4]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[4]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[4]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[4]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[4]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[4]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[5]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[5]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[5]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[5]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[5]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[5]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[6]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[6]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[6]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[6]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[6]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[6]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[7]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[7]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[7]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[7]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[7]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[7]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[8]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[8]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[8]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[8]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[8]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[8]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[9]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[9]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[9]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[9]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_DATA_BACKUP[9]                                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_DATA_BACKUP[9]                                                                                    ; N/A                                                                                                                                                            ;
; WRITE_STATE                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_STATE~0                                                                                           ; N/A                                                                                                                                                            ;
; WRITE_STATE                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_STATE~0                                                                                           ; N/A                                                                                                                                                            ;
; WRITE_STATE                                                                                   ; pre-synthesis ; connected ; Top            ; post-synthesis    ; WRITE_STATE~0                                                                                           ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_read                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|memory_avalon:memory_avalon_inst|avm_read                                          ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_read                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|memory_avalon:memory_avalon_inst|avm_read                                          ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_read                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|memory_avalon:memory_avalon_inst|avm_read                                          ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[0]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[0]~1                                                                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[0]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[0]~1                                                                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[0]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[0]~1                                                                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[10]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[10]~3                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[10]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[10]~3                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[10]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[10]~3                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[11]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[11]~5                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[11]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[11]~5                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[11]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[11]~5                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[12]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[12]~7                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[12]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[12]~7                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[12]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[12]~7                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[13]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[13]~9                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[13]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[13]~9                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[13]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[13]~9                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[14]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[14]~11                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[14]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[14]~11                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[14]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[14]~11                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[15]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[15]~13                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[15]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[15]~13                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[15]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[15]~13                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[16]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[16]~15                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[16]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[16]~15                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[16]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[16]~15                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[17]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[17]~17                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[17]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[17]~17                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[17]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[17]~17                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[18]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[18]~19                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[18]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[18]~19                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[18]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[18]~19                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[19]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[19]~21                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[19]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[19]~21                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[19]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[19]~21                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[1]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[1]~23                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[1]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[1]~23                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[1]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[1]~23                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[20]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[20]~25                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[20]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[20]~25                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[20]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[20]~25                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[21]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[21]~27                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[21]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[21]~27                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[21]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[21]~27                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[22]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[22]~29                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[22]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[22]~29                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[22]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[22]~29                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[23]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[23]~31                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[23]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[23]~31                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[23]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[23]~31                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[24]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[24]~33                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[24]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[24]~33                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[24]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[24]~33                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[25]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[25]~35                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[25]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[25]~35                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[25]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[25]~35                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[26]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[26]~37                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[26]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[26]~37                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[26]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[26]~37                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[27]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[27]~39                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[27]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[27]~39                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[27]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[27]~39                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[28]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[28]~41                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[28]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[28]~41                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[28]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[28]~41                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[29]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[29]~43                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[29]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[29]~43                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[29]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[29]~43                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[2]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[2]~45                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[2]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[2]~45                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[2]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[2]~45                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[30]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[30]~47                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[30]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[30]~47                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[30]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[30]~47                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[31]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[31]~49                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[31]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[31]~49                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[31]                                                         ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[31]~49                                                                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[3]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[3]~51                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[3]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[3]~51                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[3]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[3]~51                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[4]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[4]~53                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[4]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[4]~53                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[4]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[4]~53                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[5]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[5]~55                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[5]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[5]~55                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[5]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[5]~55                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[6]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[6]~57                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[6]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[6]~57                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[6]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[6]~57                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[7]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[7]~59                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[7]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[7]~59                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[7]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[7]~59                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[8]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[8]~61                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[8]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[8]~61                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[8]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[8]~61                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[9]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[9]~63                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[9]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[9]~63                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdata[9]                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; data_flipped[9]~63                                                                                      ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdatavalid                                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; avm_readdatavalid                                                                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdatavalid                                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; avm_readdatavalid                                                                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_readdatavalid                                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; avm_readdatavalid                                                                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_waitrequest                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; avm_waitrequest~_wirecell                                                                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_waitrequest                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; avm_waitrequest~_wirecell                                                                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_waitrequest                                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; avm_waitrequest~_wirecell                                                                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_write                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|memory_avalon:memory_avalon_inst|avm_write                                         ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_write                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|memory_avalon:memory_avalon_inst|avm_write                                         ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|avm_write                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|memory_avalon:memory_avalon_inst|avm_write                                         ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[0]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[0]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[0]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[0]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[0]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[0]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[10]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[10]                                             ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[10]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[10]                                             ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[10]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[10]                                             ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[11]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[11]                                             ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[11]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[11]                                             ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[11]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[11]                                             ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[12]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[0]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[12]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[0]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[12]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[0]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[13]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[1]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[13]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[1]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[13]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[1]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[14]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[2]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[14]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[2]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[14]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[2]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[15]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[3]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[15]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[3]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[15]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[3]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[16]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[4]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[16]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[4]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[16]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[4]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[17]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[5]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[17]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[5]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[17]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[5]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[18]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[6]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[18]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[6]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[18]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[6]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[19]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[7]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[19]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[7]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[19]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[7]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[1]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[1]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[1]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[1]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[1]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[1]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[20]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[8]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[20]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[8]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[20]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[8]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[21]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[9]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[21]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[9]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[21]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[9]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[22]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[10]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[22]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[10]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[22]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[10]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[23]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[11]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[23]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[11]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[23]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[11]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[24]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[12]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[24]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[12]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[24]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[12]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[25]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[13]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[25]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[13]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[25]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[13]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[26]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[14]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[26]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[14]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[26]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[14]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[27]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[15]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[27]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[15]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[27]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[15]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[28]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[16]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[28]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[16]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[28]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[16]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[29]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[17]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[29]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[17]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[29]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[17]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[2]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[2]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[2]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[2]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[2]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[2]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[30]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[18]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[30]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[18]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[30]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[18]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[31]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[19]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[31]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[19]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[31]                                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|micro_check_vpn[19]                                   ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[3]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[3]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[3]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[3]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[3]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[3]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[4]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[4]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[4]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[4]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[4]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[4]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[5]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[5]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[5]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[5]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[5]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[5]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[6]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[6]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[6]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[6]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[6]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[6]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[7]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[7]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[7]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[7]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[7]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[7]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[8]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[8]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[8]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[8]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[8]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[8]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[9]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[9]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[9]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[9]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|if_pc[9]                                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_if:pipeline_if_inst|if_pc[9]                                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[0]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[0]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[0]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[0]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[0]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[0]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[10]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[10]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[10]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[10]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[10]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[10]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[11]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[11]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[11]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[11]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[11]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[11]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[12]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[12]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[12]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[12]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[12]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[12]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[13]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[13]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[13]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[13]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[13]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[13]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[14]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[14]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[14]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[14]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[14]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[14]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[15]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[15]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[15]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[15]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[15]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[15]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[16]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[16]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[16]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[16]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[16]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[16]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[17]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[17]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[17]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[17]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[17]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[17]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[18]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[18]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[18]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[18]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[18]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[18]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[19]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[19]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[19]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[19]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[19]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[19]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[1]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[1]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[1]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[1]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[1]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[1]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[20]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[20]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[20]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[20]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[20]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[20]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[21]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[21]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[21]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[21]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[21]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[21]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[22]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[22]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[22]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[22]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[22]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[22]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[23]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[23]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[23]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[23]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[23]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[23]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[24]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[24]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[24]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[24]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[24]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[24]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[25]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[25]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[25]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[25]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[25]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[25]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[26]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[26]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[26]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[26]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[26]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[26]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[27]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[27]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[27]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[27]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[27]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[27]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[28]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[28]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[28]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[28]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[28]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[28]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[29]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[29]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[29]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[29]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[29]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[29]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[2]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[2]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[2]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[2]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[2]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[2]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[30]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[30]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[30]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[30]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[30]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[30]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[31]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[31]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[31]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[31]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[31]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[31]                                    ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[3]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[3]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[3]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[3]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[3]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[3]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[4]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[4]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[4]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[4]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[4]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[4]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[5]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[5]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[5]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[5]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[5]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[5]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[6]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[6]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[6]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[6]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[6]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[6]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[7]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[7]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[7]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[7]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[7]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[7]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[8]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[8]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[8]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[8]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[8]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[8]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[9]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[9]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[9]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[9]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[9]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|data_address[9]                                     ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_load                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_load                                        ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_load                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_load                                        ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_load                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_load                                        ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_store                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_store                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_store                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_store                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_store                             ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_exe:pipeline_exe_inst|exe_cmd_store                                       ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[0] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[0]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[0] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[0]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[0] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[0]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[1] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[1]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[1] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[1]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[1] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[1]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[2] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[2]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[2] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[2]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[2] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[2]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[3] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[3]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[3] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[3]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[3] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[3]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[4] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[4]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[4] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[4]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[4] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|block_cp0:block_cp0_inst|cause_exccode[4]~_wirecell ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[0]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[0]~1                                ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[0]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[0]~1                                ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[0]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[0]~1                                ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[10]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[10]~3                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[10]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[10]~3                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[10]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[10]~3                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[11]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[11]~5                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[11]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[11]~5                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[11]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[11]~5                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[12]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[12]~7                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[12]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[12]~7                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[12]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[12]~7                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[13]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[13]~9                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[13]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[13]~9                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[13]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[13]~9                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[14]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[14]~11                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[14]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[14]~11                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[14]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[14]~11                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[15]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[15]~13                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[15]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[15]~13                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[15]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[15]~13                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[16]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[16]~15                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[16]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[16]~15                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[16]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[16]~15                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[17]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[17]~17                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[17]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[17]~17                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[17]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[17]~17                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[18]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[18]~19                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[18]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[18]~19                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[18]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[18]~19                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[19]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[19]~21                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[19]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[19]~21                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[19]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[19]~21                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[1]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[1]~23                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[1]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[1]~23                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[1]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[1]~23                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[20]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[20]~25                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[20]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[20]~25                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[20]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[20]~25                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[21]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[21]~27                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[21]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[21]~27                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[21]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[21]~27                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[22]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[22]~29                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[22]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[22]~29                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[22]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[22]~29                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[23]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[23]~31                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[23]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[23]~31                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[23]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[23]~31                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[24]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[24]~33                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[24]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[24]~33                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[24]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[24]~33                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[25]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[25]~35                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[25]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[25]~35                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[25]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[25]~35                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[26]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[26]~37                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[26]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[26]~37                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[26]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[26]~37                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[27]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[27]~39                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[27]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[27]~39                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[27]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[27]~39                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[28]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[28]~41                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[28]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[28]~41                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[28]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[28]~41                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[29]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[29]~43                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[29]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[29]~43                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[29]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[29]~43                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[2]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[2]~45                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[2]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[2]~45                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[2]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[2]~45                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[30]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[30]~47                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[30]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[30]~47                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[30]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[30]~47                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[31]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[31]~49                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[31]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[31]~49                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[31]                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[31]~49                              ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[3]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[3]~51                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[3]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[3]~51                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[3]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[3]~51                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[4]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[4]~53                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[4]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[4]~53                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[4]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[4]~53                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[5]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[5]~55                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[5]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[5]~55                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[5]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[5]~55                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[6]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[6]~57                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[6]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[6]~57                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[6]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[6]~57                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[7]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[7]~59                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[7]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[7]~59                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[7]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[7]~59                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[8]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[8]~61                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[8]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[8]~61                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[8]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[8]~61                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[9]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[9]~63                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[9]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[9]~63                               ; N/A                                                                                                                                                            ;
; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[9]                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; aoR3000:aoR3000_inst|pipeline_mem:pipeline_mem_inst|data_cache_data[9]~63                               ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COLDRESET_N                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COLDRESET_N                                                        ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COLDRESET_N                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COLDRESET_N                                                        ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COLDRESET_N                                              ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COLDRESET_N                                                        ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[0]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[0]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[0]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[1]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[1]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[1]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[2]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[2]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[2]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[3]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[3]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|COUNT[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|COUNT[3]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|EOK_N                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|EOK_N~_wirecell                                                    ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|EOK_N                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|EOK_N~_wirecell                                                    ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|EOK_N                                                    ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|EOK_N~_wirecell                                                    ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|EVALID_N                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|EVALID_N~_wirecell                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|EVALID_N                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|EVALID_N~_wirecell                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|EVALID_N                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|EVALID_N~_wirecell                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|PVALID_N                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[2]~0                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|PVALID_N                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[2]~0                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|PVALID_N                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[2]~0                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[0]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[0]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[0]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[0]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[0]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[0]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[10]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[10]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[10]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[10]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[10]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[10]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[11]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[11]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[11]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[11]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[11]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[11]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[12]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[12]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[12]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[12]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[12]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[12]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[13]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[13]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[13]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[13]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[13]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[13]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[14]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[14]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[14]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[14]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[14]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[14]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[15]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[15]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[15]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[15]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[15]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[15]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[16]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[16]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[16]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[16]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[16]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[16]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[17]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[17]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[17]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[17]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[17]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[17]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[18]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[18]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[18]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[18]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[18]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[18]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[19]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[19]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[19]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[19]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[19]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[19]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[1]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[1]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[1]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[1]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[1]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[1]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[20]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[20]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[20]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[20]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[20]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[20]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[21]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[21]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[21]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[21]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[21]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[21]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[22]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[22]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[22]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[22]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[22]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[22]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[23]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[23]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[23]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[23]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[23]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[23]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[24]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[24]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[24]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[24]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[24]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[24]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[25]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[25]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[25]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[25]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[25]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[25]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[26]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[26]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[26]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[26]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[26]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[26]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[27]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[27]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[27]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[27]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[27]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[27]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[28]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[28]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[28]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[28]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[28]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[28]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[29]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[29]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[29]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[29]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[29]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[29]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[2]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[2]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[2]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[2]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[2]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[2]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[30]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[30]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[30]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[30]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[30]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[30]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[31]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[31]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[31]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[31]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[31]                                       ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[31]                                                 ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[3]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[3]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[3]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[3]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[3]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[3]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[4]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[4]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[4]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[4]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[4]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[4]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[5]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[5]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[5]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[5]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[5]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[5]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[6]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[6]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[6]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[6]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[6]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[6]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[7]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[7]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[7]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[7]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[7]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[7]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[8]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[8]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[8]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[8]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[8]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[8]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[9]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[9]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[9]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[9]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[9]                                        ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_ADDR_OUT[9]                                                  ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_READDATA_VALID                                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; VCC                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_READDATA_VALID                                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; VCC                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_READDATA_VALID                                     ; pre-synthesis ; connected ; Top            ; post-synthesis    ; VCC                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_READ_REQ                                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_READ_REQ                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_READ_REQ                                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_READ_REQ                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_READ_REQ                                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_READ_REQ                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_WRITE_ACK                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; VCC                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_WRITE_ACK                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; VCC                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_WRITE_ACK                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; VCC                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_WRITE_REQ                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_WRITE_REQ                                                    ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_WRITE_REQ                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_WRITE_REQ                                                    ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|R4300_WRITE_REQ                                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|R4300_WRITE_REQ                                                    ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|STATE[0]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|STATE[0]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|STATE[0]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|STATE[1]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|STATE[1]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|STATE[1]                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[4]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[4]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[4]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[5]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[5]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[5]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[6]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[6]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[6]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[7]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[7]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|STATE[7]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[21]~1                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[21]~1                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[0]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[21]~1                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[10]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[15]~0                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[10]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[15]~0                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[10]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[15]~0                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[11]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[19]~1                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[11]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[19]~1                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[11]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[19]~1                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[12]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[13]~2                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[12]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[13]~2                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[12]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[13]~2                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[13]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[21]~3                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[13]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[21]~3                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[13]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[21]~3                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[14]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[11]~4                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[14]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[11]~4                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[14]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[11]~4                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[15]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[12]~5                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[15]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[12]~5                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[15]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[12]~5                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[16]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[9]~6                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[16]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[9]~6                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[16]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[9]~6                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[17]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[8]~7                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[17]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[8]~7                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[17]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[8]~7                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[18]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[7]~8                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[18]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[7]~8                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[18]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[7]~8                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[19]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[6]~9                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[19]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[6]~9                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[19]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[6]~9                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[22]~2                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[22]~2                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[1]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[22]~2                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[20]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[5]~10                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[20]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[5]~10                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[20]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[5]~10                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[21]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[4]~11                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[21]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[4]~11                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[21]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[4]~11                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[22]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[3]~12                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[22]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[3]~12                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[22]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[3]~12                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[23]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[10]~13                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[23]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[10]~13                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[23]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[10]~13                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[24]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[1]~14                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[24]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[1]~14                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[24]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_0[1]~14                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[25]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[9]~3                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[25]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[9]~3                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[25]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[9]~3                                                                                             ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[26]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[10]~4                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[26]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[10]~4                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[26]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[10]~4                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[27]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[13]~5                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[27]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[13]~5                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[27]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[13]~5                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[28]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[14]~6                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[28]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[14]~6                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[28]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[14]~6                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[29]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[15]~7                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[29]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[15]~7                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[29]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[15]~7                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[23]~8                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[23]~8                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[2]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[23]~8                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[30]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[19]~9                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[30]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[19]~9                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[30]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[19]~9                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[31]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[20]~10                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[31]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[20]~10                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[31]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[20]~10                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[24]~11                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[24]~11                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[3]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[24]~11                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[4]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[25]~12                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[4]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[25]~12                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[4]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[25]~12                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[5]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[26]~13                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[5]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[26]~13                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[5]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[26]~13                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[6]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[27]~14                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[6]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[27]~14                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[6]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[27]~14                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[7]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[28]~15                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[7]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[28]~15                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[7]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[28]~15                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[8]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[29]~16                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[8]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[29]~16                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[8]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[29]~16                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[9]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[30]~17                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[9]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[30]~17                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD[9]                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[30]~17                                                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD_OE                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|SYSAD_OE                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD_OE                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|SYSAD_OE                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSAD_OE                                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; r4300_interface:r4300_interface_inst|SYSAD_OE                                                           ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[0]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[8]~18                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[0]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[8]~18                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[0]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[8]~18                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[1]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[7]~19                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[1]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[7]~19                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[1]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[7]~19                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[2]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[5]~20                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[2]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[5]~20                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[2]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[5]~20                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[3]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[4]~21                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[3]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[4]~21                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[3]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[4]~21                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[4]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[1]~22                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[4]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[1]~22                                                                                            ; N/A                                                                                                                                                            ;
; r4300_interface:r4300_interface_inst|SYSCMD[4]                                                ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GPIO_1[1]~22                                                                                            ; N/A                                                                                                                                                            ;
; state[0]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[0]                                                                                                ; N/A                                                                                                                                                            ;
; state[0]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[0]                                                                                                ; N/A                                                                                                                                                            ;
; state[0]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[0]                                                                                                ; N/A                                                                                                                                                            ;
; state[1]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[1]                                                                                                ; N/A                                                                                                                                                            ;
; state[1]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[1]                                                                                                ; N/A                                                                                                                                                            ;
; state[1]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[1]                                                                                                ; N/A                                                                                                                                                            ;
; state[2]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[2]                                                                                                ; N/A                                                                                                                                                            ;
; state[2]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[2]                                                                                                ; N/A                                                                                                                                                            ;
; state[2]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[2]                                                                                                ; N/A                                                                                                                                                            ;
; state[3]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[3]                                                                                                ; N/A                                                                                                                                                            ;
; state[3]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[3]                                                                                                ; N/A                                                                                                                                                            ;
; state[3]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[3]                                                                                                ; N/A                                                                                                                                                            ;
; state[4]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[4]                                                                                                ; N/A                                                                                                                                                            ;
; state[4]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[4]                                                                                                ; N/A                                                                                                                                                            ;
; state[4]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; state[4]                                                                                                ; N/A                                                                                                                                                            ;
; state[5]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; state[5]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; state[5]                                                                                      ; pre-synthesis ; connected ; Top            ; post-synthesis    ; GND                                                                                                     ; N/A                                                                                                                                                            ;
; CLK_DIV[1]                                                                                    ; post-fitting  ; connected ; Top            ; post-synthesis    ; CLK_DIV[1]                                                                                              ; N/A                                                                                                                                                            ;
+-----------------------------------------------------------------------------------------------+---------------+-----------+----------------+-------------------+---------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Statistics                                                                                                     ;
+---------------------------------------------+-------+------------------+--------------------------------+--------------------------------+
; Statistic                                   ; Top   ; sld_hub:auto_hub ; sld_signaltap:auto_signaltap_0 ; hard_block:auto_generated_inst ;
+---------------------------------------------+-------+------------------+--------------------------------+--------------------------------+
; Estimated Total logic elements              ; 10532 ; 190              ; 7477                           ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Total combinational functions               ; 8387  ; 174              ; 2276                           ; 0                              ;
; Logic element usage by number of LUT inputs ;       ;                  ;                                ;                                ;
;     -- 4 input functions                    ; 5308  ; 69               ; 1806                           ; 0                              ;
;     -- 3 input functions                    ; 1938  ; 65               ; 405                            ; 0                              ;
;     -- <=2 input functions                  ; 1141  ; 40               ; 65                             ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Logic elements by mode                      ;       ;                  ;                                ;                                ;
;     -- normal mode                          ; 7598  ; 166              ; 2243                           ; 0                              ;
;     -- arithmetic mode                      ; 789   ; 8                ; 33                             ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Total registers                             ; 3865  ; 112              ; 6427                           ; 0                              ;
;     -- Dedicated logic registers            ; 3865  ; 112              ; 6427                           ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Virtual pins                                ; 0     ; 0                ; 0                              ; 0                              ;
; I/O pins                                    ; 283   ; 0                ; 0                              ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 8     ; 0                ; 0                              ; 0                              ;
; Total memory bits                           ; 70144 ; 0                ; 46848                          ; 0                              ;
; Total RAM block bits                        ; 0     ; 0                ; 0                              ; 0                              ;
; JTAG                                        ; 1     ; 0                ; 0                              ; 0                              ;
; PLL                                         ; 0     ; 0                ; 0                              ; 1                              ;
;                                             ;       ;                  ;                                ;                                ;
; Connections                                 ;       ;                  ;                                ;                                ;
;     -- Input Connections                    ; 421   ; 163              ; 9466                           ; 1                              ;
;     -- Registered Input Connections         ; 288   ; 122              ; 7540                           ; 0                              ;
;     -- Output Connections                   ; 9241  ; 554              ; 1                              ; 255                            ;
;     -- Registered Output Connections        ; 5091  ; 553              ; 0                              ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Internal Connections                        ;       ;                  ;                                ;                                ;
;     -- Total Connections                    ; 57629 ; 1495             ; 33754                          ; 256                            ;
;     -- Registered Connections               ; 19047 ; 1171             ; 26299                          ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; External Connections                        ;       ;                  ;                                ;                                ;
;     -- Top                                  ; 196   ; 222              ; 8988                           ; 256                            ;
;     -- sld_hub:auto_hub                     ; 222   ; 16               ; 479                            ; 0                              ;
;     -- sld_signaltap:auto_signaltap_0       ; 8988  ; 479              ; 0                              ; 0                              ;
;     -- hard_block:auto_generated_inst       ; 256   ; 0                ; 0                              ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Partition Interface                         ;       ;                  ;                                ;                                ;
;     -- Input Ports                          ; 45    ; 29               ; 1151                           ; 1                              ;
;     -- Output Ports                         ; 500   ; 46               ; 740                            ; 3                              ;
;     -- Bidir Ports                          ; 119   ; 0                ; 0                              ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Registered Ports                            ;       ;                  ;                                ;                                ;
;     -- Registered Input Ports               ; 0     ; 3                ; 1100                           ; 0                              ;
;     -- Registered Output Ports              ; 0     ; 35               ; 731                            ; 0                              ;
;                                             ;       ;                  ;                                ;                                ;
; Port Connectivity                           ;       ;                  ;                                ;                                ;
;     -- Input Ports driven by GND            ; 0     ; 5                ; 45                             ; 0                              ;
;     -- Output Ports driven by GND           ; 0     ; 1                ; 0                              ; 0                              ;
;     -- Input Ports driven by VCC            ; 0     ; 0                ; 6                              ; 0                              ;
;     -- Output Ports driven by VCC           ; 0     ; 0                ; 0                              ; 0                              ;
;     -- Input Ports with no Source           ; 0     ; 1                ; 34                             ; 0                              ;
;     -- Output Ports with no Source          ; 0     ; 0                ; 0                              ; 0                              ;
;     -- Input Ports with no Fanout           ; 0     ; 2                ; 39                             ; 0                              ;
;     -- Output Ports with no Fanout          ; 0     ; 18               ; 731                            ; 0                              ;
+---------------------------------------------+-------+------------------+--------------------------------+--------------------------------+
Note: Resource usage numbers presented for Partitions containing post-synthesis logic are estimates.  For Partitions containing post-fit logic, resource usage numbers are accurate based on previous placement information.  Actual Fitter results may vary depending on current Fitter Preservation Level assignments.


+----------------------------------------------------------+
; Partition Merge Resource Usage Summary                   ;
+---------------------------------------------+------------+
; Resource                                    ; Usage      ;
+---------------------------------------------+------------+
; Estimated Total logic elements              ; 18,144     ;
;                                             ;            ;
; Total combinational functions               ; 10837      ;
; Logic element usage by number of LUT inputs ;            ;
;     -- 4 input functions                    ; 7183       ;
;     -- 3 input functions                    ; 2408       ;
;     -- <=2 input functions                  ; 1246       ;
;                                             ;            ;
; Logic elements by mode                      ;            ;
;     -- normal mode                          ; 10007      ;
;     -- arithmetic mode                      ; 830        ;
;                                             ;            ;
; Total registers                             ; 10404      ;
;     -- Dedicated logic registers            ; 10404      ;
;     -- I/O registers                        ; 0          ;
;                                             ;            ;
; I/O pins                                    ; 283        ;
; Total memory bits                           ; 116992     ;
; Embedded Multiplier 9-bit elements          ; 8          ;
; Total PLLs                                  ; 1          ;
;     -- PLLs                                 ; 1          ;
;                                             ;            ;
; Maximum fan-out node                        ; CLK_DIV[1] ;
; Maximum fan-out                             ; 4278       ;
; Total fan-out                               ; 82610      ;
; Average fan-out                             ; 3.72       ;
+---------------------------------------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge RAM Summary                                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------+
; Name                                                                                                                                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF             ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------+
; OSD:OSD_inst|char_ram:char_ram_inst|altsyncram:altsyncram_component|altsyncram_nqn1:auto_generated|ALTSYNCRAM                                                                                         ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None            ;
; OSD:OSD_inst|font_rom:font_rom_inst|altsyncram:altsyncram_component|altsyncram_8681:auto_generated|ALTSYNCRAM                                                                                         ; AUTO ; ROM              ; 2048         ; 8            ; --           ; --           ; 16384 ; fontRomData.mif ;
; SCRATCH_RAM:SCRATCH_RAM_inst|altsyncram:altsyncram_component|altsyncram_1hi1:auto_generated|altsyncram_hsd2:altsyncram1|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 512          ; 32           ; 512          ; 32           ; 16384 ; None            ;
; aoR3000:aoR3000_inst|memory_cache_ram:memory_cache_ram_inst|model_fifo:ram_fifo_inst|altsyncram:mem_rtl_0|altsyncram_b9h1:auto_generated|ALTSYNCRAM                                                   ; AUTO ; Simple Dual Port ; 16           ; 64           ; 16           ; 64           ; 1024  ; None            ;
; aoR3000:aoR3000_inst|memory_cache_ram:memory_cache_ram_inst|model_simple_dual_ram:cache_1_inst|altsyncram:mem_rtl_0|altsyncram_uck1:auto_generated|ALTSYNCRAM                                         ; AUTO ; Simple Dual Port ; 512          ; 32           ; 512          ; 32           ; 16384 ; None            ;
; aoR3000:aoR3000_inst|memory_cache_ram:memory_cache_ram_inst|model_simple_dual_ram:cache_2_inst|altsyncram:mem_rtl_0|altsyncram_uck1:auto_generated|ALTSYNCRAM                                         ; AUTO ; Simple Dual Port ; 512          ; 32           ; 512          ; 32           ; 16384 ; None            ;
; aoR3000:aoR3000_inst|pipeline_rf:pipeline_rf_inst|model_simple_dual_ram:regs_a_inst|altsyncram:mem_rtl_0|altsyncram_g9k1:auto_generated|ALTSYNCRAM                                                    ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None            ;
; aoR3000:aoR3000_inst|pipeline_rf:pipeline_rf_inst|model_simple_dual_ram:regs_b_inst|altsyncram:mem_rtl_0|altsyncram_g9k1:auto_generated|ALTSYNCRAM                                                    ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; None            ;
; r4300_interface:r4300_interface_inst|altsyncram:SYSAD_OUT_REG_rtl_0|altsyncram_qpf1:auto_generated|ALTSYNCRAM                                                                                         ; AUTO ; Simple Dual Port ; 16           ; 32           ; 16           ; 32           ; 512   ; None            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_3f54:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128          ; 366          ; 128          ; 366          ; 46848 ; None            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------+


+-----------------------------------------------------+
; Partition Merge DSP Block Usage Summary             ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 4           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 8           ;
; Signed Embedded Multipliers           ; 1           ;
; Unsigned Embedded Multipliers         ; 1           ;
; Mixed Sign Embedded Multipliers       ; 2           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+--------------------------+
; Partition Merge Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Partition Merge
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue Feb 06 18:59:09 2018
Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off DE1_TOP -c DE1_TOP --merge=on
Critical Warning (138069): Setting INCREMENTAL_COMPILATION to "OFF" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to "ON" instead.
Warning (35010): Previously generated Fitter netlist for partition "Top" is older than current Synthesis netlist -- using the current Synthesis netlist instead to ensure that the latest source changes are included
    Info (35011): Set the option to Ignore source file changes to force the Quartus II software to always use a previously generated Fitter netlist
Info (35007): Using synthesis netlist for partition "Top"
Info (35007): Using synthesis netlist for partition "sld_hub:auto_hub"
Info (35007): Using synthesis netlist for partition "sld_signaltap:auto_signaltap_0"
Critical Warning (35025): Partially connected in-system debug instance "auto_signaltap_0" to 1072 of its 1096 required data inputs, trigger inputs, acquisition clocks, and dynamic pins.  There were 0 illegal, 0 inaccessible, and 24 missing sources or connections.
Info (35002): Resolved and merged 3 partition(s)
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 18 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLOCK_24[0]"
    Warning (15610): No output dependent on input pin "CLOCK_24[1]"
    Warning (15610): No output dependent on input pin "CLOCK_27[1]"
    Warning (15610): No output dependent on input pin "CLOCK_50"
    Warning (15610): No output dependent on input pin "EXT_CLOCK"
    Warning (15610): No output dependent on input pin "KEY[1]"
    Warning (15610): No output dependent on input pin "SW[1]"
    Warning (15610): No output dependent on input pin "SW[2]"
    Warning (15610): No output dependent on input pin "SW[3]"
    Warning (15610): No output dependent on input pin "SW[4]"
    Warning (15610): No output dependent on input pin "SW[5]"
    Warning (15610): No output dependent on input pin "SW[6]"
    Warning (15610): No output dependent on input pin "SW[7]"
    Warning (15610): No output dependent on input pin "UART_RXD"
    Warning (15610): No output dependent on input pin "TDI"
    Warning (15610): No output dependent on input pin "TCK"
    Warning (15610): No output dependent on input pin "TCS"
    Warning (15610): No output dependent on input pin "AUD_ADCDAT"
Info (21057): Implemented 19725 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 30 input pins
    Info (21059): Implemented 138 output pins
    Info (21060): Implemented 119 bidirectional pins
    Info (21061): Implemented 18766 logic cells
    Info (21064): Implemented 662 RAM segments
    Info (21065): Implemented 1 PLLs
    Info (21062): Implemented 8 DSP elements
Info: Quartus II 64-Bit Partition Merge was successful. 0 errors, 22 warnings
    Info: Peak virtual memory: 618 megabytes
    Info: Processing ended: Tue Feb 06 18:59:13 2018
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:04