Sys68_inst.v

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II 64-Bit Version 13.0 (Build Build 232 06/12/2013)
// Created on Sat Jun 16 19:13:33 2018

Sys68 Sys68_inst
(
	.SysClk(SysClk) ,	// input  SysClk
	.Reset_n(Reset_n) ,	// input  Reset_n
	.ram_csn(ram_csn) ,	// output  ram_csn
	.ram_wrln(ram_wrln) ,	// output  ram_wrln
	.ram_wrun(ram_wrun) ,	// output  ram_wrun
	.ram_addr(ram_addr) ,	// output [16:0] ram_addr
	.ram_data(ram_data) ,	// inout [15:0] ram_data
	.LED(LED) ,	// output  LED
	.rxbit(rxbit) ,	// input  rxbit
	.txbit(txbit) ,	// output  txbit
	.rts_n(rts_n) ,	// output  rts_n
	.cts_n(cts_n) ,	// input  cts_n
	.cf_rst_n(cf_rst_n) ,	// output  cf_rst_n
	.cf_cs0_n(cf_cs0_n) ,	// output  cf_cs0_n
	.cf_cs1_n(cf_cs1_n) ,	// output  cf_cs1_n
	.cf_rd_n(cf_rd_n) ,	// output  cf_rd_n
	.cf_wr_n(cf_wr_n) ,	// output  cf_wr_n
	.cf_cs16_n(cf_cs16_n) ,	// output  cf_cs16_n
	.cf_a(cf_a) ,	// output [2:0] cf_a
	.cf_d(cf_d) ,	// inout [15:0] cf_d
	.porta(porta) ,	// inout [7:0] porta
	.portb(portb) ,	// inout [7:0] portb
	.timer_out(timer_out) ,	// output  timer_out
	.bus_addr(bus_addr) ,	// output [15:0] bus_addr
	.bus_data(bus_data) ,	// inout [7:0] bus_data
	.bus_rw(bus_rw) ,	// output  bus_rw
	.bus_cs(bus_cs) ,	// output  bus_cs
	.bus_clk(bus_clk) ,	// output  bus_clk
	.bus_reset(bus_reset) 	// output  bus_reset
);