[Feature request] Adding support of 2.5Gb Ethernet PHY

[ohault]

If UHD FPGA gateware could be updated to support 2.5Gb Ethernet PHY, this would be very nice for smaller labs.

[mbr0wn]

Hi @ohault, this is very low on our priority list. 2.5GbE may be becoming more common, but it's not even fast enough for many of our devices (at sc16 samples, it can maybe sustain 75 Msps). Also, there are no free Xilinx PHY cores we can use.

[ohault]

Hi @mbr0wn, you will find some motivation at https://github.com/enjoy-digital/liteeth
This question introduces another one, even more interesting about LiteX FPGA development for Etthus Research devices. USRP family could perhaps join https://github.com/litex-hub/litex-boards? :-)

[mbr0wn]

Hi @ohault, thanks for pointing that out, I didn't know that LiteX had a 2.5 GbE PHY (or any PHY, for that matter).

As for USRPs becoming LiteX projects: We've been working on the HDL architecture for a very long time, and won't be switching our entire architecture to make the USRP become a LiteX board. However, I could see an integration path of LiteX components (or Amaranth modules) into RFNoC (note that this is also not a high-priority roadmap item). On X410, users can already develop their own custom transport adapters, so if you could build the PHY in a container recognizable by RFNoC, then you could build your own bitfiles with 2.5 GbE, with your own out-of-tree transport adapter.

[ohault]

@mbr0wn, I never ask about switching your entire archictecture, but only the opportunity to "sponsor" the fact that Etthus Research boards and devices could also be supported by LiteX framework. This coud be a great community opportunity/initiative for Etthus Research as SDR are starting to become more ubiticious. Feel free to contact Florent from Enjoy-Digital

In the while, I have just introduced this proposal in the appropriate Github repository.