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- Demultiplexers
In this collection you will find Multiplexers and Demultiplexers. Use these blocks in your digital circuits for opensource FPGAs created with icestudio. All the components of this collection are combinational
Find information about collections and how to install them on this link: Installing the iceK collection in Icestudio. It was written for the iceK collection as an example. Use the repo of the icegates collection instead
- Download the ZIP file from the latest release (TODO)
- ...or get the ZIP file with the latest changes from the main branch: iceMux.zip
The main multiplexer are 2-to-1, 4-to-1 and 8-to-1. There are different flavours for all of them: Standard, Bus input and N-bits channel
All the multiplexers are built from the basic 2-to-1 Mux, which in turn is built from logic gates. There are different flavours
The basic 2-to-1 multiplexer have two channels of 1-bit and 1-bit sel input. There is a 1-bit output. Its value depends on the sel input: When it is 0, the channel 0 (input 0) is selected and sent to the output. When it is 1, the channel 1 (input 1) is output
In this picture two similar 2-1 muxes are shown, with flipped inputs
This example is available on the File/Examples/01-Mux-2-1/Alhambra-II/01-Mux-2-1-button-LED menu. It is an example of manually testing a 2-to-1 Mux with a button and one LED, for the Alhambra-II ICE40 FPGA board. The LED is ON at its maximum bright when the button is not pressed. When the button is pressed the Led lights at half power
The 2-to-1 Mux is implemented from logic gates
The 2-to-1 flipped mux is implemented using the standard 2-to-1 Mux, but with the inputs 1 and 0 interchanged
The Mux-2-1-verilog is exactly the same than the Mux-2-1, but implemented directly in verilog:
This is the verilog code:
assign o = sel ? i1 : i0;The Mux-2-1-bus component is exactly the same as the Mux-2-1, but both inputs, i0 and i1 are taken from the input bus instead of from isolated wires
The Mux-2-1-Bus is implemented with an split block connected to a Mux-2-1
The input channels of multiplexer can have any size. These N-bits channels are sent to the N-bit output when selected. In this figure 2-to-1 muxes of different channel sizes are shown (2, 3, 4 and 8 bits):
The 2-to-1 Muxes of N bits can be built from 2-1 Muxes of 1 bits connected in paralell. In this figure it is shown the implementation of the 2-bits Mux-2-1:
This is an example of use of the 4-bits 2-to-1 multiplexer. Every channel has a 4-bits number: 1010 and 0101. The button selects which number is displayed on the LEDs
The 4-to-1 multiplexer is built from 2-to-1 Multiplexers, which in turn are built from logic gates. There are different flavours
The 4-to-1 multiplexer have four channels of 1-bit and 2-bits sel input. There is a 1-bit output. Its value depends on the sel input. When sel is equal to n, where n is a 2-bit number (0-3), the channel n is sent to the output
In this picture two similar 4-1 muxes are shown, with flipped inputs:
This example is available on the File/Examples/03-Mux-4-1/Alhambra-II/03-Mux-4-1-button-LED menu. It is an example of manually testing a 4-to-1 Mux with a button and one LED, for the Alhambra-II ICE40 FPGA board. There are four signal with duty cicles of 0%, 25%, 50% and 100%. Initially the channel 0 is selected. By pressing the button the following channels are selected: 1,2,3 and 0 again
The Mux-4-1-Bus is implemented from three Mux-2-1 and a split block. The first two Mux-2-1 work in paralell and select the two most significant bits (sel=1x) or the two least significant bits (sel=0x). The last Mux-2-1 select between these two bits
The Mux-4-1-verilog is exactly the same than the Mux-4-1, but implemented directly in verilog:
This is the verilog code:
/-- Mux-4-1
assign o = (sel == 2'b00) ? i0 :
(sel == 2'b01) ? i1 :
(sel == 2'b10) ? i2 :
i3;
The Mux-4-1-bus component is exactly the same as the Mux-4-1, but the four inputs are taken from the input bus instead of isolated wires
The input channels of multiplexer can have any size. These N-bits channels are sent to the N-bit output when selected. In this figure 4-to-1 muxes of different channel sizes are shown (2, 3, 4 and 8 bits):
This is an example of use of the 4-bits 4-to-1 multiplexer. Every channel has a 4-bits number: 1010, 0101, 0011 and 1100. The buttons selects which number is displayed on the LEDs: channels from 0 to 3
The 4-bits Mux-4-1 is implemented by means of four 1-bits Mux-4-1 muxes in paralell, and the necessary Join and Split blocks
The 8-to-1 multiplexer is built from 2-to-1 Multiplexers, which in turn are built from logic gates. There are different flavours
The 8-to-1 multiplexer have eight channels of 1-bit, and 3-bits sel input. There is a 1-bit output. Its value depends on the sel input. When sel is equal to n, where n is a 3-bit number (0-7), the channel n is sent to the output
In this picture two similar 8-1 muxes are shown, with flipped inputs:
This example is available on the File/Examples/05-Mux-8-1/Alhambra-II/05-Mux-8-1-button-LED menu. It is an example of manually testing a 8-to-1 Mux with a button and one LED, for the Alhambra-II ICE40 FPGA board. There are four signal with duty cicles of 0%, 1.5%, 3%, 6%, 12%, 25%, 50% and 100%. Initially the channel 0 is selected. By pressing the button the following channels are selected: 0,1,2,3,4,5,6,7 and 0 again
The Mux-8-1-Bus is implemented from two Mux-4-1, one Mux-2-1 and a split block. The first two Mux-4-1 work in paralell and select the four odd numbers (block of 4 bits) or the four event numbers. The last Mux-2-1 select between these two bits
The Mux-8-1-verilog is exactly the same than the Mux-8-1, but implemented directly in verilog:
This is the verilog code:
//-- Mux-8-1
assign o = (sel == 3'b000) ? i0 :
(sel == 3'b001) ? i1 :
(sel == 3'b010) ? i2 :
(sel == 3'b011) ? i3 :
(sel == 3'b100) ? i4 :
(sel == 3'b101) ? i5 :
(sel == 3'b110) ? i6 :
i7;
The Mux-8-1-bus component is exactly the same as the Mux-8-1, but the eight inputs are taken from the input bus instead of isolated wires
The input channels of multiplexer can have any size. These N-bits channels are sent to the N-bit output when selected. In this figure 8-to-1 muxes of different channel sizes are shown (2, 3, 4 and 8 bits):
This is an example of use of the 4-bits 8-to-1 multiplexer. Every channel has a 4-bits number: 0001, 0010, 0100, 1000, 1001, 1010,1100 and 1100. The buttons selects which number is displayed on the LEDs: channels from 0 to 7
The main demultiplexer are 1-to-2, 1-to-4 and 1-to-4. There are different flavours for all of them: Standard, Bus output and N-bits channel
All the demultiplexers are built from the basic 1-to-2 DeMux, which in turn is built from logic gates. There are different flavours
The basic 1-to-2 demultiplexer have two output channels of 1-bit, one 1-bit input channel and one 1-bit sel input. The input is output to the channel given by the sel input: When it is 0, it is output to the channel 0. When it is 1, it is output to the channel 1
In this picture two similar 1-2 demuxes are shown, with flipped outputs
This example is available on the File/Examples/07-DeMux-1-2/Alhambra-II/07-DeMux-1-2-button-LED menu. It is an example of manually testing a 1-to-2 DeMux with a button and one LED, for the Alhambra-II ICE40 FPGA board. When the button is pressed, the LED1 is ON. When it is not pressed, the LED0 is ON
The 1-to-2 DeMux is implemented from logic gates
The 1-to-2 flipped mux is implemented using the standard 1-to-2 DeMux, but with the outputs 1 and 0 interchanged
The DeMux-1-2-verilog is exactly the same than the DeMux-1-2, but implemented directly in verilog:
This is the verilog code:
assign {o1,o0} = i << sel;The DeMux-1-2-bus component is exactly the same as the DeMux-1-2, but both outputs, o0 and o1 are taken from the output bus instead of isolated wires
The DeMux-1-2-Bus is implemented with a DeMux-1-2 connected to a joint block
The input channels of multiplexer can have any size. These N-bits channels are sent to the N-bit output when selected. In this figure 2-to-1 muxes of different channel sizes are shown (2, 3, 4 and 8 bits):
The 1-to-2 Demuxes of N bits can be built from 1-2 DeMuxes of 1 bits connected in paralell. In this figure it is shown the implementation of the 2-bits DeMux-1-2:
This is an example of use of the 4-bits 1-to-2 demultiplexer. The 4-bits constant is displayed either on the 4 most significant LEDs or the 4 least significant LED, depending on the button SW1
All the demultiplexers are built from the basic 1-to-2 DeMux, which in turn is built from logic gates. There are different flavours
The 1-to-4 demultiplexer have four output channels of 1-bit, one 1-bit input channel and one 2-bits sel input. The input is sent to the output channel given by the sel input: 0-3
In this picture two similar 1-4 demuxes are shown, with flipped outputs
This example is available on the File/Examples/09-DeMux-1-4/Alhambra-II/09-DeMux-1-4-button-LED menu. It is an example of manually testing a 1-to-4 DeMux with a button and one LED, for the Alhambra-II ICE40 FPGA board. The 1-bit is sent to the LED0, 1, 2 or 3 sequentially. When the button is pressed, the next LED is ON
The 1-to-4 DeMux is implemented from three 1-to-2 Demultiplexers and a split block
The DeMux-1-4-verilog is exactly the same than the DeMux-1-4, but implemented directly in verilog:
This is the verilog code:
assign {o3, o2, o1, o0} = i << sel;
The DeMux-1-4-bus component is exactly the same as the DeMux-1-4, but all the outputs are grouped into a 4-bits output bus
The DeMux-1-4-Bus is implemented with a DeMux-1-4 connected to a joint block
The input channels of multiplexer can have any size. These N-bits channels are sent to the N-bit output when selected. In this figure 4-to-1 muxes of different channel sizes are shown (2, 3, 4 and 8 bits):
The 1-to-4 Demuxes of N bits can be built from 1-2 DeMuxes of 1 bits connected in paralell. In this figure it is shown the implementation of the 2-bits DeMux-1-4:
This is an example of use of the 2-bits 1-to-4 demultiplexer. The 2-bits constant is displayed on four groups of two LEDs. Channel 0 is composed of LEDs 0 and 1, Channel 1: LEDs 2 and 3, Channel 2: LEDs 4 and 5 and Channel 3: LEDs 6 and 7. When the button is pressed, the output channel is increased
All the 1-to-8 demultiplexers are built from 1-to-4 DeMux. There are different flavours
The 1-to-8 demultiplexer have eight output channels of 1-bit, one 1-bit input channel and one 3-bits sel input. The input is sent to the output channel given by the sel input: 0-7
In this picture two similar 1-7 demuxes are shown, with flipped outputs
This example is available on the File/Examples/11-DeMux-1-8/Alhambra-II/11-DeMux-1-8-button-LEDs menu. It is an example of manually testing a 1-to-8 DeMux with a button and LEDs, for the Alhambra-II ICE40 FPGA board. The 1-bit is sent to the LED0, 1, 2,... or 7 sequentially. When the button is pressed, the next LED is ON
The 1-to-8 DeMux is implemented from seven 1-to-2 Demultiplexers and a split block
The DeMux-1-8-verilog is exactly the same than the DeMux-1-8, but implemented directly in verilog:
This is the verilog code:
assign {o7,o6, o5, o4, o3, o2, o1, o0} = i << sel;
The DeMux-1-8-bus component is exactly the same as the DeMux-1-8, but all the outputs are grouped into a 8-bits output bus
The DeMux-1-8-Bus is implemented with a DeMux-1-8 connected to a joint block
