tdse-tp2_02-model_integration.cfg

# This is an NUCLEO-F103RB board with a single STM32F103RBTx chip
#
# Generated by STM32CubeIDE
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)

source [find interface/stlink-dap.cfg]


set WORKAREASIZE 0x5000

transport select "dapdirect_swd"

set CHIPNAME STM32F103RBTx
set BOARDNAME NUCLEO-F103RB

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# STlink Debug clock frequency
set CLOCK_FREQ 8000

# Reset configuration
# use software system reset if reset done
reset_config none
set CONNECT_UNDER_RESET 0
set CORE_RESET 0

# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333





# BCTM CPU variables

source [find target/stm32f1x.cfg]