diff --git a/debian/changelog b/debian/changelog
index afdf77b9b..995db59d9 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+rom-properties (1.6-1ppa1~xenial4) xenial; urgency=medium
+
+  * ImageDecoder: Fix ARM64 linkage and AMD64 compile errors as a result of
+    the IFUNC fixes.
+
+ -- David Korth <gerbilsoft@gerbilsoft.com>  Sun, 12 Jul 2020 15:54:10 -0400
+
 rom-properties (1.6-1ppa1~xenial3) xenial; urgency=medium
 
   * ImageDecoder: Another attempt to fix ARM64 IFUNC build issues...
diff --git a/src/librpcpu/byteswap.h b/src/librpcpu/byteswap.h
index a51c018d2..376a4feb9 100644
--- a/src/librpcpu/byteswap.h
+++ b/src/librpcpu/byteswap.h
@@ -186,7 +186,7 @@ void __byte_swap_16_array_ssse3(uint16_t *ptr, size_t n);
 void __byte_swap_32_array_ssse3(uint32_t *ptr, size_t n);
 #endif /* BYTESWAP_HAS_SSSE3 */
 
-#if defined(RP_HAS_IFUNC)
+#if defined(RP_HAS_IFUNC) && (defined(RP_CPU_I386) || defined(RP_CPU_AMD64))
 /* System has IFUNC. Use it for dispatching. */
 
 /**
@@ -203,7 +203,7 @@ void __byte_swap_16_array(uint16_t *ptr, size_t n);
  */
 void __byte_swap_32_array(uint32_t *ptr, size_t n);
 
-#else /* !RP_HAS_IFUNC */
+#else /* !RP_HAS_IFUNC && !(defined(RP_CPU_I386) || defined(RP_CPU_AMD64)) */
 /* System does not have IFUNC. Use inline dispatch functions. */
 
 /**
@@ -275,7 +275,7 @@ static inline void __byte_swap_32_array(uint32_t *ptr, size_t n)
 # endif /* !BYTESWAP_ALWAYS_HAS_SSE2 */
 }
 
-#endif /* RP_HAS_IFUNC */
+#endif /* RP_HAS_IFUNC && (defined(RP_CPU_I386) || defined(RP_CPU_AMD64)) */
 
 #ifdef __cplusplus
 }
diff --git a/src/librptexture/decoder/ImageDecoder.hpp b/src/librptexture/decoder/ImageDecoder.hpp
index ef9937f74..3ff7249b2 100644
--- a/src/librptexture/decoder/ImageDecoder.hpp
+++ b/src/librptexture/decoder/ImageDecoder.hpp
@@ -783,13 +783,13 @@ rp_image *fromBC7(int width, int height,
  */
 static inline rp_image *fromLinear16(PixelFormat px_format,
 	int width, int height,
-	const uint16_t *img_buf, int img_siz, int stride = 0)
+	const uint16_t *img_buf, int img_siz, int stride)
 {
 	// amd64 always has SSE2.
 	return fromLinear16_sse2(px_format, width, height, img_buf, img_siz, stride);
 }
 
-#endif /* defined(RP_HAS_IFUNC) && defined(IMAGEDECODER_ALWAYS_HAS_SSE2) */
+#endif /* RP_HAS_IFUNC && IMAGEDECODER_ALWAYS_HAS_SSE2 */
 
 #if !defined(RP_HAS_IFUNC) || (!defined(RP_CPU_I386) && !defined(RP_CPU_AMD64))
 
@@ -874,7 +874,7 @@ static rp_image *fromLinear32(PixelFormat px_format,
 	}
 }
 
-#endif /* !defined(RP_HAS_IFUNC) || (!defined(RP_CPU_I386) && !defined(RP_CPU_AMD64)) */
+#endif /* !RP_HAS_IFUNC || (!RP_CPU_I386 && !RP_CPU_AMD64) */
 
 } }