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spu2c.py
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spu2c.py
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# SPU To C
from ida_bytes import *
from idaapi import *
from idc import *
import idaapi
import ida_bytes
import idc
#Constants
MASK_ALLSET_128 = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
MASK_ALLSET_96 = 0xFFFFFFFFFFFFFFFFFFFFFFFF
MASK_ALLSET_64 = 0xFFFFFFFFFFFFFFFF
MASK_ALLSET_32 = 0xFFFFFFFF
MASK_ALLSET_16 = 0xFFFF
UP = 0
DOWN = 1
def get_reg(reg):
if reg == 0:
return "lr"
elif reg == 1:
return "sp"
else:
return "r{:d}".format(reg)
def get_reg_with_field(reg, field):
if reg == 0:
reg = "lr"
elif reg == 1:
reg = "sp"
else:
reg = "r{:d}".format(reg)
return reg + "[{:d}]".format(field)
def get_preferred_reg(reg):
return get_reg_with_field(reg, 0)
def get_channel(ca):
if ca < 31:
ca_tbl = ["event_status", "event_mask", "event_ack", "signal_notify1", "signal_notify2", "ch5", "ch6", "decrementer", "decrementer", "multisource_sync_req",
"ch10", "event_mask", "tag_mask", "machine_status", "srr0", "srr0", "ls_address", "mfc_eah", "mfc_eal", "mfc_size",
"tag_id", "mfc_cmd", "tag_mask", "tag_update", "tag_status", "list_stall_status", "list_stall_ack", "atomic_status", "out_mailbox", "in_mailbox",
"intr_out_mailbox"]
return ca_tbl[ca]
elif ca == 69:
ca = "set_bkmk_tag"
elif ca == 70:
ca = "perf_monitor_start_event"
elif ca == 71:
ca = "perf_monitor_stop_event"
elif ca == 74:
ca = "rng"
else:
ca = "ch{:d}".format(ca)
return ca
def sign_extend_imm10(_16, value):
if value & 0x200 == 0x200:
value = (0xFFFFFE00 | value & 0x1FF)
else:
value &= 0x1FF
if _16 == 1:
value &= 0xFFFF
return value
def sign_extend_imm16(value):
if value & 0x8000 == 0x8000:
return 0xFFFF0000 | value & 0xFFFF
else:
return value & 0xFFFF
def imm10_to_signed_string(value):
sign = ""
imm = value & 0x3FF
if (imm > 0x1FF):
imm = ~imm
imm &= 0x1FF
imm += 1
sign = "-"
return sign + "0x{:X}".format(imm)
def imm16_to_signed_string(value):
sign = ""
imm = value & 0xFFFF
if (imm > 0x7FFF):
imm = ~imm
imm &= 0x7FFF
imm += 1
sign = "-"
return sign + "0x{:X}".format(imm)
def exp2(j):
i = 0
r = 1
while i < j:
r *= 2
i += 1
return "{:.1f}".format(r)
def check_abort_shufb(addr, end, msk_reg, direction):
while addr != end:
opcode = get_wide_dword(addr)
if opcode >> 31 == 1:
test_reg = (opcode >> 21) & 0x7F
else:
test_reg = opcode & 0x7F
if test_reg == msk_reg:
return 1
if direction == DOWN:
addr += 4
else:
addr -= 4
return 0
def resolve_mask(opcode, full_string, msk):
field = 0
result = 0
space = " "
new_line = "\n"
rt = get_reg((opcode >> 21) & 0x7F)
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
while field <= 15:
if field > 9:
space = ""
if field == 15:
new_line = ""
x = (msk >> (15 - field) * 8) & 0xFF
#print("X = 0x{:02X}".format(x))
if x < 0x80:
if x & 0x10 == 0x00:
full_string += rt + " byte[{:d}] ".format(field,) + space + "= byte[{:d}] from ".format(x&0xF) + ra + new_line
result |= ((x & 0x0F | 0xA0) << ((15 - field) * 8))
else:
full_string += rt + " byte[{:d}] ".format(field,) + space + "= byte[{:d}] from ".format(x&0xF) + rb + new_line
result |= ((x & 0x0F | 0xB0) << ((15 - field) * 8))
else:
if x < 0xC0:
full_string += rt + " byte[{:d}] ".format(field,) + space + "= 0x00" + new_line
result |= (0x00 << ((15 - field) * 8))
elif x >= 0xC0 and x < 0xE0:
full_string += rt + " byte[{:d}] ".format(field,) + space + "= 0xFF" + new_line
result |= (0xFF << ((15 - field) * 8))
else:
full_string += rt + " byte[{:d}] ".format(field,) + space + "= 0x80" + new_line
result |= (0x80 << ((15 - field) * 8))
field += 1
#print("MASK 0x{:032X}".format(result))
#print(full_string)
return full_string
def shufb_patterns(addr, opcode):
msk_reg = opcode & 0x7F
limit = addr - 0x500
msk = 0
full_string = ".\n"
while addr > limit:
# addr + 4 because opcode at address with cref is ok.
xref_test = get_first_fcref_to(addr+4)
# branch target, we need to check xrefs.
if xref_test != BADADDR:
abort = 1
# Test xrefs.
# Todo 0018064 in pemu 3 elf.
# When we are sure that current address is unreachable by
# any other way than that branch, we are safe to go.
#
# Good test case for successful abort in pemu 5 00007374, etc.
while xref_test != BADADDR:
if xref_test > addr+4:
direction = DOWN
else:
direction = UP
abort = check_abort_shufb(addr+4, xref_test, msk_reg, direction)
if abort != 0:
print("shufb: Aborting due to CREF at 0x{:X}, from 0x{:X}".format(addr+4, xref_test))
return 0
xref_test = get_next_fcref_to(addr+4, xref_test)
test_op = get_wide_dword(addr)
if (test_op >> 31) & 1 == 1:
target_reg = (test_op >> 21) & 0x7F
else:
target_reg = test_op & 0x7F
if target_reg == msk_reg:
print("shufb: Using opcode from 0x{:X} as a mask loader".format(addr))
name = print_insn_mnem(addr)
if name in ["ila", "il", "ilh", "ilhu"]:
if name == "ila":
msk = (test_op >> 7) & 0x3FFFF
elif name == "il":
msk = (test_op >> 7) & 0xFFFF
msk = sign_extend_imm16(msk)
elif name == "ilh":
msk = (test_op >> 7) & 0xFFFF
msk = msk | msk << 16
else: # name == "ilhu":
msk = (test_op >> 7) & 0xFFFF
msk = msk << 16
print("shufb: Pre shift mask from " + name + " opcode = 0x{:08X}".format(msk))
msk = (msk | msk << 32 | msk << 64 | msk << 96)
elif name in ["lqa", "lqr", "lqd"]:
if is_off1(ida_bytes.get_flags(addr)) == 0 and name == "lqd":
print("shufb: Can't resolve mask, unresolved lqd at 0x{:X}".format(addr))
return 0
msk_addr = get_operand_value(addr, 1);
msk = get_wide_dword(msk_addr) << 96 | get_wide_dword(msk_addr+4) << 64 | get_wide_dword(msk_addr+8) << 32 | get_wide_dword(msk_addr+12)
print("shufb: Using mask from " + name + " opcode, mask at 0x{:X}".format(msk_addr))
elif name in ["cbd", "chd", "cwd", "cdd"]:
print("shufb: Generating mask from Generate Controls instruction")
base = 0x101112131415161718191A1B1C1D1E1F
if name == "cbd":
shift = ((15 - (get_operand_value(addr, 1) & 0x0F)) * 8)
base = base & ~(0xFF << shift)
msk = 0x03 << shift
elif name == "chd":
shift = ((14 - (get_operand_value(addr, 1) & 0x0E)) * 8)
base = base & ~(MASK_ALLSET_16 << shift)
msk = 0x0203 << shift
elif name == "cwd":
shift = ((12 - (get_operand_value(addr, 1) & 0x0C)) * 8)
base = base & ~(MASK_ALLSET_32 << shift)
msk = 0x00010203 << shift
else:
shift = ((8 - (get_operand_value(addr, 1) & 0x08)) * 8)
base = base & ~(MASK_ALLSET_64 << shift)
msk = 0x0001020304050607 << shift
msk |= base
ctrl_reg = get_reg((test_op >> 7) & 0x7F)
if ctrl_reg != "sp":
full_string += "shufb: WARNING!\n" + name + " at 0x{:X} is not using sp register as a base!\n".format(addr)
full_string += "Mask can be inaccurate if " + ctrl_reg + "[32b][0] & 0x0F != 0\n"
elif name == "orbi":
tra = (test_op >> 7) & 0x7F
timm = (test_op >> 14) & 0xFF
timm = (timm | timm << 8 | timm << 16 | timm << 24) & MASK_ALLSET_32
timm = (timm | timm << 32 | timm << 64 | timm << 96) & MASK_ALLSET_128
taddr = addr - 4
tlimit = taddr - 0x300
while taddr > tlimit:
# taddr + 4 because opcode at address with cref is ok.
if get_first_fcref_to(taddr + 4) != BADADDR:
# branch target, we need to abandon searching.
# Result can be inaccurate.
print("shufb: Aborting post orbi search due to CREF AT 0x{:X}".format(taddr))
return 0
test_op = get_wide_dword(taddr)
if (test_op >> 31) & 1 == 1:
# RRRR
target_reg = (test_op >> 21) & 0x7F
else:
target_reg = test_op & 0x7F
if target_reg == tra:
print("shufb: Orbi is using opcode from 0x{:X} as a mask loader".format(taddr))
name = print_insn_mnem(taddr)
if name == "ila":
msk = (test_op >> 7) & 0x3FFFF
print("shufb: Orbi pre shift mask from ila opcode = 0x{:08X}".format(msk))
msk = (msk | msk << 32 | msk << 64 | msk << 96)
msk |= timm
break
#Unsafe, disabled for now
#elif name in ["lqa", "lqr"]:
# msk_addr = get_operand_value(taddr, 1);
# msk = get_wide_dword(msk_addr) << 96 | get_wide_dword(msk_addr+4) << 64 | get_wide_dword(msk_addr+8) << 32 | get_wide_dword(msk_addr+12)
# msk |= timm
# print("shufb!!!!: Using mask from lq opcode at 0x{:X}".format(msk_addr))
# break
else:
print("shufb: Aborting, orbi use unsupported mask base opcode")
return 0
taddr -= 4
if taddr == tlimit:
print("shufb: Aborting in orbi path, opcode with mask not found")
return 0
else:
print("shufb: Can't resolve mask, unsupported opcode")
return 0
break
addr -= 4
if addr == limit:
print("shufb: Aborting, opcode with mask not found")
return 0
print("shufb: Mask = 0x{:032X}".format(msk))
return resolve_mask(opcode, full_string, msk)
def avgb(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[16x8b] = (" + ra + " + " + rb + " + 1) >> 1 (sum before shift is 9 bits value)"
def absdb(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[16x8b] = if (" + ra + " < " + rb + "): " + rb + " - " + ra + ", else: " + ra + " - " + rb
def andc(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " & ~" + rb
def andbi(opcode):
imm = (opcode >> 14) & 0xFF
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[16x8b] = " + ra + " & 0x{:02X}".format(imm)
def andhi(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(1, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[8x16b] = " + ra + " & 0x{:04X}".format(imm)
def andi(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(0, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " & 0x{:08X}".format(imm)
def orc(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " | ~" + rb
def orbi(opcode):
imm = (opcode >> 14) & 0xFF
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[16x8b] = " + ra + " | 0x{:X}".format(imm)
def orhi(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(1, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[8x16b] = " + ra + " | 0x{:X}".format(imm)
def ori(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(0, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " | 0x{:X}".format(imm)
def orx(opcode):
ra = (opcode >> 7) & 0x7F
rt = get_reg(opcode & 0x7F)
return rt +"[32b][0] = " + get_reg_with_field(ra,0) + " | " + get_reg_with_field(ra,1) + " | " + get_reg_with_field(ra,2) + " | " + get_reg_with_field(ra,3) + " (lower 96 bits of " + rt + " = 0)"
def xorbi(opcode):
imm = (opcode >> 14) & 0xFF
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[16x8b] = " + ra + " ^ 0x{:X}".format(imm)
def xorhi(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(1, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[8x16b] = " + ra + " ^ 0x{:X}".format(imm)
def xori(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(0, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " ^ 0x{:X}".format(imm)
def eqv(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " ^ ~" + rb + " (If the bit in" + ra + " and " + rb + " are the same, the result bit is 1 else 0)"
def fsmbi(opcode):
rt = get_reg(opcode & 0x7F)
i44 = (opcode >> 7) & 0xF
i43 = (opcode >> 11) & 0xF
i42 = (opcode >> 15) & 0xF
i41 = (opcode >> 19) & 0xF
mask_44 = 0
mask_43 = 0
mask_42 = 0
mask_41 = 0
i = 0
while i < 4:
mask_temp = i44 & (1<<i)
if mask_temp != 0:
mask_44 = mask_44 | (0xFF << (i*8))
i += 1
i = 0
while i < 4:
mask_temp = i43 & (1<<i)
if mask_temp != 0:
mask_43 = mask_43 | (0xFF << (i*8))
i += 1
i = 0
while i < 4:
mask_temp = i42 & (1<<i)
if mask_temp != 0:
mask_42 = mask_42 | (0xFF << (i*8))
i += 1
i = 0
while i < 4:
mask_temp = i41 & (1<<i)
if mask_temp != 0:
mask_41 = mask_41 | (0xFF << (i*8))
i += 1
return rt + "[128b] = 0x{:08X}:{:08X}:{:08X}:{:08X}".format(mask_41,mask_42,mask_43,mask_44)
def xsbh(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[8x16b] = SignExtend16(" + ra + " & 0xFF)"
def xshw(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = SignExtend32(" + ra + " & 0xFFFF)"
def xswd(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[2x64b] = SignExtend64(" + ra + " & 0xFFFFFFFF)"
def ilh(opcode):
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 7) & 0xFFFF
return rt +"[8x16b] = 0x{:X}".format(imm)
def ilhu(opcode):
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 7) & 0xFFFF
return rt +"[4x32b] = 0x{:04X}0000".format(imm)
def il(opcode):
rt = get_reg(opcode & 0x7F)
val = (opcode >> 7) & 0xFFFF
imm = sign_extend_imm16(val)
if val > 0x7FFF:
imms = imm16_to_signed_string(val)
return rt +"[4x32b] = 0x{:X}".format(imm) + " (" + imms + ")"
return rt +"[4x32b] = 0x{:X}".format(imm)
def ila(opcode):
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 7) & 0x3FFFF
return rt +"[4x32b] = 0x{:X}".format(imm)
def iohl(opcode):
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 7) & 0xFFFF
return rt +"[4x32b] = " + rt + " | 0x{:X}".format(imm)
def ah(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[8x16b] = " + rb + " + " + ra
def a(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + rb + " + " + ra
def addx(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + ra + " + " + rb + " + (" + rt + " & 1)"
def sfh(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[8x16b] = " + rb + " - " + ra
def sf(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = " + rb + " - " + ra
def sfx(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt +"[4x32b] = (" + ra + " - " + rb + ") - ((" + rt + " & 1) ^ 1)"
def ahi(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 14) & 0x3FF
imm = imm10_to_signed_string(imm)
return rt +"[8x16b] = " + ra + " + " + imm
def ai(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 14) & 0x3FF
imm = imm10_to_signed_string(imm)
return rt +"[4x32b] = " + ra + " + " + imm
def sfhi(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 14) & 0x3FF
imm = imm10_to_signed_string(imm)
return rt +"[8x16b] = " + imm + " - " + ra
def sfi(opcode):
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
imm = (opcode >> 14) & 0x3FF
imm = imm10_to_signed_string(imm)
return rt +"[4x32b] = " + imm + " - " + ra
def bg(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return "[4x32b] if (u32)" + ra + " > (u32)" + rb + ": " + rt + " = 0, else " + rt + " = 0x00000001"
#todo
#def bgx(opcode):
#
# rt = opcode & 0x7F
# ra = (opcode >> 7) & 0x7F
# rb = (opcode >> 14) & 0x7F
# return "[4x32b] if (u32)" + ra + " > (u32)" + rb + ": " + rt + " = 0, else " + rt + " = 0x00000001"
def mpy(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (s16)(" + ra + " & 0xFFFF) * (s16)(" + rb + " & 0xFFFF)"
def mpyu(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (" + ra + " & 0xFFFF) * (" + rb + " & 0xFFFF)"
# signed rc?
def mpya(opcode):
rt = get_reg((opcode >> 21) & 0x7F)
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rc = get_reg(opcode & 0x7F)
return rt + "[4x32b] = ((s16)(" + ra + " & 0xFFFF) * (s16)(" + rb + " & 0xFFFF)) + " + rc
# signed?
def mpyh(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = ((((" + ra + " >> 16) & 0xFFFF) * (" + rb + " & 0xFFFF)) << 16) & 0xFFFF0000"
# signed?
def mpys(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = sign_extend32(((" + ra + " & 0xFFFF) * (" + rb + " & 0xFFFF)) >> 16)"
def mpyhh(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (s16)((" + ra + " >> 16) & 0xFFFF) * (s16)((" + rb + " >> 16) & 0xFFFF)"
# signed rt?
def mpyhha(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (s16)((" + ra + " >> 16) & 0xFFFF) * (s16)((" + rb + " >> 16) & 0xFFFF) + " + rt
def mpyhhu(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = ((" + ra + " >> 16) & 0xFFFF) * ((" + rb + " >> 16) & 0xFFFF)"
def mpyhhau(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = ((" + ra + " >> 16) & 0xFFFF) * ((" + rb + " >> 16) & 0xFFFF) + " + rt
def mpyi(opcode):
imm = (opcode >> 14) & 0x3FF
imm = imm10_to_signed_string(imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (s16)(" + ra + " & 0xFFFF) * " + imm
def mpyui(opcode):
imm = (opcode >> 14) & 0x3FF
imm = sign_extend_imm10(1, imm)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (" + ra + " & 0xFFFF) * 0x{:X}".format(imm)
####################
# Imm shift start: #
####################
def shlqbii(opcode):
shift = (opcode >> 14) & 7
result = MASK_ALLSET_128 << shift
result &= MASK_ALLSET_128
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = result & MASK_ALLSET_32
return rt + "[128b] = (" + ra + " << {:d}) & 0xFFFFFFFF:FFFFFFFF:FFFFFFFF:{:08X}".format(shift,a)
def shlqbyi(opcode):
shift = (opcode >> 14) & 0x1F
shift *= 8
result = MASK_ALLSET_128 << shift
result &= MASK_ALLSET_128
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = (result >> 96) & MASK_ALLSET_32
b = (result >> 64) & MASK_ALLSET_32
c = (result >> 32) & MASK_ALLSET_32
d = result & MASK_ALLSET_32
return rt + "[128b] = (" + ra + " << {:d}) & 0x{:08X}:{:08X}:{:08X}:{:08X}".format(shift,a,b,c,d)
def shli(opcode):
shift = (opcode >> 14) & 0x3F
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = (MASK_ALLSET_32 << shift) & MASK_ALLSET_32
return rt + "[4x32b] = (" + ra + " << {:d}) & 0x{:08X}".format(shift,a)
def shlhi(opcode):
shift = (opcode >> 14) & 0x1F
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = (MASK_ALLSET_16 << shift) & MASK_ALLSET_16
return rt + "[8x16b] = (" + ra + " << {:d}) & 0x{:04X}".format(shift,a)
#####################
# Imm rotate start: #
#####################
# Right arithm shift 4x32 by bit
def rotmai(opcode):
shift = (0 -(opcode >> 14)) & 0x3F
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
#fixme: arithm
return rt + "[4x32b] = (" + ra + " >> {:d})".format(shift)
# Right arithm shift 8x16 by bit
def rotmahi(opcode):
shift = (0 -(opcode >> 14)) & 0x1F
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
#fixme: arithm
return rt + "[8x16b] = (" + ra + " >> {:d})".format(shift)
# Right shift 128 by bit
def rotqmbii(opcode):
shift = (0 -(opcode >> 14)) & 0x7
const = MASK_ALLSET_128
result = const >> shift
result &= MASK_ALLSET_128
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = (result >> 96) & MASK_ALLSET_32
return rt + "[128b] = (" + ra + " >> {:d}) & 0x{:08X}:FFFFFFFF:FFFFFFFF:FFFFFFFF".format(shift,a)
# Right shift 128 by byte
def rotqmbyi(opcode):
shift = (0 -(opcode >> 14)) & 0x1F
shift *= 8
result = MASK_ALLSET_128 >> shift
result &= MASK_ALLSET_128
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = (result >> 96) & MASK_ALLSET_32
b = (result >> 64) & MASK_ALLSET_32
c = (result >> 32) & MASK_ALLSET_32
d = result & MASK_ALLSET_32
return rt + "[128b] = (" + ra + " >> {:d}) & 0x{:08X}:{:08X}:{:08X}:{:08X}".format(shift,a,b,c,d)
# Right shift 4x32 by bit
def rotmi(opcode):
shift = (0 -(opcode >> 14)) & 0x3F
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = MASK_ALLSET_32 >> shift
return rt + "[4x32b] = (" + ra + " >> {:d}) & 0x{:08X}".format(shift,a)
# Right shift 8x16 by bit
def rothmi(opcode):
shift = (0 -(opcode >> 14)) & 0x1F
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = MASK_ALLSET_16 >> shift
return rt + "[8x16b] = (" + ra + " >> {:d}) & 0x{:04X}".format(shift,a)
# Left rotate 128 by bit
def rotqbii(opcode):
shift = (opcode >> 14) & 0x7
const = MASK_ALLSET_128
result1 = const << shift
result2 = const >> (128-shift)
result1 &= MASK_ALLSET_128
result2 &= MASK_ALLSET_128
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
# fixme: maybe split in 4 rows? Ugly
return rt + "[128b] = (" + ra + " << {:d}) & 0x{:032X} | (".format(shift,result1) + ra + " >> {:d}) & 0x{:032X}".format((128-shift),result2)
# Left rotate 128 by byte
def rotqbyi(opcode):
shift = (opcode >> 14) & 0xF
shift *= 8
const = 0xAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD
result = const << shift | const >>( 128-shift)
result &= MASK_ALLSET_128
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
a = (result >> 96) & MASK_ALLSET_32
b = (result >> 64) & MASK_ALLSET_32
c = (result >> 32) & MASK_ALLSET_32
d = result & MASK_ALLSET_32
return rt + "[128b] = " + ra + " : {:08X}:{:08X}:{:08X}:{:08X}".format(a,b,c,d)
# Left rotate 4x32 by bit
def roti(opcode):
#fixme: shift is signed?
shift = (opcode >> 14) & 0x1F
result1 = MASK_ALLSET_32 << shift
result2 = MASK_ALLSET_32 >> (32-shift)
result1 &= MASK_ALLSET_32
result2 &= MASK_ALLSET_32
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = (" + ra + " << {:d}) & 0x{:08X} | (".format(shift,result1) + ra + " >> {:d}) & 0x{:08X}".format((32-shift),result2)
# Left rotate 8x16 by bit
def rothi(opcode):
shift = (opcode >> 14) & 0xF
result1 = MASK_ALLSET_16 << shift
result2 = MASK_ALLSET_16 >> (16-shift)
result1 &= MASK_ALLSET_16
result2 &= MASK_ALLSET_16
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
# we can have special case here:
if shift == 8:
return rt + "[8x16b] = byteswap16(" + ra + ")"
return rt + "[8x16b] = (" + ra + " << {:d}) & 0x{:04X} | (".format(shift,result1) + ra + " >> {:d}) & 0x{:04X}".format((16-shift),result2)
#########################
# Non imm rotate start: #
#########################
# Right arithm shift 4x32 by bit from rb
def rotma(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = " + ra + " >> -(" + rb + ") & 0x3F"
# Right arithm shift 8x16 by bit from rb
def rotmah(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[8x16b] = " + ra + " >> -(" + rb + ") & 0x1F"
# Right shift 128 by bit from rb
def rotqmbi(opcode):
rb = get_preferred_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[128b] = " + ra + " >> -(" + rb + ") & 7"
# Right shift 128 by byte from rb
def rotqmbybi(opcode):
rb = get_preferred_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[128b] = " + ra + " >> ( -(" + rb + " >> 3) & 0x1F) * 8"
# Right shift 128 by byte from rb
def rotqmby(opcode):
rb = get_preferred_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[128b] = " + ra + " >> ( -(" + rb + ") & 0x1F) * 8"
# Right logical shift 4x32 by bit from rb
def rotm(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = " + ra + " >> -(" + rb + ") & 0x3F"
# Right logical shift 8x16 by bit from rb
def rothm(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[8x16b] = " + ra + " >> -(" + rb + ") & 0x1F"
# Left rotate 128 by bit from rb
def rotqbi(opcode):
rb = get_preferred_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[128b] = " + ra + " << (" + rb + " & 7) | " + ra + " >> 128 - (" + rb + " & 7)"
#fixme wtf
def rotqbybi(opcode):
rb = get_preferred_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[128b] = " + ra + " << ((" + rb + " >> 3) & 0xF) * 8 | " + ra + " >> 128 - (((" + rb + " >> 3) & 0xF) * 8)"
# Left rotate 128 by byte from rb
def rotqby(opcode):
rb = get_preferred_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[128b] = " + ra + " << (" + rb + " & 0xF) * 8 | " + ra + " >> 128 - ((" + rb + " & 0xF) * 8)"
# Left rotate 4x32 by bit from rb
def rot(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[4x32b] = " + ra + " << (" + rb + " & 0x1F) | " + ra + " >> 32 - (" + rb + " & 0x1F)"
# Left rotate 8x16 by bit from rb
def roth(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return rt + "[8x16b] = " + ra + " << (" + rb + " & 0xF) | " + ra + " >> 16 - (" + rb + " & 0xF)"
###################
# Branches start: #
###################
# Warning! Code for branches assume that SPU program is PS3 version.
# This mean address is AND with 0x3FFFC.
# This should be changed if you are working with hardware different than PS3.
# Branch indirect (always)
def bi(opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
return "PC = " + ra + " & 0x3FFFC"
# Branch indirect and link if external data
def bisled(addr, opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
rt = get_preferred_reg(opcode & 0x7F)
return "if ext_data: PC = " + ra + "& 0x3FFFC, ", + rt + " = 0x{:05X}".format(addr + 4)
# Branch indirect and set link (always)
def bisl(addr, opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
rt = get_preferred_reg(opcode & 0x7F)
return "PC = " + ra + " & 0x3FFFC, " + rt + " = 0x{:05X}".format(addr + 4)
# Branch indirect if zero
def biz(addr, opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
rt = get_preferred_reg(opcode & 0x7F)
return "if " + rt + " == 0: PC = " + ra + " & 0x3FFFC, else: PC = 0x{:05X}".format(addr + 4)
# Branch indirect if not zero
def binz(addr, opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
rt = get_preferred_reg(opcode & 0x7F)
return "if " + rt + " != 0: PC = " + ra + " & 0x3FFFC, else: PC = 0x{:05X}".format(addr + 4)
# Branch indirect if zero halfword
def bihz(addr, opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
rt = get_preferred_reg(opcode & 0x7F)
return "if (" + rt + "[32b] & 0xFFFF) == 0: PC = " + ra + " & 0x3FFFC, else: PC = 0x{:05X}".format(addr + 4)
# Branch indirect if not zero halfword
def bihnz(addr, opcode):
ra = get_preferred_reg((opcode >> 7) & 0x7F)
rt = get_preferred_reg(opcode & 0x7F)
return "if (" + rt + "[32b] & 0xFFFF) != 0: PC = " + ra + " & 0x3FFFC, else: PC = 0x{:05X}".format(addr + 4)
###################
# Compares start: #
###################
# Compare Equal Byte
def ceqb(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return "[16x8b] if " + ra + " == " + rb + ": " + rt + " = 0xFF, else 0x00"
# Compare Equal Halfword
def ceqh(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return "[8x16b] if " + ra + " == " + rb + ": " + rt + " = 0xFFFF, else 0x0000"
# Compare Equal Word
def ceq(opcode):
rb = get_reg((opcode >> 14) & 0x7F)
ra = get_reg((opcode >> 7) & 0x7F)
rt = get_reg(opcode & 0x7F)
return "[4x32b] if " + ra + " == " + rb + ": " + rt + " = 0xFFFFFFFF, else 0x00000000"
# Compare Greater Than Byte
def cgtb(opcode):
rb = get_reg((opcode >> 14) & 0x7F)