From 68de1220f0ac46422de26ba58f7c885c58f0651d Mon Sep 17 00:00:00 2001 From: Easton Man Date: Fri, 17 Jun 2022 18:08:48 +0800 Subject: [PATCH] fix: fix dcache send wreq when excp --- src/vsrc/cpu_top.sv | 5 +++++ src/vsrc/dummy_dcache.sv | 15 ++++++++++----- src/vsrc/icache.sv | 1 - src/vsrc/pipeline/4_mem/mem_wb.sv | 5 +++++ 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/src/vsrc/cpu_top.sv b/src/vsrc/cpu_top.sv index 256c1f5..ff5a547 100644 --- a/src/vsrc/cpu_top.sv +++ b/src/vsrc/cpu_top.sv @@ -195,6 +195,7 @@ module cpu_top logic [2:0] mem_cache_rd_type; logic [3:0] mem_cache_sel; logic [31:0] mem_cache_addr,mem_cache_data; + logic [1:0] wb_dcache_flush; // flush dcache if excp assign mem_cache_ce = mem_cache_signal[0].ce | mem_cache_signal[1].ce; assign mem_cache_we = mem_cache_signal[0].we | mem_cache_signal[1].we; @@ -216,6 +217,7 @@ module cpu_top .wstrb (mem_cache_sel), .wdata (mem_cache_data), .rd_type_i (mem_cache_rd_type), + .flush_i (wb_dcache_flush!=2'b0), // If excp occurs, flush DCache .addr_ok (mem_addr_ok), .data_ok (mem_data_ok), .rdata (cache_mem_data), @@ -642,6 +644,9 @@ module cpu_top //-> tlb .tlb_mem_signal(tlb_mem_signal), + // -> DCache + .dcache_flush_o(wb_dcache_flush[i]), + //to ctrl .wb_ctrl_signal(wb_ctrl_signal[i]), .ftq_id_o(wb_ctrl_ftq_id[i]) diff --git a/src/vsrc/dummy_dcache.sv b/src/vsrc/dummy_dcache.sv index 2e8b6ee..facf391 100644 --- a/src/vsrc/dummy_dcache.sv +++ b/src/vsrc/dummy_dcache.sv @@ -12,6 +12,7 @@ module dummy_dcache ( input logic [3:0] wstrb, //写字节使能信号 input logic [31:0] wdata, //写数据 input logic [2:0] rd_type_i, //读请求类型：3'b000: 字节；3'b001: 半字；3'b010: 字；3'b100：Cache行 + input logic flush_i, // 冲刷信号，如果出于某种原因需要取消写事务，CPU拉高此信号 output logic addr_ok, //该次请求的地址传输OK，读：地址被接收；写：地址和数据被接收 output logic data_ok, //该次请求的数据传输Ok，读：数据返回；写：数据写入完成 output logic [31:0] rdata, //读Cache的结果 @@ -49,7 +50,7 @@ module dummy_dcache ( end // State transition - always_comb begin + always_comb begin : transition_comb case (state) IDLE: begin if (valid) begin @@ -66,8 +67,9 @@ module dummy_dcache ( else next_state = READ_WAIT; end WRITE_REQ: begin - if (wr_rdy) - next_state = IDLE; // If AXI is ready, then write req is accept this cycle, back to IDLE + // If AXI is ready, then write req is accept this cycle, back to IDLE + // If flushed, back to IDLE + if (wr_rdy | flush_i) next_state = IDLE; else next_state = WRITE_REQ; end default: begin @@ -95,7 +97,7 @@ module dummy_dcache ( end - assign rd_type = rd_type_i ; + assign rd_type = rd_type_i; assign wr_type = 3'b010; // word always_comb begin // Default signal @@ -118,7 +120,10 @@ module dummy_dcache ( rd_addr = rd_addr_r; end WRITE_REQ: begin - if (wr_rdy) begin + if (flush_i) begin + wr_req = 0; + wr_addr = 0; + end else if (wr_rdy) begin wr_req = 1; wr_addr = cpu_addr; // DO NOT align addr, 128b -> 32b translate need info from addr case (cpu_addr[3:2]) diff --git a/src/vsrc/icache.sv b/src/vsrc/icache.sv index 05cb70e..795466a 100644 --- a/src/vsrc/icache.sv +++ b/src/vsrc/icache.sv @@ -180,7 +180,6 @@ module icache logic p1_rreq_1, p1_rreq_2; logic [ADDR_WIDTH-1:0] p1_raddr_1, p1_raddr_2; always_ff @(posedge clk) begin - p1_tlb_rreq <= tlb_rreq_i; if (rvalid_1_o | ~p1_rreq_1) begin p1_rreq_1 <= rreq_1_i; p1_raddr_1 <= raddr_1_i; diff --git a/src/vsrc/pipeline/4_mem/mem_wb.sv b/src/vsrc/pipeline/4_mem/mem_wb.sv index 6433e08..74f065c 100644 --- a/src/vsrc/pipeline/4_mem/mem_wb.sv +++ b/src/vsrc/pipeline/4_mem/mem_wb.sv @@ -33,6 +33,9 @@ module mem_wb // load store relate difftest output wb_ctrl wb_ctrl_signal, + // -> DCache + output logic dcache_flush_o, + // <-> Frontend output logic [$clog2(FRONTEND_FTQ_SIZE)-1:0] ftq_id_o ); @@ -89,6 +92,8 @@ module mem_wb excp_pil, excp_pis, excp_ppi, excp_pme, excp_tlbr, excp_adem, mem_signal_o.excp_num }; + assign dcache_flush_o = excp; + // DEBUG logic [`RegBus] debug_mem_wdata; assign debug_mem_wdata = mem_signal_o.wdata;