This repository contains a Branch Prediction Simulator developed as part of the Computer Architecture II (MYE-005) course. The tool utilizes Intel PIN, a dynamic binary instrumentation framework, to simulate and analyze the performance of various branch prediction algorithms on the PARSEC benchmark suite.
The simulator intercepts control-flow instructions at runtime and evaluates the accuracy (MPKI - Misses Per Kilo-Instruction) of different static and dynamic prediction strategies.
The following predictors are implemented in branch_predictor.h:
| Predictor | Description |
|---|---|
| Static Not Taken | Always predicts that the branch will not be taken. |
| Static BTFNT | Backward Taken, Forward Not Taken heuristic based on target address. |
| Predictor | Configuration | Details |
|---|---|---|
| N-bit Predictor | 1-bit / 16K Entries | Uses a table of 1-bit saturating counters (Last Outcome). |
| N-bit Predictor | 2-bit / 8K Entries | Uses a table of 2-bit saturating counters. |
| Gshare | 13-bit History / 8K Entries | Uses global history XORed with PC to index 2-bit counters. |
| Predictor | Configuration | Details |
|---|---|---|
| BTB + RAS | Direct Mapped | 512 entries + 16-entry Return Address Stack (RAS). |
| BTB + RAS | 8-way Associative | 64 sets (512 total entries) + 16-entry RAS. |