vivado_16357.backup.log

#-----------------------------------------------------------
# Vivado v2019.1.1 (64-bit)
# SW Build 2580384 on Sat Jun 29 08:04:45 MDT 2019
# IP Build 2579722 on Sat Jun 29 11:35:40 MDT 2019
# Start of session at: Mon Nov 25 09:28:15 2019
# Process ID: 16357
# Current directory: /home/hwkim/work/pynq-bnn/BNN-PYNQ
# Command line: vivado
# Log file: /home/hwkim/work/pynq-bnn/BNN-PYNQ/vivado.log
# Journal file: /home/hwkim/work/pynq-bnn/BNN-PYNQ/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_integ_strm_191124/sol1/impl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 6653.723 ; gain = 262.582 ; free physical = 10835 ; free virtual = 15187
update_compile_order -fileset sources_1
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
set_property  ip_repo_paths  {} [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
set_property  ip_repo_paths  /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121 [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
open_bd_design {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd}
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - zynq_ultra_ps_e_0
WARNING: [BD 41-176] The physical port 'M_AXI_HPM0_FPD_aximm_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'M_AXI_HPM0_FPD_aximm_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'M_AXI_HPM1_FPD_aximm_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'M_AXI_HPM1_FPD_aximm_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_HP0_FPD_aximm_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_HP0_FPD_aximm_rd_socket' specified in the portmap, is not found on the block! 
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - ps8_0_axi_periph
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc
Adding component instance block -- xilinx.com:ip:system_ila:1.1 - system_ila_0
Adding component instance block -- xilinx.com:hls:BlackBoxJam:1.0 - BlackBoxJam_0
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> from </BlackBoxJam_0/Data_m_axi_hostmem>
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> from </BlackBoxJam_0/Data_m_axi_hostmem>
Successfully read diagram <design_1> from BD file </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd>
report_ip_status -name ip_status 
upgrade_ip -vlnv xilinx.com:hls:BlackBoxJam:1.0 [get_ips  design_1_BlackBoxJam_0_0] -log ip_upgrade.log
Upgrading '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-3422] Upgraded design_1_BlackBoxJam_0_0 (Blackboxjam 1.0) from revision 1911232343 to revision 1911202117
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> from </BlackBoxJam_0/Data_m_axi_hostmem>
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> from </BlackBoxJam_0/Data_m_axi_hostmem>
Wrote  : </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips design_1_BlackBoxJam_0_0] -no_script -sync -force -quiet
report_ip_status -name ip_status 
ipx::edit_ip_in_project -upgrade true -name BlackBoxJam_v1_0_project -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_hostmem_m_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_32_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_53_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_94_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_164_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_185_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_325_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_727_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs0_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs1_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs2_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs3_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs4_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights0_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights1_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights2_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights4_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights10_m_weights_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_11.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_12.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_13.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_14.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_16.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_18.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_19.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_20.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_entry17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_entry372.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoMemInit.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d5_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d9_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d13_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d17_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d21_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d25_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d29_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d33_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d37_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d41_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d45_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d46_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w16_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w24_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w32_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w32_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w61_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w61_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w64_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w128_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w192_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w256_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w264_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/infer_category.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Mem2Stream.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
ipx::edit_ip_in_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:13 . Memory (MB): peak = 6917.258 ; gain = 3.281 ; free physical = 8633 ; free virtual = 13346
update_compile_order -fileset sources_1
set_property core_revision 1911202118 [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121
INFO: [IP_Flow 19-725] Reloaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121'
report_ip_status -name ip_status 
upgrade_ip -vlnv xilinx.com:hls:BlackBoxJam:1.0 [get_ips  design_1_BlackBoxJam_0_0] -log ip_upgrade.log
Upgrading '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-3422] Upgraded design_1_BlackBoxJam_0_0 (Blackboxjam 1.0) from revision 1911202117 to revision 1911202118
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> from </BlackBoxJam_0/Data_m_axi_hostmem>
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> from </BlackBoxJam_0/Data_m_axi_hostmem>
Wrote  : </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips design_1_BlackBoxJam_0_0] -no_script -sync -force -quiet
generate_target all [get_files  /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd]
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
WARNING: [BD 41-1629] Slave segment </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> is excluded from all addressing paths.
WARNING: [BD 41-1629] Slave segment </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> is excluded from all addressing paths.
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/s01_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/s01_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [BD 41-927] Following properties on pin /BlackBoxJam_0/ap_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=design_1_zynq_ultra_ps_e_0_0_pl_clk0 
Wrote  : </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.v
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block BlackBoxJam_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps8_0_100M .
Exporting to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/hw_handoff/design_1_axi_smc_0.hwh
Generated Block Design Tcl file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/hw_handoff/design_1_axi_smc_0_bd.tcl
Generated Hardware Definition File /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/synth/design_1_axi_smc_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_smc .
Exporting to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
Generated Block Design Tcl file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1_bd.tcl
Generated Hardware Definition File /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s01_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/design_1_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s01_couplers/auto_pc .
Exporting to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.hwdef
generate_target: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 7297.645 ; gain = 55.574 ; free physical = 8027 ; free virtual = 12815
catch { config_ip_cache -export [get_ips -all design_1_BlackBoxJam_0_0] }
catch { config_ip_cache -export [get_ips -all design_1_auto_ds_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_ds_0, cache-ID = 30ff942aacf18660; cache size = 3015.465 MB.
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_0, cache-ID = dbc4c1421a76552b; cache size = 3015.465 MB.
catch { config_ip_cache -export [get_ips -all design_1_auto_ds_1] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_ds_1, cache-ID = 30ff942aacf18660; cache size = 3015.465 MB.
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_1] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_1, cache-ID = dbc4c1421a76552b; cache size = 3015.465 MB.
export_ip_user_files -of_objects [get_files /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd]
launch_runs -jobs 12 design_1_BlackBoxJam_0_0_synth_1
[Mon Nov 25 09:56:40 2019] Launched design_1_BlackBoxJam_0_0_synth_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/design_1_BlackBoxJam_0_0_synth_1/runme.log
export_simulation -of_objects [get_files /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.ip_user_files/sim_scripts -ip_user_files_dir /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.ip_user_files -ipstatic_source_dir /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.ip_user_files/ipstatic -lib_map_path [list {modelsim=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/modelsim} {questa=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/questa} {ies=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/ies} {xcelium=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/xcelium} {vcs=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/vcs} {riviera=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
report_ip_status -name ip_status 
reset_run synth_1
launch_runs synth_1 -jobs 12
[Mon Nov 25 09:57:17 2019] Launched design_1_BlackBoxJam_0_0_synth_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/design_1_BlackBoxJam_0_0_synth_1/runme.log
[Mon Nov 25 09:57:17 2019] Launched synth_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/synth_1/runme.log
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xczu7ev-ffvc1156-2-e
INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_BlackBoxJam_0_0/design_1_BlackBoxJam_0_0.dcp' for cell 'design_1_i/BlackBoxJam_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/design_1_axi_smc_0.dcp' for cell 'design_1_i/axi_smc'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.dcp' for cell 'design_1_i/rst_ps8_0_100M'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/design_1_system_ila_0_1.dcp' for cell 'design_1_i/system_ila_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.dcp' for cell 'design_1_i/zynq_ultra_ps_e_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.dcp' for cell 'design_1_i/ps8_0_axi_periph/xbar'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0.dcp' for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.dcp' for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_pc'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1.dcp' for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds'
INFO: [Project 1-454] Reading design checkpoint '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/design_1_auto_pc_1.dcp' for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_pc'
INFO: [Netlist 29-17] Analyzing 10612 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Chipscope 16-324] Core: design_1_i/system_ila_0/inst/ila_lib UUID: cd4c83c8-23a6-596d-99ad-09be1335c6b0 
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_zynq_ultra_ps_e_0_0.xdc] for cell 'design_1_i/zynq_ultra_ps_e_0/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0_board.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_ps8_0_100M_0/design_1_rst_ps8_0_100M_0.xdc] for cell 'design_1_i/rst_ps8_0_100M/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0_board.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/ip/ip_1/bd_afc3_psr_aclk_0.xdc] for cell 'design_1_i/axi_smc/inst/clk_map/psr_aclk/U0'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc] for cell 'design_1_i/system_ila_0/inst/ila_lib/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/constrs_1/new/design_1_consts.xdc]
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/constrs_1/new/design_1_consts.xdc]
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst'
Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst'
Finished Parsing XDC File [/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_clocks.xdc] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl:2]
all_registers: Time (s): cpu = 00:00:18 ; elapsed = 00:00:10 . Memory (MB): peak = 9013.574 ; gain = 565.816 ; free physical = 8093 ; free virtual = 11320
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'design_1_i/ps8_0_axi_periph/s01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
Finished Sourcing Tcl File [/home/hwkim/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl] for cell 'design_1_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9013.574 ; gain = 0.000 ; free physical = 8295 ; free virtual = 11522
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 4603 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 272 instances
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 22 instances
  RAM16X1S => RAM32X1S (RAMS32): 4016 instances
  RAM32M16 => RAM32M16 (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 69 instances
  RAM32X1S => RAM32X1S (RAMS32): 224 instances

open_run: Time (s): cpu = 00:01:17 ; elapsed = 00:00:59 . Memory (MB): peak = 9165.969 ; gain = 1682.141 ; free physical = 8006 ; free virtual = 11241
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
connect_debug_port u_ila_0/clk [get_nets [list design_1_i/zynq_ultra_ps_e_0/inst/pl_clk0 ]]
set_property port_width 128 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[63]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[64]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[65]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[66]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[67]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[68]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[69]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[70]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[71]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[72]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[73]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[74]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[75]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[76]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[77]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[78]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[79]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[80]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[81]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[82]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[83]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[84]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[85]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[86]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[87]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[88]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[89]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[90]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[91]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[92]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[93]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[94]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[95]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[96]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[97]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[98]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[99]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[100]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[101]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[102]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[103]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[104]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[105]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[106]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[107]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[108]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[109]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[110]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[111]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[112]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[113]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[114]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[115]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[116]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[117]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[118]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[119]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[120]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[121]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[122]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[123]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[124]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[125]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[126]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din[127]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/icmp_ln662_loc_dout[0]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[31]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[32]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[33]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[34]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[35]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[36]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[37]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[38]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[39]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[40]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[41]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[42]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[43]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[44]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[45]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[46]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[47]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[48]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[49]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[50]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[51]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[52]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[53]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[54]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[55]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[56]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[57]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[58]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[59]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[60]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[61]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[62]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[23]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[24]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[25]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[26]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[27]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[28]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[29]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[30]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 24 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[15]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[16]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[17]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[18]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[19]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[20]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[21]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[22]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout[23]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[0]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[1]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[2]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[3]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[4]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[5]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[6]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[7]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[8]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[9]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[10]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[11]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[12]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[13]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[14]} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din[15]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/icmp_ln662_loc_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/icmp_ln662_loc_read_reg_44 ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_empty_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_read ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
connect_debug_port u_ila_0/probe42 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
connect_debug_port u_ila_0/probe43 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
connect_debug_port u_ila_0/probe44 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
connect_debug_port u_ila_0/probe45 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_full_n ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
connect_debug_port u_ila_0/probe46 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_write ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
connect_debug_port u_ila_0/probe47 [get_nets [list design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_write ]]
save_constraints
launch_runs impl_1 -to_step write_bitstream -jobs 12
Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.11 . Memory (MB): peak = 9280.180 ; gain = 0.000 ; free physical = 7896 ; free virtual = 11164
INFO: [Timing 38-480] Writing timing data to binary archive.
[Mon Nov 25 10:15:27 2019] Launched impl_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 9280.180 ; gain = 0.000 ; free physical = 7828 ; free virtual = 11124
close_design
open_run impl_1
INFO: [Netlist 29-17] Analyzing 11321 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 9359.633 ; gain = 79.453 ; free physical = 6436 ; free virtual = 10369
Restored from archive | CPU: 12.370000 secs | Memory: 152.283035 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 9359.633 ; gain = 79.453 ; free physical = 6419 ; free virtual = 10353
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 9359.633 ; gain = 0.000 ; free physical = 6453 ; free virtual = 10404
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 4992 instances were transformed.
  CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 720 instances
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 22 instances
  RAM16X1S => RAM32X1S (RAMS32): 3968 instances
  RAM32M16 => RAM32M16 (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 58 instances
  RAM32X1S => RAM32X1S (RAMS32): 224 instances

open_run: Time (s): cpu = 00:00:55 ; elapsed = 00:00:49 . Memory (MB): peak = 9661.902 ; gain = 381.723 ; free physical = 6158 ; free virtual = 10111
open_report: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 9694.367 ; gain = 27.461 ; free physical = 5730 ; free virtual = 9695
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
file copy -force /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.sysdef /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk/design_1_wrapper.hdf

launch_sdk -workspace /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk -hwspec /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk -hwspec /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.sdk/design_1_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
open_hw
connect_hw_server -url 121.155.128.106:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:121.155.128.106:3121
current_hw_target [get_hw_targets */xilinx_tcf/Xilinx/88281A]
set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Xilinx/88281A]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target 121.155.128.106:3121/xilinx_tcf/Xilinx/88281A
open_hw_target: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 11961.770 ; gain = 856.035 ; free physical = 2549 ; free virtual = 6919
set_property PROGRAM.FILE {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xczu7_0]
set_property PROBES.FILE {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xczu7_0]
set_property FULL_PROBES.FILE {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/impl_1/design_1_wrapper.ltx} [get_hw_devices xczu7_0]
current_hw_device [get_hw_devices xczu7_0]
refresh_hw_device [lindex [get_hw_devices xczu7_0] 0]
INFO: [Labtools 27-2302] Device xczu7 (JTAG device index = 0) is programmed with a design that has 2 ILA core(s).
refresh_hw_device: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 12025.184 ; gain = 50.414 ; free physical = 2504 ; free virtual = 6876
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"design_1_i/system_ila_0/inst/ila_lib"}]]
Processed interface BlackBoxJam_0_m_axi_hostmem_ila1_slot0
display_hw_ila_data [ get_hw_ila_data hw_ila_data_2 -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log1_V_V_dout was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log1_V_V_empty_n was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log1_V_V_read was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log2_V_V_dout was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log2_V_V_empty_n was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log2_V_V_read was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log3_V_V_dout was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log3_V_V_empty_n was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/act_log3_V_V_read was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/ap_CS_fsm was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/integrate_stream_U0/ap_CS_fsm__0 was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/in_V_V_dout was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/in_V_V_empty_n was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/in_V_V_read was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/out_log_V_V_din was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/out_log_V_V_full_n was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/out_log_V_V_write was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/out_V_V_din was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/out_V_V_full_n was not found in the design.
WARNING: Simulation object design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/out_V_V_write was not found in the design.
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu7_0]
add_wave -into {hw_ila_data_2.wcfg} -radix hex { {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/icmp_ln662_loc_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/icmp_ln662_loc_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/icmp_ln662_loc_read_reg_44} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/mvOut_log_m_buffer_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/inter2_log_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_17_U0/mvOut_log_m_buffer_V_V_1_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/inter3_log_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_Wid_19_U0/mvOut_log_m_buffer_V_V_2_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_log_m_buffer_V_V_1_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/mvOut_m_buffer_V_V_1_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_log_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_4_U0/out_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_dout} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_empty_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/in_V_V_read} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_log_V_V_write} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_din} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_full_n} {design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_6_U0/out_V_V_write} }
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_2' trigger was armed at 2019-Nov-25 11:00:06
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_2' triggered at 2019-Nov-25 11:00:06
INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.hw/backup/hw_ila_data_2.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/DoCompute_Block_pro_U0/inter1_log_V_V_write -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
set_property TRIGGER_COMPARE_VALUE eq1'bR [get_hw_probes design_1_i/BlackBoxJam_0/inst/grp_DoCompute_fu_1130/Matrix_Vector_Activa_2_U0/convInp_V_V_1_read -of_objects [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
INFO: [Labtools 27-1964] The ILA core 'hw_ila_2' trigger was armed at 2019-Nov-25 11:01:29
wait_on_hw_ila -timeout 0 [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
INFO: [Labtools 27-1965] The ILA core 'hw_ila_2' trigger was stopped by user at 2019-Nov-25 11:01:37
WARNING: [Labtools 27-157] hw_ila [hw_ila_2] stopped. No data to upload.
run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}] -trigger_now
INFO: [Labtools 27-1964] The ILA core 'hw_ila_2' trigger was armed at 2019-Nov-25 11:01:45
wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xczu7_0] -filter {CELL_NAME=~"u_ila_0"}]]
INFO: [Labtools 27-1966] The ILA core 'hw_ila_2' triggered at 2019-Nov-25 11:01:45
INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.hw/backup/hw_ila_data_2.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data.
open_bd_design {/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd}
ipx::edit_ip_in_project -upgrade true -name BlackBoxJam_v1_0_project -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_hostmem_m_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_32_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_53_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_94_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_164_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_185_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_325_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_727_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs0_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs1_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs2_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs3_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs4_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights0_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights1_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights2_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights4_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights10_m_weights_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_11.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_12.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_13.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_14.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_16.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_18.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_19.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_20.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_entry17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_entry372.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoMemInit.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d5_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d9_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d13_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d17_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d21_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d25_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d29_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d33_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d37_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d41_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d45_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d46_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w16_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w24_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w32_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w32_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w61_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w61_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w64_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w128_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w192_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w256_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w264_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/infer_category.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Mem2Stream.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
ipx::edit_ip_in_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:13 . Memory (MB): peak = 12159.211 ; gain = 0.000 ; free physical = 3921 ; free virtual = 8354
update_compile_order -fileset sources_1
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/StreamingDataWidthCo_1.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/StreamingDataWidthCo_1.v:]
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/StreamingDataWidthCo_1.v:]
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
ipx::unload_core /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/component.xml
close_project
ipx::edit_ip_in_project -upgrade true -name BlackBoxJam_v1_0_project -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_hostmem_m_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_32_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_53_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_94_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_164_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_185_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_325_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_727_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs0_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs1_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs2_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs3_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs4_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights0_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights1_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights2_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights4_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights10_m_weights_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_11.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_12.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_13.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_14.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_16.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_18.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_19.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_20.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_entry17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoCompute_entry372.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/DoMemInit.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d5_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d9_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d13_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d17_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d21_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d25_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d29_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d33_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d37_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d41_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d45_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w1_d46_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w16_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w24_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w32_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w32_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w61_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w61_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w64_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w128_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w192_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w256_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/fifo_w264_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/infer_category.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_stream_gen_191121/sol1/impl/ip/hdl/verilog/Mem2Stream.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
ipx::edit_ip_in_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 12351.602 ; gain = 0.000 ; free physical = 3482 ; free virtual = 7954
update_compile_order -fileset sources_1
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
close_project
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
set_property  ip_repo_paths  {} [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
set_property  ip_repo_paths  /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
report_ip_status -name ip_status 
upgrade_ip -vlnv xilinx.com:hls:BlackBoxJam:1.0 [get_ips  design_1_BlackBoxJam_0_0] -log ip_upgrade.log
Upgrading '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-3422] Upgraded design_1_BlackBoxJam_0_0 (Blackboxjam 1.0) from revision 1911202118 to revision 1911251314
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> from </BlackBoxJam_0/Data_m_axi_hostmem>
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> from </BlackBoxJam_0/Data_m_axi_hostmem>
Wrote  : </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips design_1_BlackBoxJam_0_0] -no_script -sync -force -quiet
report_ip_status -name ip_status 
ipx::edit_ip_in_project -upgrade true -name BlackBoxJam_v1_0_project -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.tmp/BlackBoxJam_v1_0_project /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hwkim/Xilinx/Vivado/2019.1/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_control_s_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_hostmem_m_axi.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_32_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_42_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_53_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_94_24_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_164_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_185_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_325_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_16_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_366_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_mux_727_32_1_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs0_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs1_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs2_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs3_m_threshold_31.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_threshs4_m_threshold_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights0_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights1_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights2_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights4_m_weights_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/BlackBoxJam_weights10_m_weights_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_2_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_4_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/ConvolutionInputGene_inputBuf_0_V.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_pro_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_10.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_11.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_12.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_13.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_14.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_15.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_16.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_18.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_19.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Block_Wid_20.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_entry17.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_entry373.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoCompute_Loop_1_pro.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/DoMemInit.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d5_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d9_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d13_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d17_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d21_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d25_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d29_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d33_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d37_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d41_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d45_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w1_d46_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w16_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w24_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w32_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w32_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w61_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w61_d48_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w64_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w128_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w192_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w256_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/fifo_w264_d2_A.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/infer_category.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_1.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_2.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_3.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_4.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_5.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_6.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_7.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_8.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_9.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip/hdl/verilog/Matrix_Vector_Activa_10.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
ipx::edit_ip_in_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 12422.027 ; gain = 0.000 ; free physical = 2887 ; free virtual = 9062
update_compile_order -fileset sources_1
set_property core_revision 1911251315 [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::save_core [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path /data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip
INFO: [IP_Flow 19-725] Reloaded user IP repository '/data_drive/bnn_seg_hls_project_backup/bnn_fpga_dbg_sel_strm_191125/sol1/impl/ip'
report_ip_status -name ip_status 
upgrade_ip -vlnv xilinx.com:hls:BlackBoxJam:1.0 [get_ips  design_1_BlackBoxJam_0_0] -log ip_upgrade.log
Upgrading '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd'
INFO: [IP_Flow 19-3422] Upgraded design_1_BlackBoxJam_0_0 (Blackboxjam 1.0) from revision 1911251314 to revision 1911251315
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> from </BlackBoxJam_0/Data_m_axi_hostmem>
Excluding </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> from </BlackBoxJam_0/Data_m_axi_hostmem>
Wrote  : </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
INFO: [Coretcl 2-1525] Wrote upgrade log to '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips design_1_BlackBoxJam_0_0] -no_script -sync -force -quiet
generate_target all [get_files  /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd]
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug.
Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager.
For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
WARNING: [BD 41-1629] Slave segment </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> is excluded from all addressing paths.
WARNING: [BD 41-1629] Slave segment </zynq_ultra_ps_e_0/SAXIGP2/HP0_QSPI> is excluded from all addressing paths.
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/s01_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/s01_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [BD 41-927] Following properties on pin /BlackBoxJam_0/ap_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=design_1_zynq_ultra_ps_e_0_0_pl_clk0 
Wrote  : </home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd> 
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.v
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_arlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_ARLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/axi_smc/S00_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
WARNING: [BD 41-235] Width mismatch when connecting pin: '/system_ila_0/SLOT_0_AXI_awlock'(1) to net 'BlackBoxJam_0_m_axi_hostmem_AWLOCK'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/sim/design_1.v
VHDL Output written to : /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block BlackBoxJam_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps8_0_100M .
Exporting to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/hw_handoff/design_1_axi_smc_0.hwh
Generated Block Design Tcl file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/hw_handoff/design_1_axi_smc_0_bd.tcl
Generated Hardware Definition File /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_smc_0/bd_0/synth/design_1_axi_smc_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_smc .
Exporting to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1.hwh
Generated Block Design Tcl file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/hw_handoff/design_1_system_ila_0_1_bd.tcl
Generated Hardware Definition File /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_1/bd_0/synth/design_1_system_ila_0_1.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block system_ila_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s01_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/design_1_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps8_0_axi_periph/s01_couplers/auto_pc .
Exporting to file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh
Generated Block Design Tcl file /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
Generated Hardware Definition File /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/synth/design_1.hwdef
generate_target: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 12422.027 ; gain = 0.000 ; free physical = 2657 ; free virtual = 8897
catch { config_ip_cache -export [get_ips -all design_1_BlackBoxJam_0_0] }
catch { config_ip_cache -export [get_ips -all design_1_auto_ds_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_ds_0, cache-ID = 30ff942aacf18660; cache size = 3148.983 MB.
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_0, cache-ID = dbc4c1421a76552b; cache size = 3148.983 MB.
catch { config_ip_cache -export [get_ips -all design_1_auto_ds_1] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_ds_1, cache-ID = 30ff942aacf18660; cache size = 3148.983 MB.
catch { config_ip_cache -export [get_ips -all design_1_auto_pc_1] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP design_1_auto_pc_1, cache-ID = dbc4c1421a76552b; cache size = 3148.983 MB.
export_ip_user_files -of_objects [get_files /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd]
launch_runs -jobs 12 design_1_BlackBoxJam_0_0_synth_1
[Mon Nov 25 13:39:07 2019] Launched design_1_BlackBoxJam_0_0_synth_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/design_1_BlackBoxJam_0_0_synth_1/runme.log
export_simulation -of_objects [get_files /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -directory /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.ip_user_files/sim_scripts -ip_user_files_dir /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.ip_user_files -ipstatic_source_dir /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.ip_user_files/ipstatic -lib_map_path [list {modelsim=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/modelsim} {questa=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/questa} {ies=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/ies} {xcelium=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/xcelium} {vcs=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/vcs} {riviera=/home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
report_ip_status -name ip_status 
reset_run synth_1
launch_runs synth_1 -jobs 12
[Mon Nov 25 13:39:58 2019] Launched design_1_BlackBoxJam_0_0_synth_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/design_1_BlackBoxJam_0_0_synth_1/runme.log
[Mon Nov 25 13:39:58 2019] Launched synth_1...
Run output will be captured here: /home/hwkim/work/pynq-bnn/BNN-PYNQ/bnn/src/network/output/vivado/bnn_seg_net_zcu104/project_1/project_1.runs/synth_1/runme.log