Experiment : Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates.
Discipline | Electrical Engineering |
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Lab | Digital Electronics |
Experiment | 6. Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates. |
Sr. No | Learning Objective | Cognitive Level | Action Verb |
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1. | User will be able to: Identify RS, JK, T and D flip-flops. |
Recall | Identify |
2. | User will be able to: Apply input and output values of RS, JK, T and D flip-flops. |
Apply | Apply |
3. | User will be able to: Examine the truth table of RS, JK, T and D flip-flops and verify. |
Analyse | Examine |
Description: Instructional Strategy will be implemented in the simulator as follows:
The Experiment contains RS, JK, T and D flip-flops. During the experiment students will be able to choose their desired flip-flop and apply input and output values.
Read the theory and comprehend the concepts related to the experiment. [LO1, LO2, LO3]
Sr. No | Learning Objective | Task to be performed by the student in the simulator |
Assessment Questions as per LO & Task |
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1. | Student will be able to Identify RS, JK, T and D flip-flops. |
Study about the various flip-flops involved in the experiment from the theory section. |
Q1. How many types of flip-flops are? A.2 B. 3 C .4 D.5 Q2. The SET-RESET flip flop is designed with the help of? A. Two NOR gates and also two NAND gates. B. Two NOR gates C. Two NAND gates D.None of the Mentioned Q3. In J-K flip-flop letters ‘J” and ‘K’ stands for? A. Letter ‘J’ stands for clear and letter ‘K’ stands for set. B. Letter ‘J’ stands for set and letter ‘K’ stands for clear. C. Both a and b. D. None of these Q4. In D flip-flop, D stands for A. Distant. B. Delay. C. Desired. D. None of the above |
2. | Student will be able to Apply input and output values of RS, JK, T and D flip-flops. | Apply input and output values to design the different flipflops using Nand and Nor gates. |
Q1. How is a J-K flip-flop made to toggle? A. J = 1, K = 0 B. J = 0, K = 1 C. J = 0, K = 0 D. J = 1, K = 1 Q2. In J-K flip-flop, “no change” condition appears when A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1 Q3. The D flip-flop has _______ input. A. 1 B. 2 C. 3 D. 4 Q4. In D flip-flop, if clock input is HIGH & D=1, then output is A. 0 B. 1 C. Forbidden D. Toggle |
3. | Student will be able to Examine the truth table of RS, JK, T and D flip-flops and verify. | Examine the truth table based upon the input and output value. |
Q1. The truth table for an S-R flip-flop has how many VALID entries? A. 1 B. 2 C. 3 D. 4 Q2. When both inputs of a J-K flip-flop cycle, the output will A. Invalid B. Change C. No Change D. Toggle Q3. What is the hold condition of a flip-flop? A. Both S and R inputs activated B. No active S or R input C. Only S is active D. Only R is active Q4. The flip-flops which has not any invalid states are A. S-R, J-K, D B. S-R, J-K, T C. J-K, D, S-R D. J-K, D, T |
Sr.No | What Students will do? | What Simulator will do? | Purpose of the task |
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1. | Choose a flip-flop. |
Display the simulator window for particular flip-flop. |
To perform experiment on a particular flip-flop. |
2. | Enter the Binary inputs and corresponding outputs and then click on Check. |
Input and Output will be added to table with corresponding remarks. |
To check the knowledge of operation of flip-flops. |
3. | Click on “Reset” button. |
Clear all the input and Output Fields. |
To provide space for further entries. |