diff --git a/.github/scripts/release.py b/.github/scripts/release.py index 969eb887..5809e723 100755 --- a/.github/scripts/release.py +++ b/.github/scripts/release.py @@ -1,7 +1,7 @@ import argparse, copy, hashlib, json, re, requests, os, shutil -version = '0.2.0' +version = '0.2.1' xmc_ino_root_path = os.path.relpath(os.path.join(os.path.join(os.getcwd(), os.pardir), os.pardir)) build_dir_name = 'pkg_build' @@ -37,8 +37,12 @@ def build_package(pkg_name): 'README.md' ] + ignore_pattern = shutil.ignore_patterns() + for dir in dirs_to_copy: - shutil.copytree(os.path.join(xmc_ino_root_path, dir), os.path.join(pkg_build_path, dir)) + if dir == 'libraries': + ignore_pattern = shutil.ignore_patterns('Makefile', 'Makefile.test', 'test') + shutil.copytree(os.path.join(xmc_ino_root_path, dir), os.path.join(pkg_build_path, dir), ignore=ignore_pattern) for file in files_to_copy: shutil.copyfile(os.path.join(xmc_ino_root_path, file), os.path.join(pkg_build_path, file)) diff --git a/.github/workflows/compile-platform-examples.yml b/.github/workflows/compile-platform-examples.yml index 0feaddac..30dcb853 100644 --- a/.github/workflows/compile-platform-examples.yml +++ b/.github/workflows/compile-platform-examples.yml @@ -44,6 +44,7 @@ jobs: stackMem: true dma: false alarmRtc: false + can: false - fqbn: Infineon:xmc:XMC1100_XMC2GO i2s: true dieTemp: true @@ -53,6 +54,7 @@ jobs: stackMem: true dma: false alarmRtc: false + can: false - fqbn: Infineon:xmc:XMC1300_Boot_Kit i2s: false dieTemp: true @@ -63,6 +65,7 @@ jobs: multiSerial: false dma: false alarmRtc: false + can: false - fqbn: Infineon:xmc:XMC4200_Platform2GO i2s: false dieTemp: false @@ -73,6 +76,7 @@ jobs: multiSerial: false dma: false alarmRtc: true + can: true - fqbn: Infineon:xmc:XMC4400_Platform2GO i2s: false dieTemp: false @@ -82,6 +86,7 @@ jobs: stackMem: true dma: false alarmRtc: false + can: true - fqbn: Infineon:xmc:XMC4700_Relax_Kit i2s: true dieTemp: true @@ -92,6 +97,7 @@ jobs: multiSerial: true dma: true alarmRtc: true + can: true - fqbn: Infineon:xmc:XMC1400_XMC2GO i2s: true dieTemp: true @@ -101,6 +107,7 @@ jobs: stackMem: false dma: false alarmRtc: false + can: true - fqbn: Infineon:xmc:XMC1400_Arduino_Kit i2s: false dieTemp: true @@ -111,6 +118,7 @@ jobs: multiSerial: false dma: false alarmRtc: false + can: false # Make board type-specific customizations to the matrix jobs include: @@ -146,12 +154,16 @@ jobs: alarmRtc: true alarmRtc-sketch-paths: | - libraries/RTC/examples/AlarmRTC + - board: + can: true + can-sketch-paths: | + - libraries/CAN/examples steps: - name: Checkout repository - uses: actions/checkout@v2 + uses: actions/checkout@v4 - name: Compile examples - uses: arduino/compile-sketches@v1 + uses: arduino/compile-sketches@v1.1.1 with: github-token: ${{ secrets.GITHUB_TOKEN }} fqbn: ${{ matrix.board.fqbn }} @@ -178,12 +190,13 @@ jobs: ${{ matrix.multiSerial-sketch-paths }} ${{ matrix.dma-sketch-paths }} ${{ matrix.alarmRtc-sketch-paths }} + ${{ matrix.can-sketch-paths }} enable-deltas-report: false sketches-report-path: ${{ env.SKETCHES_REPORTS_PATH }} - name: Save sketches report as workflow artifact - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v3 with: if-no-files-found: error path: ${{ env.SKETCHES_REPORTS_PATH }} - name: ${{ env.SKETCHES_REPORTS_PATH }} \ No newline at end of file + name: ${{ env.SKETCHES_REPORTS_PATH }} diff --git a/.gitignore b/.gitignore index f8dacaac..2fbce262 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,6 @@ .history .vscode -pkg_build \ No newline at end of file +pkg_build +build +.clang-format +**/__pycache__/ \ No newline at end of file diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index b735e252..3ae89b6c 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -16,6 +16,22 @@ Check the **develop** branch for any Beta releases fixes for any issues you may 4. Other branches are for other tests and not to be treated as anything but work in progress for now 5. Check [XMC-for-Arduino Wiki](https://github.com/Infineon/XMC-for-Arduino/wiki) for any additional information +### Develop Built-in Library + + +### Add new XMC Board + ### Local Running using Arduino IDE (**ON WINDOWS**): Clone the repository in arduino folder: - Open Arduino and install any Infineon XMC library (e.g. 2.2.0) diff --git a/README.md b/README.md index 32ea10de..87ad35b2 100644 --- a/README.md +++ b/README.md @@ -21,6 +21,7 @@ This repository integrates [Infineon's](https://www.infineon.com/) XMC microcont * [XMC1100 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_2go_xmc1100_v1/) * [XMC1100 Boot Kit](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc11_boot_001/) * [XMC1300 Boot Kit](https://www.infineon.com/cms/de/product/evaluation-boards/kit_xmc13_boot_001/) +* [XMC1400 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc14_2go/) * [XMC1400 Kit for Arduino](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc1400_arduino/) * [XMC4200 Platform 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_plt2go_xmc4200/) * [XMC4400 Platform 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_plt2go_xmc4400//) @@ -35,6 +36,7 @@ Please visit also the Wiki for additional information, e.g. datasheets, pin out * Page for [XMC1100 XMC 2Go](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC-2Go) * Page for [XMC1100 Boot Kit](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC1100-Boot-Kit) * Page for [XMC1300 Boot Kit](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC1300-Boot-Kit) +* Page for [XMC1400 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc14_2go/) * Page for [XMC1400 Kit for Arduino](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC1400-Kit-for-Arduino) * Page for [XMC4200 Platform 2Go](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC4200-Platform2Go) * Page for [XMC4400 Platform 2Go](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC4400-Platform2Go) diff --git a/boards.txt b/boards.txt index 08dd09cb..a8139ec0 100644 --- a/boards.txt +++ b/boards.txt @@ -154,7 +154,7 @@ XMC1400_XMC2GO.serial.disableRTS=true XMC1400_XMC2GO.build.mcu=cortex-m0 XMC1400_XMC2GO.build.f_cpu=48000000L XMC1400_XMC2GO.build.board=ARM_XMC -XMC1400_XMC2GO.build.board.version=1402 +XMC1400_XMC2GO.build.board.version=1404 XMC1400_XMC2GO.build.board.type=Q040x0200 XMC1400_XMC2GO.build.board.v=0200 XMC1400_XMC2GO.build.core=./ diff --git a/cores/Arduino.h b/cores/Arduino.h index 4f17e132..2e25b81d 100644 --- a/cores/Arduino.h +++ b/cores/Arduino.h @@ -50,6 +50,7 @@ extern "C" { #include #include #include +#include //**************************************************************************** // @Defines @@ -247,9 +248,40 @@ extern "C" { #endif } XMC_I2S_t; -//**************************************************************************** -// @Imported Global Variables -//**************************************************************************** +#ifdef CAN_xmc + /* + * XMC (Arduino) CAN type + */ + + typedef enum + { + XMC_NODE_NUM_0, + XMC_NODE_NUM_1 + } + XMC_CAN_NODE_NUM_t; + + typedef struct + { + CAN_NODE_TypeDef *can_node; + XMC_CAN_NODE_NUM_t can_node_num; + XMC_CAN_CANCLKSRC_t can_clock; + uint32_t can_frequency; + XMC_PORT_PIN_t rx; + XMC_GPIO_CONFIG_t rx_config; + XMC_PORT_PIN_t tx; + XMC_GPIO_CONFIG_t tx_config; + XMC_CAN_NODE_RECEIVE_INPUT_t node_input; + IRQn_Type irq_num; + uint32_t irq_service_request; +#if (UC_SERIES == XMC14) + XMC_SCU_IRQCTRL_t irq_source; +#endif + } XMC_ARD_CAN_t; +#endif + + //**************************************************************************** + // @Imported Global Variables + //**************************************************************************** extern const XMC_PORT_PIN_t mapping_port_pin[]; extern const XMC_PIN_INTERRUPT_t mapping_interrupt[]; extern const uint8_t mapping_pin_PWM4[][ 2 ]; @@ -277,6 +309,9 @@ extern "C" { extern XMC_I2S_t i2s_config; +#ifdef CAN_xmc + extern XMC_ARD_CAN_t XMC_CAN_0; +#endif //**************************************************************************** // @Prototypes Of Global Functions //**************************************************************************** diff --git a/cores/xmc_lib/README.md b/cores/xmc_lib/README.md new file mode 100644 index 00000000..38a006a2 --- /dev/null +++ b/cores/xmc_lib/README.md @@ -0,0 +1,18 @@ +# Develop notes +## XMCLib version +The current one is V4.3.0. The macro of XMCLib version is also defined in ```cores\xmc_lib\XMCLib\inc\xmc_common.h``` + +## CAN macro + +Because XMClibs use CAN macro, conflicts with Arduino default CAN class name, so we manually changed XMClib (CAN -> CAN_xmc). +changed files: + +.h header files: +- XMCLib\inc\xmc_can.h +- XMCLib\inc\xmc_pau.h +- XMCLib\inc\xmc1_scu.h +- XMCLib\inc\xmc4_scu.h + +.c source files: +- XMCLib\src\xmc_can.c +- XMCLib\src\xmc1_scu.c \ No newline at end of file diff --git a/cores/xmc_lib/XMCLib/License.txt b/cores/xmc_lib/XMCLib/License.txt index b31b2217..cf584655 100644 --- a/cores/xmc_lib/XMCLib/License.txt +++ b/cores/xmc_lib/XMCLib/License.txt @@ -1,19 +1,31 @@ License Terms and Copyright Information ======================================= -Copyright (c) 2015-2016, Infineon Technologies AG All rights reserved. +Copyright (c) 2015-2023, Infineon Technologies AG All rights reserved. -Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. -- Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software - without specific prior written permission. +Boost Software License - Version 1.0 - August 17th, 2003 -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS -BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +Permission is hereby granted, free of charge, to any person or organization +obtaining a copy of the software and accompanying documentation covered by +this license (the "Software") to use, reproduce, display, distribute, +execute, and transmit the Software, and to prepare derivative works of the +Software, and to permit third-parties to whom the Software is furnished to +do so, all subject to the following: -To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with Infineon Technologies AG (support@infineon.com). +The copyright notices in the Software and this entire statement, including +the above license grant, this restriction and the following disclaimer, +must be included in all copies of the Software, in whole or in part, and +all derivative works of the Software, unless such copies or derivative +works are solely in the form of machine-executable object code generated by +a source language processor. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT +SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE +FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. + +To improve the quality of the software, users are encouraged to share modifications, +enhancements or bug fixes with Infineon Technologies AG at XMCSupport@infineon.com. diff --git a/cores/xmc_lib/XMCLib/Readme.txt b/cores/xmc_lib/XMCLib/Readme.txt deleted file mode 100644 index 74ada94e..00000000 --- a/cores/xmc_lib/XMCLib/Readme.txt +++ /dev/null @@ -1,80 +0,0 @@ -== INTRODUCTION == - -The XMC Peripheral Library (XMC Lib) consists of low-level drivers for the XMC product family peripherals. -It addition the Cortex Microcontroller Software Interface Standard (CMSIS) is included. -CMSIS provides a hardware abstraction layer for the Cortex-M processor series. -XMC Lib is built on top of CMSIS and MISRA-C 2004 compliant. - -The following tool chains are supported: -- GNU GCC for ARM (gcc) -- MDK-ARM Microcontroller Development Kit v5 (armcc) -- IAR Embedded Workbench for ARM (iccarm) -- TASKING VX-toolset for ARM v5.(carm) - -The following 32-Bit Industrial Microcontrollers based on ARM Cortex are supported: -- XMC4800 series -- XMC4700 series -- XMC4500 series -- XMC4400 series -- XMC4300 series -- XMC4200 series -- XMC4100 series -- XMC1400 series -- XMC1300 series -- XMC1200 series -- XMC1100 series - -== CONTENTS == - - Readme.txt - License.txt - XMClib/ - doc/ - examples/ - /inc - /src - CMSIS/ - Include/ - Infineon/ - SVD/ - XMC1100_series/ - XMC1200_series/ - XMC1300_series/ - XMC1400_series/ - XMC4100_series/ - XMC4200_series/ - XMC4300_series/ - XMC4400_series/ - XMC4500_series/ - XMC4700_series/ - XMC4800_series/ - Lib/ - -Now let's explain the purpose of each directory: - - XMClib: The XMC Peripheral Library - - XMClib/doc: Holds complete documentation - - XMClib/examples: Contains examples using the XMClib for the supported devices and tool chains. - - XMClib/inc: Include files per peripheral - - XMClib/src: Implementation files per peripheral - - CMSIS: The Cortex Microcontroller Software Interface Standard abstraction layer - - CMSIS/Include: Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, - NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions - - CMSIS/Infineon: Includes System View Description files (SVD) for use with debuggers, device header files with the register description, - system files and startup files defined by CMSIS - - CMSIS/Lib: Precompiled CMSIS DSP libraries for XMC4 (ARM Cortex M4F) and XMC1 (ARM Cortex M0) families. - -== USAGE == - -Several examples for the supported tool chains are provided that can serve as starting point. - -To start a project from scratch follow the steps: -1. Copy the CMSIS, XMClib and Newlib folders into your project. -3. Add the following folders into the include paths of your project: - - ${ProjName}/XMCLib/inc - - ${ProjName}/CMSIS/Include - - ${ProjName}/CMSIS/Infineon/XMC4400_series/Include -4. Select the device for which your compiling defining a preprocessor symbol, i.e. XMC4500_F144x1024 -5. Include into your source the header files of the peripherals you want to use, i.e. #include -6. Configure the peripheral and make use of the APIs described in the documentation. - - diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h b/cores/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h index 32f3dc6a..d3380505 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_ccu4_map.h @@ -1,43 +1,41 @@ /** * @file xmc1_ccu4_map.h - * @date 2015-08-25 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-08-25: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -1377,7 +1375,8 @@ #define CCU41_IN0_P4_0 2 #define CCU41_IN0_P4_4 21 #define CCU41_IN0_P4_8 26 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_CCU40_ST1 11 #define CCU41_IN1_CCU41_GP02 12 @@ -1398,7 +1397,8 @@ #define CCU41_IN1_P4_1 2 #define CCU41_IN1_P4_5 21 #define CCU41_IN1_P4_9 26 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_CCU40_ST2 11 #define CCU41_IN2_CCU41_GP03 12 @@ -1419,8 +1419,10 @@ #define CCU41_IN2_P4_10 26 #define CCU41_IN2_P4_2 2 #define CCU41_IN2_P4_6 21 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -1438,7 +1440,8 @@ #define CCU41_IN3_P4_11 26 #define CCU41_IN3_P4_3 2 #define CCU41_IN3_P4_7 21 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -1534,7 +1537,8 @@ #define CCU41_IN0_P0_4 1 #define CCU41_IN0_P3_0 0 #define CCU41_IN0_P4_4 21 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_CCU40_ST1 11 #define CCU41_IN1_CCU41_GP02 12 @@ -1553,7 +1557,8 @@ #define CCU41_IN1_P0_5 1 #define CCU41_IN1_P3_0 0 #define CCU41_IN1_P4_5 21 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_CCU40_ST2 11 #define CCU41_IN2_CCU41_GP03 12 @@ -1572,8 +1577,10 @@ #define CCU41_IN2_P0_6 1 #define CCU41_IN2_P3_0 0 #define CCU41_IN2_P4_6 21 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -1589,7 +1596,8 @@ #define CCU41_IN3_P0_7 1 #define CCU41_IN3_P3_0 0 #define CCU41_IN3_P4_7 21 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -1734,7 +1742,8 @@ #define CCU41_IN0_POSIF1_OUT3 6 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -1763,7 +1772,8 @@ #define CCU41_IN1_POSIF1_OUT4 7 #define CCU41_IN1_SCU_ACMP2_OUT 18 #define CCU41_IN1_SCU_ACMP3_OUT 17 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -1793,10 +1803,12 @@ #define CCU41_IN2_POSIF1_OUT4 7 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -1821,7 +1833,8 @@ #define CCU41_IN3_POSIF1_OUT5 5 #define CCU41_IN3_SCU_ACMP0_OUT 17 #define CCU41_IN3_SCU_ACMP3_OUT 18 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -1949,7 +1962,8 @@ #define CCU41_IN0_P0_4 1 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -1969,7 +1983,8 @@ #define CCU41_IN1_ERU1_PDOUT1 22 #define CCU41_IN1_P0_5 1 #define CCU41_IN1_SCU_ACMP2_OUT 18 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -1990,10 +2005,12 @@ #define CCU41_IN2_P0_6 1 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -2009,7 +2026,8 @@ #define CCU41_IN3_ERU1_PDOUT3 22 #define CCU41_IN3_P0_7 1 #define CCU41_IN3_SCU_ACMP0_OUT 17 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -2144,7 +2162,8 @@ #define CCU41_IN0_POSIF1_OUT3 6 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -2171,7 +2190,8 @@ #define CCU41_IN1_POSIF1_OUT4 7 #define CCU41_IN1_SCU_ACMP2_OUT 18 #define CCU41_IN1_SCU_ACMP3_OUT 17 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -2199,10 +2219,12 @@ #define CCU41_IN2_POSIF1_OUT4 7 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -2225,7 +2247,8 @@ #define CCU41_IN3_POSIF1_OUT5 5 #define CCU41_IN3_SCU_ACMP0_OUT 17 #define CCU41_IN3_SCU_ACMP3_OUT 18 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -2370,7 +2393,8 @@ #define CCU41_IN0_POSIF1_OUT3 6 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -2399,7 +2423,8 @@ #define CCU41_IN1_POSIF1_OUT4 7 #define CCU41_IN1_SCU_ACMP2_OUT 18 #define CCU41_IN1_SCU_ACMP3_OUT 17 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -2429,10 +2454,12 @@ #define CCU41_IN2_POSIF1_OUT4 7 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -2457,7 +2484,8 @@ #define CCU41_IN3_POSIF1_OUT5 5 #define CCU41_IN3_SCU_ACMP0_OUT 17 #define CCU41_IN3_SCU_ACMP3_OUT 18 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -2585,7 +2613,8 @@ #define CCU41_IN0_P0_4 1 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -2605,7 +2634,8 @@ #define CCU41_IN1_ERU1_PDOUT1 22 #define CCU41_IN1_P0_5 1 #define CCU41_IN1_SCU_ACMP2_OUT 18 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -2626,10 +2656,12 @@ #define CCU41_IN2_P0_6 1 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -2645,7 +2677,8 @@ #define CCU41_IN3_ERU1_PDOUT3 22 #define CCU41_IN3_P0_7 1 #define CCU41_IN3_SCU_ACMP0_OUT 17 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -2736,7 +2769,8 @@ #define CCU41_IN0_ERU1_PDOUT0 22 #define CCU41_IN0_ERU1_PDOUT1 24 #define CCU41_IN0_P0_4 1 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_CCU40_ST1 11 #define CCU41_IN1_CCU41_GP02 12 @@ -2753,7 +2787,8 @@ #define CCU41_IN1_ERU1_PDOUT0 24 #define CCU41_IN1_ERU1_PDOUT1 22 #define CCU41_IN1_P0_5 1 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_CCU40_ST2 11 #define CCU41_IN2_CCU41_GP03 12 @@ -2770,8 +2805,10 @@ #define CCU41_IN2_ERU1_PDOUT2 22 #define CCU41_IN2_ERU1_PDOUT3 24 #define CCU41_IN2_P0_6 1 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -2785,7 +2822,8 @@ #define CCU41_IN3_ERU1_PDOUT2 24 #define CCU41_IN3_ERU1_PDOUT3 22 #define CCU41_IN3_P0_7 1 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -2879,7 +2917,8 @@ #define CCU41_IN0_P0_4 1 #define CCU41_IN0_P3_0 0 #define CCU41_IN0_P4_4 21 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_CCU40_ST1 11 #define CCU41_IN1_CCU41_GP02 12 @@ -2898,7 +2937,8 @@ #define CCU41_IN1_P0_5 1 #define CCU41_IN1_P3_0 0 #define CCU41_IN1_P4_5 21 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_CCU40_ST2 11 #define CCU41_IN2_CCU41_GP03 12 @@ -2917,8 +2957,10 @@ #define CCU41_IN2_P0_6 1 #define CCU41_IN2_P3_0 0 #define CCU41_IN2_P4_6 21 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -2934,7 +2976,8 @@ #define CCU41_IN3_P0_7 1 #define CCU41_IN3_P3_0 0 #define CCU41_IN3_P4_7 21 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -3037,7 +3080,8 @@ #define CCU41_IN0_P4_0 2 #define CCU41_IN0_P4_4 21 #define CCU41_IN0_P4_8 26 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_CCU40_ST1 11 #define CCU41_IN1_CCU41_GP02 12 @@ -3058,7 +3102,8 @@ #define CCU41_IN1_P4_1 2 #define CCU41_IN1_P4_5 21 #define CCU41_IN1_P4_9 26 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_CCU40_ST2 11 #define CCU41_IN2_CCU41_GP03 12 @@ -3079,8 +3124,10 @@ #define CCU41_IN2_P4_10 26 #define CCU41_IN2_P4_2 2 #define CCU41_IN2_P4_6 21 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -3098,7 +3145,8 @@ #define CCU41_IN3_P4_11 26 #define CCU41_IN3_P4_3 2 #define CCU41_IN3_P4_7 21 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -3245,7 +3293,8 @@ #define CCU41_IN0_POSIF1_OUT3 6 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -3274,7 +3323,8 @@ #define CCU41_IN1_POSIF1_OUT4 7 #define CCU41_IN1_SCU_ACMP2_OUT 18 #define CCU41_IN1_SCU_ACMP3_OUT 17 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -3304,10 +3354,12 @@ #define CCU41_IN2_POSIF1_OUT4 7 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -3332,10 +3384,202 @@ #define CCU41_IN3_POSIF1_OUT5 5 #define CCU41_IN3_SCU_ACMP0_OUT 17 #define CCU41_IN3_SCU_ACMP3_OUT 18 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define CCU40_IN0_BCCU0_OUT0 16 +#define CCU40_IN0_BCCU0_OUT6 25 +#define CCU40_IN0_CCU40_GP01 12 +#define CCU40_IN0_CCU40_SR0 27 +#define CCU40_IN0_CCU40_SR2 19 +#define CCU40_IN0_CCU40_ST0 20 +#define CCU40_IN0_CCU40_ST1 13 +#define CCU40_IN0_CCU40_ST2 14 +#define CCU40_IN0_CCU40_ST3 15 +#define CCU40_IN0_CCU80_ST3 7 +#define CCU40_IN0_ERU0_IOUT0 10 +#define CCU40_IN0_ERU0_PDOUT0 9 +#define CCU40_IN0_ERU0_PDOUT1 3 +#define CCU40_IN0_ERU1_IOUT0 23 +#define CCU40_IN0_ERU1_PDOUT0 22 +#define CCU40_IN0_ERU1_PDOUT1 24 +#define CCU40_IN0_P0_0 2 +#define CCU40_IN0_P0_12 0 +#define CCU40_IN0_P0_6 1 +#define CCU40_IN0_POSIF0_OUT0 4 +#define CCU40_IN0_POSIF0_OUT1 5 +#define CCU40_IN0_POSIF0_OUT3 6 +#define CCU40_IN0_SCU_ACMP0_OUT 18 +#define CCU40_IN0_SCU_ACMP1_OUT 17 +#define CCU40_IN0_SCU_GSC40 8 +#define CCU40_IN0_U0C0_DX2INS 11 +#define CCU40_IN1_BCCU0_OUT3 25 +#define CCU40_IN1_BCCU0_OUT8 16 +#define CCU40_IN1_CCU40_GP02 12 +#define CCU40_IN1_CCU40_SR1 27 +#define CCU40_IN1_CCU40_SR2 19 +#define CCU40_IN1_CCU40_ST0 13 +#define CCU40_IN1_CCU40_ST1 20 +#define CCU40_IN1_CCU40_ST2 14 +#define CCU40_IN1_CCU40_ST3 15 +#define CCU40_IN1_ERU0_IOUT1 10 +#define CCU40_IN1_ERU0_PDOUT0 3 +#define CCU40_IN1_ERU0_PDOUT1 9 +#define CCU40_IN1_ERU1_IOUT1 23 +#define CCU40_IN1_ERU1_PDOUT0 24 +#define CCU40_IN1_ERU1_PDOUT1 22 +#define CCU40_IN1_P0_1 2 +#define CCU40_IN1_P0_12 0 +#define CCU40_IN1_P0_7 1 +#define CCU40_IN1_POSIF0_OUT0 4 +#define CCU40_IN1_POSIF0_OUT1 5 +#define CCU40_IN1_POSIF0_OUT3 6 +#define CCU40_IN1_POSIF0_OUT4 7 +#define CCU40_IN1_SCU_ACMP2_OUT 18 +#define CCU40_IN1_SCU_GSC40 8 +#define CCU40_IN1_U0C1_DX2INS 11 +#define CCU40_IN2_BCCU0_OUT4 16 +#define CCU40_IN2_BCCU0_OUT7 25 +#define CCU40_IN2_CCU40_GP03 12 +#define CCU40_IN2_CCU40_SR1 19 +#define CCU40_IN2_CCU40_SR2 27 +#define CCU40_IN2_CCU40_ST0 13 +#define CCU40_IN2_CCU40_ST1 14 +#define CCU40_IN2_CCU40_ST2 20 +#define CCU40_IN2_CCU40_ST3 15 +#define CCU40_IN2_ERU0_IOUT2 10 +#define CCU40_IN2_ERU0_PDOUT2 9 +#define CCU40_IN2_ERU0_PDOUT3 3 +#define CCU40_IN2_ERU1_IOUT2 23 +#define CCU40_IN2_ERU1_PDOUT2 22 +#define CCU40_IN2_ERU1_PDOUT3 24 +#define CCU40_IN2_P0_12 0 +#define CCU40_IN2_P0_2 2 +#define CCU40_IN2_P0_8 1 +#define CCU40_IN2_POSIF0_OUT0 28 +#define CCU40_IN2_POSIF0_OUT1 4 +#define CCU40_IN2_POSIF0_OUT2 5 +#define CCU40_IN2_POSIF0_OUT3 6 +#define CCU40_IN2_POSIF0_OUT4 7 +#define CCU40_IN2_SCU_ACMP1_OUT 18 +#define CCU40_IN2_SCU_ACMP2_OUT 17 +#define CCU40_IN2_SCU_GSC40 8 +#define CCU40_IN3_BCCU0_OUT1 25 +#define CCU40_IN3_BCCU0_OUT5 16 +#define CCU40_IN3_CCU40_GP00 12 +#define CCU40_IN3_CCU40_SR1 19 +#define CCU40_IN3_CCU40_SR3 27 +#define CCU40_IN3_CCU40_ST0 13 +#define CCU40_IN3_CCU40_ST1 14 +#define CCU40_IN3_CCU40_ST2 15 +#define CCU40_IN3_CCU40_ST3 20 +#define CCU40_IN3_CCU80_IGBTO 7 +#define CCU40_IN3_ERU0_IOUT3 10 +#define CCU40_IN3_ERU0_PDOUT2 3 +#define CCU40_IN3_ERU0_PDOUT3 9 +#define CCU40_IN3_ERU1_IOUT3 23 +#define CCU40_IN3_ERU1_PDOUT2 24 +#define CCU40_IN3_ERU1_PDOUT3 22 +#define CCU40_IN3_P0_12 0 +#define CCU40_IN3_P0_3 2 +#define CCU40_IN3_P0_9 1 +#define CCU40_IN3_POSIF0_OUT0 28 +#define CCU40_IN3_POSIF0_OUT1 29 +#define CCU40_IN3_POSIF0_OUT3 4 +#define CCU40_IN3_POSIF0_OUT5 5 +#define CCU40_IN3_SCU_ACMP0_OUT 17 +#define CCU40_IN3_SCU_GSC40 8 +#define CCU40_IN3_VADC0_G0ARBCNT 6 +#define CCU41_IN0_BCCU0_OUT0 16 +#define CCU41_IN0_BCCU0_OUT6 25 +#define CCU41_IN0_CCU41_GP01 12 +#define CCU41_IN0_CCU41_SR0 27 +#define CCU41_IN0_CCU41_SR2 19 +#define CCU41_IN0_CCU41_ST0 20 +#define CCU41_IN0_CCU41_ST1 13 +#define CCU41_IN0_CCU41_ST2 14 +#define CCU41_IN0_CCU41_ST3 15 +#define CCU41_IN0_CCU81_ST3 7 +#define CCU41_IN0_ERU0_IOUT0 10 +#define CCU41_IN0_ERU0_PDOUT0 9 +#define CCU41_IN0_ERU0_PDOUT1 3 +#define CCU41_IN0_ERU1_IOUT0 23 +#define CCU41_IN0_ERU1_PDOUT0 22 +#define CCU41_IN0_ERU1_PDOUT1 24 +#define CCU41_IN0_P0_4 1 +#define CCU41_IN0_SCU_ACMP0_OUT 18 +#define CCU41_IN0_SCU_ACMP1_OUT 17 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 +#define CCU41_IN0_U1C0_DX2INS 28 +#define CCU41_IN1_BCCU0_OUT1 16 +#define CCU41_IN1_BCCU0_OUT3 25 +#define CCU41_IN1_CCU40_ST1 11 +#define CCU41_IN1_CCU41_GP02 12 +#define CCU41_IN1_CCU41_SR1 27 +#define CCU41_IN1_CCU41_SR2 19 +#define CCU41_IN1_CCU41_ST0 13 +#define CCU41_IN1_CCU41_ST1 20 +#define CCU41_IN1_CCU41_ST2 14 +#define CCU41_IN1_CCU41_ST3 15 +#define CCU41_IN1_ERU0_IOUT1 10 +#define CCU41_IN1_ERU0_PDOUT0 3 +#define CCU41_IN1_ERU0_PDOUT1 9 +#define CCU41_IN1_ERU1_IOUT1 23 +#define CCU41_IN1_ERU1_PDOUT0 24 +#define CCU41_IN1_ERU1_PDOUT1 22 +#define CCU41_IN1_P0_5 1 +#define CCU41_IN1_SCU_ACMP2_OUT 18 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 +#define CCU41_IN1_U1C1_DX2INS 28 +#define CCU41_IN2_BCCU0_OUT2 16 +#define CCU41_IN2_BCCU0_OUT7 25 +#define CCU41_IN2_CCU40_ST2 11 +#define CCU41_IN2_CCU41_GP03 12 +#define CCU41_IN2_CCU41_SR1 19 +#define CCU41_IN2_CCU41_SR2 27 +#define CCU41_IN2_CCU41_ST0 13 +#define CCU41_IN2_CCU41_ST1 14 +#define CCU41_IN2_CCU41_ST2 20 +#define CCU41_IN2_CCU41_ST3 15 +#define CCU41_IN2_ERU0_IOUT2 10 +#define CCU41_IN2_ERU0_PDOUT2 9 +#define CCU41_IN2_ERU0_PDOUT3 3 +#define CCU41_IN2_ERU1_IOUT2 23 +#define CCU41_IN2_ERU1_PDOUT2 22 +#define CCU41_IN2_ERU1_PDOUT3 24 +#define CCU41_IN2_P0_6 1 +#define CCU41_IN2_SCU_ACMP1_OUT 18 +#define CCU41_IN2_SCU_ACMP2_OUT 17 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 +#define CCU41_IN3_BCCU0_OUT5 16 +#define CCU41_IN3_BCCU0_OUT8 25 +#define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 +#define CCU41_IN3_CCU41_SR1 19 +#define CCU41_IN3_CCU41_SR3 27 +#define CCU41_IN3_CCU41_ST0 13 +#define CCU41_IN3_CCU41_ST1 14 +#define CCU41_IN3_CCU41_ST2 15 +#define CCU41_IN3_CCU41_ST3 20 +#define CCU41_IN3_CCU81_IGBTO 7 +#define CCU41_IN3_ERU0_IOUT3 10 +#define CCU41_IN3_ERU0_PDOUT2 3 +#define CCU41_IN3_ERU0_PDOUT3 9 +#define CCU41_IN3_ERU1_IOUT3 23 +#define CCU41_IN3_ERU1_PDOUT2 24 +#define CCU41_IN3_ERU1_PDOUT3 22 +#define CCU41_IN3_P0_7 1 +#define CCU41_IN3_SCU_ACMP0_OUT 17 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 +#define CCU41_IN3_VADC0_G0ARBCNT 6 +#endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) #define CCU40_IN0_BCCU0_OUT0 16 @@ -3469,7 +3713,8 @@ #define CCU41_IN0_POSIF1_OUT3 6 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -3496,7 +3741,8 @@ #define CCU41_IN1_POSIF1_OUT4 7 #define CCU41_IN1_SCU_ACMP2_OUT 18 #define CCU41_IN1_SCU_ACMP3_OUT 17 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -3524,10 +3770,12 @@ #define CCU41_IN2_POSIF1_OUT4 7 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 +#define CCU41_IN3_CCU41_GP00 12 #define CCU41_IN3_CCU41_SR1 19 #define CCU41_IN3_CCU41_SR3 27 #define CCU41_IN3_CCU41_ST0 13 @@ -3550,7 +3798,8 @@ #define CCU41_IN3_POSIF1_OUT5 5 #define CCU41_IN3_SCU_ACMP0_OUT 17 #define CCU41_IN3_SCU_ACMP3_OUT 18 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif @@ -3697,7 +3946,8 @@ #define CCU41_IN0_POSIF1_OUT3 6 #define CCU41_IN0_SCU_ACMP0_OUT 18 #define CCU41_IN0_SCU_ACMP1_OUT 17 -#define CCU41_IN0_SCU_GSC40 8 +#define CCU41_IN0_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN0_SCU_GSC41 */ +#define CCU41_IN0_SCU_GSC41 8 #define CCU41_IN0_U1C0_DX2INS 28 #define CCU41_IN1_BCCU0_OUT1 16 #define CCU41_IN1_BCCU0_OUT3 25 @@ -3726,7 +3976,8 @@ #define CCU41_IN1_POSIF1_OUT4 7 #define CCU41_IN1_SCU_ACMP2_OUT 18 #define CCU41_IN1_SCU_ACMP3_OUT 17 -#define CCU41_IN1_SCU_GSC40 8 +#define CCU41_IN1_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN1_SCU_GSC41 */ +#define CCU41_IN1_SCU_GSC41 8 #define CCU41_IN1_U1C1_DX2INS 28 #define CCU41_IN2_BCCU0_OUT2 16 #define CCU41_IN2_BCCU0_OUT7 25 @@ -3756,7 +4007,8 @@ #define CCU41_IN2_POSIF1_OUT4 7 #define CCU41_IN2_SCU_ACMP1_OUT 18 #define CCU41_IN2_SCU_ACMP2_OUT 17 -#define CCU41_IN2_SCU_GSC40 8 +#define CCU41_IN2_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN2_SCU_GSC41 */ +#define CCU41_IN2_SCU_GSC41 8 #define CCU41_IN3_BCCU0_OUT5 16 #define CCU41_IN3_BCCU0_OUT8 25 #define CCU41_IN3_CCU40_ST3 11 @@ -3784,7 +4036,8 @@ #define CCU41_IN3_POSIF1_OUT5 5 #define CCU41_IN3_SCU_ACMP0_OUT 17 #define CCU41_IN3_SCU_ACMP3_OUT 18 -#define CCU41_IN3_SCU_GSC40 8 +#define CCU41_IN3_SCU_GSC40 8 /**< @deprecated use instead CCU41_IN3_SCU_GSC41 */ +#define CCU41_IN3_SCU_GSC41 8 #define CCU41_IN3_VADC0_G0ARBCNT 6 #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h b/cores/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h index 404e5343..42acf5d9 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_ccu8_map.h @@ -1,43 +1,41 @@ /** * @file xmc1_ccu8_map.h - * @date 2015-08-25 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-08-25: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -830,7 +828,8 @@ #define CCU81_IN0_POSIF1_OUT5 4 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -855,7 +854,8 @@ #define CCU81_IN1_POSIF1_OUT5 4 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -880,7 +880,8 @@ #define CCU81_IN2_POSIF1_OUT5 4 #define CCU81_IN2_SCU_ACMP0_OUT 17 #define CCU81_IN2_SCU_ACMP3_OUT 18 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -905,7 +906,8 @@ #define CCU81_IN3_POSIF1_OUT5 4 #define CCU81_IN3_SCU_ACMP2_OUT 18 #define CCU81_IN3_SCU_ACMP3_OUT 17 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif @@ -1022,7 +1024,8 @@ #define CCU81_IN0_P0_12 20 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -1043,7 +1046,8 @@ #define CCU81_IN1_P0_13 20 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -1064,7 +1068,8 @@ #define CCU81_IN2_P0_10 1 #define CCU81_IN2_P0_14 20 #define CCU81_IN2_SCU_ACMP0_OUT 17 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -1084,7 +1089,8 @@ #define CCU81_IN3_ERU1_PDOUT3 21 #define CCU81_IN3_P0_15 20 #define CCU81_IN3_SCU_ACMP2_OUT 18 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif @@ -1207,7 +1213,8 @@ #define CCU81_IN0_POSIF1_OUT5 4 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -1231,7 +1238,8 @@ #define CCU81_IN1_POSIF1_OUT5 4 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -1256,7 +1264,8 @@ #define CCU81_IN2_POSIF1_OUT5 4 #define CCU81_IN2_SCU_ACMP0_OUT 17 #define CCU81_IN2_SCU_ACMP3_OUT 18 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -1280,7 +1289,8 @@ #define CCU81_IN3_POSIF1_OUT5 4 #define CCU81_IN3_SCU_ACMP2_OUT 18 #define CCU81_IN3_SCU_ACMP3_OUT 17 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif @@ -1407,7 +1417,8 @@ #define CCU81_IN0_POSIF1_OUT5 4 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -1432,7 +1443,8 @@ #define CCU81_IN1_POSIF1_OUT5 4 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -1457,7 +1469,8 @@ #define CCU81_IN2_POSIF1_OUT5 4 #define CCU81_IN2_SCU_ACMP0_OUT 17 #define CCU81_IN2_SCU_ACMP3_OUT 18 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -1482,7 +1495,8 @@ #define CCU81_IN3_POSIF1_OUT5 4 #define CCU81_IN3_SCU_ACMP2_OUT 18 #define CCU81_IN3_SCU_ACMP3_OUT 17 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif @@ -1599,7 +1613,8 @@ #define CCU81_IN0_P0_12 20 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -1620,7 +1635,8 @@ #define CCU81_IN1_P0_13 20 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -1641,7 +1657,8 @@ #define CCU81_IN2_P0_10 1 #define CCU81_IN2_P0_14 20 #define CCU81_IN2_SCU_ACMP0_OUT 17 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -1661,9 +1678,191 @@ #define CCU81_IN3_ERU1_PDOUT3 21 #define CCU81_IN3_P0_15 20 #define CCU81_IN3_SCU_ACMP2_OUT 18 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define CCU80_IN0_BCCU0_OUT0 8 +#define CCU80_IN0_BCCU0_OUT1 9 +#define CCU80_IN0_BCCU0_OUT2 16 +#define CCU80_IN0_CCU40_GP2 2 +#define CCU80_IN0_CCU40_SR2 10 +#define CCU80_IN0_CCU80_ST0 19 +#define CCU80_IN0_CCU80_ST1 13 +#define CCU80_IN0_CCU80_ST2 14 +#define CCU80_IN0_CCU80_ST3 15 +#define CCU80_IN0_CCU80_ST3B 24 +#define CCU80_IN0_CCU81_GP0 12 +#define CCU80_IN0_ERU0_IOUT0 6 +#define CCU80_IN0_ERU0_PDOUT0 5 +#define CCU80_IN0_ERU0_PDOUT1 11 +#define CCU80_IN0_ERU1_IOUT0 22 +#define CCU80_IN0_ERU1_PDOUT0 21 +#define CCU80_IN0_ERU1_PDOUT1 23 +#define CCU80_IN0_P0_12 0 +#define CCU80_IN0_P0_4 1 +#define CCU80_IN0_POSIF0_OUT2 3 +#define CCU80_IN0_POSIF0_OUT5 4 +#define CCU80_IN0_SCU_ACMP1_OUT 17 +#define CCU80_IN0_SCU_ACMP2_OUT 18 +#define CCU80_IN0_SCU_GSC80 7 +#define CCU80_IN1_BCCU0_OUT2 8 +#define CCU80_IN1_BCCU0_OUT3 9 +#define CCU80_IN1_BCCU0_OUT7 16 +#define CCU80_IN1_CCU40_SR2 10 +#define CCU80_IN1_CCU41_GP2 2 +#define CCU80_IN1_CCU80_ST0B 24 +#define CCU80_IN1_CCU80_ST1 19 +#define CCU80_IN1_CCU80_ST2 14 +#define CCU80_IN1_CCU80_ST3 15 +#define CCU80_IN1_CCU82_GP0 12 +#define CCU80_IN1_ERU0_IOUT1 6 +#define CCU80_IN1_ERU0_PDOUT0 11 +#define CCU80_IN1_ERU0_PDOUT1 5 +#define CCU80_IN1_ERU1_IOUT1 22 +#define CCU80_IN1_ERU1_PDOUT0 23 +#define CCU80_IN1_ERU1_PDOUT1 21 +#define CCU80_IN1_P0_12 0 +#define CCU80_IN1_P0_5 1 +#define CCU80_IN1_POSIF0_OUT2 3 +#define CCU80_IN1_POSIF0_OUT5 4 +#define CCU80_IN1_SCU_ACMP1_OUT 18 +#define CCU80_IN1_SCU_ACMP2_OUT 17 +#define CCU80_IN1_SCU_GSC80 7 +#define CCU80_IN2_BCCU0_OUT1 16 +#define CCU80_IN2_BCCU0_OUT4 8 +#define CCU80_IN2_BCCU0_OUT5 9 +#define CCU80_IN2_CCU40_SR3 10 +#define CCU80_IN2_CCU42_GP2 2 +#define CCU80_IN2_CCU80_ST0 13 +#define CCU80_IN2_CCU80_ST1B 24 +#define CCU80_IN2_CCU80_ST2 19 +#define CCU80_IN2_CCU80_ST3 15 +#define CCU80_IN2_CCU83_GP0 12 +#define CCU80_IN2_ERU0_IOUT2 6 +#define CCU80_IN2_ERU0_PDOUT0 11 +#define CCU80_IN2_ERU0_PDOUT2 5 +#define CCU80_IN2_ERU1_IOUT2 22 +#define CCU80_IN2_ERU1_PDOUT0 23 +#define CCU80_IN2_ERU1_PDOUT2 21 +#define CCU80_IN2_P0_10 1 +#define CCU80_IN2_P0_12 0 +#define CCU80_IN2_POSIF0_OUT2 3 +#define CCU80_IN2_POSIF0_OUT5 4 +#define CCU80_IN2_SCU_ACMP0_OUT 17 +#define CCU80_IN2_SCU_GSC80 7 +#define CCU80_IN3_BCCU0_OUT6 8 +#define CCU80_IN3_BCCU0_OUT7 9 +#define CCU80_IN3_BCCU0_OUT8 16 +#define CCU80_IN3_CCU40_SR3 10 +#define CCU80_IN3_CCU43_GP2 2 +#define CCU80_IN3_CCU80_GP0 12 +#define CCU80_IN3_CCU80_ST0 13 +#define CCU80_IN3_CCU80_ST1 14 +#define CCU80_IN3_CCU80_ST2 15 +#define CCU80_IN3_CCU80_ST2B 24 +#define CCU80_IN3_CCU80_ST3 19 +#define CCU80_IN3_ERU0_IOUT3 6 +#define CCU80_IN3_ERU0_PDOUT0 11 +#define CCU80_IN3_ERU0_PDOUT3 5 +#define CCU80_IN3_ERU1_IOUT3 22 +#define CCU80_IN3_ERU1_PDOUT0 23 +#define CCU80_IN3_ERU1_PDOUT3 21 +#define CCU80_IN3_P0_12 0 +#define CCU80_IN3_P0_13 1 +#define CCU80_IN3_POSIF0_OUT2 3 +#define CCU80_IN3_POSIF0_OUT5 4 +#define CCU80_IN3_SCU_ACMP0_OUT 18 +#define CCU80_IN3_SCU_GSC80 7 +#define CCU81_IN0_BCCU0_OUT0 8 +#define CCU81_IN0_BCCU0_OUT6 9 +#define CCU81_IN0_CCU40_GP2 2 +#define CCU81_IN0_CCU41_SR2 10 +#define CCU81_IN0_CCU81_GP0 12 +#define CCU81_IN0_CCU81_SR0 16 +#define CCU81_IN0_CCU81_ST0 19 +#define CCU81_IN0_CCU81_ST1 13 +#define CCU81_IN0_CCU81_ST2 14 +#define CCU81_IN0_CCU81_ST3 15 +#define CCU81_IN0_CCU81_ST3B 24 +#define CCU81_IN0_ERU0_IOUT0 6 +#define CCU81_IN0_ERU0_PDOUT0 5 +#define CCU81_IN0_ERU0_PDOUT1 11 +#define CCU81_IN0_ERU1_IOUT0 22 +#define CCU81_IN0_ERU1_PDOUT0 21 +#define CCU81_IN0_ERU1_PDOUT1 23 +#define CCU81_IN0_P0_12 20 +#define CCU81_IN0_SCU_ACMP0_OUT 18 +#define CCU81_IN0_SCU_ACMP1_OUT 17 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 +#define CCU81_IN1_BCCU0_OUT4 8 +#define CCU81_IN1_BCCU0_OUT7 9 +#define CCU81_IN1_CCU41_GP2 2 +#define CCU81_IN1_CCU41_SR2 10 +#define CCU81_IN1_CCU81_SR1 16 +#define CCU81_IN1_CCU81_ST0 13 +#define CCU81_IN1_CCU81_ST0B 24 +#define CCU81_IN1_CCU81_ST1 19 +#define CCU81_IN1_CCU81_ST2 14 +#define CCU81_IN1_CCU81_ST3 15 +#define CCU81_IN1_CCU82_GP0 12 +#define CCU81_IN1_ERU0_IOUT1 6 +#define CCU81_IN1_ERU0_PDOUT0 11 +#define CCU81_IN1_ERU0_PDOUT1 5 +#define CCU81_IN1_ERU1_IOUT1 22 +#define CCU81_IN1_ERU1_PDOUT0 23 +#define CCU81_IN1_ERU1_PDOUT1 21 +#define CCU81_IN1_P0_13 20 +#define CCU81_IN1_SCU_ACMP1_OUT 18 +#define CCU81_IN1_SCU_ACMP2_OUT 17 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 +#define CCU81_IN2_BCCU0_OUT1 9 +#define CCU81_IN2_BCCU0_OUT5 8 +#define CCU81_IN2_CCU41_SR3 10 +#define CCU81_IN2_CCU42_GP2 2 +#define CCU81_IN2_CCU81_SR2 16 +#define CCU81_IN2_CCU81_ST0 13 +#define CCU81_IN2_CCU81_ST1 14 +#define CCU81_IN2_CCU81_ST1B 24 +#define CCU81_IN2_CCU81_ST2 19 +#define CCU81_IN2_CCU81_ST3 15 +#define CCU81_IN2_CCU83_GP0 12 +#define CCU81_IN2_ERU0_IOUT2 6 +#define CCU81_IN2_ERU0_PDOUT0 11 +#define CCU81_IN2_ERU0_PDOUT2 5 +#define CCU81_IN2_ERU1_IOUT2 22 +#define CCU81_IN2_ERU1_PDOUT0 23 +#define CCU81_IN2_ERU1_PDOUT2 21 +#define CCU81_IN2_P0_10 1 +#define CCU81_IN2_P0_14 20 +#define CCU81_IN2_SCU_ACMP0_OUT 17 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 +#define CCU81_IN3_BCCU0_OUT2 9 +#define CCU81_IN3_BCCU0_OUT8 8 +#define CCU81_IN3_CCU41_SR3 10 +#define CCU81_IN3_CCU43_GP2 2 +#define CCU81_IN3_CCU80_GP0 12 +#define CCU81_IN3_CCU81_SR3 16 +#define CCU81_IN3_CCU81_ST0 13 +#define CCU81_IN3_CCU81_ST1 14 +#define CCU81_IN3_CCU81_ST2 15 +#define CCU81_IN3_CCU81_ST2B 24 +#define CCU81_IN3_CCU81_ST3 19 +#define CCU81_IN3_ERU0_IOUT3 6 +#define CCU81_IN3_ERU0_PDOUT0 11 +#define CCU81_IN3_ERU0_PDOUT3 5 +#define CCU81_IN3_ERU1_IOUT3 22 +#define CCU81_IN3_ERU1_PDOUT0 23 +#define CCU81_IN3_ERU1_PDOUT3 21 +#define CCU81_IN3_P0_15 20 +#define CCU81_IN3_SCU_ACMP2_OUT 18 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 +#endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64) #define CCU80_IN0_BCCU0_OUT0 8 @@ -1788,7 +1987,8 @@ #define CCU81_IN0_POSIF1_OUT5 4 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -1813,7 +2013,8 @@ #define CCU81_IN1_POSIF1_OUT5 4 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -1838,7 +2039,8 @@ #define CCU81_IN2_POSIF1_OUT5 4 #define CCU81_IN2_SCU_ACMP0_OUT 17 #define CCU81_IN2_SCU_ACMP3_OUT 18 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -1863,7 +2065,8 @@ #define CCU81_IN3_POSIF1_OUT5 4 #define CCU81_IN3_SCU_ACMP2_OUT 18 #define CCU81_IN3_SCU_ACMP3_OUT 17 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif @@ -1986,7 +2189,8 @@ #define CCU81_IN0_POSIF1_OUT5 4 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -2010,7 +2214,8 @@ #define CCU81_IN1_POSIF1_OUT5 4 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -2035,7 +2240,8 @@ #define CCU81_IN2_POSIF1_OUT5 4 #define CCU81_IN2_SCU_ACMP0_OUT 17 #define CCU81_IN2_SCU_ACMP3_OUT 18 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -2059,7 +2265,8 @@ #define CCU81_IN3_POSIF1_OUT5 4 #define CCU81_IN3_SCU_ACMP2_OUT 18 #define CCU81_IN3_SCU_ACMP3_OUT 17 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif @@ -2186,7 +2393,8 @@ #define CCU81_IN0_POSIF1_OUT5 4 #define CCU81_IN0_SCU_ACMP0_OUT 18 #define CCU81_IN0_SCU_ACMP1_OUT 17 -#define CCU81_IN0_SCU_GSC80 7 +#define CCU81_IN0_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN0_SCU_GSC81 */ +#define CCU81_IN0_SCU_GSC81 7 #define CCU81_IN1_BCCU0_OUT4 8 #define CCU81_IN1_BCCU0_OUT7 9 #define CCU81_IN1_CCU41_GP2 2 @@ -2211,7 +2419,8 @@ #define CCU81_IN1_POSIF1_OUT5 4 #define CCU81_IN1_SCU_ACMP1_OUT 18 #define CCU81_IN1_SCU_ACMP2_OUT 17 -#define CCU81_IN1_SCU_GSC80 7 +#define CCU81_IN1_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN1_SCU_GSC81 */ +#define CCU81_IN1_SCU_GSC81 7 #define CCU81_IN2_BCCU0_OUT1 9 #define CCU81_IN2_BCCU0_OUT5 8 #define CCU81_IN2_CCU41_SR3 10 @@ -2236,7 +2445,8 @@ #define CCU81_IN2_POSIF1_OUT5 4 #define CCU81_IN2_SCU_ACMP0_OUT 17 #define CCU81_IN2_SCU_ACMP3_OUT 18 -#define CCU81_IN2_SCU_GSC80 7 +#define CCU81_IN2_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN2_SCU_GSC81 */ +#define CCU81_IN2_SCU_GSC81 7 #define CCU81_IN3_BCCU0_OUT2 9 #define CCU81_IN3_BCCU0_OUT8 8 #define CCU81_IN3_CCU41_SR3 10 @@ -2261,7 +2471,8 @@ #define CCU81_IN3_POSIF1_OUT5 4 #define CCU81_IN3_SCU_ACMP2_OUT 18 #define CCU81_IN3_SCU_ACMP3_OUT 17 -#define CCU81_IN3_SCU_GSC80 7 +#define CCU81_IN3_SCU_GSC80 7 /**< @deprecated use instead CCU81_IN3_SCU_GSC81 */ +#define CCU81_IN3_SCU_GSC81 7 #endif #endif /* XMC1_CCU8_MAP_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_eru_map.h b/cores/xmc_lib/XMCLib/inc/xmc1_eru_map.h index 8cbc6249..23ce12a2 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_eru_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_eru_map.h @@ -1,49 +1,45 @@ /** - * @file xmc1_eru_map.h - * @date 2015-08-25 - * - * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial version - * - * 2015-08-25: - * - Added support for XMC1400 devices - * - * @endcond - */ + * @file xmc1_eru_map.h + * + * @cond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond + */ + #ifndef XMC1_ERU_MAP_H #define XMC1_ERU_MAP_H @@ -65,13 +61,13 @@ #define ERU1_ETL1 XMC_ERU1, 1 #define ERU1_ETL2 XMC_ERU1, 2 #define ERU1_ETL3 XMC_ERU1, 3 - + #define ERU1_OGU0 XMC_ERU1, 0 #define ERU1_OGU1 XMC_ERU1, 1 #define ERU1_OGU2 XMC_ERU1, 2 #define ERU1_OGU3 XMC_ERU1, 3 #endif - + #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN24) #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 @@ -1709,6 +1705,80 @@ #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3 +#define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2 +#define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1 +#define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3 +#define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2 +#define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1 +#define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0 +#define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL0_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL0_INPUTB_CCU40_ST0 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL0_INPUTB_CCU41_ST0 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL0_INPUTB_CCU80_ST0 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL0_INPUTB_CCU81_ST0 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL1_INPUTB_CCU40_ST1 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL1_INPUTB_CCU41_ST1 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL1_INPUTB_CCU80_ST3 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL1_INPUTB_CCU81_ST3 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL2_INPUTB_CCU40_ST2 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL2_INPUTB_CCU41_ST2 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL2_INPUTB_CCU80_ST1 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL2_INPUTB_CCU81_ST1 XMC_ERU_ETL_INPUT_B3 +#define ERU1_ETL3_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 +#define ERU1_ETL3_INPUTB_CCU40_ST3 XMC_ERU_ETL_INPUT_B0 +#define ERU1_ETL3_INPUTB_CCU41_ST3 XMC_ERU_ETL_INPUT_B1 +#define ERU1_ETL3_INPUTB_CCU80_ST2 XMC_ERU_ETL_INPUT_B2 +#define ERU1_ETL3_INPUTB_CCU81_ST2 XMC_ERU_ETL_INPUT_B3 + +#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU41_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU0_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU41_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU1_PERIPHERAL_TRIGGER_CCU81_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU41_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU2_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 +#define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 +#endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0 @@ -1890,5 +1960,5 @@ #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU41_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1 #define ERU1_OGU3_PERIPHERAL_TRIGGER_CCU81_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3 #endif - + #endif /* XMC1_ERU_MAP_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_flash.h b/cores/xmc_lib/XMCLib/inc/xmc1_flash.h index 1effd8ba..5ebf60d4 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_flash.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_flash.h @@ -1,49 +1,43 @@ /** * @file xmc1_flash.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2014-12-10: - * - Initial
- * 2015-02-20: - * - Updated for Documentation related changes
- * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -58,12 +52,8 @@ #if UC_FAMILY == XMC1 -#include +#include "XMC1000_RomFunctionTable.h" -/** -* @addtogroup XMClib XMC Peripheral Library -* @{ -*/ /** * @addtogroup FLASH @@ -106,14 +96,14 @@ typedef enum XMC_FLASH_STATUS { XMC_FLASH_STATUS_OK = 0U, /**< Flash related operation was successfully completed*/ - XMC_FLASH_STATUS_BUSY = NVM_NVMSTATUS_BUSY_Msk , /**< Cannot execute the flash request because + XMC_FLASH_STATUS_BUSY = NVM_NVMSTATUS_BUSY_Msk, /**< Cannot execute the flash request because another operation is in progress*/ - XMC_FLASH_STATUS_SLEEP_MODE = NVM_NVMSTATUS_SLEEP_Msk , /**< Flash is in sleep mode*/ - XMC_FLASH_STATUS_VERIFY_ERROR = NVM_NVMSTATUS_VERR_Msk , /**< Flash reported a verification failure*/ + XMC_FLASH_STATUS_SLEEP_MODE = NVM_NVMSTATUS_SLEEP_Msk, /**< Flash is in sleep mode*/ + XMC_FLASH_STATUS_VERIFY_ERROR = NVM_NVMSTATUS_VERR_Msk, /**< Flash reported a verification failure*/ XMC_FLASH_STATUS_ECC1_READ_ERROR = NVM_NVMSTATUS_ECC1READ_Msk, /**< Flash reports a single bit failure, and it is automatically corrected.*/ XMC_FLASH_STATUS_ECC2_READ_ERROR = NVM_NVMSTATUS_ECC2READ_Msk, /**< Flash reported at least two bit failure*/ - XMC_FLASH_STATUS_WRITE_PROTOCOL_ERROR = NVM_NVMSTATUS_WRPERR_Msk , /**< Write/Verify operation on a block is + XMC_FLASH_STATUS_WRITE_PROTOCOL_ERROR = NVM_NVMSTATUS_WRPERR_Msk, /**< Write/Verify operation on a block is failed due to protocol violations or write protected sectors*/ } XMC_FLASH_STATUS_t; @@ -146,12 +136,51 @@ typedef enum XMC_FLASH_HARDREAD_LEVEL extern "C" { #endif +/** + * + * @param address Pointer to the starting address of flash page from where the programming starts. + * @param data Pointer to the source address where targeted data is located. + * + * @return Status of operation (NVM_STATUS) + * + * \parDescription:
+ * Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one + * page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr) + * to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines + * (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation. + * + * \parNote:
+ * Flash will be busy state during write is ongoing, hence no operations allowed until it completes. + * + * \parRelated APIs:
+ * None + * + */ +int32_t XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data); + +/** + * + * @param address Pointer to the starting address of the page to be erased. + * + * @return Status of operation (NVM_STATUS) + * + * \parDescription:
+ * Erases a complete sector starting from the \a address specified.\n\n XMC1000 Flash can be erased with granularity + * of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls XMC_FLASH_ErasePages API 16 + * times starting from the first page of the sector.. Call XMC_FLASH_GetStatus() API after calling this API, + * to verify the erase operation.\n + * + * \parRelated APIs:
+ * XMC_FLASH_ErasePages() \n\n\n + */ +int32_t XMC_FLASH_EraseSector(uint32_t *address); + /** * * @param address Pointer to the starting address of the flash page from where the erase starts * @param num_pages Number of pages to be erased.
Range: [1 to (flash size / 256)] * - * @return None + * @return Status of operation (NVM_STATUS) * * \parDescription:
* Erases a set of flash memory pages.

@@ -168,10 +197,10 @@ extern "C" { * XMC_FLASH_EraseSector(), XMC_FLASH_ErasePage() \n\n\n * * \parRelated APIs:
- * None - * + * None + * */ -void XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages); +int32_t XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages); /** * @@ -191,8 +220,8 @@ void XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages); * Flash will be busy state during write is ongoing, hence no operations allowed until it completes. * * \parRelated APIs:
- * None - * + * None + * */ void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num_blocks, bool verify); @@ -212,8 +241,8 @@ void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num * validates the result of verification. * * \parRelated APIs:
- * None - * + * None + * */ void XMC_FLASH_VerifyBlocks(uint32_t *address, const uint32_t *data, uint32_t num_blocks); @@ -232,8 +261,8 @@ void XMC_FLASH_VerifyBlocks(uint32_t *address, const uint32_t *data, uint32_t nu * verifies the read operation. * * \parRelated APIs:
- * None - * + * None + * */ void XMC_FLASH_ReadBlocks(uint32_t *address, uint32_t *data, uint32_t num_blocks); @@ -250,7 +279,7 @@ void XMC_FLASH_ReadBlocks(uint32_t *address, uint32_t *data, uint32_t num_blocks * API returns the read status. * * \parRelated APIs:
- * XMC_FLASH_ReadBlocks() + * XMC_FLASH_ReadBlocks() * */ __STATIC_INLINE uint32_t XMC_FLASH_ReadWord(const uint32_t *const address) @@ -262,7 +291,7 @@ __STATIC_INLINE uint32_t XMC_FLASH_ReadWord(const uint32_t *const address) * * @param address Pointer to the starting address of the page to be erased * - * @return None + * @return Status of operation (NVM_STATUS) * * \parDescription:
* Erases a single flash page associated to the specified \a address.\n\n XMC1000 Flash can be erased with granularity @@ -274,14 +303,14 @@ __STATIC_INLINE uint32_t XMC_FLASH_ReadWord(const uint32_t *const address) * \parRelated APIs:
* XMC_FLASH_ErasePages() \n\n\n */ -void XMC_FLASH_ErasePage(uint32_t *address); +int32_t XMC_FLASH_ErasePage(uint32_t *address); /** * * @param address Pointer to the starting address of flash page from where the programming starts. * @param data Pointer to the source address where targeted data blocks are located. * - * @return None + * @return Status of operation (NVM_STATUS) * * \parDescription:
* Erases, programs and verifies a single flash page starting from the \a address specified.\n\n XMC1000 Flash can be @@ -291,10 +320,10 @@ void XMC_FLASH_ErasePage(uint32_t *address); * calling this API, to verify the erase operation. * * \parRelated APIs:
- * None - * + * None + * */ -void XMC_FLASH_ProgramVerifyPage(uint32_t *address, const uint32_t *data); +int32_t XMC_FLASH_ProgramVerifyPage(uint32_t *address, const uint32_t *data); /** * @@ -346,7 +375,7 @@ __STATIC_INLINE void XMC_FLASH_ExitSleepMode(void) * Finds the starting address of the specified \a sector number.\n\n * * \parRelated APIs:
- * None + * None * */ __STATIC_INLINE uint32_t XMC_FLASH_GetSectorAddress(uint32_t sector) @@ -356,7 +385,7 @@ __STATIC_INLINE uint32_t XMC_FLASH_GetSectorAddress(uint32_t sector) /** - * + * * @param num_sectors Number of sectors to be protected
Range: [0 to 51] * * @return None @@ -367,7 +396,7 @@ __STATIC_INLINE uint32_t XMC_FLASH_GetSectorAddress(uint32_t sector) * this API at runtime with a different value of \a num_sectors.\n\n * * \parRelated APIs:
- * None + * None * */ __STATIC_INLINE void XMC_FLASH_SetSectorProtection(uint32_t num_sectors) @@ -378,7 +407,7 @@ __STATIC_INLINE void XMC_FLASH_SetSectorProtection(uint32_t num_sectors) /** - * + * * @param level Hard read levels specified in \a XMC_FLASH_HARDREAD_LEVEL_t. * * @return None @@ -389,23 +418,19 @@ __STATIC_INLINE void XMC_FLASH_SetSectorProtection(uint32_t num_sectors) * value. This hardread level is used until the end of the verification sequence and, may not be changed in between.\n\n * * \parRelated APIs:
- * None + * None * */ __STATIC_INLINE void XMC_FLASH_SetHardReadLevel(XMC_FLASH_HARDREAD_LEVEL_t level) { NVM->NVMCONF &= (uint16_t)(~(uint16_t)NVM_NVMCONF_HRLEV_Msk); - NVM->NVMCONF |= (uint16_t)(level<< (uint16_t)NVM_NVMCONF_HRLEV_Pos); + NVM->NVMCONF |= (uint16_t)(level << (uint16_t)NVM_NVMCONF_HRLEV_Pos); } #ifdef __cplusplus } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_gpio.h b/cores/xmc_lib/XMCLib/inc/xmc1_gpio.h index e242b5ec..53f478e2 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_gpio.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_gpio.h @@ -1,48 +1,44 @@ /** * @file xmc1_gpio.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
- * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond + * */ #ifndef XMC1_GPIO_H @@ -58,11 +54,6 @@ #include "xmc1_gpio_map.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - /** * @addtogroup GPIO * @{ @@ -114,13 +105,12 @@ XMC_GPIO_CHECK_PORT4(port)) #define XMC_GPIO_CHECK_OUTPUT_PORT(port) XMC_GPIO_CHECK_PORT(port) - + #define XMC_GPIO_CHECK_ANALOG_PORT(port) (port == XMC_GPIO_PORT2) - + #define XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis) ((hysteresis == XMC_GPIO_INPUT_HYSTERESIS_STANDARD) || \ (hysteresis == XMC_GPIO_INPUT_HYSTERESIS_LARGE)) - /********************************************************************************************************************** * ENUMS *********************************************************************************************************************/ @@ -147,10 +137,10 @@ typedef enum XMC_GPIO_MODE XMC_GPIO_MODE_OUTPUT_ALT5 = 0x5UL << PORT_IOCR_PC_Pos, XMC_GPIO_MODE_OUTPUT_ALT6 = 0x6UL << PORT_IOCR_PC_Pos, XMC_GPIO_MODE_OUTPUT_ALT7 = 0x7UL << PORT_IOCR_PC_Pos, -#if (UC_SERIES == XMC14) +#if (UC_SERIES == XMC14) XMC_GPIO_MODE_OUTPUT_ALT8 = 0x8UL << PORT_IOCR_PC_Pos, XMC_GPIO_MODE_OUTPUT_ALT9 = 0x9UL << PORT_IOCR_PC_Pos, -#endif +#endif XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Push-pull alternate output function 1 */ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Push-pull alternate output function 2 */ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Push-pull alternate output function 3 */ @@ -158,7 +148,7 @@ typedef enum XMC_GPIO_MODE XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT5 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT5, /**< Push-pull alternate output function 5 */ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT6, /**< Push-pull alternate output function 6 */ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT7, /**< Push-pull alternate output function 7 */ -#if (UC_SERIES == XMC14) +#if (UC_SERIES == XMC14) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT8, /**< Push-pull alternate output function 8 */ XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT9, /**< Push-pull alternate output function 9 */ #endif @@ -169,21 +159,21 @@ typedef enum XMC_GPIO_MODE XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT5, /**< Open drain alternate output function 5 */ XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT6, /**< Open drain alternate output function 6 */ XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT7, /**< Open drain alternate output function 7 */ -#if (UC_SERIES == XMC14) +#if (UC_SERIES == XMC14) XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT8 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT8, /**< Open drain alternate output function 8 */ XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT9 /**< Open drain alternate output function 9 */ #endif } XMC_GPIO_MODE_t; /** - * Configures input hysteresis mode of pin. Use type \a XMC_GPIO_INPUT_HYSTERESIS_t for this - * enum. Selecting the appropriate pad hysteresis allows optimized pad oscillation behaviour + * Configures input hysteresis mode of pin. Use type \a XMC_GPIO_INPUT_HYSTERESIS_t for this enum. + * Selecting the appropriate pad hysteresis allows optimized pad oscillation behavior * for touch-sensing applications. */ typedef enum XMC_GPIO_INPUT_HYSTERESIS { - XMC_GPIO_INPUT_HYSTERESIS_STANDARD = 0x0, /**< Standard hysteresis */ - XMC_GPIO_INPUT_HYSTERESIS_LARGE = 0x4 /**< Large hysteresis */ + XMC_GPIO_INPUT_HYSTERESIS_STANDARD = 0x0U, /**< Standard hysteresis */ + XMC_GPIO_INPUT_HYSTERESIS_LARGE = 0x4U /**< Large hysteresis */ } XMC_GPIO_INPUT_HYSTERESIS_t; @@ -193,7 +183,8 @@ typedef enum XMC_GPIO_INPUT_HYSTERESIS /** * Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure. */ -typedef struct XMC_GPIO_PORT { +typedef struct XMC_GPIO_PORT +{ __IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output */ __O uint32_t OMR; /**< The port output modification register contains control bits that make it @@ -221,11 +212,10 @@ typedef struct XMC_GPIO_PORT { typedef struct XMC_GPIO_CONFIG { XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */ - XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */ XMC_GPIO_INPUT_HYSTERESIS_t input_hysteresis; /**< Defines input pad hysteresis of a pin */ + XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */ } XMC_GPIO_CONFIG_t; - /********************************************************************************************************************** * API PROTOTYPES *********************************************************************************************************************/ @@ -250,7 +240,7 @@ __STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) #if (UC_SERIES == XMC14) (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8) || (mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9) || -#endif +#endif (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) || (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) || (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) || @@ -258,12 +248,12 @@ __STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4) || (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT5) || (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6) || - (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7) + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7) #if (UC_SERIES == XMC14) || (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT8) || - (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9) -#endif - ); + (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT9) +#endif + ); } @@ -285,19 +275,19 @@ __STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) * * \parNote:
* Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). + * */ -void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, - const uint8_t pin, + +void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, + const uint8_t pin, const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis); /** * @} (end addtogroup GPIO) */ -/** - * @} (end addtogroup XMClib) - */ #endif /* UC_FAMILY == XMC1 */ #endif /* XMC1_GPIO_H */ + diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_gpio_map.h b/cores/xmc_lib/XMCLib/inc/xmc1_gpio_map.h index cf2079d5..fd4d9cfa 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_gpio_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_gpio_map.h @@ -1,58 +1,41 @@ /** * @file xmc1_gpio_map.h - * @date 2016-08-22 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft - * - * 2015-06-20: - * - Updated copyright information + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-08-25: - * - Added XMC1400 + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-03-09: - * - Fixed VADC_EMUX signals - * - Added P1_6_AF_BCCU0_OUT2 for (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN40) - * - Added HWCTRL_U1C0_DOUTx for XMC14xx + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-08-22: - * - Added P1_5_AF_U0C0_DOUT0 for XMC14xx - * - Add missing P4_5_AF_BCCU0_OUT8 for XMC1402/04 64/48 pins package + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -6192,6 +6175,225 @@ #define P4_11_HWCTRL_LEDTS2_TSIN7 XMC_GPIO_HWCTRL_PERIPHERAL1 #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define P0_0 XMC_GPIO_PORT0, 0 +#define P0_1 XMC_GPIO_PORT0, 1 +#define P0_2 XMC_GPIO_PORT0, 2 +#define P0_3 XMC_GPIO_PORT0, 3 +#define P0_4 XMC_GPIO_PORT0, 4 +#define P0_5 XMC_GPIO_PORT0, 5 +#define P0_6 XMC_GPIO_PORT0, 6 +#define P0_7 XMC_GPIO_PORT0, 7 +#define P0_8 XMC_GPIO_PORT0, 8 +#define P0_9 XMC_GPIO_PORT0, 9 +#define P0_10 XMC_GPIO_PORT0, 10 +#define P0_11 XMC_GPIO_PORT0, 11 +#define P0_12 XMC_GPIO_PORT0, 12 +#define P0_13 XMC_GPIO_PORT0, 13 +#define P0_14 XMC_GPIO_PORT0, 14 +#define P0_15 XMC_GPIO_PORT0, 15 +#define P1_0 XMC_GPIO_PORT1, 0 +#define P1_1 XMC_GPIO_PORT1, 1 +#define P1_2 XMC_GPIO_PORT1, 2 +#define P1_3 XMC_GPIO_PORT1, 3 +#define P1_4 XMC_GPIO_PORT1, 4 +#define P1_5 XMC_GPIO_PORT1, 5 +#define P1_6 XMC_GPIO_PORT1, 6 +#define P2_0 XMC_GPIO_PORT2, 0 +#define P2_1 XMC_GPIO_PORT2, 1 +#define P2_2 XMC_GPIO_PORT2, 2 +#define P2_3 XMC_GPIO_PORT2, 3 +#define P2_4 XMC_GPIO_PORT2, 4 +#define P2_5 XMC_GPIO_PORT2, 5 +#define P2_6 XMC_GPIO_PORT2, 6 +#define P2_7 XMC_GPIO_PORT2, 7 +#define P2_8 XMC_GPIO_PORT2, 8 +#define P2_9 XMC_GPIO_PORT2, 9 +#define P2_10 XMC_GPIO_PORT2, 10 +#define P2_11 XMC_GPIO_PORT2, 11 + + +/* Alternate Output Function */ +#define P0_0_AF_ERU0_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_0_AF_ERU0_GOUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_0_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_0_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_0_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_0_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_0_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_0_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_1_AF_ERU0_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_1_AF_ERU0_GOUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_1_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_1_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_1_AF_BCCU0_OUT8 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_1_AF_SCU_VDROP XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_1_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_1_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_2_AF_ERU0_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_2_AF_ERU0_GOUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_2_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_2_AF_CCU80_OUT02 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_2_AF_VADC_EMUX02 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_2_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_2_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_2_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_3_AF_ERU0_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_3_AF_ERU0_GOUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P0_3_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_3_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_3_AF_VADC_EMUX01 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_3_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_3_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_3_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_4_AF_BCCU0_OUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_4_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_4_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_4_AF_VADC_EMUX00 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_4_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_4_AF_U1C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_5_AF_BCCU0_OUT1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_5_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_5_AF_CCU80_OUT12 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_5_AF_ACMP2_OUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_5_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_5_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_6_AF_BCCU0_OUT2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_6_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_6_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_6_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_6_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_6_AF_VADC_EMUX11 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_6_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_7_AF_BCCU0_OUT3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_7_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_7_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_7_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_7_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_7_AF_VADC_EMUX12 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_7_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_8_AF_BCCU0_OUT4 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_8_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_8_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_8_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_8_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_8_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_8_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_9_AF_BCCU0_OUT5 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_9_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_9_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_9_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_9_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_9_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_9_AF_CCU41_OUT3 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P0_10_AF_BCCU0_OUT6 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_10_AF_ACMP0_OUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_10_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_10_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_10_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_10_AF_CCU81_OUT22 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_11_AF_BCCU0_OUT7 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_11_AF_U0C0_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P0_11_AF_CCU80_OUT23 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_11_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_11_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_11_AF_CCU81_OUT23 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P0_12_AF_BCCU0_OUT6 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_12_AF_CCU80_OUT33 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_12_AF_U0C0_SELO3 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_12_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_13_AF_WDT_REQUEST XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_13_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_13_AF_U0C0_SELO4 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_13_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_14_AF_BCCU0_OUT7 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_14_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_14_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_14_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT7 +#define P0_15_AF_BCCU0_OUT8 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P0_15_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P0_15_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P0_15_AF_U0C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_0_AF_BCCU0_OUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_0_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_0_AF_CCU80_OUT00 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_0_AF_ACMP1_OUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_0_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_0_AF_CCU81_OUT00 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_1_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_1_AF_CCU80_OUT01 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_1_AF_CCU81_OUT01 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_2_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_2_AF_CCU80_OUT10 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_2_AF_ACMP2_OUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_2_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_2_AF_CCU81_OUT10 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_3_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_3_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_3_AF_CCU80_OUT11 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_3_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_3_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_3_AF_CCU81_OUT11 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_4_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_4_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_4_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_4_AF_U0C0_SELO0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_4_AF_U0C1_SELO1 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_4_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_4_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P1_5_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_5_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_5_AF_BCCU0_OUT1 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_5_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_5_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_5_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_5_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_5_AF_CCU41_OUT1 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P1_6_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_6_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 +#define P1_6_AF_BCCU0_OUT2 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P1_6_AF_U0C0_SELO2 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P1_6_AF_U0C1_SELO3 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P1_6_AF_CCU81_OUT30 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P1_6_AF_CCU41_OUT2 XMC_GPIO_MODE_OUTPUT_ALT9 +#define P2_0_AF_ERU0_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_0_AF_CCU40_OUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_0_AF_ERU0_GOUT3 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_0_AF_CCU80_OUT20 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P2_0_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P2_0_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT7 +#define P2_0_AF_CCU81_OUT20 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P2_1_AF_ERU0_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_1_AF_CCU40_OUT1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_1_AF_ERU0_GOUT2 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_1_AF_CCU80_OUT21 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P2_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT6 +#define P2_1_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT7 +#define P2_1_AF_CCU81_OUT21 XMC_GPIO_MODE_OUTPUT_ALT8 +#define P2_10_AF_ERU0_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_CCU40_OUT2 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_10_AF_ERU0_GOUT1 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_10_AF_CCU80_OUT30 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P2_10_AF_ACMP0_OUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P2_10_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 +#define P2_11_AF_ERU0_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_11_AF_CCU40_OUT3 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P2_11_AF_ERU0_GOUT0 XMC_GPIO_MODE_OUTPUT_ALT3 +#define P2_11_AF_CCU80_OUT31 XMC_GPIO_MODE_OUTPUT_ALT5 +#define P2_11_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT6 +#define P2_11_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT7 + +/* HW control options */ +#define P1_0_HWCTRL_U0C0_DOUT0 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_1_HWCTRL_U0C0_DOUT1 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_2_HWCTRL_U0C0_DOUT2 XMC_GPIO_HWCTRL_PERIPHERAL2 +#define P1_3_HWCTRL_U0C0_DOUT3 XMC_GPIO_HWCTRL_PERIPHERAL2 +#endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) #define P0_0 XMC_GPIO_PORT0, 0 diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_rtc.h b/cores/xmc_lib/XMCLib/inc/xmc1_rtc.h index 5d74507a..08c2e9ee 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_rtc.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_rtc.h @@ -1,64 +1,55 @@ /** * @file xmc1_rtc.h - * @date 2015-05-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version - * - * 2015-05-20: - * - Documentation updates
- * - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ #ifndef XMC1_RTC_H #define XMC1_RTC_H -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup RTC * @{ */ - + /********************************************************************************************************************* * ENUMS *********************************************************************************************************************/ @@ -69,7 +60,7 @@ typedef enum XMC_RTC_DEBUG_MODE { XMC_RTC_RUN_IN_DEBUG_MODE = 0U, /**< RTC is not stopped during halting mode debug */ - XMC_RTC_STOP_IN_DEBUG_MODE = 1U /**< RTC is stopped during halting mode debug */ + XMC_RTC_STOP_IN_DEBUG_MODE = 1U /**< RTC is stopped during halting mode debug */ } XMC_RTC_DEBUG_MODE_t; /********************************************************************************************************************* @@ -81,16 +72,16 @@ extern "C" { #endif /** - * @param debug_mode Debug mode value containing in (::XMC_RTC_DEBUG_MODE_t) to be set + * @param debug_mode Debug mode value containing in (::XMC_RTC_DEBUG_MODE_t) to be set * @return None * * \parDescription:
* Configures the RTC into running or stopping mode during halting mode debug
* * \par - * The function sets the CTR.SUS bitfield to configure the RTC into running + * The function sets the CTR.SUS bitfield to configure the RTC into running * or stopping mode during halting mode debug. - */ + */ void XMC_RTC_SetDebugMode(const XMC_RTC_DEBUG_MODE_t debug_mode); #ifdef __cplusplus @@ -101,8 +92,5 @@ void XMC_RTC_SetDebugMode(const XMC_RTC_DEBUG_MODE_t debug_mode); * @} */ -/** - * @} - */ - + #endif /* XMC1_RTC_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_scu.h b/cores/xmc_lib/XMCLib/inc/xmc1_scu.h index 9ada6734..b0f9cd2c 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_scu.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_scu.h @@ -1,70 +1,42 @@ /** * @file xmc1_scu.h - * @date 2017-08-03 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2023, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial - * - * 2015-05-20: - * - Description updated
- * - * 2015-06-20: - * - XMC_SCU_INTERRUPT_EVENT enum elements are typecasted to int64_t - * - * 2015-06-20: - * - Added support for XMC1400 - * - * 2015-11-30: - * - Documentation improved - * - * 2015-12-09: - * - Added XMC_SCU_EnablePrefetchUnit and XMC_SCU_DisablePrefetchUnit - * - * 2016-03-09: - * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor - * - * 2017-03-28: - * - Fixed prescaler formula comments for XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration() - * - Added XMC_SCU_SetBMI() - * - * 2017-08-03: - * - Removed unused XMC_SCU_CLOCK_DEEP_SLEEP_t - * - Added XMC_SCU_CLOCK_EnableFlashPowerDown() and XMC_SCU_CLOCK_DisableFlashPowerDown() - * * @endcond * */ @@ -79,10 +51,6 @@ #if UC_FAMILY == XMC1 -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup SCU @@ -137,7 +105,7 @@ #define XMC_SCU_INTERRUPT_EVENT_TSE_DONE SCU_INTERRUPT_SRMSK_TSE_DONE_Msk /**< Temperature measurement Completion event. */ #define XMC_SCU_INTERRUPT_EVENT_TSE_HIGH SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk /**< Temperature too high event. */ #define XMC_SCU_INTERRUPT_EVENT_TSE_LOW SCU_INTERRUPT_SRMSK_TSE_LOW_Msk /**< Temperature too low event. */ -#if defined(CAN) +#if defined(CAN_xmc) #define XMC_SCU_INTERRUPT_EVENT_PEMCAN (((int64_t)SCU_INTERRUPT_SRMSK1_PEMCI_Msk) << 32U) /**< MultiCAN SRAM Parity Error Event. */ #endif #if (UC_SERIES == XMC14) || defined(DOXYGEN) @@ -148,20 +116,24 @@ /* * These are the flags which may be passed to XMC_SCU_SetBMI(). */ -#if defined(CAN) || defined(DOXYGEN) -#define XMC_SCU_BMI_HWCFG_CAN_BSL (0x0080U) /**< CAN Bootstrap Loader Start-up Mode */ -#define XMC_SCU_BMI_HWCFG_CAN_BSLTO (0x0090U) /**< CAN Bootstrap Loader Start-up Mode with time-out */ -#define XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (0x00A0U) /**< Secure Bootstrap Loader Start-up Mode over CANopen */ +#if defined(CAN_xmc) || defined(DOXYGEN) +#define XMC_SCU_BMI_HWCFG_CAN_BSL (0x0000U) /**< CAN Bootstrap Loader Start-up Mode */ +#define XMC_SCU_BMI_HWCFG_CAN_BSLTO (0x0010U) /**< CAN Bootstrap Loader Start-up Mode with time-out */ +#define XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (0x0020U) /**< Secure Bootstrap Loader Start-up Mode over CANopen */ #endif -#define XMC_SCU_BMI_HWCFG_ASC_BSL (0x00C0U) /**< ASC Bootstrap Loader Start-up Mode */ -#define XMC_SCU_BMI_HWCFG_UPM (0x00C1U) /**< User productive Start-up Mode */ -#define XMC_SCU_BMI_HWCFG_UMD (0x00C3U) /**< User Start-up Mode with debug enabled */ -#define XMC_SCU_BMI_HWCFG_UMHAR (0x00C7U) /**< User Start-up Mode with debug enabled and halt after reset (HAR) */ -#define XMC_SCU_BMI_HWCFG_SSC_BSL (0x00C8U) /**< SSC Bootstrap Loader Start-up Mode */ -#define XMC_SCU_BMI_HWCFG_ASC_BSLTO (0x00D0U) /**< ASC BSL Start-up Mode with time-out */ -#define XMC_SCU_BMI_HWCFG_SSC_BSLTO (0x00D8U) /**< SSC BSL Start-up Mode with time-out */ -#define XMC_SCU_BMI_HWCFG_SBSL (0x00FAU) /**< Secure Bootstrap Loader Start-up Mode over ASC */ +#define XMC_SCU_BMI_HWCFG_ASC_BSL (0x0040U) /**< ASC Bootstrap Loader Start-up Mode */ +#define XMC_SCU_BMI_HWCFG_UPM (0x0041U) /**< User productive Start-up Mode */ +#define XMC_SCU_BMI_HWCFG_UMD (0x0043U) /**< User Start-up Mode with debug enabled */ +#define XMC_SCU_BMI_HWCFG_UMHAR (0x0047U) /**< User Start-up Mode with debug enabled and halt after reset (HAR) */ +#define XMC_SCU_BMI_HWCFG_SSC_BSL (0x0048U) /**< SSC Bootstrap Loader Start-up Mode */ +#define XMC_SCU_BMI_HWCFG_ASC_BSLTO (0x0050U) /**< ASC BSL Start-up Mode with time-out */ +#define XMC_SCU_BMI_HWCFG_SSC_BSLTO (0x0058U) /**< SSC BSL Start-up Mode with time-out */ +#define XMC_SCU_BMI_HWCFG_SBSL (0x007AU) /**< Secure Bootstrap Loader Start-up Mode over ASC */ + +#if (UC_SERIES == XMC14) || defined(DOXYGEN) +#define XMC_SCU_BMI_HWCFG_PINDIS (0x0080U) /**< Boot Configuration Type Selection, Boot from BMI is selected */ +#endif #define XMC_SCU_BMI_DAPTYP_SWD (0U << 8) /**< Serial wire debug (SWD) interface is selected */ #define XMC_SCU_BMI_DAPTYP_SPD (1U << 8) /**< Single pin debug (SPD) interface is selected */ @@ -169,11 +141,13 @@ #define XMC_SCU_BMI_DAPDIS_CHANNEL_0 (0U << 9) /**< SWD/SPD_0 pin is selected */ #define XMC_SCU_BMI_DAPDIS_CHANNEL_1 (1U << 9) /**< SWD/SPD_1 pin is selected */ -#if defined(CAN) || defined(DOXYGEN) +#if defined(CAN_xmc) || defined(DOXYGEN) #define XMC_SCU_BMI_CANCLK_DCO1 (0U << 11) /**< Synchronous CAN clock via internal oscillator (DCO1) with enabled trimming via external reference is selected */ #define XMC_SCU_BMI_CANCLK_OSCHP (1U << 11) /**< Synchronous CAN clock via external oscillator (OSC_HP) is selected */ #endif +#define XMC_BMI_ADDR (0x10000e00U) /**< Boot Mode Index (BMI) address holding information about start-up mode and debug configuration of the device. */ + /********************************************************************************************************************* * ENUMS ********************************************************************************************************************/ @@ -263,6 +237,16 @@ typedef enum XMC_SCU_CLOCK_DCLKSRC XMC_SCU_CLOCK_DCLKSRC_EXT_XTAL = 1UL << SCU_CLK_CLKCR1_DCLKSEL_Pos, /**< External crystal oscillator */ } XMC_SCU_CLOCK_DCLKSRC_t; +/** + * ADC clock source selection + * @note Only available in XMC1400 series + */ +typedef enum XMC_SCU_CLOCK_ADCCLKSRC +{ + XMC_SCU_CLOCK_ADCCLKSRC_48MHZ = 0UL << SCU_CLK_CLKCR1_ADCCLKSEL_Pos, /**< Internal oscillator DCO1 (48MHz) */ + XMC_SCU_CLOCK_ADCCLKSRC_32MHZ = 1UL << SCU_CLK_CLKCR1_ADCCLKSEL_Pos, /**< Internal oscillator DCO1 (48MHz) divided by 1.5 */ +} XMC_SCU_CLOCK_ADCCLKSRC_t; + /** * OSCHP mode * @note Only available in XMC1400 series @@ -349,7 +333,7 @@ typedef enum XMC_SCU_PERIPHERAL_CLOCK #if defined(POSIF1) XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF0 peripheral clock gate. */ #endif -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_PERIPHERAL_CLOCK_MCAN = SCU_CLK_CGATSTAT0_MCAN0_Msk, /**< POSIF0 peripheral clock gate. */ #endif } XMC_SCU_PERIPHERAL_CLOCK_t; @@ -382,60 +366,60 @@ typedef enum XMC_SCU_CCU_TRIGGER typedef enum XMC_SCU_IRQCTRL { XMC_SCU_IRQCTRL_SCU_SR0_IRQ0 = (0U << 8U) | 0U, /**< SCU_SR0 connected to IRQ0 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR0_IRQ0 = (0U << 8U) | 1U, /**< CAN0_SR0 connected to IRQ0 */ #endif XMC_SCU_IRQCTRL_CCU40_SR0_IRQ0 = (0U << 8U) | 2U, /**< CCU40_SR0 connected to IRQ0 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_SCU_SR0_OR_CAN0_SR0_IRQ0 = (0U << 8U) | 3U, /**< SCU_SR0 and CAN_SR0 are both connected to IRQ0*/ #endif XMC_SCU_IRQCTRL_SCU_SR1_IRQ1 = (1U << 8U) | 0U, /**< SCU_SR1 connected to IRQ1 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR1_IRQ1 = (1U << 8U) | 1U, /**< CAN0_SR1 connected to IRQ1 */ #endif #if defined(CCU80) XMC_SCU_IRQCTRL_CCU80_SR0_IRQ1 = (1U << 8U) | 2U, /**< CCU80_SR0 connected to IRQ1 */ #endif -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_SCU_SR1_OR_CAN0_SR1_IRQ1 = (1U << 8U) | 3U, /**< SCU_SR1 and CAN0_SR1 connected to IRQ1 */ #endif XMC_SCU_IRQCTRL_SCU_SR2_IRQ2 = (2U << 8U) | 0U, /**< SCU_SR2 connected to IRQ2 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR2_IRQ2 = (2U << 8U) | 1U, /**< CAN0_SR2 connected to IRQ2 */ #endif #if defined(CCU80) XMC_SCU_IRQCTRL_CCU80_SR1_IRQ2 = (2U << 8U) | 2U, /**< CCU80_SR1 connected to IRQ2 */ #endif -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_SCU_SR2_OR_CAN0_SR2_IRQ2 = (2U << 8U) | 3U, /**< SCU_SR2 and CAN0_SR2 connected to IRQ2 */ #endif XMC_SCU_IRQCTRL_ERU0_SR0_IRQ3 = (3U << 8U) | 0U, /**< ERU0_SR0 connected to IRQ3 */ XMC_SCU_IRQCTRL_ERU1_SR0_IRQ3 = (3U << 8U) | 1U, /**< ERU1_SR0 connected to IRQ3 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR0_IRQ3 = (3U << 8U) | 2U, /**< CAN0_SR0 connected to IRQ3 */ #endif XMC_SCU_IRQCTRL_ERU0_SR0_OR_ERU1_SR0_IRQ3 = (3U << 8U) | 3U, /**< ERU0_SR0 and ERU1_SR0 connected to IRQ3 */ XMC_SCU_IRQCTRL_ERU0_SR1_IRQ4 = (4U << 8U) | 0U, /**< ERU0_SR1 connected to IRQ4 */ XMC_SCU_IRQCTRL_ERU1_SR1_IRQ4 = (4U << 8U) | 1U, /**< ERU1_SR1 connected to IRQ4 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR1_IRQ4 = (4U << 8U) | 2U, /**< CAN0_SR1 connected to IRQ4 */ #endif XMC_SCU_IRQCTRL_ERU0_SR1_OR_ERU1_SR1_IRQ4 = (4U << 8U) | 3U, /**< ERU0_SR1 and ERU1_SR1 connected to IRQ4 */ XMC_SCU_IRQCTRL_ERU0_SR2_IRQ5 = (5U << 8U) | 0U, /**< ERU0_SR2 connected to IRQ5 */ XMC_SCU_IRQCTRL_ERU1_SR2_IRQ5 = (5U << 8U) | 1U, /**< ERU1_SR2 connected to IRQ5 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR2_IRQ5 = (5U << 8U) | 2U, /**< CAN0_SR2 connected to IRQ5 */ #endif XMC_SCU_IRQCTRL_ERU0_SR2_OR_ERU1_SR2_IRQ5 = (5U << 8U) | 3U, /**< ERU0_SR2 and ERU1_SR2 connected to IRQ5 */ XMC_SCU_IRQCTRL_ERU0_SR3_IRQ6 = (6U << 8U) | 0U, /**< ERU0_SR3 connected to IRQ6 */ XMC_SCU_IRQCTRL_ERU1_SR3_IRQ6 = (6U << 8U) | 1U, /**< ERU1_SR3 connected to IRQ6 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR3_IRQ6 = (6U << 8U) | 2U, /**< CAN0_SR3 connected to IRQ6 */ #endif XMC_SCU_IRQCTRL_ERU0_SR3_OR_ERU1_SR3_IRQ6 = (6U << 8U) | 3U, /**< ERU0_SR3 and ERU1_SR3 connected to IRQ6 */ @@ -443,7 +427,7 @@ typedef enum XMC_SCU_IRQCTRL #if defined(MATH) XMC_SCU_IRQCTRL_MATH_SR0_IRQ7 = (7U << 8U) | 0U, /**< MATH_SR0 connected to IRQ7 */ #endif -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR3_IRQ7 = (7U << 8U) | 1U, /**< CAN0_SR3 connected to IRQ7 */ #endif XMC_SCU_IRQCTRL_CCU40_SR1_IRQ7 = (7U << 8U) | 2U, /**< CCU40_SR1 connected to IRQ7 */ @@ -534,29 +518,30 @@ typedef enum XMC_SCU_IRQCTRL XMC_SCU_IRQCTRL_VADC0_G0SR0_IRQ17 = (17U << 8U) | 0U, /**< VADC0_G0SR0 connected to IRQ17 */ XMC_SCU_IRQCTRL_USIC0_SR2_IRQ17 = (17U << 8U) | 1U, /**< USIC0_SR2 connected to IRQ17 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR0_IRQ17 = (17U << 8U) | 2U, /**< CAN0_SR0 connected to IRQ17 */ #endif XMC_SCU_IRQCTRL_VADC0_G0SR0_OR_USIC0_SR2_IRQ17 = (17U << 8U) | 3U, /**< VADC0_G0SR0 and USIC0_SR2 connected to IRQ17 */ XMC_SCU_IRQCTRL_VADC0_G0SR1_IRQ18 = (18U << 8U) | 0U, /**< VADC0_G0SR1 connected to IRQ18 */ XMC_SCU_IRQCTRL_USIC0_SR3_IRQ18 = (18U << 8U) | 1U, /**< USIC0_SR3 connected to IRQ18 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR1_IRQ18 = (18U << 8U) | 2U, /**< CAN0_SR1 connected to IRQ18 */ #endif XMC_SCU_IRQCTRL_VADC0_G0SR1_OR_USIC0_SR3_IRQ18 = (18U << 8U) | 3U, /**< VADC0_G0SR1 and USIC0_SR3 connected to IRQ18 */ XMC_SCU_IRQCTRL_VADC0_G1SR0_IRQ19 = (19U << 8U) | 0U, /**< VADC0_G1SR0 connected to IRQ19 */ XMC_SCU_IRQCTRL_USIC0_SR4_IRQ19 = (19U << 8U) | 1U, /**< USIC0_SR4 connected to IRQ19 */ -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_IRQCTRL_CAN0_SR2_IRQ19 = (19U << 8U) | 2U, /**< CAN0_SR2 connected to IRQ19 */ #endif XMC_SCU_IRQCTRL_VADC0_G1SR0_OR_USIC0_SR4_IRQ19 = (19U << 8U) | 3U, /**< VADC0_G1SR0 and USIC0_SR4 connected to IRQ19 */ XMC_SCU_IRQCTRL_VADC0_G1SR1_IRQ20 = (20U << 8U) | 0U, /**< VADC0_G1SR1 connected to IRQ20 */ XMC_SCU_IRQCTRL_USIC0_SR5_IRQ20 = (20U << 8U) | 1U, /**< USIC0_SR5 connected to IRQ20 */ -#if defined(CAN) - XMC_SCU_IRQCTRL_CAN0_SR4_IRQ20 = (20U << 8U) | 2U, /**< CAN0_SR4 connected to IRQ20 */ +#if defined(CAN_xmc) + XMC_SCU_IRQCTRL_CAN0_SR3_IRQ20 = (20U << 8U) | 2U, /**< CAN0_SR3 connected to IRQ20 */ + XMC_SCU_IRQCTRL_CAN0_SR4_IRQ20 = (20U << 8U) | 2U, /**< @deprecated use instead XMC_SCU_IRQCTRL_CAN0_SR3_IRQ20 */ #endif XMC_SCU_IRQCTRL_VADC0_G1SR1_OR_USIC0_SR5_IRQ20 = (20U << 8U) | 3U, /**< VADC0_G1SR1 and USIC0_SR5 connected to IRQ20 */ @@ -707,7 +692,7 @@ typedef struct XMC_SCU_SUPPLYMONITOR
  • 00B sets threshold value to 2.25V
  • 01B sets threshold value to 3.0V -
  • 10B sets threshold value to 4.4V +
  • 10B sets threshold value to 4.4V
*/ uint32_t ext_supply_monitor_speed; /**< Speed of the voltage monitor(VDEL Timing Setting).\n \b Range: @@ -718,25 +703,25 @@ typedef struct XMC_SCU_SUPPLYMONITOR
  • 11B sets monitor speed with no delay - fastest response time. */ bool enable_prewarning_int; /**< Configure pre-warning interrupt generation.\n - \b Range: + \b Range:
    • \a true to enable the interrupt.
    • \a false to disable the interrupt.
    */ bool enable_vdrop_int; /**< Configure VDROP interrupt generation.\n - \b Range: + \b Range:
    • \a true to enable the interrupt. -
    • \a false to disable the interrupt. +
    • \a false to disable the interrupt.
    */ bool enable_vclip_int; /**< Configure VCLIP interrupt.\n - \b Range: + \b Range:
    • \a true to enable the interrupt. -
    • \a false to disable the interrupt. +
    • \a false to disable the interrupt.
    */ bool enable_at_init; /**< Whether the monitor has to be enabled (VDEL unit Enable) after initialization.\n - \b Range: + \b Range:
    • \a true to enable after initialization.
    • \a false to enable after initialization. @@ -893,8 +878,8 @@ void XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj); * @return XMC_SCU_STATUS_t status of limit installation * * \parDescription
      - * Set lower temperature compare limit. - * A low temperature interrupt (SCU_IRQ1) is triggered if Tchip < limit and the event and interrupt are enabled. + * Set lower temperature compare limit. + * A low temperature interrupt (SCU_IRQ1) is triggered if Tchip < limit and the event and interrupt are enabled. * Alternatively XMC_SCU_LowTemperature() can be used to check the status. * \parRelated APIs:
      * XMC_SCU_LowTemperature()\n\n\n @@ -907,8 +892,8 @@ XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit); * @return XMC_SCU_STATUS_t status of limit installation * * \parDescription
      - * Set higher temperature compare limit. - * A high temperature interrupt (SCU_IRQ1) is triggered if Tchip > limit and the event and interrupt are enabled. + * Set higher temperature compare limit. + * A high temperature interrupt (SCU_IRQ1) is triggered if Tchip > limit and the event and interrupt are enabled. * Alternatively XMC_SCU_HighTemperature() can be used to check the status. * \parRelated APIs:
      * XMC_SCU_HighTemperature()\n\n\n @@ -1120,19 +1105,31 @@ void XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t so * \parDescription
      * DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy. * This function start the DCO1 calibration based on temperature. - * + * */ void XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature(int32_t temperature); #if (UC_SERIES == XMC14) || defined(DOXYGEN) +/** + * + * @param adcclk_src Clock source selected as external reference. @ref XMC_SCU_CLOCK_ADCCLKSRC_t + * + * @return None + * + * \parDescription
      + * ADC converter clock (fCONV) selection + * @note Only available for XMC1400 series + */ +void XMC_SCU_CLOCK_SetAdcClockSrc(XMC_SCU_CLOCK_ADCCLKSRC_t adcclk_src); + /** * * @param sync_clk Clock source selected as external reference. @ref XMC_SCU_CLOCK_SYNC_CLKSRC_t - * @param prescaler integer(\f$\frac{3000 \times f_{OSC}[MHz]}{48}\f$) - * @param syn_preload integer(\f$\frac{48 \times prescaler}{f_{OSC}[MHz]}\f$) + * @param prescaler integer(\f$\frac{syn_preload \times f_{OSC}[MHz]}{48}\f$) + * @param syn_preload max. value 0x1FFF integer(\f$\frac{48 \times prescaler}{f_{OSC}[MHz]}\f$) * * @return None - * + * * \parDescription
      * DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy. * This function starts the automatic DCO1 calibration based on the selected clock source. @@ -1143,7 +1140,7 @@ void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration(XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_ /** * * @return None - * + * * \parDescription
      * This function stops the automatic DCO1 calibration based on the selected clock source. * @note Only available for XMC1400 series @@ -1154,7 +1151,7 @@ void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration(void); * * @return true DCO1 is synchronized to the selected XTAL frequency * @return false Actual DCO1 frequency is out of target - * + * * \parDescription
      * This functions checks the status of the synchronisation * @note Only available for XMC1400 series @@ -1162,95 +1159,22 @@ void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration(void); bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady(void); /** - * + * @param mode Oscillator mode. @ref XMC_SCU_CLOCK_OSCHP_MODE_t * @return None - * - * \parDescription
      - * This function enables the watchdog on the DCO1 frequency - * @note Only available for XMC1400 series - */ -void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void); - -/** * - * @return None - * * \parDescription
      - * This function disables the watchdog on the DCO1 frequency - * @note Only available for XMC1400 series + * Configure functional mode of the OSCHP. */ -void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void); +void XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode(XMC_SCU_CLOCK_OSCHP_MODE_t mode); /** - * - * @return None - * - * \parDescription
      - * This function clears the status of the watchdog on the DCO1 frequency - * @note Only available for XMC1400 series - */ -void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void); - -/* - * - * @return true The OSC frequency is usable - * @return false The OSC frequency is not usable. Frequency is too high or too low - * - * \parDescription
      - * This function checks if the DCO1 frequency is in the limits of the watchdog - * @note Only available for XMC1400 series - */ -bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void); - -/* - * + * @param mode Oscillator mode. @ref XMC_SCU_CLOCK_OSCLP_MODE_t * @return None - * - * \parDescription
      - * This function enables flash power down when entering power save mode (SLEEP or DEEPSLEEP modes). - * Upon wake-up, CPU is able to fetch code from flash. - * - * @usage - * @code - * - * // The clock of the peripherals that are not needed during sleep state can be gated before entering sleep state - * XMC_SCU_CLOCK_GatePeripheralClock(SCU_CLK_CGATSTAT0_MATH_Msk); - * - * // Enable FLASH power down during SLEEP and DEEPSLEEP mode - * XMC_SCU_CLOCK_EnableFlashPowerDown(); - * - * // Make sure that SLEEPDEEP bit is set - * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk; * - * // Return to SLEEP mode after handling the wakeup event - * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; - * - * // Put system in DEEPSLEEP state - * __WFI(); - * - * @endcode - * - * \parRelated APIs:
      - * XMC_FLASH_EnterSleepMode() - */ -__STATIC_INLINE void XMC_SCU_CLOCK_EnableFlashPowerDown(void) -{ - SCU_CLK->PWRSVCR = SCU_CLK_PWRSVCR_FPD_Msk; -} - -/* - * - * @return None - * * \parDescription
      - * This function disables flash power down when entering power save mode (SLEEP or DEEPSLEEP modes). - * \parRelated APIs:
      - * XMC_FLASH_EnterSleepMode() + * Configure functional mode of the OSCLP. */ -__STATIC_INLINE void XMC_SCU_CLOCK_DisableFlashPowerDown(void) -{ - SCU_CLK->PWRSVCR = 0; -} +void XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode(XMC_SCU_CLOCK_OSCLP_MODE_t mode); /** * This function selects service request source for a NVIC interrupt node. @@ -1291,7 +1215,7 @@ __STATIC_INLINE void XMC_SCU_DisablePrefetchUnit(void) #endif -/** +/** * * @param range VDEL Range Select ::XMC_SCU_POWER_MONITOR_RANGE_t * @param delay VDEL Timing Setting ::XMC_SCU_POWER_MONITOR_DELAY_t @@ -1304,8 +1228,8 @@ __STATIC_INLINE void XMC_SCU_DisablePrefetchUnit(void) */ __STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(XMC_SCU_POWER_MONITOR_RANGE_t range, XMC_SCU_POWER_MONITOR_DELAY_t delay) { - SCU_ANALOG->ANAVDEL = SCU_ANALOG_ANAVDEL_VDEL_EN_Msk | - (uint32_t)range | + SCU_ANALOG->ANAVDEL = SCU_ANALOG_ANAVDEL_VDEL_EN_Msk | + (uint32_t)range | (uint32_t)delay; } @@ -1318,32 +1242,34 @@ __STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(XMC_SCU_POWER_MONITOR_RANGE_t r */ __STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void) { - SCU_ANALOG->ANAVDEL &= ~SCU_ANALOG_ANAVDEL_VDEL_EN_Msk; + SCU_ANALOG->ANAVDEL &= ~SCU_ANALOG_ANAVDEL_VDEL_EN_Msk; } /** * * @param flags may be any of:
      - * \ref XMC_SCU_BMI_HWCFG_CAN_BSL (only available for XMC1400 series with CAN Module)
      - * \ref XMC_SCU_BMI_HWCFG_CAN_BSLTO (only available for XMC1400 series with CAN Module)
      - * \ref XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (only available for XMC1400 series with CAN Module)
      - * \ref XMC_SCU_BMI_HWCFG_ASC_BSL
      - * \ref XMC_SCU_BMI_HWCFG_UPM
      - * \ref XMC_SCU_BMI_HWCFG_UMD
      - * \ref XMC_SCU_BMI_HWCFG_UMHAR
      - * \ref XMC_SCU_BMI_HWCFG_SSC_BSL
      - * \ref XMC_SCU_BMI_HWCFG_ASC_BSLTO
      - * \ref XMC_SCU_BMI_HWCFG_SSC_BSLTO
      + * \ref XMC_SCU_BMI_HWCFG_CAN_BSL (only available for XMC1400 series with CAN Module)
      + * \ref XMC_SCU_BMI_HWCFG_CAN_BSLTO (only available for XMC1400 series with CAN Module)
      + * \ref XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (only available for XMC1400 series with CAN Module)
      + * \ref XMC_SCU_BMI_HWCFG_ASC_BSL
      + * \ref XMC_SCU_BMI_HWCFG_UPM
      + * \ref XMC_SCU_BMI_HWCFG_UMD
      + * \ref XMC_SCU_BMI_HWCFG_UMHAR
      + * \ref XMC_SCU_BMI_HWCFG_SSC_BSL
      + * \ref XMC_SCU_BMI_HWCFG_ASC_BSLTO
      + * \ref XMC_SCU_BMI_HWCFG_SSC_BSLTO
      * \ref XMC_SCU_BMI_HWCFG_SBSL

      - * optionally OR'd together with any of:
      - * \ref XMC_SCU_BMI_DAPTYP_SWD
      - * \ref XMC_SCU_BMI_DAPTYP_SPD

      - * optionally OR'd together with any of:
      - * \ref XMC_SCU_BMI_DAPDIS_CHANNEL_0
      + * optionally OR'd together with any of (only available for XMC1400 series):
      + * \ref XMC_SCU_BMI_HWCFG_PINDIS + * optionally OR'd together with any of:
      + * \ref XMC_SCU_BMI_DAPTYP_SWD
      + * \ref XMC_SCU_BMI_DAPTYP_SPD

      + * optionally OR'd together with any of:
      + * \ref XMC_SCU_BMI_DAPDIS_CHANNEL_0
      * \ref XMC_SCU_BMI_DAPDIS_CHANNEL_1

      * @image html "xmc1000_debugif.png" - * optionally OR'd together with any of (only available for XMC1400 series with CAN Module):
      - * \ref XMC_SCU_BMI_CANCLK_DCO1
      + * optionally OR'd together with any of (only available for XMC1400 series with CAN Module):
      + * \ref XMC_SCU_BMI_CANCLK_DCO1
      * \ref XMC_SCU_BMI_CANCLK_OSCHP

      * * @param timeout Only relevant if a start up mode is selected that uses timeout. The time-out duration is BSLTO*2664000 MCLK cycles, the supported time-out range is 0.3-5s (333...4995ms) @@ -1352,7 +1278,7 @@ __STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void) * \parDescription
      * This procedure initiates installation of a new BMI value. In particular, it can be used as * well as to restore the state upon delivery for a device already in User Productive mode. - * + * * @code * // Switch to ASC Bootstrap Loader * XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_ASC_BSL, 0); @@ -1363,18 +1289,142 @@ __STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void) */ uint32_t XMC_SCU_SetBMI(uint32_t flags, uint8_t timeout); -#ifdef __cplusplus +/** + * + * @return uint32_t Current BMI value. + * + * \parDescription
      + * This procedure initiates installation of a new BMI value. In particular, it can be used as + * well as to restore the state upon delivery for a device already in User Productive mode. + * + * @code + * // Switch to ASC Bootstrap Loader + * bmi_value = XMC_SCU_GetBMI(); + * + * if ((bmi_value & 0x000000ffU) != XMC_SCU_BMI_HWCFG_ASC) + * { + * XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_ASC, 0); + * } + * + * @endcode + */ +__STATIC_INLINE uint32_t XMC_SCU_GetBMI(void) +{ + return *(volatile uint32_t *)XMC_BMI_ADDR; +} + +/* + * + * @return None + * + * \parDescription
      + * This function enables flash power down when entering power save mode (SLEEP or DEEPSLEEP modes). + * Upon wake-up, CPU is able to fetch code from flash. + * + * @usage + * @code + * + * // The clock of the peripherals that are not needed during sleep state can be gated before entering sleep state + * XMC_SCU_CLOCK_GatePeripheralClock(SCU_CLK_CGATSTAT0_MATH_Msk); + * + * // Enable FLASH power down during SLEEP and DEEPSLEEP mode + * XMC_SCU_CLOCK_EnableFlashPowerDown(); + * + * // Make sure that SLEEPDEEP bit is set + * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk; + * + * // Return to SLEEP mode after handling the wakeup event + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * + * // Put system in DEEPSLEEP state + * __WFI(); + * + * @endcode + * + * \parRelated APIs:
      + * XMC_FLASH_EnterSleepMode() + */ +__STATIC_INLINE void XMC_SCU_CLOCK_EnableFlashPowerDown(void) +{ + SCU_CLK->PWRSVCR = SCU_CLK_PWRSVCR_FPD_Msk; +} + +/* + * + * @return None + * + * \parDescription
      + * This function disables flash power down when entering power save mode (SLEEP or DEEPSLEEP modes). + * \parRelated APIs:
      + * XMC_FLASH_EnterSleepMode() + */ +__STATIC_INLINE void XMC_SCU_CLOCK_DisableFlashPowerDown(void) +{ + SCU_CLK->PWRSVCR = 0; } -#endif /** - * @} + * + * @return None + * + * \parDescription
      + * This function enables the watchdog on the DCO1 frequency + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void) +{ + SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDEN_Msk; +} + +/** + * + * @return None + * + * \parDescription
      + * This function disables the watchdog on the DCO1 frequency + * @note Only available for XMC1400 series + */ +__STATIC_INLINE void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void) +{ + SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_OWDEN_Msk; +} + +/** + * + * @return None + * + * \parDescription
      + * This function clears the status of the watchdog on the DCO1 frequency + * @note Only available for XMC1400 series */ +__STATIC_INLINE void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void) +{ + SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDRES_Msk; +} + +/* + * + * @return true The OSC frequency is usable + * @return false The OSC frequency is not usable. Frequency is too high or too low + * + * \parDescription
      + * This function checks if the DCO1 frequency is in the limits of the watchdog + * @note Only available for XMC1400 series + */ +__STATIC_INLINE bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void) +{ + return ((SCU_CLK->OSCCSR & (SCU_CLK_OSCCSR_OSC2L_Msk | SCU_CLK_OSCCSR_OSC2H_Msk)) == 0U); +} + +#ifdef __cplusplus +} +#endif /** * @} */ + #endif /* UC_FAMILY == XMC1 */ #endif /* XMC1_SCU_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc1_usic_map.h b/cores/xmc_lib/XMCLib/inc/xmc1_usic_map.h index 6f5d6221..16a540e0 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc1_usic_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc1_usic_map.h @@ -1,54 +1,43 @@ /** * @file xmc1_usic_map.h - * @date 2016-08-22 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-08-25: - * - Added XMC1400 + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-06-17: - * - Added support for XMC1201 TSSOP28, XMC1302 TSSOP28, XMC1402 TSSOP38, XMC1403 VQFN40 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-08-22: - * - Added USIC1_C0_DX1_P3_4 for XMC14xx 64 pins package + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * @endcond + * @endcond * */ @@ -3595,4 +3584,129 @@ #define USIC1_C1_DX5_SELO0 6 #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define USIC0_C0_DX0_DX3INS 6 +#define USIC0_C0_DX0_P0_14 0 +#define USIC0_C0_DX0_P0_15 1 +#define USIC0_C0_DX0_P1_0 2 +#define USIC0_C0_DX0_P1_1 3 +#define USIC0_C0_DX0_P2_0 4 +#define USIC0_C0_DX0_P2_1 5 +#define USIC0_C0_DX1_DX0INS 5 +#define USIC0_C0_DX1_DX4INS 6 +#define USIC0_C0_DX1_P0_14 0 +#define USIC0_C0_DX1_P0_7 2 +#define USIC0_C0_DX1_P0_8 1 +#define USIC0_C0_DX1_P1_1 3 +#define USIC0_C0_DX1_P2_0 4 +#define USIC0_C0_DX2_DX5INS 6 +#define USIC0_C0_DX2_P0_0 0 +#define USIC0_C0_DX2_P0_10 2 +#define USIC0_C0_DX2_P0_11 3 +#define USIC0_C0_DX2_P0_12 4 +#define USIC0_C0_DX2_P0_13 5 +#define USIC0_C0_DX2_P0_9 1 +#define USIC0_C0_DX3_DOUT0 6 +#define USIC0_C0_DX3_DX5INS 5 +#define USIC0_C0_DX3_P2_10 2 +#define USIC0_C0_DX3_P2_2 0 +#define USIC0_C0_DX3_P2_4 1 +#define USIC0_C0_DX3_P2_6 4 +#define USIC0_C0_DX3_P2_8 3 +#define USIC0_C0_DX4_DX5INS 5 +#define USIC0_C0_DX4_P2_10 2 +#define USIC0_C0_DX4_P2_2 0 +#define USIC0_C0_DX4_P2_4 1 +#define USIC0_C0_DX4_P2_6 4 +#define USIC0_C0_DX4_P2_8 3 +#define USIC0_C0_DX4_SCLKOUT 6 +#define USIC0_C0_DX5_P1_4 4 +#define USIC0_C0_DX5_P1_6 5 +#define USIC0_C0_DX5_P2_3 1 +#define USIC0_C0_DX5_P2_5 3 +#define USIC0_C0_DX5_P2_7 2 +#define USIC0_C0_DX5_P2_9 0 +#define USIC0_C0_DX5_SELO0 6 +#define USIC0_C1_DX0_DX3INS 6 +#define USIC0_C1_DX0_P0_6 2 +#define USIC0_C1_DX0_P0_7 3 +#define USIC0_C1_DX0_P1_2 1 +#define USIC0_C1_DX0_P1_3 0 +#define USIC0_C1_DX0_P2_10 5 +#define USIC0_C1_DX0_P2_11 4 +#define USIC0_C1_DX1_DX0INS 5 +#define USIC0_C1_DX1_DX4INS 6 +#define USIC0_C1_DX1_P0_7 2 +#define USIC0_C1_DX1_P0_8 1 +#define USIC0_C1_DX1_P1_3 0 +#define USIC0_C1_DX1_P2_11 4 +#define USIC0_C1_DX2_DX5INS 6 +#define USIC0_C1_DX2_P0_0 0 +#define USIC0_C1_DX2_P0_10 2 +#define USIC0_C1_DX2_P0_11 3 +#define USIC0_C1_DX2_P0_9 1 +#define USIC0_C1_DX2_P1_1 4 +#define USIC0_C1_DX2_P2_0 5 +#define USIC0_C1_DX3_DOUT0 6 +#define USIC0_C1_DX3_DX5INS 5 +#define USIC0_C1_DX3_P2_1 0 +#define USIC0_C1_DX3_P2_3 2 +#define USIC0_C1_DX3_P2_5 4 +#define USIC0_C1_DX3_P2_7 3 +#define USIC0_C1_DX3_P2_9 1 +#define USIC0_C1_DX4_DX5INS 5 +#define USIC0_C1_DX4_P2_1 0 +#define USIC0_C1_DX4_P2_3 2 +#define USIC0_C1_DX4_P2_5 4 +#define USIC0_C1_DX4_P2_7 3 +#define USIC0_C1_DX4_P2_9 1 +#define USIC0_C1_DX4_SCLKOUT 6 +#define USIC0_C1_DX5_P1_4 4 +#define USIC0_C1_DX5_P1_5 5 +#define USIC0_C1_DX5_P2_2 0 +#define USIC0_C1_DX5_P2_4 1 +#define USIC0_C1_DX5_P2_6 3 +#define USIC0_C1_DX5_P2_8 2 +#define USIC0_C1_DX5_SR0 6 +#define USIC1_C0_DX0_DX3INS 6 +#define USIC1_C0_DX0_P0_2 0 +#define USIC1_C0_DX0_P0_3 1 +#define USIC1_C0_DX1_DX0INS 5 +#define USIC1_C0_DX1_DX4INS 6 +#define USIC1_C0_DX1_P0_2 0 +#define USIC1_C0_DX2_DX5INS 6 +#define USIC1_C0_DX3_DOUT0 6 +#define USIC1_C0_DX3_DX5INS 5 +#define USIC1_C0_DX3_P2_3 4 +#define USIC1_C0_DX4_DX5INS 5 +#define USIC1_C0_DX4_P2_3 4 +#define USIC1_C0_DX4_SCLKOUT 6 +#define USIC1_C0_DX5_P2_2 4 +#define USIC1_C0_DX5_P2_4 5 +#define USIC1_C0_DX5_SELO0 6 +#define USIC1_C1_DX0_DX3INS 6 +#define USIC1_C1_DX0_P0_0 0 +#define USIC1_C1_DX0_P0_1 1 +#define USIC1_C1_DX1_DX0INS 5 +#define USIC1_C1_DX1_DX4INS 6 +#define USIC1_C1_DX1_P0_1 0 +#define USIC1_C1_DX2_DX5INS 6 +#define USIC1_C1_DX2_SR0 5 +#define USIC1_C1_DX3_DOUT0 6 +#define USIC1_C1_DX3_DX5INS 5 +#define USIC1_C1_DX3_P0_15 1 +#define USIC1_C1_DX3_P2_4 2 +#define USIC1_C1_DX3_P2_6 4 +#define USIC1_C1_DX4_DX5INS 5 +#define USIC1_C1_DX4_P0_15 1 +#define USIC1_C1_DX4_P2_4 2 +#define USIC1_C1_DX4_P2_6 4 +#define USIC1_C1_DX4_SCLKOUT 6 +#define USIC1_C1_DX5_P0_14 1 +#define USIC1_C1_DX5_P2_3 2 +#define USIC1_C1_DX5_P2_5 3 +#define USIC1_C1_DX5_P2_7 4 +#define USIC1_C1_DX5_SELO0 6 +#endif + #endif /* XMC1_USIC_MAP_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h b/cores/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h index 0e96a8a2..fd3ff4ae 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_ccu4_map.h @@ -1,46 +1,41 @@ /** * @file xmc4_ccu4_map.h - * @date 2015-12-07 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-08-25: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-07: - * - Add XMC4300 support + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -137,6 +132,8 @@ #define CCU41_IN0_CCU41_ST3 15 #define CCU41_IN0_ERU1_PDOUT0 9 #define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_HRPWM0_QOUT0 5 +#define CCU41_IN0_HRPWM0_QOUT3 6 #define CCU41_IN0_P1_4 2 #define CCU41_IN0_P2_5 0 #define CCU41_IN0_P2_9 1 @@ -149,6 +146,9 @@ #define CCU41_IN1_CCU41_ST3 15 #define CCU41_IN1_ERU1_PDOUT0 3 #define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_HRPWM0_QOUT0 7 +#define CCU41_IN1_HRPWM0_QOUT1 5 +#define CCU41_IN1_HRPWM0_QOUT3 6 #define CCU41_IN1_P1_5 2 #define CCU41_IN1_P2_4 0 #define CCU41_IN1_P2_9 1 @@ -160,6 +160,9 @@ #define CCU41_IN2_CCU41_ST3 15 #define CCU41_IN2_ERU1_PDOUT0 3 #define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_HRPWM0_QOUT0 7 +#define CCU41_IN2_HRPWM0_QOUT2 5 +#define CCU41_IN2_HRPWM0_QOUT3 6 #define CCU41_IN2_P2_3 0 #define CCU41_IN2_P2_9 1 #define CCU41_IN2_SCU_ERU1_IOUT2 10 @@ -171,6 +174,8 @@ #define CCU41_IN3_CCU41_ST3 15 #define CCU41_IN3_ERU1_PDOUT0 3 #define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_HRPWM0_QOUT0 7 +#define CCU41_IN3_HRPWM0_QOUT3 5 #define CCU41_IN3_P2_2 0 #define CCU41_IN3_P2_9 1 #define CCU41_IN3_SCU_ERU1_IOUT3 10 @@ -246,6 +251,8 @@ #define CCU41_IN0_CCU41_ST3 15 #define CCU41_IN0_ERU1_PDOUT0 9 #define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_HRPWM0_QOUT0 5 +#define CCU41_IN0_HRPWM0_QOUT3 6 #define CCU41_IN0_P1_4 2 #define CCU41_IN0_P2_5 0 #define CCU41_IN0_SCU_ERU1_IOUT0 10 @@ -257,6 +264,9 @@ #define CCU41_IN1_CCU41_ST3 15 #define CCU41_IN1_ERU1_PDOUT0 3 #define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_HRPWM0_QOUT0 7 +#define CCU41_IN1_HRPWM0_QOUT1 5 +#define CCU41_IN1_HRPWM0_QOUT3 6 #define CCU41_IN1_P1_5 2 #define CCU41_IN1_P2_4 0 #define CCU41_IN1_SCU_ERU1_IOUT1 10 @@ -267,6 +277,9 @@ #define CCU41_IN2_CCU41_ST3 15 #define CCU41_IN2_ERU1_PDOUT0 3 #define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_HRPWM0_QOUT0 7 +#define CCU41_IN2_HRPWM0_QOUT2 5 +#define CCU41_IN2_HRPWM0_QOUT3 6 #define CCU41_IN2_P2_3 0 #define CCU41_IN2_SCU_ERU1_IOUT2 10 #define CCU41_IN2_SCU_GSC41 8 @@ -277,6 +290,8 @@ #define CCU41_IN3_CCU41_ST3 15 #define CCU41_IN3_ERU1_PDOUT0 3 #define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_HRPWM0_QOUT0 7 +#define CCU41_IN3_HRPWM0_QOUT3 5 #define CCU41_IN3_P2_2 0 #define CCU41_IN3_SCU_ERU1_IOUT3 10 #define CCU41_IN3_SCU_GSC41 8 @@ -355,6 +370,8 @@ #define CCU41_IN0_CCU41_ST3 15 #define CCU41_IN0_ERU1_PDOUT0 9 #define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_HRPWM0_QOUT0 5 +#define CCU41_IN0_HRPWM0_QOUT3 6 #define CCU41_IN0_P1_4 2 #define CCU41_IN0_P2_5 0 #define CCU41_IN0_P2_9 1 @@ -367,6 +384,9 @@ #define CCU41_IN1_CCU41_ST3 15 #define CCU41_IN1_ERU1_PDOUT0 3 #define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_HRPWM0_QOUT0 7 +#define CCU41_IN1_HRPWM0_QOUT1 5 +#define CCU41_IN1_HRPWM0_QOUT3 6 #define CCU41_IN1_P1_5 2 #define CCU41_IN1_P2_4 0 #define CCU41_IN1_P2_9 1 @@ -378,6 +398,9 @@ #define CCU41_IN2_CCU41_ST3 15 #define CCU41_IN2_ERU1_PDOUT0 3 #define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_HRPWM0_QOUT0 7 +#define CCU41_IN2_HRPWM0_QOUT2 5 +#define CCU41_IN2_HRPWM0_QOUT3 6 #define CCU41_IN2_P2_3 0 #define CCU41_IN2_P2_9 1 #define CCU41_IN2_SCU_ERU1_IOUT2 10 @@ -389,6 +412,8 @@ #define CCU41_IN3_CCU41_ST3 15 #define CCU41_IN3_ERU1_PDOUT0 3 #define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_HRPWM0_QOUT0 7 +#define CCU41_IN3_HRPWM0_QOUT3 5 #define CCU41_IN3_P2_2 0 #define CCU41_IN3_P2_9 1 #define CCU41_IN3_SCU_ERU1_IOUT3 10 @@ -462,6 +487,8 @@ #define CCU41_IN0_CCU41_ST3 15 #define CCU41_IN0_ERU1_PDOUT0 9 #define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_HRPWM0_QOUT0 5 +#define CCU41_IN0_HRPWM0_QOUT3 6 #define CCU41_IN0_P1_4 2 #define CCU41_IN0_P2_5 0 #define CCU41_IN0_SCU_ERU1_IOUT0 10 @@ -473,6 +500,9 @@ #define CCU41_IN1_CCU41_ST3 15 #define CCU41_IN1_ERU1_PDOUT0 3 #define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_HRPWM0_QOUT0 7 +#define CCU41_IN1_HRPWM0_QOUT1 5 +#define CCU41_IN1_HRPWM0_QOUT3 6 #define CCU41_IN1_P1_5 2 #define CCU41_IN1_P2_4 0 #define CCU41_IN1_SCU_ERU1_IOUT1 10 @@ -483,6 +513,9 @@ #define CCU41_IN2_CCU41_ST3 15 #define CCU41_IN2_ERU1_PDOUT0 3 #define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_HRPWM0_QOUT0 7 +#define CCU41_IN2_HRPWM0_QOUT2 5 +#define CCU41_IN2_HRPWM0_QOUT3 6 #define CCU41_IN2_P2_3 0 #define CCU41_IN2_SCU_ERU1_IOUT2 10 #define CCU41_IN2_SCU_GSC41 8 @@ -493,6 +526,8 @@ #define CCU41_IN3_CCU41_ST3 15 #define CCU41_IN3_ERU1_PDOUT0 3 #define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_HRPWM0_QOUT0 7 +#define CCU41_IN3_HRPWM0_QOUT3 5 #define CCU41_IN3_P2_2 0 #define CCU41_IN3_SCU_ERU1_IOUT3 10 #define CCU41_IN3_SCU_GSC41 8 @@ -793,6 +828,8 @@ #define CCU41_IN0_CCU41_ST3 15 #define CCU41_IN0_ERU1_PDOUT0 9 #define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_HRPWM0_QOUT0 5 +#define CCU41_IN0_HRPWM0_QOUT3 6 #define CCU41_IN0_P1_4 2 #define CCU41_IN0_P2_5 0 #define CCU41_IN0_P2_9 1 @@ -805,6 +842,9 @@ #define CCU41_IN1_CCU41_ST3 15 #define CCU41_IN1_ERU1_PDOUT0 3 #define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_HRPWM0_QOUT0 7 +#define CCU41_IN1_HRPWM0_QOUT1 5 +#define CCU41_IN1_HRPWM0_QOUT3 6 #define CCU41_IN1_P1_5 2 #define CCU41_IN1_P2_4 0 #define CCU41_IN1_P2_9 1 @@ -816,6 +856,9 @@ #define CCU41_IN2_CCU41_ST3 15 #define CCU41_IN2_ERU1_PDOUT0 3 #define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_HRPWM0_QOUT0 7 +#define CCU41_IN2_HRPWM0_QOUT2 5 +#define CCU41_IN2_HRPWM0_QOUT3 6 #define CCU41_IN2_P2_3 0 #define CCU41_IN2_P2_9 1 #define CCU41_IN2_SCU_ERU1_IOUT2 10 @@ -827,6 +870,8 @@ #define CCU41_IN3_CCU41_ST3 15 #define CCU41_IN3_ERU1_PDOUT0 3 #define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_HRPWM0_QOUT0 7 +#define CCU41_IN3_HRPWM0_QOUT3 5 #define CCU41_IN3_P2_2 0 #define CCU41_IN3_P2_9 1 #define CCU41_IN3_SCU_ERU1_IOUT3 10 @@ -902,6 +947,8 @@ #define CCU41_IN0_CCU41_ST3 15 #define CCU41_IN0_ERU1_PDOUT0 9 #define CCU41_IN0_ERU1_PDOUT1 3 +#define CCU41_IN0_HRPWM0_QOUT0 5 +#define CCU41_IN0_HRPWM0_QOUT3 6 #define CCU41_IN0_P1_4 2 #define CCU41_IN0_P2_5 0 #define CCU41_IN0_SCU_ERU1_IOUT0 10 @@ -913,6 +960,9 @@ #define CCU41_IN1_CCU41_ST3 15 #define CCU41_IN1_ERU1_PDOUT0 3 #define CCU41_IN1_ERU1_PDOUT1 9 +#define CCU41_IN1_HRPWM0_QOUT0 7 +#define CCU41_IN1_HRPWM0_QOUT1 5 +#define CCU41_IN1_HRPWM0_QOUT3 6 #define CCU41_IN1_P1_5 2 #define CCU41_IN1_P2_4 0 #define CCU41_IN1_SCU_ERU1_IOUT1 10 @@ -923,6 +973,9 @@ #define CCU41_IN2_CCU41_ST3 15 #define CCU41_IN2_ERU1_PDOUT0 3 #define CCU41_IN2_ERU1_PDOUT2 9 +#define CCU41_IN2_HRPWM0_QOUT0 7 +#define CCU41_IN2_HRPWM0_QOUT2 5 +#define CCU41_IN2_HRPWM0_QOUT3 6 #define CCU41_IN2_P2_3 0 #define CCU41_IN2_SCU_ERU1_IOUT2 10 #define CCU41_IN2_SCU_GSC41 8 @@ -933,6 +986,8 @@ #define CCU41_IN3_CCU41_ST3 15 #define CCU41_IN3_ERU1_PDOUT0 3 #define CCU41_IN3_ERU1_PDOUT3 9 +#define CCU41_IN3_HRPWM0_QOUT0 7 +#define CCU41_IN3_HRPWM0_QOUT3 5 #define CCU41_IN3_P2_2 0 #define CCU41_IN3_SCU_ERU1_IOUT3 10 #define CCU41_IN3_SCU_GSC41 8 @@ -940,6 +995,7 @@ #define CCU41_IN3_VADC0_G1ARBCNT 6 #endif + #if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100) #define CCU40_IN0_CAN0_SR7 7 #define CCU40_IN0_CCU40_ST0 12 @@ -1042,6 +1098,7 @@ #define CCU41_IN3_VADC0_G1ARBCNT 6 #endif + #if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100) #define CCU40_IN0_CAN0_SR7 7 #define CCU40_IN0_CCU40_ST0 12 diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h b/cores/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h index fcdedf97..41b1a734 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_ccu8_map.h @@ -1,46 +1,41 @@ /** * @file xmc4_ccu8_map.h - * @date 2015-12-07 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-08-25: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-07: - * - Add XMC4300 support + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_eru_map.h b/cores/xmc_lib/XMCLib/inc/xmc4_eru_map.h index 42df18f4..81a142f8 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_eru_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_eru_map.h @@ -1,49 +1,41 @@ /** * @file xmc4_eru_map.h - * @date 2016-10-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-07: - * - Add XMC4300 support + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-10-27: - * - Fixed: Remove incorrect ERU0_ETL1_INPUTB_P0_1 and replace it by ERU0_ETL1_INPUTB_SCU_HIB_SR1 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_flash.h b/cores/xmc_lib/XMCLib/inc/xmc4_flash.h index 5a06e200..55d772e4 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_flash.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_flash.h @@ -1,62 +1,43 @@ /** * @file xmc4_flash.h - * @date 2016-03-22 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.14 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2014-12-10: - * - Initial
      - * 2015-02-20: - * - Updated for Documentation related changes
      - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * 2015-08-17: - * - Added the below API's to the public interface. - * 1. XMC_FLASH_Reset - * 2. XMC_FLASH_ErasePhysicalSector - * 3. XMC_FLASH_EraseUCB - * 4. XMC_FLASH_ResumeProtection - * 5. XMC_FLASH_RepairPhysicalSector - * - Added support for XMC4800/4700 devices - * 2015-12-07: - * - Fix XMC_FLASH_READ_ACCESS_TIME for XMC43, 47 and 48 devices - * 2016-03-18: - * - Fix implementation of XMC_PREFETCH_EnableInstructionBuffer and XMC_PREFETCH_DisableInstructionBuffer - * 2016-03-22: - * - Fix implementation of XMC_PREFETCH_InvalidateInstructionBuffer - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -71,10 +52,6 @@ #if UC_FAMILY == XMC4 -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup FLASH @@ -145,6 +122,8 @@ #define XMC_FLASH_READ_ACCESS_TIME (20E-9F) #endif +#define XMC_FLASH_BMI_VALID (uint32_t)(0x1 << 31) /**< This is always 0 in UCB. The copy of this BMI word in DSRAM1 has this ?BMI Valid? bit set to 1 after SSW has validated the XOR checksum */ + /********************************************************************************************************************* * ENUMS ********************************************************************************************************************/ @@ -156,35 +135,35 @@ typedef enum XMC_FLASH_STATUS XMC_FLASH_STATUS_OK = 0U, /**< Operation completed successfully*/ XMC_FLASH_STATUS_BUSY = FLASH_FSR_PBUSY_Msk, /**< API cannot proceed since FLASH is busy*/ XMC_FLASH_STATUS_PROGRAMMING_STATE = FLASH_FSR_PROG_Msk, /**< Write page is in progress or finished */ - XMC_FLASH_STATUS_ERASE_STATE = FLASH_FSR_ERASE_Msk, /**< Erase page is in progress or finished */ - XMC_FLASH_STATUS_PAGE_MODE = FLASH_FSR_PFPAGE_Msk, /**< Flash is in page mode. Assembly buffer + XMC_FLASH_STATUS_ERASE_STATE = FLASH_FSR_ERASE_Msk, /**< Erase page is in progress or finished */ + XMC_FLASH_STATUS_PAGE_MODE = FLASH_FSR_PFPAGE_Msk, /**< Flash is in page mode. Assembly buffer of PFLASH is in use */ XMC_FLASH_STATUS_OPERATION_ERROR = FLASH_FSR_PFOPER_Msk, /**< Flash Operation aborted */ - XMC_FLASH_STATUS_COMMAND_SEQUENCE_ERROR = FLASH_FSR_SQER_Msk, /**< Improper address or Invalid state machine - operation */ - XMC_FLASH_STATUS_PROTECTION_ERROR = FLASH_FSR_PROER_Msk, /**< Flash operation addressing the locked + XMC_FLASH_STATUS_COMMAND_SEQUENCE_ERROR = FLASH_FSR_SQER_Msk, /**< Improper address or Invalid state machine + operation */ + XMC_FLASH_STATUS_PROTECTION_ERROR = FLASH_FSR_PROER_Msk, /**< Flash operation addressing the locked sector */ - XMC_FLASH_STATUS_SINGLE_BIT_ERROR_AND_CORRECTION = FLASH_FSR_PFSBER_Msk, /**< Single bit error detected and + XMC_FLASH_STATUS_SINGLE_BIT_ERROR_AND_CORRECTION = FLASH_FSR_PFSBER_Msk, /**< Single bit error detected and corrected */ XMC_FLASH_STATUS_DOUBLE_BIT_ERROR = FLASH_FSR_PFDBER_Msk, /**< Multiple bit error occurred */ - XMC_FLASH_STATUS_PROTECTION_INSTALLED = FLASH_FSR_PROIN_Msk, /**< Confirmation of the read or/and write + XMC_FLASH_STATUS_PROTECTION_INSTALLED = FLASH_FSR_PROIN_Msk, /**< Confirmation of the read or/and write protection is successful */ - XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED = FLASH_FSR_RPROIN_Msk, /**< Confirmation of read and global write + XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED = FLASH_FSR_RPROIN_Msk, /**< Confirmation of read and global write protection is successful for user-0 */ - XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE = FLASH_FSR_RPRODIS_Msk, /**< Read or/and write protection is + XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE = FLASH_FSR_RPRODIS_Msk, /**< Read or/and write protection is temporarily disabled */ - XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB0 = FLASH_FSR_WPROIN0_Msk, /**< Sector write protection is installed + XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB0 = FLASH_FSR_WPROIN0_Msk, /**< Sector write protection is installed for user-0 */ - XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB1 = FLASH_FSR_WPROIN1_Msk, /**< Sector write protection is installed + XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB1 = FLASH_FSR_WPROIN1_Msk, /**< Sector write protection is installed for user-1 */ - XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB2 = FLASH_FSR_WPROIN2_Msk, /**< Sector OTP protection is installed + XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB2 = FLASH_FSR_WPROIN2_Msk, /**< Sector OTP protection is installed for user-2 */ - XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB0 = FLASH_FSR_WPRODIS0_Msk, /**< Sector write protection is disabled + XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB0 = FLASH_FSR_WPRODIS0_Msk, /**< Sector write protection is disabled for user-0 */ - XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB1 = FLASH_FSR_WPRODIS1_Msk, /**< Sector write protection is disabled + XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB1 = FLASH_FSR_WPRODIS1_Msk, /**< Sector write protection is disabled for user-1 */ XMC_FLASH_STATUS_SLEEP_MODE = FLASH_FSR_SLM_Msk, /**< Indicates flash in sleep mode or not */ - XMC_FLASH_STATUS_VERIFY_ERROR = (int32_t)FLASH_FSR_VER_Msk, /**< Write verification and Erase + XMC_FLASH_STATUS_VERIFY_ERROR = (int32_t)FLASH_FSR_VER_Msk, /**< Write verification and Erase verification error occurred */ } XMC_FLASH_STATUS_t; @@ -193,7 +172,7 @@ typedef enum XMC_FLASH_STATUS */ typedef enum XMC_FLASH_MARGIN { - XMC_FLASH_MARGIN_DEFAULT = 0x0U << FLASH_MARP_MARGIN_Pos, /**< Default margin */ + XMC_FLASH_MARGIN_DEFAULT = 0x0U << FLASH_MARP_MARGIN_Pos, /**< Default margin */ XMC_FLASH_MARGIN_TIGHT0 = 0x1U << FLASH_MARP_MARGIN_Pos, /**< Sub-optimal 0-bits are read as 1s */ XMC_FLASH_MARGIN_TIGHT1 = 0x4U << FLASH_MARP_MARGIN_Pos /**< Sub-optimal 1-bits are read as 0s */ } XMC_FLASH_MARGIN_t; @@ -203,11 +182,11 @@ typedef enum XMC_FLASH_MARGIN */ typedef enum XMC_FLASH_EVENT { - XMC_FLASH_EVENT_VERIFY_AND_OPERATION_ERROR = 0x01U << FLASH_FCON_VOPERM_Pos, /**< Flash verify and operation error + XMC_FLASH_EVENT_VERIFY_AND_OPERATION_ERROR = 0x01U << FLASH_FCON_VOPERM_Pos, /**< Flash verify and operation error event */ XMC_FLASH_EVENT_COMMAND_SEQUENCE_ERROR = 0x02U << FLASH_FCON_VOPERM_Pos, /**< Flash command sequence error event*/ XMC_FLASH_EVENT_PROTECTION_ERROR = 0x04U << FLASH_FCON_VOPERM_Pos, /**< Flash protection error event */ - XMC_FLASH_EVENT_SINGLE_BIT_ERROR = 0x08U << FLASH_FCON_VOPERM_Pos, /**< Flash single bit error event */ + XMC_FLASH_EVENT_SINGLE_BIT_ERROR = 0x08U << FLASH_FCON_VOPERM_Pos, /**< Flash single bit error event */ XMC_FLASH_EVENT_DOUBLE_BIT_ERROR = 0x20U << FLASH_FCON_VOPERM_Pos, /**< Flash double bit error event*/ XMC_FLASH_EVENT_END_OF_BUSY = (int32_t)(0x80U << FLASH_FCON_VOPERM_Pos) /**< Flash end of busy event*/ } XMC_FLASH_EVENT_t; @@ -235,6 +214,41 @@ typedef enum XMC_FLASH_PROTECTION XMC_FLASH_PROTECTION_READ_GLOBAL = 0x8000UL /**< Global read protection (Applicable for UserLevel0 alone)*/ } XMC_FLASH_PROTECTION_t; +/** + * BMI Word configuration + */ +typedef enum XMC_FLASH_BMI +{ + XMC_FLASH_BMI_BOOT_MODE_NORMAL = 0x0UL, /**< Normal boot mode */ + XMC_FLASH_BMI_BOOT_MODE_ASC_BSL = 0x1UL, /**< ASC BSL boot mode */ + XMC_FLASH_BMI_BOOT_MODE_CAN_BSL = 0x3UL, /**< CAN BSL boot mode */ + XMC_FLASH_BMI_BOOT_MODE_PSRAM = 0x4UL, /**< PSRAM boot mode */ + XMC_FLASH_BMI_BOOT_MODE_ABM0 = 0x5UL, /**< ABM0 boot mode */ + XMC_FLASH_BMI_BOOT_MODE_ABM1 = 0x6UL, /**< ABM1 boot mode */ + XMC_FLASH_BMI_BOOT_MODE_FALLBACK_ABM = 0x7UL, /**< Fallback ABM boot mode */ + XMC_FLASH_BMI_MAC_BIT_MSK = 0x1UL << 5, /**< Valid MAC address part of BMI string */ + XMC_FLASH_BMI_IPV4_BIT_MSK = 0x1UL << 7, /**< Ethernet IP extension contains a IPv4 address */ + XMC_FLASH_BMI_IPV6_BIT_MSK = 0x1UL << 8, /**< Ethernet IP extension contains a IPv6 address */ + XMC_FLASH_BMI_USB_BIT_MAK = 0x1UL << 10, /**< Valid USB Serial Number part of BMI string */ + XMC_FLASH_BMI_PAI_PSRAM_MSK = 0x1UL << 12, /**< Parity of PSRAM to be initialized by SSW */ + XMC_FLASH_BMI_PAI_DSRAM_MSK = 0x1UL << 13, /**< Parity of DSRAM1 to be initialized by SSW */ + XMC_FLASH_BMI_PAI_CMSRAM_MSK = 0x1UL << 14, /**< Parity of DSRAM-Comm to be initialized by SSW */ + XMC_FLASH_BMI_SPEEDUP_BIT_MSK = 0x1UL << 15, /**< Clock Tree of the device to be setup to maximum frequency */ +} XMC_FLASH_BMI_t; + +/** + * BMI String configuration + */ +typedef struct XMC_FLASH_BMI_STRING +{ + uint32_t bmi; /**< See ::XMC_FLASH_BMI_t */ + uint8_t mac_addr[6]; /**< MAC address extension */ + uint8_t ip_extension[16]; /**< Ethernet IP extension */ + uint8_t usb_serial_no[4]; /**< USB Serial Number */ + uint32_t reserved; + uint16_t reserved1; +} XMC_FLASH_BMI_STRING_t; + /********************************************************************************************************************* * API PROTOTYPES ********************************************************************************************************************/ @@ -243,6 +257,46 @@ typedef enum XMC_FLASH_PROTECTION extern "C" { #endif +/** + * + * @param address Pointer to the starting address of flash page from where the programming starts. + * @param data Pointer to the source address where targeted data is located. + * + * @return None + * + * \parDescription:
      + * Programs a single flash page associated with the specified \a address.\n\n XMC4000 flash can be programmed with a + * granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status + * bits inside status register. It starts the write process by issuing the page mode command followed by the load page + * command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page + * command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the + * programming operation.\n + * + * \parNote:
      + * Flash will be busy state during write is ongoing, hence no operations allowed until it completes. + * + * \parRelated APIs:
      + * None + * + */ +void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data); + +/** + * + * @param address Pointer to the starting address of the page to be erased. + * + * @return None + * + * \parDescription:
      + * Erases a sector associated with the specified \a address.\n\n Before erase, it clears the error status bits inside + * FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash + * erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n + * + * \parRelated APIs:
      + * None + */ +void XMC_FLASH_EraseSector(uint32_t *address); + /** * * @param None @@ -454,7 +508,7 @@ __STATIC_INLINE void XMC_FLASH_SetWaitStates(uint32_t num_wait_states) */ __STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void) { - PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk; + PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk; } /** @@ -471,7 +525,7 @@ __STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void) */ __STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void) { - PREF->PCON |= PREF_PCON_IBYP_Msk; + PREF->PCON |= PREF_PCON_IBYP_Msk; } /** @@ -502,6 +556,23 @@ __STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void) } +/** + * @param bmi_string BMI string configuration + * + * @return None + * + * \parDescription:
      + * BMI provides a provision for end user to customize boot sequence. + * A 32 bit BMI word describes a set of activities that must be performed by SSW. + * BMI word along with associated parameters is known as the BMI string. + * The function calculates the XOR checksum of the BMI String. + * Before calling this function the UCB2 should be erased. + * + * \parRelated APIs:
      + * XMC_FLASH_EraseUCB() + */ +void XMC_FLASH_InstallBMI(XMC_FLASH_BMI_STRING_t *const bmi_string); + /** * * @param user ID number of the user configuration block (UCB).
      Range: [0 to 2] @@ -527,7 +598,7 @@ __STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void) */ void XMC_FLASH_InstallProtection(uint8_t user, uint32_t protection_mask, - uint32_t password_0, + uint32_t password_0, uint32_t password_1); /** @@ -546,7 +617,7 @@ void XMC_FLASH_InstallProtection(uint8_t user, * * \parRelated APIs:
      * XMC_FLASH_InstallProtection()
      - * + * */ void XMC_FLASH_ConfirmProtection(uint8_t user); @@ -564,7 +635,7 @@ void XMC_FLASH_ConfirmProtection(uint8_t user); * Resumption of read protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset. * * \parRelated APIs:
      - * XMC_FLASH_InstallProtection()
      + * XMC_FLASH_InstallProtection()
      * XMC_FLASH_VerifyWriteProtection()
      * XMC_FLASH_ResumeProtection()
      */ @@ -589,13 +660,13 @@ bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1); * Resumption of write protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset. * * \parRelated APIs:
      - * XMC_FLASH_InstallProtection()
      + * XMC_FLASH_InstallProtection()
      * XMC_FLASH_VerifyReadProtection()
      * XMC_FLASH_ResumeProtection()
      */ -bool XMC_FLASH_VerifyWriteProtection(uint32_t user, - uint32_t protection_mask, - uint32_t password_0, +bool XMC_FLASH_VerifyWriteProtection(uint32_t user, + uint32_t protection_mask, + uint32_t password_0, uint32_t password_1); /** @@ -606,8 +677,8 @@ bool XMC_FLASH_VerifyWriteProtection(uint32_t user, * * \parDescription:
      * Resumes flash protection as it was configured before.\n\n - * It clears all the disable proection status flags FSR.WPRODISx and FSR.RPRODIS. But FSR.WPRODISx is not - * cleared when corresponding UCBx is not in the “confirmed” state. + * It clears all the disable proection status flags FSR.WPRODISx and FSR.RPRODIS. But FSR.WPRODISx is not + * cleared when corresponding UCBx is not in the ?confirmed? state. * * \parRelated APIs:
      * None @@ -621,10 +692,10 @@ void XMC_FLASH_ResumeProtection(void); * @return None * * \parDescription:
      - * Repairs the physical sector "PS4".\n\n - * For selected devices, Erase Physical Sector can also be used for Sector Soft Repair, depending on the configuration - * of PROCON1.PSR. This command sequence is required to run an EEPROM emulation algorithm that cycles the logical - * sectors S4..S7 of PS4. This command sequence repairs the corrupted logical sectors inside the physical sector due to + * Repairs the physical sector "PS4".\n\n + * For selected devices, Erase Physical Sector can also be used for Sector Soft Repair, depending on the configuration + * of PROCON1.PSR. This command sequence is required to run an EEPROM emulation algorithm that cycles the logical + * sectors S4..S7 of PS4. This command sequence repairs the corrupted logical sectors inside the physical sector due to * interrupted erase operation. * * \parRelated APIs:
      @@ -639,8 +710,8 @@ void XMC_FLASH_RepairPhysicalSector(void); * @return None * * \parDescription:
      - * Erases the physical sector "PSA".\n\n If "PSA" does not point to base address of a correct sector or an unavailable - * sector, it returns SQER. + * Erases the physical sector "PSA".\n\n If "PSA" does not point to base address of a correct sector or an unavailable + * sector, it returns SQER. * * * \parRelated APIs:
      @@ -650,17 +721,17 @@ void XMC_FLASH_ErasePhysicalSector(uint32_t *sector_start_address); /** * - * @param ucb_sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_UCBx MACRO + * @param ucb_sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_UCBx MACRO * defined in xmc4_flash.h file. * * @return None * * \parDescription:
      - * The addressed user configuration block “UCB” is erased.\n\n - * Erases UCB whose startting address specified in the input parameter \a ucb_sector_start_address. When the UCB has - * an active write protection or the Flash module has an active global read protection the execution fails and + * The addressed user configuration block ?UCB? is erased.\n\n + * Erases UCB whose startting address specified in the input parameter \a ucb_sector_start_address. When the UCB has + * an active write protection or the Flash module has an active global read protection the execution fails and * PROER is set. The command fails with SQER when \a ucb_sector_start_address is not the start address of a valid UCB. - * Call \ref XMC_FLASH_GetStatus API after this API to verify the erase was proper ot not. + * Call \ref XMC_FLASH_GetStatus API after this API to verify the erase was proper ot not. * * \parRelated APIs:
      * None @@ -675,8 +746,8 @@ void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address); * * \parDescription:
      * Resets the command interpreter to its initial state.\n\n - * Reset to Read can cancel every command sequence before its last command cycle has been received. All error flags - * gets cleared by calling this API. + * Reset to Read can cancel every command sequence before its last command cycle has been received. All error flags + * gets cleared by calling this API. * \parNote:
      * todo * @@ -695,9 +766,6 @@ void XMC_FLASH_Reset(void); * @} */ -/** - * @} - */ #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_gpio.h b/cores/xmc_lib/XMCLib/inc/xmc4_gpio.h index 46bd003c..4f0c6b36 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_gpio.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_gpio.h @@ -1,50 +1,44 @@ /** * @file xmc4_gpio.h - * @date 2015-10-09 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
      - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2015-10-09: - * - Added PORT MACRO checks and definitions for XMC4800/4700 devices * @endcond + * */ #ifndef XMC4_GPIO_H @@ -60,17 +54,12 @@ #include "xmc4_gpio_map.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup GPIO * @{ */ - /********************************************************************************************************************** * MACROS *********************************************************************************************************************/ @@ -193,7 +182,6 @@ (strength == XMC_GPIO_OUTPUT_STRENGTH_MEDIUM) ||\ (strength == XMC_GPIO_OUTPUT_STRENGTH_WEAK)) - /********************************************************************************************************************** * ENUMS *********************************************************************************************************************/ @@ -235,12 +223,12 @@ typedef enum XMC_GPIO_MODE */ typedef enum XMC_GPIO_OUTPUT_STRENGTH { - XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE = 0x0, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ - XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE = 0x1, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ - XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE = 0x2, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ - XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE = 0x3, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ - XMC_GPIO_OUTPUT_STRENGTH_MEDIUM = 0x4, /**< Defines pad driver mode, for low speed 3.3V LVTTL outputs */ - XMC_GPIO_OUTPUT_STRENGTH_WEAK = 0x7 /**< Defines pad driver mode, low speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE = 0x0U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE = 0x1U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE = 0x2U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE = 0x3U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_MEDIUM = 0x4U, /**< Defines pad driver mode, for low speed 3.3V LVTTL outputs */ + XMC_GPIO_OUTPUT_STRENGTH_WEAK = 0x7U /**< Defines pad driver mode, low speed 3.3V LVTTL outputs */ } XMC_GPIO_OUTPUT_STRENGTH_t; @@ -251,7 +239,8 @@ typedef enum XMC_GPIO_OUTPUT_STRENGTH * Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure. */ -typedef struct XMC_GPIO_PORT { +typedef struct XMC_GPIO_PORT +{ __IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output */ __O uint32_t OMR; /**< The port output modification register contains control bits that make it possible @@ -283,7 +272,6 @@ typedef struct XMC_GPIO_CONFIG XMC_GPIO_OUTPUT_STRENGTH_t output_strength; /**< Defines pad driver mode of a pin */ } XMC_GPIO_CONFIG_t; - /********************************************************************************************************************** * API PROTOTYPES *********************************************************************************************************************/ @@ -310,7 +298,6 @@ __STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) (mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4)); } - /** * * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDR. @@ -329,17 +316,16 @@ __STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode) * * \parNote:
      * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * */ + void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength); /** * @} (end addtogroup GPIO) */ -/** - * @} (end addtogroup XMClib) - */ - #endif /* UC_FAMILY == XMC4 */ #endif /* XMC4_GPIO_H */ + diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_gpio_map.h b/cores/xmc_lib/XMCLib/inc/xmc4_gpio_map.h index a7050443..b0b470a6 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_gpio_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_gpio_map.h @@ -1,69 +1,41 @@ /** * @file xmc4_gpio_map.h - * @date 2016-08-22 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
      - * - * 2015-06-20: - * - Updated copyright information + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-11-12: - * - Added XMC4800 + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-06-20: - * - Missing CAN_N0_TXD connectivity - * - VADC_EMUXn_IN replaced by VADC_EMUX0xy - * - DSD_MCLKOUT replaced by DSD_MCLKx - * - Missing connectivity for XMC48/47 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-12-07: - * - Add XMC4300 support - * - * 2016-03-09: - * - Fixed SDMMC signals names - * - Added P2_0_AF_CAN_N0_TXD for XMC44xx - * - Added P1_9_AF_U0C0_SCLKOUT, P4_7_AF_U2C1_DOUT0, P6_6_AF_U2C0_DOUT0 for XMC47/48 BGA196 - * - * 2016-03-22: - * - Fixed EBU CS signal names - * - * 2016-08-22: - * - Added P2_0_AF_CAN_N0_TXD for XMC4300 + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -1243,9 +1215,12 @@ #define P1_6_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 #define P1_7_AF_ECAT0_P0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 #define P1_7_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_7_AF_U1C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT4 #define P1_8_AF_ECAT0_P0_TXD2 XMC_GPIO_MODE_OUTPUT_ALT1 #define P1_8_AF_U0C0_SELO1 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P1_8_AF_U1C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 #define P1_9_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_9_AF_U1C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 #define P1_10_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 #define P1_10_AF_U0C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 #define P1_10_AF_ECAT0_LED_ERR XMC_GPIO_MODE_OUTPUT_ALT4 @@ -1262,6 +1237,7 @@ #define P1_14_AF_U0C1_SELO2 XMC_GPIO_MODE_OUTPUT_ALT2 #define P1_14_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT4 #define P1_15_AF_SCU_EXTCLK XMC_GPIO_MODE_OUTPUT_ALT1 +#define P1_15_AF_U1C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_0_AF_CAN_N0_TXD XMC_GPIO_MODE_OUTPUT_ALT1 #define P2_0_AF_LEDTS0_COL1 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_1_AF_LEDTS0_COL0 XMC_GPIO_MODE_OUTPUT_ALT4 @@ -1280,6 +1256,7 @@ #define P2_5_AF_U0C1_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 #define P2_5_AF_CCU41_OUT0 XMC_GPIO_MODE_OUTPUT_ALT3 #define P2_5_AF_LEDTS0_LINE3 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P2_6_AF_ERU1_PDOUT3 XMC_GPIO_MODE_OUTPUT_ALT2 #define P2_6_AF_CCU80_OUT13 XMC_GPIO_MODE_OUTPUT_ALT3 #define P2_6_AF_LEDTS0_COL3 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_7_AF_ETH0_MDC XMC_GPIO_MODE_OUTPUT_ALT1 @@ -1287,12 +1264,15 @@ #define P2_7_AF_CCU80_OUT03 XMC_GPIO_MODE_OUTPUT_ALT3 #define P2_7_AF_LEDTS0_COL2 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_8_AF_ETH0_TXD0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_8_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT2 #define P2_8_AF_CCU80_OUT32 XMC_GPIO_MODE_OUTPUT_ALT3 #define P2_8_AF_LEDTS0_LINE4 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_9_AF_ETH0_TXD1 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_9_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT2 #define P2_9_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 #define P2_9_AF_LEDTS0_LINE5 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_10_AF_VADC_EMUX10 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P2_10_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT2 #define P2_10_AF_ECAT0_PHY_RESET XMC_GPIO_MODE_OUTPUT_ALT3 #define P2_10_AF_ECAT0_SYNC1 XMC_GPIO_MODE_OUTPUT_ALT4 #define P2_11_AF_CCU80_OUT22 XMC_GPIO_MODE_OUTPUT_ALT3 @@ -1319,10 +1299,14 @@ #define P3_6_AF_U1C1_SELO4 XMC_GPIO_MODE_OUTPUT_ALT2 #define P3_6_AF_U0C1_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 #define P4_0_AF_ECAT0_PHY_CLK25 XMC_GPIO_MODE_OUTPUT_ALT2 +#define P4_0_AF_U1C0_SCLKOUT XMC_GPIO_MODE_OUTPUT_ALT4 #define P4_1_AF_U1C1_MCLKOUT XMC_GPIO_MODE_OUTPUT_ALT2 #define P4_1_AF_U0C1_SELO0 XMC_GPIO_MODE_OUTPUT_ALT4 +#define P5_0_AF_ERU1_PDOUT0 XMC_GPIO_MODE_OUTPUT_ALT4 #define P5_1_AF_U0C0_DOUT0 XMC_GPIO_MODE_OUTPUT_ALT1 +#define P5_1_AF_ERU1_PDOUT1 XMC_GPIO_MODE_OUTPUT_ALT4 #define P5_2_AF_ECAT0_P0_LED_LINK_ACT XMC_GPIO_MODE_OUTPUT_ALT2 +#define P5_2_AF_ERU1_PDOUT2 XMC_GPIO_MODE_OUTPUT_ALT4 #define P5_7_AF_ECAT0_SYNC0 XMC_GPIO_MODE_OUTPUT_ALT1 #define P5_7_AF_LEDTS0_COLA XMC_GPIO_MODE_OUTPUT_ALT4 diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_rtc.h b/cores/xmc_lib/XMCLib/inc/xmc4_rtc.h index a4ef8f3d..44456d60 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_rtc.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_rtc.h @@ -1,58 +1,49 @@ /** * @file xmc4_rtc.h - * @date 2015-05-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial - * - * 2015-05-20: - * - Documentation updates
      - * - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ #ifndef XMC4_RTC_H #define XMC4_RTC_H -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup RTC @@ -94,10 +85,10 @@ extern "C" { * Enable Wakeup from hibernate mode
      * * \par - * The function sets the bitfields of CTR register to enable wakeup from hibernate mode. - * Setting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t + * The function sets the bitfields of CTR register to enable wakeup from hibernate mode. + * Setting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t * leads to a wakeup from hibernate mode. - * + * * \parRelated APIs:
      * XMC_RTC_DisableHibernationWakeUp() */ @@ -105,17 +96,17 @@ void XMC_RTC_EnableHibernationWakeUp(const uint32_t event); /** * @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of - * logically OR'd events + * logically OR'd events * @return None * * \parDescription:
      * Disable Wakeup from hibernate mode
      * * \par - * The function resets the bitfields of CTR register to disable wakeup from hibernate mode. - * Resetting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t + * The function resets the bitfields of CTR register to disable wakeup from hibernate mode. + * Resetting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t * disables wakeup from hibernate mode. - * + * * \parRelated APIs:
      * XMC_RTC_EnableHibernationWakeUp() */ @@ -129,8 +120,5 @@ void XMC_RTC_DisableHibernationWakeUp(const uint32_t event); * @} */ -/** - * @} - */ #endif /* XMC4_RTC_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_scu.h b/cores/xmc_lib/XMCLib/inc/xmc4_scu.h index 6c19fd04..86a1d757 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_scu.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_scu.h @@ -1,81 +1,43 @@ /** * @file xmc4_scu.h - * @date 2016-06-15 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-06-20: - * - Initial version - * - Documentation improved - * - * 2015-11-30: - * - Documentation improved - * - * 2016-03-09: - * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor - * XMC_SCU_POWER_GetEVRStatus, XMC_SCU_POWER_GetEVR13Voltage, XMC_SCU_POWER_GetEVR33Voltage - * - Added XMC_SCU_HIB_GetHibernateControlStatus, - * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent, - * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent - * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel, - * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState - * - * 2016-04-15: - * - Fixed naming of XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG peripheral clock. - * Added enable and disable for peripheral clocks - * - * 2016-05-19: - * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() - * - Added XMC_SCU_POWER_WaitForInterrupt() and XMC_SCU_POWER_WaitForEvent() - * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus() - * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus() - * - Removed XMC_SCU_INTERRUPT_EVENT_OSCULSTAT_UPDATED, XMC_SCU_INTERRUPT_EVENT_HDSTAT_UPDATED - * - * 2016-06-14: - * - Added XMC_SCU_HIB_IsWakeupEventDetected() and XMC_SCU_HIB_ClearWakeupEventDetectionStatus() - * - * 2016-06-15: - * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series. - * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series. - * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series. - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -90,11 +52,7 @@ #if UC_FAMILY == XMC4 -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - + /** * @addtogroup SCU * @{ @@ -194,29 +152,29 @@ typedef enum XMC_SCU_CCU_TRIGGER } XMC_SCU_CCU_TRIGGER_t; /** - * Defines enumerations representing the status of trap cause. The cause of the trap gets automatically stored in + * Defines enumerations representing the status of trap cause. The cause of the trap gets automatically stored in * the \a TRAPSTAT register and can be checked by user software to determine the state of the system and for debug - * purpose. + * purpose. * Use type \a XMC_SCU_TRAP_t for accessing these enum parameters. */ -typedef enum XMC_SCU_TRAP +typedef enum XMC_SCU_TRAP { XMC_SCU_TRAP_OSC_WDG = SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk, /**< OSC_HP Oscillator Watchdog trap. */ XMC_SCU_TRAP_VCO_LOCK = SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk, /**< PLL loss of lock trap. */ - XMC_SCU_TRAP_USB_VCO_LOCK = SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk, /**< USB PLL loss of lock trap. */ - XMC_SCU_TRAP_PARITY_ERROR = SCU_TRAP_TRAPSTAT_PET_Msk, /**< Memory Parity error trap. */ - XMC_SCU_TRAP_BROWNOUT = SCU_TRAP_TRAPSTAT_BRWNT_Msk, /**< Brownout trap. */ - XMC_SCU_TRAP_ULP_WDG = SCU_TRAP_TRAPSTAT_ULPWDGT_Msk, /**< Unstable 32KHz clock trap. */ - XMC_SCU_TRAP_PER_BRIDGE0 = SCU_TRAP_TRAPSTAT_BWERR0T_Msk, /**< Bad memory access of peripherals on Bridge-0. */ - XMC_SCU_TRAP_PER_BRIDGE1 = SCU_TRAP_TRAPSTAT_BWERR1T_Msk, /**< Bad memory access of peripherals on Bridge-1. */ + XMC_SCU_TRAP_USB_VCO_LOCK = SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk, /**< USB PLL loss of lock trap. */ + XMC_SCU_TRAP_PARITY_ERROR = SCU_TRAP_TRAPSTAT_PET_Msk, /**< Memory Parity error trap. */ + XMC_SCU_TRAP_BROWNOUT = SCU_TRAP_TRAPSTAT_BRWNT_Msk, /**< Brownout trap. */ + XMC_SCU_TRAP_ULP_WDG = SCU_TRAP_TRAPSTAT_ULPWDGT_Msk, /**< Unstable 32KHz clock trap. */ + XMC_SCU_TRAP_PER_BRIDGE0 = SCU_TRAP_TRAPSTAT_BWERR0T_Msk, /**< Bad memory access of peripherals on Bridge-0. */ + XMC_SCU_TRAP_PER_BRIDGE1 = SCU_TRAP_TRAPSTAT_BWERR1T_Msk, /**< Bad memory access of peripherals on Bridge-1. */ #if defined(SCU_TRAP_TRAPSTAT_TEMPHIT_Msk) - XMC_SCU_TRAP_DIETEMP_HIGH = SCU_TRAP_TRAPSTAT_TEMPHIT_Msk, /**< Die temperature higher than expected. */ + XMC_SCU_TRAP_DIETEMP_HIGH = SCU_TRAP_TRAPSTAT_TEMPHIT_Msk, /**< Die temperature higher than expected. */ #endif #if defined(SCU_TRAP_TRAPSTAT_TEMPLOT_Msk) - XMC_SCU_TRAP_DIETEMP_LOW = SCU_TRAP_TRAPSTAT_TEMPLOT_Msk, /**< Die temperature lower than expected. */ + XMC_SCU_TRAP_DIETEMP_LOW = SCU_TRAP_TRAPSTAT_TEMPLOT_Msk, /**< Die temperature lower than expected. */ #endif #if defined(ECAT0) - XMC_SCU_TRAP_ECAT_RESET = SCU_TRAP_TRAPSTAT_ECAT0RST_Msk, /**< EtherCat Reset */ + XMC_SCU_TRAP_ECAT_RESET = SCU_TRAP_TRAPSTAT_ECAT0RST_Msk, /**< EtherCat Reset */ #endif } XMC_SCU_TRAP_t; @@ -229,37 +187,40 @@ typedef enum XMC_SCU_TRAP */ typedef enum XMC_SCU_PARITY { - XMC_SCU_PARITY_PSRAM_MEM = SCU_PARITY_PEEN_PEENPS_Msk, /**< Program SRAM parity error trap. */ - XMC_SCU_PARITY_DSRAM1_MEM = SCU_PARITY_PEEN_PEENDS1_Msk, /**< Data SRAM-1 parity error trap. */ -#if defined(XMC_SCU_PARITY_DSRAM2_MEM) - XMC_SCU_PARITY_DSRAM2_MEM = SCU_PARITY_PEEN_PEENDS2_Msk, /**< Data SRAM-2 parity error trap. */ + XMC_SCU_PARITY_PSRAM_MEM = SCU_PARITY_PEEN_PEENPS_Msk, /**< Program SRAM parity error trap. */ + XMC_SCU_PARITY_DSRAM1_MEM = SCU_PARITY_PEEN_PEENDS1_Msk, /**< Data SRAM-1 parity error trap. */ +#if defined(SCU_PARITY_PEEN_PEENDS2_Msk) + XMC_SCU_PARITY_DSRAM2_MEM = SCU_PARITY_PEEN_PEENDS2_Msk, /**< Data SRAM-2 parity error trap. */ #endif - XMC_SCU_PARITY_USIC0_MEM = SCU_PARITY_PEEN_PEENU0_Msk, /**< USIC0 memory parity error trap. */ -#if defined(XMC_SCU_PARITY_USIC1_MEM) - XMC_SCU_PARITY_USIC1_MEM = SCU_PARITY_PEEN_PEENU1_Msk, /**< USIC1 memory parity error trap. */ + XMC_SCU_PARITY_USIC0_MEM = SCU_PARITY_PEEN_PEENU0_Msk, /**< USIC0 memory parity error trap. */ +#if defined(SCU_PARITY_PEEN_PEENU1_Msk) + XMC_SCU_PARITY_USIC1_MEM = SCU_PARITY_PEEN_PEENU1_Msk, /**< USIC1 memory parity error trap. */ #endif -#if defined(XMC_SCU_PARITY_USIC2_MEM) - XMC_SCU_PARITY_USIC2_MEM = SCU_PARITY_PEEN_PEENU2_Msk, /**< USIC2 memory parity error trap. */ +#if defined(SCU_PARITY_PEEN_PEENU2_Msk) + XMC_SCU_PARITY_USIC2_MEM = SCU_PARITY_PEEN_PEENU2_Msk, /**< USIC2 memory parity error trap. */ #endif XMC_SCU_PARITY_MCAN_MEM = SCU_PARITY_PEEN_PEENMC_Msk, /**< CAN memory parity error trap. */ - XMC_SCU_PARITY_PMU_MEM = SCU_PARITY_PEEN_PEENPPRF_Msk, /**< PMU Prefetch memory parity error trap. */ - XMC_SCU_PARITY_USB_MEM = SCU_PARITY_PEEN_PEENUSB_Msk, /**< USB memory parity error trap. */ + XMC_SCU_PARITY_PMU_MEM = SCU_PARITY_PEEN_PEENPPRF_Msk, /**< PMU Prefetch memory parity error trap. */ + XMC_SCU_PARITY_USB_MEM = SCU_PARITY_PEEN_PEENUSB_Msk, /**< USB memory parity error trap. */ #if defined(SCU_PARITY_PEEN_PEENETH0TX_Msk) - XMC_SCU_PARITY_ETH_TXMEM = SCU_PARITY_PEEN_PEENETH0TX_Msk, /**< Ethernet transmit memory parity error trap. */ + XMC_SCU_PARITY_ETH_TXMEM = SCU_PARITY_PEEN_PEENETH0TX_Msk, /**< Ethernet transmit memory parity error trap. */ #endif #if defined(SCU_PARITY_PEEN_PEENETH0RX_Msk) - XMC_SCU_PARITY_ETH_RXMEM = SCU_PARITY_PEEN_PEENETH0RX_Msk, /**< Ethernet receive memory parity error trap. */ + XMC_SCU_PARITY_ETH_RXMEM = SCU_PARITY_PEEN_PEENETH0RX_Msk, /**< Ethernet receive memory parity error trap. */ #endif #if defined(SCU_PARITY_PEEN_PEENSD0_Msk) - XMC_SCU_PARITY_SDMMC_MEM0 = SCU_PARITY_PEEN_PEENSD0_Msk, /**< SDMMC Memory-0 parity error trap. */ + XMC_SCU_PARITY_SDMMC_MEM0 = SCU_PARITY_PEEN_PEENSD0_Msk, /**< SDMMC Memory-0 parity error trap. */ #endif #if defined(SCU_PARITY_PEEN_PEENSD1_Msk) - XMC_SCU_PARITY_SDMMC_MEM1 = SCU_PARITY_PEEN_PEENSD1_Msk, /**< SDMMC Memory-1 parity error trap. */ + XMC_SCU_PARITY_SDMMC_MEM1 = SCU_PARITY_PEEN_PEENSD1_Msk, /**< SDMMC Memory-1 parity error trap. */ +#endif +#if defined(SCU_PARITY_PEEN_PEENECAT0_Msk) + XMC_SCU_PARITY_ECAT_MEM = SCU_PARITY_PEEN_PEENECAT0_Msk, /**< ECAT0 SRAM parity error trap. */ #endif } XMC_SCU_PARITY_t; /** - * Defines the different causes for last reset. The cause of the last reset gets automatically stored in + * Defines the different causes for last reset. The cause of the last reset gets automatically stored in * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debuggging * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register. * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters. @@ -276,13 +237,13 @@ typedef enum XMC_SCU_RESET_REASON } XMC_SCU_RESET_REASON_t; /** - * Defines enumerations for events which can lead to interrupt. These enumeration values represent the - * status of one of the bits in \a SRSTAT register. + * Defines enumerations for events which can lead to interrupt. These enumeration values represent the + * status of one of the bits in \a SRSTAT register. * Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. */ typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t; - + /** * Defines enumeration for the events that can generate non maskable interrupt(NMI). * The NMI generation can be enabled with \a NMIREQEN register. The event will be reflected in \a SRSTAT or will be @@ -293,15 +254,15 @@ typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t; */ typedef enum XMC_SCU_NMIREQ { - XMC_SCU_NMIREQ_WDT_WARN = SCU_INTERRUPT_NMIREQEN_PRWARN_Msk, /**< Watchdog timer Pre-Warning event */ - XMC_SCU_NMIREQ_RTC_PI = SCU_INTERRUPT_NMIREQEN_PI_Msk, /**< RTC Periodic event */ - XMC_SCU_NMIREQ_RTC_AI = SCU_INTERRUPT_NMIREQEN_AI_Msk, /**< RTC Alarm event */ - XMC_SCU_NMIREQ_ERU0_0 = SCU_INTERRUPT_NMIREQEN_ERU00_Msk, /**< Channel 0 event of ERU0 */ - XMC_SCU_NMIREQ_ERU0_1 = SCU_INTERRUPT_NMIREQEN_ERU01_Msk, /**< Channel 1 event of ERU0 */ - XMC_SCU_NMIREQ_ERU0_2 = SCU_INTERRUPT_NMIREQEN_ERU02_Msk, /**< Channel 2 event of ERU0 */ - XMC_SCU_NMIREQ_ERU0_3 = SCU_INTERRUPT_NMIREQEN_ERU03_Msk /**< Channel 3 event of ERU0 */ + XMC_SCU_NMIREQ_WDT_WARN = SCU_INTERRUPT_NMIREQEN_PRWARN_Msk, /**< Watchdog timer Pre-Warning event */ + XMC_SCU_NMIREQ_RTC_PI = SCU_INTERRUPT_NMIREQEN_PI_Msk, /**< RTC Periodic event */ + XMC_SCU_NMIREQ_RTC_AI = SCU_INTERRUPT_NMIREQEN_AI_Msk, /**< RTC Alarm event */ + XMC_SCU_NMIREQ_ERU0_0 = SCU_INTERRUPT_NMIREQEN_ERU00_Msk, /**< Channel 0 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_1 = SCU_INTERRUPT_NMIREQEN_ERU01_Msk, /**< Channel 1 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_2 = SCU_INTERRUPT_NMIREQEN_ERU02_Msk, /**< Channel 2 event of ERU0 */ + XMC_SCU_NMIREQ_ERU0_3 = SCU_INTERRUPT_NMIREQEN_ERU03_Msk /**< Channel 3 event of ERU0 */ } XMC_SCU_NMIREQ_t; - + /** * Defines enumeration representing different peripheral reset bits in the \a PRSTAT registers. @@ -312,26 +273,26 @@ typedef enum XMC_SCU_NMIREQ */ typedef enum XMC_SCU_PERIPHERAL_RESET { - XMC_SCU_PERIPHERAL_RESET_VADC = SCU_RESET_PRSTAT0_VADCRS_Msk, /**< VADC reset. */ + XMC_SCU_PERIPHERAL_RESET_VADC = SCU_RESET_PRSTAT0_VADCRS_Msk, /**< VADC reset. */ #if defined(DSD) XMC_SCU_PERIPHERAL_RESET_DSD = SCU_RESET_PRSTAT0_DSDRS_Msk, /**< DSD reset. */ #endif XMC_SCU_PERIPHERAL_RESET_CCU40 = SCU_RESET_PRSTAT0_CCU40RS_Msk, /**< CCU40 reset. */ #if defined(CCU41) XMC_SCU_PERIPHERAL_RESET_CCU41 = SCU_RESET_PRSTAT0_CCU41RS_Msk, /**< CCU41 reset. */ -#endif +#endif #if defined(CCU42) XMC_SCU_PERIPHERAL_RESET_CCU42 = SCU_RESET_PRSTAT0_CCU42RS_Msk, /**< CCU42 reset. */ #endif #if defined(CCU80) XMC_SCU_PERIPHERAL_RESET_CCU80 = SCU_RESET_PRSTAT0_CCU80RS_Msk, /**< CCU80 reset. */ -#endif +#endif #if defined(CCU81) XMC_SCU_PERIPHERAL_RESET_CCU81 = SCU_RESET_PRSTAT0_CCU81RS_Msk, /**< CCU81 reset. */ #endif #if defined(POSIF0) XMC_SCU_PERIPHERAL_RESET_POSIF0 = SCU_RESET_PRSTAT0_POSIF0RS_Msk, /**< POSIF0 reset. */ -#endif +#endif #if defined(POSIF1) XMC_SCU_PERIPHERAL_RESET_POSIF1 = SCU_RESET_PRSTAT0_POSIF1RS_Msk, /**< POSIF1 reset.*/ #endif @@ -345,19 +306,19 @@ typedef enum XMC_SCU_PERIPHERAL_RESET #endif #if defined(LEDTS0) XMC_SCU_PERIPHERAL_RESET_LEDTS0 = (SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk | 0x10000000UL), /**< LEDTS0 reset. */ -#endif -#if defined(CAN) +#endif +#if defined(CAN_xmc) XMC_SCU_PERIPHERAL_RESET_MCAN = (SCU_RESET_PRSTAT1_MCAN0RS_Msk | 0x10000000UL), /**< MCAN reset. */ -#endif -#if defined(DAC) +#endif +#if defined(DAC) XMC_SCU_PERIPHERAL_RESET_DAC = (SCU_RESET_PRSTAT1_DACRS_Msk | 0x10000000UL), /**< DAC reset. */ -#endif +#endif #if defined(SDMMC) XMC_SCU_PERIPHERAL_RESET_SDMMC = (SCU_RESET_PRSTAT1_MMCIRS_Msk | 0x10000000UL), /**< SDMMC reset. */ #endif #if defined(USIC1) XMC_SCU_PERIPHERAL_RESET_USIC1 = (SCU_RESET_PRSTAT1_USIC1RS_Msk | 0x10000000UL), /**< USIC1 reset. */ -#endif +#endif #if defined(USIC2) XMC_SCU_PERIPHERAL_RESET_USIC2 = (SCU_RESET_PRSTAT1_USIC2RS_Msk | 0x10000000UL), /**< USIC2 reset. */ #endif @@ -373,12 +334,12 @@ typedef enum XMC_SCU_PERIPHERAL_RESET #if defined(FCE) XMC_SCU_PERIPHERAL_RESET_FCE = (SCU_RESET_PRSTAT2_FCERS_Msk | 0x20000000UL), /**< FCE reset. */ #endif -#if defined(USB0) +#if defined(USB0) XMC_SCU_PERIPHERAL_RESET_USB0 = (SCU_RESET_PRSTAT2_USBRS_Msk | 0x20000000UL), /**< USB0 reset. */ -#endif -#if defined(ECAT0) +#endif +#if defined(ECAT0) XMC_SCU_PERIPHERAL_RESET_ECAT0 = (SCU_RESET_PRSTAT2_ECAT0RS_Msk | 0x20000000UL), /**< ECAT0 reset. */ -#endif +#endif #if defined(EBU) XMC_SCU_PERIPHERAL_RESET_EBU = (SCU_RESET_PRSTAT3_EBURS_Msk | 0x30000000UL) /**< EBU reset. */ #endif @@ -407,7 +368,7 @@ typedef enum XMC_SCU_CLOCK #if(UC_SERIES != XMC45) /** - * Defines enumeration for peripherals that support clock gating. + * Defines enumeration for peripherals that support clock gating. * The enumerations can be used for gating or ungating the peripheral clocks. * All the enum items are tabulated as per bits present in \a CGATSTAT0 register. * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters. @@ -421,19 +382,19 @@ typedef enum XMC_SCU_PERIPHERAL_CLOCK XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral gating. */ #if defined(CCU41) XMC_SCU_PERIPHERAL_CLOCK_CCU41 = SCU_CLK_CGATSTAT0_CCU41_Msk, /**< CCU41 peripheral gating. */ -#endif +#endif #if defined(CCU42) XMC_SCU_PERIPHERAL_CLOCK_CCU42 = SCU_CLK_CGATSTAT0_CCU42_Msk, /**< CCU42 peripheral gating. */ #endif #if defined(CCU80) XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral gating. */ -#endif +#endif #if defined(CCU81) XMC_SCU_PERIPHERAL_CLOCK_CCU81 = SCU_CLK_CGATSTAT0_CCU81_Msk, /**< CCU81 peripheral gating. */ #endif #if defined(POSIF0) XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral gating. */ -#endif +#endif #if defined(POSIF1) XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF1 peripheral gating. */ #endif @@ -447,19 +408,19 @@ typedef enum XMC_SCU_PERIPHERAL_CLOCK #endif #if defined(LEDTS0) XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = (SCU_CLK_CGATSTAT1_LEDTSCU0_Msk | 0x10000000UL), /**< LEDTS0 peripheral gating. */ -#endif -#if defined(CAN) +#endif +#if defined(CAN_xmc) XMC_SCU_PERIPHERAL_CLOCK_MCAN = (SCU_CLK_CGATSTAT1_MCAN0_Msk | 0x10000000UL), /**< MCAN peripheral gating. */ #endif -#if defined(DAC) +#if defined(DAC) XMC_SCU_PERIPHERAL_CLOCK_DAC = (SCU_CLK_CGATSTAT1_DAC_Msk | 0x10000000UL), /**< DAC peripheral gating. */ -#endif +#endif #if defined(SDMMC) XMC_SCU_PERIPHERAL_CLOCK_SDMMC = (SCU_CLK_CGATSTAT1_MMCI_Msk | 0x10000000UL), /**< SDMMC peripheral gating. */ #endif #if defined(USIC1) XMC_SCU_PERIPHERAL_CLOCK_USIC1 = (SCU_CLK_CGATSTAT1_USIC1_Msk | 0x10000000UL), /**< USIC1 peripheral gating. */ -#endif +#endif #if defined(USIC2) XMC_SCU_PERIPHERAL_CLOCK_USIC2 = (SCU_CLK_CGATSTAT1_USIC2_Msk | 0x10000000UL), /**< USIC2 peripheral gating. */ #endif @@ -474,13 +435,13 @@ typedef enum XMC_SCU_PERIPHERAL_CLOCK #endif #if defined(FCE) XMC_SCU_PERIPHERAL_CLOCK_FCE = (SCU_CLK_CGATSTAT2_FCE_Msk | 0x20000000UL), /**< FCE peripheral gating. */ -#endif +#endif #if defined(USB0) XMC_SCU_PERIPHERAL_CLOCK_USB0 = (SCU_CLK_CGATSTAT2_USB_Msk | 0x20000000UL), /**< USB0 peripheral gating. */ -#endif +#endif #if defined(ECAT0) XMC_SCU_PERIPHERAL_CLOCK_ECAT0 = (SCU_CLK_CGATSTAT2_ECAT0_Msk | 0x20000000UL), /**< ECAT0 peripheral gating. */ -#endif +#endif #if defined(EBU) XMC_SCU_PERIPHERAL_CLOCK_EBU = (SCU_CLK_CGATSTAT3_EBU_Msk | 0x30000000UL) /**< EBU peripheral gating. */ #endif @@ -489,12 +450,12 @@ typedef enum XMC_SCU_PERIPHERAL_CLOCK /** * Defines options for system clock (fSYS) source. These enums are used to configure \a SYSSEL bits of \a SYSCLKCR - * Clock Control Register. + * Clock Control Register. * Use type \a XMC_SCU_CLOCK_SYSCLKSRC_t for accessing these enum parameters. - */ + */ typedef enum XMC_SCU_CLOCK_SYSCLKSRC { - XMC_SCU_CLOCK_SYSCLKSRC_OFI = (0UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos), /**< Internal Fast Clock (fOFI) as a + XMC_SCU_CLOCK_SYSCLKSRC_OFI = (0UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos), /**< Internal Fast Clock (fOFI) as a source for system clock (fSYS). */ XMC_SCU_CLOCK_SYSCLKSRC_PLL = (1UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos) /**< PLL output (fPLL) as a source for system clock (fSYS). */ @@ -502,9 +463,9 @@ typedef enum XMC_SCU_CLOCK_SYSCLKSRC /** * Defines options for selecting the P-Divider input frequency. These enums are used to configure \a PINSEL bits of \a PLLCON2 - * register. + * register. * Use type \a XMC_SCU_CLOCK_OSCCLKSRC_t for accessing these enum parameters. - */ + */ typedef enum XMC_SCU_CLOCK_SYSPLLCLKSRC { XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP = 0UL, /**< External crystal oscillator @@ -516,21 +477,21 @@ typedef enum XMC_SCU_CLOCK_SYSPLLCLKSRC /** * Defines options for selecting the USB clock source(fUSB/fSDMMC). * These enums are used to configure \a USBSEL bits of \a USBCLKCR - * register. User can choose either fPLL or fUSBPLL clock as a source for USB clock. + * register. User can choose either fPLL or fUSBPLL clock as a source for USB clock. * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters. - */ + */ typedef enum XMC_SCU_CLOCK_USBCLKSRC { - XMC_SCU_CLOCK_USBCLKSRC_USBPLL = (0UL << SCU_CLK_USBCLKCR_USBSEL_Pos), /**< USB PLL(fUSB PLL) as a + XMC_SCU_CLOCK_USBCLKSRC_USBPLL = (0UL << SCU_CLK_USBCLKCR_USBSEL_Pos), /**< USB PLL(fUSB PLL) as a source for USB clock (fUSB/fSDMMC). */ XMC_SCU_CLOCK_USBCLKSRC_SYSPLL = (1UL << SCU_CLK_USBCLKCR_USBSEL_Pos) /**< Main PLL output (fPLL) as a source for USB clock (fUSB/fSDMMC). */ } XMC_SCU_CLOCK_USBCLKSRC_t; -#if defined(ECAT0) +#if defined(ECAT0) /** * Defines options for selecting the ECAT clock source. - */ + */ typedef enum XMC_SCU_CLOCK_ECATCLKSRC { XMC_SCU_CLOCK_ECATCLKSRC_USBPLL = (0UL << SCU_CLK_ECATCLKCR_ECATSEL_Pos), /**< USB PLL (fUSBPLL) as a source for ECAT clock. */ @@ -540,14 +501,14 @@ typedef enum XMC_SCU_CLOCK_ECATCLKSRC /** * Defines options for selecting the source of WDT clock(fWDT). These enums are used to configure \a WDTSEL bits of \a WDTCLKCR - * register. User can choose either fOFI or fPLL or fSTDBY clock as a source for WDT clock. + * register. User can choose either fOFI or fPLL or fSTDBY clock as a source for WDT clock. * Use type \a XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters. - */ + */ typedef enum XMC_SCU_CLOCK_WDTCLKSRC { - XMC_SCU_CLOCK_WDTCLKSRC_OFI = (0UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Internal Fast Clock + XMC_SCU_CLOCK_WDTCLKSRC_OFI = (0UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Internal Fast Clock (fOFI) as the source for WDT clock (fWDT). */ - XMC_SCU_CLOCK_WDTCLKSRC_STDBY = (1UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Standby clock + XMC_SCU_CLOCK_WDTCLKSRC_STDBY = (1UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos), /**< Standby clock (fSTDBY) as the source for WDT clock (fWDT). */ XMC_SCU_CLOCK_WDTCLKSRC_PLL = (2UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos) /**< PLL output (fPLL) as the source for WDT clock (fWDT). */ @@ -557,7 +518,7 @@ typedef enum XMC_SCU_CLOCK_WDTCLKSRC * Defines options for selecting the source of external clock out (fEXT). These enums are used to configure \a ECKSEL bits of \a EXTCLKCR * register. User can choose either fSYS or fPLL or fUSBPLL clock as a source for external clock out (fEXT). * Use type \a XMC_SCU_CLOCK_EXTOUTCLKSRC_t for accessing these enum parameters. - */ + */ typedef enum XMC_SCU_CLOCK_EXTOUTCLKSRC { XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS = (0UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos), /**< System clock (fSYS) as @@ -592,7 +553,7 @@ typedef enum XMC_SCU_HIB_RTCCLKSRC */ typedef enum XMC_SCU_HIB_STDBYCLKSRC { - XMC_SCU_HIB_STDBYCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos), /**< Internal Slow Clock + XMC_SCU_HIB_STDBYCLKSRC_OSI = (0UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos), /**< Internal Slow Clock (fOSI) as the source for Standby Clock (fSTDBY). */ XMC_SCU_HIB_STDBYCLKSRC_OSCULP = (1UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos) /**< Ultra Low Power Clock @@ -606,7 +567,7 @@ typedef enum XMC_SCU_HIB_STDBYCLKSRC */ typedef enum XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE { - XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY = 0UL, /**< Factory Oscillator Calibration: + XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY = 0UL, /**< Factory Oscillator Calibration: Force adjustment of the internal oscillator with the firmware defined values.*/ XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC = 1UL /**< Automatic Oscillator Calibration adjustment of the fOFI clock with fSTDBY clock. */ } XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t; @@ -617,19 +578,19 @@ typedef enum XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE * User can choose among various boot modes by configuring SWCON bits. * Use type \a XMC_SCU_BOOTMODE_t for accessing these enum parameters. */ -typedef enum XMC_SCU_BOOTMODE +typedef enum XMC_SCU_BOOTMODE { XMC_SCU_BOOTMODE_NORMAL = (0UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from start of flash. */ XMC_SCU_BOOTMODE_ASC_BSL = (1UL << SCU_GENERAL_STCON_SWCON_Pos), /**< UART bootstrap. */ - XMC_SCU_BOOTMODE_BMI = (2UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot Mode Index - Customized boot + XMC_SCU_BOOTMODE_BMI = (2UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot Mode Index - Customized boot sequence. */ XMC_SCU_BOOTMODE_CAN_BSL = (3UL << SCU_GENERAL_STCON_SWCON_Pos), /**< CAN bootstrap. */ XMC_SCU_BOOTMODE_PSRAM_BOOT = (4UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from PSRAM. */ XMC_SCU_BOOTMODE_ABM0 = (8UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative address 0. */ - XMC_SCU_BOOTMODE_ABM1 = (12UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative + XMC_SCU_BOOTMODE_ABM1 = (12UL << SCU_GENERAL_STCON_SWCON_Pos), /**< Boot from flash - fixed alternative address 1. */ - XMC_SCU_BOOTMODE_FABM = (14UL << SCU_GENERAL_STCON_SWCON_Pos), /**< fallback Alternate Boot Mode (ABM) - + XMC_SCU_BOOTMODE_FABM = (14UL << SCU_GENERAL_STCON_SWCON_Pos), /**< fallback Alternate Boot Mode (ABM) - Try ABM-0 then try ABM-1. */ } XMC_SCU_BOOTMODE_t; @@ -646,19 +607,19 @@ typedef enum XMC_SCU_CLOCK_SYSPLL_MODE XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR /**< fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed). */ } XMC_SCU_CLOCK_SYSPLL_MODE_t; -/** +/** * Defines the source of the system clock and peripherals clock gating in SLEEP state. * Use this enum as parameter of XMC_SCU_CLOCK_SetSleepConfig before going to SLEEP state. * * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is - * stopped. Peripherals are only clocked when configured to stay enabled. + * stopped. Peripherals are only clocked when configured to stay enabled. * * Peripherals can continue to operate unaffected and eventually generate an event to * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP * state. - * + * */ typedef enum XMC_SCU_CLOCK_SLEEP_MODE_CONFIG { @@ -667,36 +628,36 @@ typedef enum XMC_SCU_CLOCK_SLEEP_MODE_CONFIG #if defined(USB0) XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_SLEEPCR_USBCR_Msk, /**< USB clock enabled in SLEEP state */ -#endif +#endif #if defined(SDMMC) XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_SLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in SLEEP state */ -#endif +#endif #if defined(ETH0) XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_SLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in SLEEP state */ -#endif +#endif #if defined(EBU) XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_SLEEPCR_EBUCR_Msk, /**< EBU clock enabled in SLEEP state */ -#endif +#endif XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU = 0, /**< CCU clock disabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_SLEEPCR_CCUCR_Msk, /**< CCU clock enabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT = 0, /**< WDT clock disabled in SLEEP state */ XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_SLEEPCR_WDTCR_Msk, /**< WDT clock enabled in SLEEP state */ } XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t; -/** +/** * Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. * In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. * Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state. * * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is - * stopped. + * stopped. * * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked - * by a free-running clock. Peripherals are only clocked when configured to stay enabled. + * by a free-running clock. Peripherals are only clocked when configured to stay enabled. * Configuration of peripherals and any SRAM content is preserved. * The Flash module can be put into low-power mode to achieve a further power reduction. * On wake-up Flash module will be restarted again before instructions or data access is possible. @@ -713,26 +674,26 @@ typedef enum XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG #if defined(USB0) XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB = 0, /**< USB clock disabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB = SCU_CLK_DSLEEPCR_USBCR_Msk, /**< USB clock enabled in DEEPSLEEP state */ -#endif +#endif #if defined(SDMMC) XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC = 0,/**< SDMMC clock disabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC = SCU_CLK_DSLEEPCR_MMCCR_Msk,/**< SDMMC clock enabled in DEEPSLEEP state */ -#endif +#endif #if defined(ETH0) XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH = 0, /**< ETH clock disabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH = SCU_CLK_DSLEEPCR_ETH0CR_Msk, /**< ETH clock enabled in DEEPSLEEP state */ -#endif +#endif #if defined(EBU) XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU = 0, /**< EBU clock disabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU = SCU_CLK_DSLEEPCR_EBUCR_Msk, /**< EBU clock enabled in DEEPSLEEP state */ -#endif +#endif XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU = 0, /**< CCU clock disabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU = SCU_CLK_DSLEEPCR_CCUCR_Msk, /**< CCU clock enabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT = 0, /**< WDT clock disabled in DEEPSLEEP state */ XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT = SCU_CLK_DSLEEPCR_WDTCR_Msk, /**< WDT clock enabled in DEEPSLEEP state */ } XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t; -/** +/** * Defines status of EVR13 regulator */ typedef enum XMC_SCU_POWER_EVR_STATUS @@ -742,7 +703,7 @@ typedef enum XMC_SCU_POWER_EVR_STATUS } XMC_SCU_POWER_EVR_STATUS_t; /** - * Define status of external hibernate control + * Define status of external hibernate control */ typedef enum XMC_SCU_HIB_CTRL_STATUS { @@ -750,7 +711,7 @@ typedef enum XMC_SCU_HIB_CTRL_STATUS XMC_SCU_HIB_CTRL_STATUS_ACTIVE = SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk, /**< Hibernate driven active to pads */ } XMC_SCU_HIB_CTRL_STATUS_t; -/** +/** * Hibernate domain event status */ typedef enum XMC_SCU_HIB_EVENT @@ -768,21 +729,21 @@ typedef enum XMC_SCU_HIB_EVENT XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk, /**< Wake-up on LPAC positive edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */ XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE = SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk, /**< Wake-up on LPAC negative edge of HIB_IO_1 threshold crossing. @note Only available in XMC44 series and LQFP100. */ #endif -#endif +#endif } XMC_SCU_HIB_EVENT_t; -/** +/** * Hibernate domain dedicated pins */ typedef enum XMC_SCU_HIB_IO { - XMC_SCU_HIB_IO_0 = 0, /**< HIB_IO_0 pin. + XMC_SCU_HIB_IO_0 = 0, /**< HIB_IO_0 pin. At the first power-up and with every reset of the hibernate domain this pin is configured as opendrain output and drives "0". As output the medium driver mode is active. */ #if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) - XMC_SCU_HIB_IO_1 = 1 /**< HIB_IO_1 pin. - At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active. + XMC_SCU_HIB_IO_1 = 1 /**< HIB_IO_1 pin. + At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active. @note : Only available in certain packages*/ -#endif +#endif } XMC_SCU_HIB_IO_t; /** @@ -798,7 +759,7 @@ typedef enum XMC_SCU_HIB_PIN_MODE XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO = 10 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Push-pull GPIO output */ XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL = 12 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain HIB control output */ XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV = 13 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain WDT service output */ - XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO = 14 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain GPIO output */ + XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO = 14 << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos, /**< Open drain GPIO output */ } XMC_SCU_HIB_PIN_MODE_t; /** @@ -827,9 +788,9 @@ typedef enum XMC_SCU_HIB_HIBERNATE_MODE typedef enum XMC_SCU_HIB_SR0_INPUT { XMC_SCU_HIB_SR0_INPUT_HIB_IO_0 = SCU_HIBERNATE_HDCR_GPI0SEL_Msk, /**< Set HIB_SR0 to HIB_IO_0 digital input */ -#if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) +#if (defined(DOXYGEN) || (UC_PACKAGE == BGA196) || (UC_PACKAGE == BGA144) || (UC_PACKAGE == LQFP144) || (UC_PACKAGE == LQFP100)) XMC_SCU_HIB_SR0_INPUT_HIB_IO_1 = 0, /**< Set HIB_SR0 to HIB_IO_1 digital input. @note Only available in certain packages. */ -#endif +#endif #if (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) XMC_SCU_HIB_SR0_INPUT_ACMP0 = SCU_HIBERNATE_HDCR_ADIG0SEL_Msk, /**< Set HIB_SR0 to LPAC CMP0. @note Only available in XMC44, XMC42 and XMC41 series. */ #endif @@ -858,9 +819,9 @@ typedef enum XMC_SCU_HIB_LPAC_INPUT XMC_SCU_HIB_LPAC_INPUT_DISABLED = 0 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator permanently in power down */ XMC_SCU_HIB_LPAC_INPUT_VBAT = 0x1 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for VBAT input */ XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0 = 0x2 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_0 input */ -#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1 = 0x4 << SCU_HIBERNATE_LPACCONF_CMPEN_Pos, /**< Comparator activated for HIB_IO_1 input. @note Only available in XMC44 series and LQFP100 package. */ -#endif +#endif } XMC_SCU_HIB_LPAC_INPUT_t; /** @@ -884,14 +845,14 @@ typedef enum XMC_SCU_HIB_LPAC_STATUS { XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE = SCU_HIBERNATE_LPACST_VBATSCMP_Msk, /**< VBAT compare operation completed */ XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk, /**< HBI_IO_0 compare operation completed */ -#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE = SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk, /**< HBI_IO_1 compare operation completed. @note Only available in XMC44 series and LQFP100 package. */ -#endif +#endif XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_VBATVAL_Msk, /**< VBAT comparison result above programmed threshold */ XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk, /**< HBI_IO_0 comparison result above programmed threshold */ -#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) +#if (defined(DOXYGEN) || ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100))) XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD = SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk, /**< HBI_IO_1 comparison result above programmed threshold. @note Only available in XMC44 series and LQFP100 package. */ -#endif +#endif } XMC_SCU_HIB_LPAC_STATUS_t; #endif /* (defined(DOXYGEN) || (UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) */ @@ -902,7 +863,7 @@ typedef enum XMC_SCU_HIB_LPAC_STATUS /** * Defines a data structure for initializing the PLL functional block. - * Structure holds divider values for N-DIV, P-DIV, K1-DIV, K2-DIV in order to generate desired + * Structure holds divider values for N-DIV, P-DIV, K1-DIV, K2-DIV in order to generate desired * frequency using VCO. It holds the PLL mode of operation either normal or prescaler (VCO bypassed). * Use type \a XMC_SCU_CLOCK_PLL_CONFIG_t for accessing these structure parameters. */ @@ -954,7 +915,7 @@ extern "C" { #endif /** - * + * * @param group ADC Group to which the channel being monitored belongs to.\n * \b Range: 0 or 1. * @param channel The channel whose voltage range has to be monitored.\n @@ -973,7 +934,7 @@ extern "C" { void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel); /** - * + * * @param group ADC Group to which the channel being monitored belongs to.\n * \b Range: 0 or 1. * @param channel The channel whose voltage range has to be monitored.\n @@ -1040,8 +1001,8 @@ bool XMC_SCU_IsTemperatureSensorEnabled(void); * Calibrates the measurement of temperature by configuring the values of offset and gain of \a DTSCON register. \n\n * Allows to improve the accuracy of the temperature measurement with the adjustment of \a OFFSET and \a GAIN bit fields * in the \a DTSCON register. - * Offset adjustment is defined as a shift of the conversion result. The range of the offset adjustment is 7 bits with a - * resolution that corresponds to +/- 12.5�C. The offset value gets added to the measure result. + * Offset adjustment is defined as a shift of the conversion result. The range of the offset adjustment is 7 bits with a + * resolution that corresponds to +/- 12.5�C. The offset value gets added to the measure result. * Offset is considered as a signed value. * Gain adjustment helps in minimizing gain error. When the \a gain value is 0, result is generated with maximum gain. * When the \a gain value is 63, result is generated with least gain, i.e, \a RESULT - 63 at the highest measured temperature.\n @@ -1061,7 +1022,7 @@ void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain); /** * @return XMC_SCU_STATUS_t Result of starting the temperature measurement.\n - * \b Range: \n + * \b Range: \n * XMC_SCU_STATUS_OK if the measurement is started successfully.\n * XMC_SCU_STATUS_ERROR if temperature sensor is not enabled.\n * XMC_SCU_STATUS_BUSY if temperature sensor is busy measuring the temperature.\n @@ -1126,7 +1087,7 @@ bool XMC_SCU_IsTemperatureSensorBusy(void); */ bool XMC_SCU_IsTemperatureSensorReady(void); -#if (UC_SERIES != XMC45) +#if ((UC_SERIES == XMC41) || (UC_SERIES == XMC42) || (UC_SERIES == XMC44)) /** * @return bool Indicates if the measured die temperature value has exceeded the configured upper limit.\n * \b Range: \a true if the temperature value has exceeded the configured upper limit. \a false @@ -1135,18 +1096,19 @@ bool XMC_SCU_IsTemperatureSensorReady(void); * \parDescription
      * Checks if the measured temperature has exceeded the configured upper limit of temperature.\n\n * The API checks \a OVERFL bit (Upper Limit Overflow Status bit) of \a DTEMPALARM register. - * The \a OVERFL bit will be set if the measured temperature has exceeded the limit configured in + * The \a OVERFL bit will be set if the measured temperature has exceeded the limit configured in * the bitfield \a UPPER in the \a DTEMPLIM register. * \parRelated APIs:
      * XMC_SCU_SetRawTempLimits(),XMC_SCU_LowTemperature() \n\n\n + * \note Only available in XMC44, XMC42 and XMC41 series */ bool XMC_SCU_HighTemperature(void); /** * - * @param lower_temp Lower threshold of die temperature. If measured temperature falls below this value, + * @param lower_temp Lower threshold of die temperature. If measured temperature falls below this value, * alarm bit will be set in \a UNDERFL bit field of \a DTEMPALARM register. - * @param upper_temp Upper threshold of die temperature. If measured temperature exceeds this value, + * @param upper_temp Upper threshold of die temperature. If measured temperature exceeds this value, * alarm bit will be set in \a OVERFL bit field of \a DTEMPALARM register. * * @return None @@ -1163,6 +1125,7 @@ bool XMC_SCU_HighTemperature(void); * - Use \a XMC_SCU_HighTemperature() and XMC_SCU_LowTemperature() to monitor the temperature.\n * \parRelated APIs:
      * XMC_SCU_HighTemperature(), XMC_SCU_LowTemperature() \n\n\n + * \note Only available in XMC44, XMC42 and XMC41 series */ void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp); @@ -1174,10 +1137,11 @@ void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_te * \parDescription
      * Checks if the measured temperature has dropped below the configured lower limit of temperature.\n\n * The API checks \a UNDERFL bit (Lower LimitUnderflow Status bit) of \a DTEMPALARM register. - * The \a UNDERFL bit will be set if the measured temperature has dropped below the limit configured in + * The \a UNDERFL bit will be set if the measured temperature has dropped below the limit configured in * the bitfield \a LOWER in the \a DTEMPLIM register. * \parRelated APIs:
      * XMC_SCU_SetRawTempLimits(),XMC_SCU_HighTemperature() \n\n\n + * \note Only available in XMC44, XMC42 and XMC41 series */ bool XMC_SCU_LowTemperature(void); #endif @@ -1204,9 +1168,9 @@ uint32_t XMC_SCU_GetBootMode(void); * * \parDescription
      * Configures the desired boot mode for the device.\n\n - * The XMC4 series devices support multiple boot modes. A running application can set a desired bootmode and + * The XMC4 series devices support multiple boot modes. A running application can set a desired bootmode and * launch it by means of software reset. Switching of boot modes should be handled carefully. User should ensure that - * the initial boot sequence is executed. A stable execution environment should be maintained when program control is + * the initial boot sequence is executed. A stable execution environment should be maintained when program control is * eventually handed over to the application program.\n * It is recommended to use following steps to launch requested bootmode:\n * - Call \a XMC_SCU_SetBootMode() with desired boot mode value.\n @@ -1232,7 +1196,7 @@ void XMC_SCU_SetBootMode(const XMC_SCU_BOOTMODE_t mode); * XMC_SCU_WriteGPR()\n\n\n */ uint32_t XMC_SCU_ReadGPR(const uint32_t index); - + /** * * @param index The SCU general purpose register to be written.\n @@ -1264,9 +1228,9 @@ void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data); * * \parDescription
      * Writes input data to the selected address of Retention memory in hibernate domain.\n\n - * The retention memory is located in hibernate domain. + * The retention memory is located in hibernate domain. * It is used for the purpose of store/restore of context information. - * Access to the retention memory space is served over shared serial interface. + * Access to the retention memory space is served over shared serial interface. * Retention memory content is retained even in hibernate mode. * \parRelated APIs:
      * XMC_SCU_ReadFromRetentionMemory() \n\n\n @@ -1286,9 +1250,9 @@ void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data); * * \parDescription
      * Reads data from selected address of retention memory in hibernate domain.\n\n - * The retention memory is located in hibernate domain. + * The retention memory is located in hibernate domain. * It is used for the purpose of store/restore of context information. - * Access to the retention memory space is served over shared serial interface. + * Access to the retention memory space is served over shared serial interface. * Retention memory content is retained even in hibernate mode. * \parRelated APIs:
      * XMC_SCU_WriteToRetentionMemory() \n\n\n @@ -1298,14 +1262,14 @@ uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address); /** * * @param request Non-maskable interrupt (NMI) request source to be enabled.\n - * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple + * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple * sources can be combined using \a OR operation. * - * @return None + * @return None * * \parDescription
      * Selectively enables interrupt sources to generate non maskable interrupt(NMI).\n\n - * NMI assertion can be individually enabled by setting corresponding bit of an interrupt in the + * NMI assertion can be individually enabled by setting corresponding bit of an interrupt in the * \a NMIREQEN register. * \parRelated APIs:
      * XMC_SCU_INTERRUPT_DisableNmiRequest() \n\n\n @@ -1315,10 +1279,10 @@ void XMC_SCU_INTERRUPT_EnableNmiRequest(const uint32_t request); /** * * @param request Non-maskable interrupt (NMI) request source to be disabled.\n - * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple + * \b Range: Use type @ref XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple * sources can be combined using \a OR operation. * - * @return None + * @return None * * \parDescription
      * Selectively disables interrupt sources from generating non maskable interrupt(NMI).\n\n @@ -1333,11 +1297,11 @@ void XMC_SCU_INTERRUPT_DisableNmiRequest(const uint32_t request); * @param trap The event for which, trap generation has to be enabled.\n * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. * - * @return None + * @return None * * \parDescription
      * Enables assertion of trap for the selected trap event.\n\n - * Trap assertion can be individually enabled by clearing respective bit of the + * Trap assertion can be individually enabled by clearing respective bit of the * event in \a TRAPDIS register in order to get an exception. * \parRelated APIs:
      * XMC_SCU_TRAP_Disable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n @@ -1349,11 +1313,11 @@ void XMC_SCU_TRAP_Enable(const uint32_t trap); * @param trap The event for which, trap generation has to be disabled.\n * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. * - * @return None + * @return None * * \parDescription
      * Disables assertion of trap for the selected trap event.\n\n - * Trap assertion can be individually disabled by setting the respective event bit + * Trap assertion can be individually disabled by setting the respective event bit * in the \a TRAPDIS register in order to suppress trap generation. * \parRelated APIs:
      * XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus() \n\n\n @@ -1365,12 +1329,12 @@ void XMC_SCU_TRAP_Disable(const uint32_t trap); * @param trap The event for which, trap status bit has to be cleared.\n * \b Range: Use type @ref XMC_SCU_TRAP_t to identify the event. * - * @return None + * @return None * * \parDescription
      * Clears the trap status of input event.\n\n - * Once a trap event is detected, it will have to be acknowledged and later serviced. - * The trap status bit should be cleared to detect the occurence of trap next time. + * Once a trap event is detected, it will have to be acknowledged and later serviced. + * The trap status bit should be cleared to detect the occurence of trap next time. * This is useful while polling for TRAPSTAT without enabling the NMI for trap. * Trap status can be cleared by setting the event bit in the \a TRAPCLR register. * \parRelated APIs:
      @@ -1393,7 +1357,7 @@ void XMC_SCU_TRAP_ClearStatus(const uint32_t trap); * \parRelated APIs:
      * XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_ClearStatus() \n\n\n */ -uint32_t XMC_SCU_TRAP_GetStatus(void); +uint32_t XMC_SCU_TRAP_GetStatus(void); /** * @@ -1404,7 +1368,7 @@ uint32_t XMC_SCU_TRAP_GetStatus(void); * * \parDescription
      * Triggers trap generation for the event specified. \n\n - * The trap source has to be enabled before invocation of this API. + * The trap source has to be enabled before invocation of this API. * Trap event can be triggered by setting its respective bit in the \a TRAPSET register. * Trap event can be configured to generate a non maskable interrupt by using the API XMC_SCU_INTERRUPT_EnableNmiRequest().\n * It is recommended to use following steps to manually assert a trap event:\n @@ -1469,27 +1433,27 @@ void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peri * \parDescription
      * Checks the reset status of the selected peripheral.\n\n * The API reads the reset status from \a PRSTATn register. Returns true if the peripheral is in - * reset state. On power up of the device, all the peripherals will be in reset state. + * reset state. On power up of the device, all the peripherals will be in reset state. * If the peripheral is enabled, \a false will be returned as the status. * \parRelated APIs:
      - * XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n + * XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset() \n\n\n */ bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t peripheral); - + /** * * @param memory The on-chip RAM type, for which the parity error status has to be cleared.\n - * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple * memory status bits can be cleared by using the \a OR operation. * * @return None * * \parDescription
      * Clears the parity error status bit. \n\n - * When a memory parity error is detected using the status bits in \a PEFLAG register. It has to + * When a memory parity error is detected using the status bits in \a PEFLAG register. It has to * be cleared by software to detect the parity error from the same memory next time. - * The API clears the parity error status bit of the selected peripheral by setting the - * respective bit in the \a PEFLAG register. Status of multiple memory parity errors + * The API clears the parity error status bit of the selected peripheral by setting the + * respective bit in the \a PEFLAG register. Status of multiple memory parity errors * can be cleared by combining the enum values using \a OR operation. * \parRelated APIs:
      * XMC_SCU_PARITY_GetStatus(), XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_EnableTrapGeneration() \n\n\n @@ -1499,10 +1463,10 @@ void XMC_SCU_PARITY_ClearStatus(const uint32_t memory); /** * * @param memory The on-chip RAM type, for which the parity error checking has to be enabled.\n - * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple * memory types can be combined using the \a OR operation. * - * @return None + * @return None * * \parDescription
      * Enables parity error checking for the selected on-chip RAM type.\n\n @@ -1518,10 +1482,10 @@ void XMC_SCU_PARITY_Enable(const uint32_t memory); /** * * @param memory The on-chip RAM type, for which the parity error checking has to be disabled.\n - * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple * memory types can be combined using the \a OR operation. * - * @return None + * @return None * * \parDescription
      * Disables parity error checking for the selected on-chip RAM type.\n\n @@ -1534,10 +1498,10 @@ void XMC_SCU_PARITY_Disable(const uint32_t memory); /** * * @param memory The on-chip RAM type, for which the parity error trap generation has to be enabled.\n - * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple * memory types can be combined using the \a OR operation. * - * @return None + * @return None * * \parDescription
      * Enables trap assertion for the parity error source.\n\n @@ -1553,10 +1517,10 @@ void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory); /** * * @param memory The on-chip RAM type, for which the parity error trap generation has to be disabled.\n - * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple * memory types can be combined using the \a OR operation. * - * @return None + * @return None * * \parDescription
      * Disables the assertion of trap for the parity error source.\n\n @@ -1575,13 +1539,83 @@ void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory); * \parDescription
      * Provides the status of parity error detection for the on-chip RAM modules.\n\n * Parity error status information is obtained from the \a PEFLAG register. - * If a particular RAM module has parity error, its respective bit field will be set to 1 in the + * If a particular RAM module has parity error, its respective bit field will be set to 1 in the * returned value. A check for the status of a particular RAM module can be done by * masking the returned value with the RAM module identifier from the type @ref XMC_SCU_PARITY_t. * \parRelated APIs:
      * XMC_SCU_PARITY_ClearStatus() \n\n\n */ -uint32_t XMC_SCU_PARITY_GetStatus(void); +uint32_t XMC_SCU_PARITY_GetStatus(void); + +/** + * + * @param memory The on-chip RAM type, for which the parity logic should be overriden.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple + * memory types can be combined using the \a OR operation. + * + * @return None + * + * \parDescription
      + * Enable access to parity bits of SRAM modules for various types of peripherals. + * Enable direct write to parity bits using value selected using XMC_SCU_PARITY_SetParityWriteValue()\n\n + * \parRelated APIs:
      + * XMC_SCU_PARITY_SetParityWriteValue() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_PARITY_OverrideParityBitLogic(uint32_t memory) +{ + SCU_PARITY->MCHKCON = memory; +} + +/** + * @param memory The on-chip RAM type, for which the parity test has to be enabled.\n + * \b Range: Use type @ref XMC_SCU_PARITY_t to identify the on-chip RAM type. + * \b Only a single memory type should be specified. + * + * @return None + * + * \parDescription
      + * Selects parity test output from a memory instance that can be inspected using XMC_SCU_PARITY_GetParityReadValue() + * \parRelated APIs:
      + * XMC_SCU_PARITY_GetParityReadValue() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_PARITY_SelectMemoryTest(const XMC_SCU_PARITY_t memory) +{ + SCU_PARITY->PMTSR = memory; +} + +/** + * @param write_value parity bits value stored with next write access\n + * + * @return None + * + * \parDescription
      + * For each byte of a memory module the parity bits corresponding to the next write access are selected here. + * + * \parRelated APIs:
      + * XMC_SCU_PARITY_OverrideParityBitLogic() \n\n\n + * + */ +__STATIC_INLINE void XMC_SCU_PARITY_SetParityWriteValue(uint8_t write_value) +{ + SCU_PARITY->PMTPR = ((write_value << SCU_PARITY_PMTPR_PWR_Pos) & SCU_PARITY_PMTPR_PWR_Msk); +} + +/** + * @return parity bits generated during last read access + * + * \parDescription
      + * For each byte of a memory module the parity bits generated during the most recent read access can be read. + * + * \parRelated APIs:
      + * XMC_SCU_PARITY_OverrideParityBitLogic() \n\n\n + * + */ +__STATIC_INLINE uint8_t XMC_SCU_PARITY_GetParityReadValue(void) +{ + return ((SCU_PARITY->PMTPR & SCU_PARITY_PMTPR_PRD_Msk) >> SCU_PARITY_PMTPR_PRD_Pos); +} /** * @@ -1631,7 +1665,7 @@ void XMC_SCU_CLOCK_DisableClock(const XMC_SCU_CLOCK_t clock); * * \parDescription
      * Checks the status of peripheral source clock.\n\n - * The status of peripheral source clock is read from the \a CLKSTATn register. + * The status of peripheral source clock is read from the \a CLKSTATn register. * Returns \a true if clock is enabled and returns \a false otherwise. * \parRelated APIs:
      * XMC_SCU_CLOCK_EnableClock(), XMC_SCU_CLOCK_DisableClock() \n\n\n @@ -1651,7 +1685,7 @@ bool XMC_SCU_CLOCK_IsClockEnabled(const XMC_SCU_CLOCK_t clock); * Selects the source for system clock (fSYS).\n\n * System clock is selected by setting \a SYSSEL bits in the \a SYSCLKCR register. * If \a XMC_SCU_CLOCK_SYSCLKSRC_PLL is selected, then the dividers of the PLL have to be - * additionally configured to achieve the required system clock frequency. + * additionally configured to achieve the required system clock frequency. * \parRelated APIs:
      * XMC_SCU_CLOCK_StartSystemPll(), XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n */ @@ -1740,7 +1774,7 @@ void XMC_SCU_CLOCK_SetWdtClockSource(const XMC_SCU_CLOCK_WDTCLKSRC_t source); * \parDescription
      * Provides the source of clock used for watchdog timer.\n\n * The value is obtained by reading \a WDTSEL bits of \a WDTCLKCR register. - * The time for timeout or pre-warning of watchdog has to be calculated based on + * The time for timeout or pre-warning of watchdog has to be calculated based on * the clock source selected. * \parRelated APIs:
      * XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetWdtClockSource() \n\n\n @@ -1891,7 +1925,7 @@ __STATIC_INLINE XMC_SCU_CLOCK_EXTOUTCLKSRC_t XMC_SCU_CLOCK_GetExternalOutputCloc * \parDescription
      * Selects the source of system PLL.\n\n * The value is configured to \a VCOBYP bit of \a PLLCON0 register. - * If \a XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP is selected, ensure that the high performance oscillator is + * If \a XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP is selected, ensure that the high performance oscillator is * enabled by using the API XMC_SCU_CLOCK_EnableHighPerformanceOscillator(). * \parRelated APIs:
      * XMC_SCU_CLOCK_EnableHighPerformanceOscillator()\n\n\n @@ -1915,7 +1949,7 @@ __STATIC_INLINE XMC_SCU_CLOCK_SYSPLLCLKSRC_t XMC_SCU_CLOCK_GetSystemPllClockSour return (XMC_SCU_CLOCK_SYSPLLCLKSRC_t)(SCU_PLL->PLLCON0 & SCU_PLL_PLLCON0_VCOBYP_Msk); } -#if defined(ECAT0) +#if defined(ECAT0) /** * * @param source Source of ECAT clock.\n @@ -1934,7 +1968,7 @@ __STATIC_INLINE XMC_SCU_CLOCK_SYSPLLCLKSRC_t XMC_SCU_CLOCK_GetSystemPllClockSour __STATIC_INLINE void XMC_SCU_CLOCK_SetECATClockSource(const XMC_SCU_CLOCK_ECATCLKSRC_t source) { SCU_CLK->ECATCLKCR = (SCU_CLK->ECATCLKCR & ((uint32_t)~SCU_CLK_ECATCLKCR_ECATSEL_Msk)) | - ((uint32_t)source); + ((uint32_t)source); } /** @@ -1964,7 +1998,7 @@ __STATIC_INLINE XMC_SCU_CLOCK_ECATCLKSRC_t XMC_SCU_CLOCK_GetECATClockSource(void * * \parDescription
      * Configures the ratio of system clock source to the value of system clock frequency.\n\n - * The value is configured as \a SYSDIV bits of \a SYSCLKCR register. The divider value is + * The value is configured as \a SYSDIV bits of \a SYSCLKCR register. The divider value is * decremented by 1 before configuring. * \parRelated APIs:
      * XMC_SCU_CLOCK_GetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n @@ -2268,9 +2302,9 @@ __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetECATClockDivider(void) * * \parDescription
      * Enables the high precision oscillator by configuring external crystal mode.\n\n - * The API configures \a MODE bits of \a OSCHPCTRL register to 0, there by configuring the + * The API configures \a MODE bits of \a OSCHPCTRL register to 0, there by configuring the * external clock input. - * The System Oscillator Watchdog is enabled. The user should check the status + * The System Oscillator Watchdog is enabled. The user should check the status * of the oscillator using XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() * \parRelated APIs:
      * XMC_SCU_CLOCK_DisableHighPerformanceOscillator() \n\n\n @@ -2282,8 +2316,8 @@ void XMC_SCU_CLOCK_EnableHighPerformanceOscillator(void); * * \parDescription
      * Disables the high precision oscillator by disabling the external oscillator.\n\n - * The API configures \a MODE bits of \a OSCHPCTRL register to 1, there by disabling the - * external oscillator. + * The API configures \a MODE bits of \a OSCHPCTRL register to 1, there by disabling the + * external oscillator. * \parRelated APIs:
      * XMC_SCU_CLOCK_EnableHighPerformanceOscillator() \n\n\n */ @@ -2343,12 +2377,12 @@ uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus(voi * Enables ultra low power oscillator(ULP). \n\n * It enables the hibernate domain, configures the ultra low power oscillator * uisng the \a MODE bits of the \a OSCULCTRL register. The \a Mode bits will be - * reset to 0 to enable the low power oscillator. Mirror register update delays + * reset to 0 to enable the low power oscillator. Mirror register update delays * are handled internally. - * The OSC_ULP Oscillator Watchdog is enabled. The user should check the status + * The OSC_ULP Oscillator Watchdog is enabled. The user should check the status * of the oscillator using XMC_SCU_CLOCK_IsLowPowerOscillatorStable() * \parRelated APIs:
      - * XMC_SCU_CLOCK_DisableLowPowerOscillator() + * XMC_SCU_CLOCK_DisableLowPowerOscillator() * XMC_SCU_CLOCK_IsLowPowerOscillatorStable() \n\n\n */ void XMC_SCU_CLOCK_EnableLowPowerOscillator(void); @@ -2411,7 +2445,7 @@ void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void); /** * - * @return Status OSC_ULP XTAL1 pin + * @return Status OSC_ULP XTAL1 pin * * \parDescription
      * Monitor the status of OSC_ULP XTAL1 pin. @@ -2486,7 +2520,7 @@ __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetSystemClockFrequency(void) { return SystemCoreClock << ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) >> SCU_CLK_CPUCLKCR_CPUDIV_Pos); } - + /** * @@ -2515,7 +2549,7 @@ uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void); * \parRelated APIs:
      * XMC_SCU_CLOCK_GetUsbClockSource(), XMC_SCU_CLOCK_GetUsbClockDivider() \n\n\n */ -uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void); +uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void); /** * @return uint32_t Ethernet clock frequency in Hertz. @@ -2539,15 +2573,15 @@ __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetEthernetClockFrequency(void) * * \parDescription
      * Provides the frequency of EBU clock(fEBU).\n\n - * The value is derived from system PLL clock frequency(fPLL) by applying the EBU divider. + * The value is derived from system PLL clock frequency(fPLL) by applying the EBU divider. * It is calculated using the following formula:\n * fETH = fPLL /(EBUDIV+1) * \parRelated APIs:
      * XMC_SCU_CLOCK_GetEbuClockDivider(), XMC_SCU_CLOCK_GetSystemPllClockFrequency() \n\n\n */ -uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void); +uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void); #endif - + /** * @return uint32_t WDT clock frequency in Hertz. * @@ -2562,7 +2596,7 @@ uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void); * \parRelated APIs:
      * XMC_SCU_CLOCK_GetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider() \n\n\n */ -uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void); +uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void); /** * @@ -2579,9 +2613,9 @@ uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void); * \parRelated APIs:
      * XMC_SCU_CLOCK_GetExternalOutputClockDivider(), XMC_SCU_CLOCK_GetExternalOutputClockSource() \n\n\n */ -uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void); +uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void); -#if defined(ECAT) +#if defined(ECAT0) /** * @return uint32_t ECAT clock frequency in Hertz. * @@ -2604,25 +2638,25 @@ uint32_t XMC_SCU_CLOCK_GetECATClockFrequency(void); * \parDescription
      * Enables main PLL for system clock. \n\n * System PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. - * By default the system PLL is in power saving mode. The API enables the PLL and the voltage + * By default the system PLL is in power saving mode. The API enables the PLL and the voltage * controlled oscillator associated with it. * \parRelated APIs:
      * XMC_SCU_CLOCK_DisableSystemPll(), XMC_SCU_CLOCK_StartSystemPll() \n\n\n */ void XMC_SCU_CLOCK_EnableSystemPll(void); - - /** - * @return None - * - * \parDescription
      - * Disables main PLL for system clock. \n\n - * System PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. - * By default the system PLL is in power saving mode. If the system PLL is explicitly enabled, - * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. - * \parRelated APIs:
      - * XMC_SCU_CLOCK_EnableSystemPll(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n - */ - void XMC_SCU_CLOCK_DisableSystemPll(void); + +/** +* @return None +* +* \parDescription
      +* Disables main PLL for system clock. \n\n +* System PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a PLLCON0 register. +* By default the system PLL is in power saving mode. If the system PLL is explicitly enabled, +* the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. +* \parRelated APIs:
      +* XMC_SCU_CLOCK_EnableSystemPll(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n +*/ +void XMC_SCU_CLOCK_DisableSystemPll(void); /** * @param source PLL clock source. \n @@ -2644,7 +2678,7 @@ void XMC_SCU_CLOCK_EnableSystemPll(void); * \parDescription
      * Enables system PLL.\n\n * Based on the selected source of clock, either external frequency fOHP or internal clock fOFI will be used. - * Based on the selected PLL mode, either voltage controlled oscillator(VCO) output(fVCO) or direct input frequency + * Based on the selected PLL mode, either voltage controlled oscillator(VCO) output(fVCO) or direct input frequency * is used for the output dividers.\n * The API implements the following sequence:\n * - Store the value of TRAPDIS register into a temporary variable before disabling all traps.\n @@ -2655,7 +2689,7 @@ void XMC_SCU_CLOCK_EnableSystemPll(void); * - If prescaler mode is selected, configure the value of K1DIV.\n * - Wait for LOCK.\n * - Restore the trap configuration from stored temporary variable.\n - * + * * \parRelated APIs:
      * XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StopSystemPll() \n\n\n */ @@ -2694,7 +2728,7 @@ void XMC_SCU_CLOCK_StopSystemPll(void); * Ramps up or ramps down the PLL output frequency in provided step. \n\n * The PLL output frequency is divided by the \a kdiv value. This generates a step of ramp * for the PLL output frequency. The API waits for the clock to stabilize before the completing its - * execution. + * execution. * \parRelated APIs:
      * XMC_SCU_CLOCK_StartSystemPll() \n\n\n */ @@ -2705,7 +2739,7 @@ void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv); * @return Boolean value indicating if System PLL is locked * * \parDescription
      - * Return status of System PLL VCO. + * Return status of System PLL VCO. * \parRelated APIs:
      * XMC_SCU_CLOCK_StartSystemPll() \n\n\n */ @@ -2717,26 +2751,26 @@ bool XMC_SCU_CLOCK_IsSystemPllLocked(void); * \parDescription
      * Enables USB PLL for USB clock. \n\n * USB PLL is enabled by clearing the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. - * By default the USB PLL is in power saving mode. The API enables the PLL and the voltage + * By default the USB PLL is in power saving mode. The API enables the PLL and the voltage * controlled oscillator associated with it. * \parRelated APIs:
      * XMC_SCU_CLOCK_DisableUsbPll(), XMC_SCU_CLOCK_StartUsbPll() \n\n\n */ - void XMC_SCU_CLOCK_EnableUsbPll(void); - - /** - * @return None - * - * \parDescription
      - * Disables USB PLL for USB clock. \n\n - * USB PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. - * By default the USB PLL is in power saving mode. If the USB PLL is explicitly enabled, - * the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. - * \parRelated APIs:
      - * XMC_SCU_CLOCK_EnableUsbPll(), XMC_SCU_CLOCK_StopUsbPll() \n\n\n - */ +void XMC_SCU_CLOCK_EnableUsbPll(void); + +/** +* @return None +* +* \parDescription
      +* Disables USB PLL for USB clock. \n\n +* USB PLL is disabled by setting the \a PLLPWD and \a VCOPWD bits of \a USBPLLCON register. +* By default the USB PLL is in power saving mode. If the USB PLL is explicitly enabled, +* the API disables the PLL and the voltage controlled oscillator(VCO) associated with it. +* \parRelated APIs:
      +* XMC_SCU_CLOCK_EnableUsbPll(), XMC_SCU_CLOCK_StopUsbPll() \n\n\n +*/ void XMC_SCU_CLOCK_DisableUsbPll(void); - + /** * * @param pdiv Input divider value. Represents (PDIV+1) divider for the USB PLL.\n @@ -2790,7 +2824,7 @@ void XMC_SCU_CLOCK_StopUsbPll(void); * @return Boolean value indicating if USB PLL is locked * * \parDescription
      - * Return status of USB PLL VCO. + * Return status of USB PLL VCO. * \parRelated APIs:
      * XMC_SCU_CLOCK_StartUsbPll() \n\n\n */ @@ -2808,8 +2842,8 @@ bool XMC_SCU_CLOCK_IsUsbPllLocked(void); * Configures the calibration mode of internal oscillator.\n\n * Based on the calibration mode selected, the internal oscillator calibration will be configured. * The calibration is useful while using fast internal clock(fOFI). When factory mode calibration is used, - * the internal oscillator is trimmed using the firmware configured values. If automatic calibration is - * selected, the internal oscillator will be monitored using the backup clock. + * the internal oscillator is trimmed using the firmware configured values. If automatic calibration is + * selected, the internal oscillator will be monitored using the backup clock. * * \parRelated APIs:
      * XMC_SCU_CLOCK_SetSystemClockSource() \n\n\n @@ -2830,7 +2864,7 @@ void XMC_SCU_CLOCK_SetBackupClockCalibrationMode(XMC_SCU_CLOCK_FOFI_CALIBRATION_ */ __STATIC_INLINE void XMC_SCU_POWER_WaitForInterrupt(XMC_SCU_POWER_MODE_t mode, bool sleep_on_exit) { - SCB->SCR = mode | (sleep_on_exit ? SCB_SCR_SLEEPONEXIT_Msk : 0); + SCB->SCR = mode | (sleep_on_exit ? SCB_SCR_SLEEPONEXIT_Msk : 0); __WFI(); } @@ -2848,7 +2882,7 @@ __STATIC_INLINE void XMC_SCU_POWER_WaitForInterrupt(XMC_SCU_POWER_MODE_t mode, b */ __STATIC_INLINE void XMC_SCU_POWER_WaitForEvent(XMC_SCU_POWER_MODE_t mode) { - SCB->SCR = mode | SCB_SCR_SEVONPEND_Msk; + SCB->SCR = mode | SCB_SCR_SEVONPEND_Msk; __WFE(); } @@ -2867,8 +2901,8 @@ __STATIC_INLINE void XMC_SCU_POWER_WaitForEvent(XMC_SCU_POWER_MODE_t mode) */ __STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(uint8_t threshold, uint8_t interval) { - SCU_POWER->PWRMON = SCU_POWER_PWRMON_ENB_Msk | - ((uint32_t)threshold << SCU_POWER_PWRMON_THRS_Pos) | + SCU_POWER->PWRMON = SCU_POWER_PWRMON_ENB_Msk | + ((uint32_t)threshold << SCU_POWER_PWRMON_THRS_Pos) | ((uint32_t)interval << SCU_POWER_PWRMON_INTV_Pos); } @@ -2880,12 +2914,12 @@ __STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(uint8_t threshold, uint8_t inte */ __STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void) { - SCU_POWER->PWRMON &= ~SCU_POWER_PWRMON_ENB_Msk; + SCU_POWER->PWRMON &= ~SCU_POWER_PWRMON_ENB_Msk; } /** * @return ::XMC_SCU_POWER_EVR_STATUS_t - * + * * \parDescription
      * Returns status of the EVR13. * @@ -2941,6 +2975,44 @@ void XMC_SCU_POWER_EnableUsb(void); */ void XMC_SCU_POWER_DisableUsb(void); +/** + * @return Status of pull-up activation + * + * \parDescription
      + * Сhecks status of weak pull-up activation for USB-Device. + * Returns 'true' if pull-up enabled. + * + * \parRelated APIs:
      + * XMC_SCU_PCU_EnableUsbPullUp(), XMC_SCU_PCU_DisableUsbPullUp() \n\n\n + */ +bool XMC_SCU_PCU_IsEnabledUsbPullUp(void); + +/** + * @return None + * + * \parDescription
      + * Enables the USB weak pull-up.\n\n + * Sets the \a USBPUWQ bit of \a PWRSET register to '1'. + * This enables USB weak pull-up. + * + * \parRelated APIs:
      + * XMC_SCU_PCU_IsEnabledUsbPullUp(), XMC_SCU_PCU_DisableUsbPullUp() \n\n\n + */ +void XMC_SCU_PCU_EnableUsbPullUp(void); + +/** + * @return None + * + * \parDescription
      + * Disables the USB weak pull-up.\n\n + * Sets the \a USBPUWQ bit of \a PWRCLR register to '1'. + * This disables USB weak pull-up. + * + * \parRelated APIs:
      + * XMC_SCU_PCU_IsEnabledUsbPullUp(), XMC_SCU_PCU_EnableUsbPullUp() \n\n\n + */ +void XMC_SCU_PCU_DisableUsbPullUp(void); + /** * @return None * @@ -2949,7 +3021,7 @@ void XMC_SCU_POWER_DisableUsb(void); * Hibernate domain should be enabled before using any peripheral from the hibernate domain. * It enables the power to the hibernate domain and moves it out of reset state. * Power to hibernate domain is enabled by setting the \a HIB bit of \a PWRSET register only if it is currently powered down. - * The API will wait until HIB domain is enabled. If hibernate domain is in a state of reset, + * The API will wait until HIB domain is enabled. If hibernate domain is in a state of reset, * \a HIBRS bit of \a RSTCLR register is set to move it out of reset state.\n * It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:\n * - Call \a XMC_SCU_HIB_EnableHibernateDomain . @@ -2983,11 +3055,11 @@ void XMC_SCU_HIB_DisableHibernateDomain(void); * \b Range: Boolean state value.\n * \a true if hibernate domain is enabled.\n * \a false if hibernate domain is disabled.\n - * + * * * \parDescription
      * Checks whether hibernation domain is enabled/disabled.\n\n - * The API can be used before using the peripherals from hibernation domain to ensure that the + * The API can be used before using the peripherals from hibernation domain to ensure that the * power is supplied to the peripherals and also that the hibernation domain is not in reset state. * The status is obtained using the \a HIBEN bit of \a PWRSTAT register and \a HIBRS bit of \a RSTSET register. * \parRelated APIs:
      @@ -2997,19 +3069,19 @@ bool XMC_SCU_HIB_IsHibernateDomainEnabled(void); /** * @return ::XMC_SCU_HIB_CTRL_STATUS_t - * + * * \parDescription
      * Returns status of the external hibernate control. * */ -__STATIC_INLINE int32_t XMC_SCU_HIB_GetHibernateControlStatus(void) +__STATIC_INLINE int32_t XMC_SCU_HIB_GetHibernateControlStatus(void) { - return (SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk); + return (SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk); } -/** +/** * @return ::XMC_SCU_HIB_EVENT_t - * + * * \parDescription
      * Returns status of hibernate wakeup events. * @@ -3022,15 +3094,15 @@ __STATIC_INLINE int32_t XMC_SCU_HIB_GetEventStatus(void) /** * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t * @return None - * + * * \parDescription
      - * Clear hibernate wakeup event status + * Clear hibernate wakeup event status * * \note * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus() * * \parRelated APIs:
      - * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(), + * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(), * XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus() \n\n\n * */ @@ -3039,7 +3111,7 @@ void XMC_SCU_HIB_ClearEventStatus(int32_t event); /** * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t * @return None - * + * * \parDescription
      * Trigger hibernate wakeup event * @@ -3048,7 +3120,7 @@ void XMC_SCU_HIB_ClearEventStatus(int32_t event); * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus() * * \parRelated APIs:
      - * XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_HIB_EnableEvent(), + * XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_HIB_EnableEvent(), * XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus() \n\n\n * */ @@ -3057,16 +3129,16 @@ void XMC_SCU_HIB_TriggerEvent(int32_t event); /** * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t * @return None - * + * * \parDescription
      - * Enable hibernate wakeup event source + * Enable hibernate wakeup event source * * * \note * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus() * * \parRelated APIs:
      - * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_ClearEventStatus(), + * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_ClearEventStatus(), * XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus() \n\n\n * */ @@ -3075,16 +3147,16 @@ void XMC_SCU_HIB_EnableEvent(int32_t event); /** * @param event Hibernate wakeup event ::XMC_SCU_HIB_EVENT_t * @return None - * + * * \parDescription
      - * Disable hibernate wakeup event source + * Disable hibernate wakeup event source * * * \note * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus() * * \parRelated APIs:
      - * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(), + * XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(), * XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_GetMirrorStatus() \n\n\n * */ @@ -3092,7 +3164,7 @@ void XMC_SCU_HIB_DisableEvent(int32_t event); /** * @return None - * + * * \parDescription
      * Request enter external hibernate state * @@ -3146,7 +3218,7 @@ __STATIC_INLINE void XMC_SCU_HIB_ClearWakeupEventDetectionStatus(void) /** * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t * @return None - * + * * \parDescription
      * Selects input for Wake-Up from Hibernate * @@ -3163,7 +3235,7 @@ void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin); * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t * @param mode Hibernate domain dedicated pin mode ::XMC_SCU_HIB_PIN_MODE_t * @return None - * + * * \parDescription
      * Selects mode of hibernate domain dedicated pins HIB_IOx * @@ -3180,7 +3252,7 @@ void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode); * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t * @param level Output polarity of the hibernate domain dedicated pins HIB_IOx ::XMC_SCU_HIB_IO_OUTPUT_LEVEL_t * @return None - * + * * \parDescription
      * Selects the output polarity of the hibernate domain dedicated pins HIB_IOx * @@ -3196,7 +3268,7 @@ void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_L /** * @param pin Hibernate domain dedicated pin ::XMC_SCU_HIB_IO_t * @return None - * + * * \parDescription
      * Selects input to ERU0 module (HIB_SR0) that optionally can be used with software as a general purpose input. * @@ -3401,8 +3473,8 @@ void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input); * By default on device power up, the slow internall oscillator is enabled. * It can be disabled only if the external oscillator(fULP) is enabled and toggling. * It is recommended to enable fOSI to prevent deadlock if fULP fails. - * fOSI is enabled by clearing the \a PWD bit of \a OSCSICTRL register. - * The API waits for the mirror register update of the configured register. + * fOSI is enabled by clearing the \a PWD bit of \a OSCSICTRL register. + * The API waits for the mirror register update of the configured register. * The slow internal oscillator registers are in hibernate domain. * Ensure that the hibernate domain is enabled before changing the configuration. * @@ -3410,7 +3482,7 @@ void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input); * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus() * * \parRelated APIs:
      - * XMC_SCU_HIB_DisableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), + * XMC_SCU_HIB_DisableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_GetMirrorStatus() \n\n\n */ void XMC_SCU_HIB_EnableInternalSlowClock(void); @@ -3424,8 +3496,8 @@ void XMC_SCU_HIB_EnableInternalSlowClock(void); * By default on device power up, the slow internall oscillator is enabled. * It can be disabled only if the external oscillator(fULP) is enabled and toggling. * It is recommended to enable fOSI to prevent deadlock if fULP fails. - * fOSI is disabled by setting the \a PWD bit of \a OSCSICTRL register. - * The API waits for the mirror register update of the configured register. + * fOSI is disabled by setting the \a PWD bit of \a OSCSICTRL register. + * The API waits for the mirror register update of the configured register. * The slow internal oscillator registers are in hibernate domain. * Ensure that the hibernate domain is enabled before changing the configuration. * @@ -3433,7 +3505,7 @@ void XMC_SCU_HIB_EnableInternalSlowClock(void); * The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus() * * \parRelated APIs:
      - * XMC_SCU_HIB_EnableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), + * XMC_SCU_HIB_EnableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), * XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_GetMirrorStatus() \n\n\n */ void XMC_SCU_HIB_DisableInternalSlowClock(void); @@ -3449,34 +3521,43 @@ void XMC_SCU_HIB_DisableInternalSlowClock(void); * * The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is - * stopped. + * stopped. * * In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked - * by a free-running clock. Peripherals are only clocked when configured to stay enabled. + * by a free-running clock. Peripherals are only clocked when configured to stay enabled. * Configuration of peripherals and any SRAM content is preserved. * The Flash module can be put into low-power mode to achieve a further power reduction. * On wake-up Flash module will be restarted again before instructions or data access is possible. * Any interrupt will bring the system back to operation via the NVIC.The clock setup before * entering Deep Sleep state is restored upon wake-up. * - * @usage * @code * // Configure system during SLEEP state - * XMC_SCU_CLOCK_SetDeepSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI | + * XMC_SCU_CLOCK_SetDeepSleepConfig(XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI | * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN | - * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN); - * + * XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN); + * * // Make sure that SLEEPDEEP bit is set - * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk; + * SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; * * // Return to SLEEP mode after handling the wakeup event - * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; - * + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * * // Put system in DEEPSLEEP state * __WFI(); * * @endcode * + * \note + * The PLL re-initialization is required after a wake-up from Deep Sleep mode + * if the the PLL was enabled before entering Deep Sleep mode and configured to + * go into power down while in Deep Sleep mode. + * To re-initialize the PLL: + * 1. Enable the PLL by XMC_SCU_CLOCK_EnableSystemPll(). + * 2. Start the PLL by XMC_SCU_CLOCK_StartSystemPll(). + * 3. Select the PLL as the source for the system clock by + * XMC_SCU_CLOCK_SetSystemClockSource(). + * *\parRelated APIs:
      * XMC_SCU_CLOCK_Init() \n\n\n * @@ -3495,24 +3576,24 @@ __STATIC_INLINE void XMC_SCU_CLOCK_SetDeepSleepConfig(int32_t config) * * The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is * entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is - * stopped. Peripherals are only clocked when configured to stay enabled. + * stopped. Peripherals are only clocked when configured to stay enabled. * * Peripherals can continue to operate unaffected and eventually generate an event to * wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The * clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP * state. - * + * * @usage * @code * // Configure system during SLEEP state * XMC_SCU_CLOCK_SetSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI); - * + * * // Make sure that SLEEPDEEP bit is cleared - * SCB->SCR &= ~ SCB_SCR_DEEPSLEEP_Msk; + * SCB->SCR &= ~ SCB_SCR_SLEEPDEEP_Msk; * * // Return to SLEEP mode after handling the wakeup event - * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; - * + * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + * * // Put system in SLEEP state * __WFI(); * @@ -3530,15 +3611,12 @@ __STATIC_INLINE void XMC_SCU_CLOCK_SetSleepConfig(int32_t config) /** * @} */ - -/** - * @} - */ - + + #ifdef __cplusplus } #endif - + #endif /* UC_FAMILY == XMC4 */ #endif /* XMC4_SCU_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc4_usic_map.h b/cores/xmc_lib/XMCLib/inc/xmc4_usic_map.h index 07f9f427..f41db6e9 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc4_usic_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc4_usic_map.h @@ -1,56 +1,43 @@ /** * @file xmc4_usic_map.h - * @date 2016-07-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-08-25: - * - Added XMC4800 - * - * 2015-12-07: - * - Add XMC4300 support + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-07-20: - * - Add missing USIC2_C1_DX0_P4_6,USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5, USIC2_C0_DX0_P9_4, USIC2_C1_DX1_P9_9, USIC2_C1_DX2_P9_8 for XMC47/48 BGA196 - * - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14 for XMC47/48 LQFP100 - * - Add missing USIC2_C1_DX0_P4_6, USIC1_C0_DX0_P1_14, USIC2_C0_DX0_P6_5 for XMC47/48 LQFP144 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * @endcond + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -60,7 +47,7 @@ /******************************************************************************* * MACROS *******************************************************************************/ - + #define USIC_INPUT_ALWAYS_1 7 #if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64) diff --git a/cores/xmc_lib/XMCLib/inc/xmc_acmp.h b/cores/xmc_lib/XMCLib/inc/xmc_acmp.h index 114dc57b..68b03fd8 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_acmp.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_acmp.h @@ -1,84 +1,56 @@ /** * @file xmc_acmp.h - * @date 2015-09-02 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2014-12-10: - * - Initial version - * 2015-02-20: - * - Removed unused declarations
      - * 2015-05-08: - * - Fixed sequence problem of low power mode in XMC_ACMP_Init() API
      - * - Fixed wrong register setting in XMC_ACMP_SetInput() API
      - * - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API.
      - * Additional call to XMC_ACMP_EnableComparator() API needed to start Comparator after Init.
      - * 2015-06-04: - * - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API.
      - * - Divided XMC_ACMP_SetInput into two 3 APIs to reduce the code size and complexity as stated below
      - * (a)XMC_ACMP_EnableReferenceDivider
      - * (b)XMC_ACMP_DisableReferenceDivider
      - * (c)XMC_ACMP_SetInput
      - * - Optimized enable and disable API's and moved to header file as static inline APIs. - * - XMC_ACMP_t typedef changed to structure which overrides the standard header file structure. - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * 2015-06-26: - * - API help documentation modified. - * 2015-09-02: - * - API help documentation modified for XMC1400 device support. - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * @endcond * */ - + #ifndef XMC_ACMP_H #define XMC_ACMP_H - -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup ACMP * @brief Analog Comparator(ACMP) low level driver for XMC1 family of microcontrollers.
      * - * The ACMP module consists of minimum of 3 analog comparators. Each analog comparator has two inputs, INP and INN. + * The ACMP module consists of minimum of 3 analog comparators. Each analog comparator has two inputs, INP and INN. * Input INP is compared with input INN in the pad voltage domain. - * It generates a digital comparator output signal. The digital comparator output signal is shifted down from VDDP + * It generates a digital comparator output signal. The digital comparator output signal is shifted down from VDDP * power supply voltage level to VDDC core voltage level. The ACMP module provides the following functionalities.\n * -# Monitor external voltage level * -# Operates in low power mode @@ -86,19 +58,19 @@ * \par The ACMP low level driver funtionalities *
        - *
      1. Initializes an instance of analog comparator module with the @ref XMC_ACMP_CONFIG_t configuration structure + *
      2. Initializes an instance of analog comparator module with the @ref XMC_ACMP_CONFIG_t configuration structure * using the API XMC_ACMP_Init().
        3. - *
      3. Programs the source of input(INP) specified by @ref XMC_ACMP_INP_SOURCE_t parameter using the API + *
      4. Programs the source of input(INP) specified by @ref XMC_ACMP_INP_SOURCE_t parameter using the API * XMC_ACMP_SetInput().
        5. *
      5. Sets the low power mode of operation using XMC_ACMP_SetLowPowerMode() API.
        6. *
      * @{ */ - + /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_common.h" /********************************************************************************************************************* * MACROS @@ -126,27 +98,27 @@ /** * Defines the return value of an API. - */ + */ typedef enum XMC_ACMP_STATUS { XMC_ACMP_STATUS_SUCCESS = 0U, /**< API completes the execution successfully */ - XMC_ACMP_STATUS_ERROR , /**< API cannot fulfill the request */ + XMC_ACMP_STATUS_ERROR, /**< API cannot fulfill the request */ } XMC_ACMP_STATUS_t; /** * Defines the hysteresis voltage levels to reduce noise sensitivity. - */ + */ typedef enum XMC_ACMP_HYSTERESIS { XMC_ACMP_HYSTERESIS_OFF = 0U, /**< No hysteresis */ - XMC_ACMP_HYSTERESIS_10 , /**< Hysteresis = 10mv */ - XMC_ACMP_HYSTERESIS_15 , /**< Hysteresis = 15mv */ + XMC_ACMP_HYSTERESIS_10, /**< Hysteresis = 10mv */ + XMC_ACMP_HYSTERESIS_15, /**< Hysteresis = 15mv */ XMC_ACMP_HYSTERESIS_20 /**< Hysteresis = 20mv */ } XMC_ACMP_HYSTERESIS_t; /** * Defines the comparator output status options. - */ + */ typedef enum XMC_ACMP_COMP_OUT { XMC_ACMP_COMP_OUT_NO_INVERSION = 0U, /**< ACMP output is HIGH when, Input Positive(INP) greater than Input @@ -157,7 +129,7 @@ typedef enum XMC_ACMP_COMP_OUT /** * Defines the analog comparator input connection method. - */ + */ typedef enum XMC_ACMP_INP_SOURCE { XMC_ACMP_INP_SOURCE_STANDARD_PORT = 0U, /**< Input is connected to port */ @@ -172,16 +144,17 @@ typedef enum XMC_ACMP_INP_SOURCE /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** * ACMP module */ -typedef struct { +typedef struct XMC_ACMP +{ __IO uint32_t ORCCTRL; __I uint32_t RESERVED[726]; __IO uint32_t ANACMP[XMC_ACMP_MAX_INSTANCES]; @@ -211,13 +184,13 @@ typedef struct XMC_ACMP_CONFIG /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif #ifdef __cplusplus - extern "C" { +extern "C" { #endif /********************************************************************************************************************* @@ -230,7 +203,7 @@ typedef struct XMC_ACMP_CONFIG * Range:
      0 - ACMP0
      * 1 - ACMP1
      * 2 - ACMP2
      - * 3 - ACMP3 - Only applicable for XMC1400 devices
      + * 3 - ACMP3 - Only applicable for XMC1400 devices
      * * @param config Pointer to configuration data. Refer data structure @ref XMC_ACMP_CONFIG_t for settings. * @return @@ -257,8 +230,8 @@ void XMC_ACMP_Init(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_AC * * \parDescription:
      * Enables an instance of ACMP module.
      \n - * Starts the comparator by setting CMP_EN bit of respective ANACMP \a instance register. The \a instance number - * determines which analog comparator to be switched on. Call this API after the successful completion of the comparator + * Starts the comparator by setting CMP_EN bit of respective ANACMP \a instance register. The \a instance number + * determines which analog comparator to be switched on. Call this API after the successful completion of the comparator * initilization and input selection. * * \parRelated APIs:
      @@ -280,12 +253,12 @@ __STATIC_INLINE void XMC_ACMP_EnableComparator(XMC_ACMP_t *const peripheral, uin * Range:
      0 - ACMP0
      * 1 - ACMP1
      * 2 - ACMP2
      - * 3 - ACMP3 - Only applicable for XMC1400 devices
      + * 3 - ACMP3 - Only applicable for XMC1400 devices
      * @return * None
      * \parDescription:
      * Disables an instance of ACMP module.
      \n - * Stops the comparator by resetting CMP_EN bit of respective ANACMP \a instance register. The \a instance number + * Stops the comparator by resetting CMP_EN bit of respective ANACMP \a instance register. The \a instance number * determines which analog comparator to be switched off. * * \parRelated APIs:
      @@ -300,7 +273,7 @@ __STATIC_INLINE void XMC_ACMP_DisableComparator(XMC_ACMP_t *const peripheral, ui } /** - * @param None + * @param None * @return * None
      * @@ -308,7 +281,7 @@ __STATIC_INLINE void XMC_ACMP_DisableComparator(XMC_ACMP_t *const peripheral, ui * Enables the reference divider for analog comparator instance 1.
      \n * ACMP1 input INP is driven by an internal reference voltage by setting DIV_EN bit of ANACMP1 register. * Other comparator instances can also share this reference divider option by calling the XMC_ACMP_SetInput() API. - * + * * \parRelated APIs:
      * XMC_ACMP_SetInput(). */ @@ -319,13 +292,13 @@ __STATIC_INLINE void XMC_ACMP_EnableReferenceDivider(void) } /** - * @param None + * @param None * @return * None
      * * \parDescription:
      * Disables the reference divider for analog comparator instance 1.
      \n - * ACMP1 input INP is disconnected from the reference divider. This is achieved by reseting DIV_EN bit of ANACMP1 + * ACMP1 input INP is disconnected from the reference divider. This is achieved by reseting DIV_EN bit of ANACMP1 * register. * * \parRelated APIs:
      @@ -342,17 +315,17 @@ __STATIC_INLINE void XMC_ACMP_DisableReferenceDivider(void) * @param instance ACMP instance number.
      * Range:
      0 - ACMP0
      * 2 - ACMP2
      - * 3 - ACMP3 - Only applicable for XMC1400 devices
      + * 3 - ACMP3 - Only applicable for XMC1400 devices
      * @param source ACMP input source selection options.
      * Range:
      XMC_ACMP_INP_SOURCE_STANDARD_PORT - Input is connected to port
      - * XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT - Input is connected to port and ACMP1 INP
      + * XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT - Input is connected to port and ACMP1 INP
      * @return * None
      * * \parDescription:
      * Sets the analog comparartor input selection for ACMP0, ACMP2 instances.
      \n * Apart from ACMP1 instance, each ACMP instances can be connected to its own port and ACMP1 INP. - * Calling @ref XMC_ACMP_EnableReferenceDivider() API, after this API can share the reference divider to one of the + * Calling @ref XMC_ACMP_EnableReferenceDivider() API, after this API can share the reference divider to one of the * comparartor input as explained in the following options.
      * The hardware options to set input are listed below.
      *
        @@ -365,7 +338,7 @@ __STATIC_INLINE void XMC_ACMP_DisableReferenceDivider(void) * * \parRelated APIs:
        * @ref XMC_ACMP_EnableReferenceDivider.
        - * @ref XMC_ACMP_DisableReferenceDivider. + * @ref XMC_ACMP_DisableReferenceDivider. */ void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, const XMC_ACMP_INP_SOURCE_t source); @@ -378,7 +351,7 @@ void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, const XM * \parDescription:
        * Set the comparartors to operate in low power mode, by setting the LPWR bit of ANACMP0 register.
        \n * The low power mode is controlled by ACMP0 instance. Low power mode is applicable for all instances of the - * comparator. In low power mode, blanking time will be introduced to ensure the stability of comparartor output. This + * comparator. In low power mode, blanking time will be introduced to ensure the stability of comparartor output. This * will slow down the comparator operation. * * \parRelated APIs:
        @@ -390,14 +363,14 @@ __STATIC_INLINE void XMC_ACMP_SetLowPowerMode(void) } /** - * @param None + * @param None * @return * None
        * * \parDescription:
        * Exits the low power mode by reseting LPWR bit of ANACMP0 register.
        \n * The low power mode is controlled by ACMP0 module. Low power mode is applicable for all instances of the - * comparator. To re-enable the low power mode, call the related API @ref XMC_ACMP_SetLowPowerMode(). + * comparator. To re-enable the low power mode, call the related API @ref XMC_ACMP_SetLowPowerMode(). * * \parRelated APIs:
        * XMC_ACMP_SetLowPowerMode(). @@ -411,10 +384,6 @@ __STATIC_INLINE void XMC_ACMP_ClearLowPowerMode(void) * @} */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_bccu.h b/cores/xmc_lib/XMCLib/inc/xmc_bccu.h index 1b7888fd..b1b08e62 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_bccu.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_bccu.h @@ -1,57 +1,41 @@ /** * @file xmc_bccu.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-19: - * - Initial draft
        - * - Documentation improved
        - * - * 2015-05-08: - * - Minor bug fix in XMC_BCCU_ClearEventFlag(). - * - New APIs are added: XMC_BCCU_DIM_ReadDimDivider(), XMC_BCCU_DIM_GetDimCurve(), XMC_BCCU_IsDitherEnable()
        - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * - * Detailed description of file:
        - * APIs for the functional blocks of BCCU have been defined:
        - * -- GLOBAL configuration
        - * -- Clock configuration, Function/Event configuration, Interrupt configuration
        - * + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * @endcond * */ @@ -62,33 +46,29 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_common.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup BCCU * @brief Brightness and Color Control Unit (BCCU) driver for the XMC1 microcontroller family. * * The Brightness and Color Control Unit (BCCU) is a dimming control peripheral for LED lighting applications. The BCCU - * module can be used to control multiple LED channels. Every channel generates one-bit sigma-delta bit stream with a + * module can be used to control multiple LED channels. Every channel generates one-bit sigma-delta bit stream with a * user adjustable 12-bit average value. The dimming engine changes the brightness gradually (exponential curve) to appear * natural to the human eye. It supports color control by adjusting the relative intensity of selected channels using a * linear walk scheme for smooth color changes. It also supports high-power multi-channel LED lamps by optionally packing * the bitstream. The optional packer which decreases the average rate of output switching by enforcing a defined on-time. * The BCCU module generates two trigger signals to the ADC (BCCU_TRIGOUT0 and BCCU_TRIGOU1) to start conversions in a - * synchronized manner. The module can also be used as a multi-channel digital-analog converter with low-pass filters on the + * synchronized manner. The module can also be used as a multi-channel digital-analog converter with low-pass filters on the * outputs. The BCCU module supports 3 independent dimming engines, 9 independent channels, Trap functions and 2 ADC * triggering modes. * * The driver is divided into global control (BCCU), channel control (BCCU_CH) and dimming control (BCCU_DIM). - * + * * BCCU features: * -# Configuration structure XMC_BCCU_GLOBAL_CONFIG_t and initialization function XMC_BCCU_GlobalInit() - * -# Allows configuring of clock settings (Fast clock, Bit clock and Dimming clock). XMC_BCCU_SetFastClockPrescaler(), + * -# Allows configuring of clock settings (Fast clock, Bit clock and Dimming clock). XMC_BCCU_SetFastClockPrescaler(), * -# XMC_BCCU_SelectBitClock(), XMC_BCCU_SetDimClockPrescaler(). * -# Allows configuring global trigger settings. XMC_BCCU_ConfigGlobalTrigger() * -# Allows enabling multiple channels together. XMC_BCCU_ConcurrentEnableChannels() @@ -106,7 +86,7 @@ * -# Allows knowing the status of linear walk completion. XMC_BCCU_IsLinearWalkComplete() * -# Allows setting flicker watchdog. XMC_BCCU_CH_EnableFlickerWatchdog(). * -# Allows configuring packer settings. XMC_BCCU_CH_EnablePacker(), XMC_BCCU_CH_SetPackerThreshold(), - * XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOffCounte(), XMC_BCCU_CH_SetPackerOnCounter() + * XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOffCounte(), XMC_BCCU_CH_SetPackerOnCounter() * -# Allows selecting dimming bypass. XMC_BCCU_CH_DisableDimmingBypass() * * BCCU_DIM features: @@ -116,7 +96,7 @@ * -# Allows knowing the status of dimming completion. XMC_BCCU_IsDimmingFinished() * -# Allows configuring dimming divider. XMC_BCCU_DIM_SetDimDivider() * -# Allows configuring dimming curve. XMC_BCCU_DIM_ConfigDimCurve() - * + * * Recommended programming sequence: * -# Set output passive and active levels using XMC_BCCU_ConcurrentSetOutputPassiveLevel() or XMC_BCCU_SetOutputPassiveLevel() * -# Initializes global features using XMC_BCCU_GlobalInit() @@ -147,100 +127,109 @@ /** * Defines the status of BCCU driver, to verify the related API calls. Use type \a XMC_BCCU_STATUS_t for this enum. */ - typedef enum { - XMC_BCCU_STATUS_SUCCESS = 0U, /**< Operation completed successfully */ - XMC_BCCU_STATUS_ERROR = 1U, /**< Operation has some errors */ +typedef enum XMC_BCCU_STATUS +{ + XMC_BCCU_STATUS_SUCCESS = 0U, /**< Operation completed successfully */ + XMC_BCCU_STATUS_ERROR = 1U, /**< Operation has some errors */ } XMC_BCCU_STATUS_t; - + /** * Provides the options to select bit clock mode. */ -typedef enum { - XMC_BCCU_BCLK_MODE_NORMAL = 0U, /**< Normal Mode: Bit clock runs at 1/4 of fast clock */ - XMC_BCCU_BCLK_MODE_FAST = 1U, /**< Fast Mode: Bit clock runs at same as fast clock */ +typedef enum XMC_BCCU_BCLK_MODE +{ + XMC_BCCU_BCLK_MODE_NORMAL = 0U, /**< Normal Mode: Bit clock runs at 1/4 of fast clock */ + XMC_BCCU_BCLK_MODE_FAST = 1U, /**< Fast Mode: Bit clock runs at same as fast clock */ } XMC_BCCU_BCLK_MODE_t; /** * Provides the options to select trigger mode. */ -typedef enum { - XMC_BCCU_TRIGMODE0 = 0U, /**< Mode0: Trigger on Any Channel using OR logic */ - XMC_BCCU_TRIGMODE1 = 1U, /**< Mode1: Trigger on Active channel using round-robin*/ +typedef enum XMC_BCCU_TRIGMODE +{ + XMC_BCCU_TRIGMODE0 = 0U, /**< Mode0: Trigger on Any Channel using OR logic */ + XMC_BCCU_TRIGMODE1 = 1U, /**< Mode1: Trigger on Active channel using round-robin*/ } XMC_BCCU_TRIGMODE_t; /** * Provides the options to select trigger delay, and only be used if Bit clock in Normal mode */ -typedef enum { - XMC_BCCU_TRIGDELAY_NO_DELAY = 0U, /**< BCCU trigger occurs on channel trigger(without delay) */ - XMC_BCCU_TRIGDELAY_QUARTER_BIT = 1U, /**< BCCU trigger occurs on 1/4 bit time delayed after channel trigger */ - XMC_BCCU_TRIGDELAY_HALF_BIT = 2U, /**< BCCU trigger occurs on 1/2 bit time delayed after channel trigger */ +typedef enum XMC_BCCU_TRIGDELAY +{ + XMC_BCCU_TRIGDELAY_NO_DELAY = 0U, /**< BCCU trigger occurs on channel trigger(without delay) */ + XMC_BCCU_TRIGDELAY_QUARTER_BIT = 1U, /**< BCCU trigger occurs on 1/4 bit time delayed after channel trigger */ + XMC_BCCU_TRIGDELAY_HALF_BIT = 2U, /**< BCCU trigger occurs on 1/2 bit time delayed after channel trigger */ } XMC_BCCU_TRIGDELAY_t; /** * Provides the options to select suspend mode */ -typedef enum { - XMC_BCCU_SUSPEND_MODE_IGNORE = 0U, /**< Request ignored, and module cannot get suspended */ - XMC_BCCU_SUSPEND_MODE_FREEZE = 1U, /**< All running channels gets stopped, and freeze into a last state (without safe stop) - */ - XMC_BCCU_SUSPEND_MODE_SAFE_FREEZE = 2U, /**< All running channels gets stopped, and freeze into a last state (with safe - stop) */ +typedef enum XMC_BCCU_SUSPEND_MODE +{ + XMC_BCCU_SUSPEND_MODE_IGNORE = 0U, /**< Request ignored, and module cannot get suspended */ + XMC_BCCU_SUSPEND_MODE_FREEZE = 1U, /**< All running channels gets stopped, and freeze into a last state (without safe stop) */ + XMC_BCCU_SUSPEND_MODE_SAFE_FREEZE = 2U, /**< All running channels gets stopped, and freeze into a last state (with safe stop) */ } XMC_BCCU_SUSPEND_MODE_t; /** * Provides the options to select trap edge */ -typedef enum { - XMC_BCCU_TRAPEDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */ - XMC_BCCU_TRAPEDGE_FALLING = 1U, /**< Trap on falling edge of the BCCU.TRAPL signal */ +typedef enum XMC_BCCU_TRAPEDGE +{ + XMC_BCCU_TRAPEDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */ + XMC_BCCU_TRAPEDGE_FALLING = 1U, /**< Trap on falling edge of the BCCU.TRAPL signal */ } XMC_BCCU_TRAPEDGE_t; /** * Provides the options to enable/disable the events. * The members can be combined using 'OR' operator for multiple selection.
        */ -typedef enum { - XMC_BCCU_EVENT_TRIGGER0 = 0x1U, /**< Trigger 0 event */ - XMC_BCCU_EVENT_TRIGGER1 = 0x2U, /**< Trigger 1 event */ - XMC_BCCU_EVENT_FIFOFULL = 0x4U, /**< FIFO Full event */ - XMC_BCCU_EVENT_FIFOEMPTY = 0x8U, /**< FIFO Empty event */ - XMC_BCCU_EVENT_TRAP = 0x10U, /**< Trap event */ +typedef enum XMC_BCCU_EVENT +{ + XMC_BCCU_EVENT_TRIGGER0 = 0x1U, /**< Trigger 0 event */ + XMC_BCCU_EVENT_TRIGGER1 = 0x2U, /**< Trigger 1 event */ + XMC_BCCU_EVENT_FIFOFULL = 0x4U, /**< FIFO Full event */ + XMC_BCCU_EVENT_FIFOEMPTY = 0x8U, /**< FIFO Empty event */ + XMC_BCCU_EVENT_TRAP = 0x10U, /**< Trap event */ } XMC_BCCU_EVENT_t; /** * Provides the options to know the status of the event flags. * The members can be combined using 'OR' operator for multiple selection.
        */ -typedef enum { - XMC_BCCU_EVENT_STATUS_TRIGGER0 = 0x1U, /**< Trigger 0 Event flag status */ - XMC_BCCU_EVENT_STATUS_TRIGGER1 = 0x2U, /**< Trigger 1 Event flag status */ - XMC_BCCU_EVENT_STATUS_FIFOFULL = 0x4U, /**< FIFO Full Event flag status */ - XMC_BCCU_EVENT_STATUS_FIFOEMPTY = 0x8U, /**< FIFO Empty Event flag status */ - XMC_BCCU_EVENT_STATUS_TRAP = 0x10U, /**< Trap Event flag status (Without Trap Set) */ - XMC_BCCU_EVENT_STATUS_TRAP_STATE = 0x40U, /**< Trap state flag status */ +typedef enum XMC_BCCU_EVENT_STATUS +{ + XMC_BCCU_EVENT_STATUS_TRIGGER0 = 0x1U, /**< Trigger 0 Event flag status */ + XMC_BCCU_EVENT_STATUS_TRIGGER1 = 0x2U, /**< Trigger 1 Event flag status */ + XMC_BCCU_EVENT_STATUS_FIFOFULL = 0x4U, /**< FIFO Full Event flag status */ + XMC_BCCU_EVENT_STATUS_FIFOEMPTY = 0x8U, /**< FIFO Empty Event flag status */ + XMC_BCCU_EVENT_STATUS_TRAP = 0x10U, /**< Trap Event flag status (Without Trap Set) */ + XMC_BCCU_EVENT_STATUS_TRAP_STATE = 0x40U, /**< Trap state flag status */ } XMC_BCCU_EVENT_STATUS_t; /** * Provides the options to know the status of trap occurrence */ -typedef enum { - XMC_BCCU_TRAP_STATUS_DEACTIVE = 0x0U, /**< BCCU module is not in a Trap State */ - XMC_BCCU_TRAP_STATUS_ACTIVE = 0x1U, /**< BCCU module is in a Trap State */ +typedef enum XMC_BCCU_TRAP_STATUS +{ + XMC_BCCU_TRAP_STATUS_DEACTIVE = 0x0U, /**< BCCU module is not in a Trap State */ + XMC_BCCU_TRAP_STATUS_ACTIVE = 0x1U, /**< BCCU module is in a Trap State */ } XMC_BCCU_TRAP_STATUS_t; /** * Provides the options to know the current level of trap */ -typedef enum { - XMC_BCCU_TRAP_LEVEL_LOW = 0x0U, /**< BCCU.TRAPL is Low */ - XMC_BCCU_TRAP_LEVEL_HIGH = 0x1U, /**< BCCU.TRAPL is High */ +typedef enum XMC_BCCU_TRAP_LEVEL +{ + XMC_BCCU_TRAP_LEVEL_LOW = 0x0U, /**< BCCU.TRAPL is Low */ + XMC_BCCU_TRAP_LEVEL_HIGH = 0x1U, /**< BCCU.TRAPL is High */ } XMC_BCCU_TRAP_LEVEL_t; /** * Provides the options to select flicker watchdog enable/disable */ -typedef enum { +typedef enum XMC_BCCU_CH_FLICKER_WD +{ XMC_BCCU_CH_FLICKER_WD_DS = 0U, /**< Disable: No control over a sigma-delta modulator output */ XMC_BCCU_CH_FLICKER_WD_EN = 1U, /**< Enable: Limit consecutive zeros at sigma-delta modulator output */ } XMC_BCCU_CH_FLICKER_WD_t; @@ -248,7 +237,8 @@ typedef enum { /** * Provides the options to select gating functionality enable/disable, and be used for peak-current control */ -typedef enum { +typedef enum XMC_BCCU_CH_GATING_FUNC +{ XMC_BCCU_CH_GATING_FUNC_DISABLE = 0U, /**< Disable: No control over a BCCU module output */ XMC_BCCU_CH_GATING_FUNC_ENABLE = 1U, /**< Enable: External gating signal which controls BCCU module output */ } XMC_BCCU_CH_GATING_FUNC_t; @@ -256,7 +246,8 @@ typedef enum { /** * Provides the options to bypass dimming engine */ -typedef enum { +typedef enum XMC_BCCU_CH_DIMMING_ENGINE_BYPASS +{ XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_DISABLE = 0U, /**< Disable: Brightness = Dimming Level * Intensity */ XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_ENABLE = 1U, /**< Enable: Brightness = Intensity */ } XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t; @@ -264,7 +255,8 @@ typedef enum { /** * Provides the options to select passive level of the channel output */ -typedef enum{ +typedef enum XMC_BCCU_CH_ACTIVE_LEVEL +{ XMC_BCCU_CH_ACTIVE_LEVEL_HIGH = 0U, /**< Default passive level of the channel is low */ XMC_BCCU_CH_ACTIVE_LEVEL_LOW = 1U, /**< Default passive level of the channel is high */ } XMC_BCCU_CH_ACTIVE_LEVEL_t; @@ -272,7 +264,7 @@ typedef enum{ /** * Provides the options to select trigger edge */ -typedef enum +typedef enum XMC_BCCU_CH_TRIG_EDGE { XMC_BCCU_CH_TRIG_EDGE_PASS_TO_ACT = 0U, /**< Trigger on output transition from passive to active */ XMC_BCCU_CH_TRIG_EDGE_ACT_TO_PASS = 1U, /**< Trigger on output transition from active to passive */ @@ -281,7 +273,7 @@ typedef enum /** * Provides the options to select source of trap input */ -typedef enum +typedef enum XMC_BCCU_CH_TRAP_IN { XMC_BCCU_CH_TRAP_INA = 0x0U, /**< Trap INA */ XMC_BCCU_CH_TRAP_INB = 0x1U, /**< Trap INB */ @@ -304,7 +296,7 @@ typedef enum /** * Provides the options to select edge for trap occurrence */ -typedef enum +typedef enum XMC_BCCU_CH_TRAP_EDGE { XMC_BCCU_CH_TRAP_EDGE_RISING = 0U, /**< Trap on rising edge of the BCCU.TRAPL signal */ XMC_BCCU_CH_TRAP_EDGE_FALLING = 1U /**< Trap on falling edge of the BCCU.TRAPL signal */ @@ -313,7 +305,8 @@ typedef enum /** * Provides the options to select trigger output, and only be used in XMC_BCCU_TRIGMODE1 */ -typedef enum { +typedef enum XMC_BCCU_CH_TRIGOUT +{ XMC_BCCU_CH_TRIGOUT0 = 0U, /**< Trigger occurrence on BCCU_TRIGOUT0 signal */ XMC_BCCU_CH_TRIGOUT1 = 1U, /**< Trigger occurrence on BCCU_TRIGOUT1 signal */ } XMC_BCCU_CH_TRIGOUT_t; @@ -321,7 +314,8 @@ typedef enum { /** * Provides the options to select dimming source of the channel */ -typedef enum { +typedef enum XMC_BCCU_CH_DIMMING_SOURCE +{ XMC_BCCU_CH_DIMMING_SOURCE_GLOBAL = 7U, /**< Global Dimming Engine */ XMC_BCCU_CH_DIMMING_SOURCE_DE0 = 0U, /**< Dimming Engine 0 */ XMC_BCCU_CH_DIMMING_SOURCE_DE1 = 1U, /**< Dimming Engine 1 */ @@ -331,10 +325,11 @@ typedef enum { /** * Provides the options to select exponential dimming curve */ -typedef enum { - XMC_BCCU_DIM_CURVE_COARSE = 0U, /**< Coarse curve: Slope of the linear pieces doubles every time, when it passes specific +typedef enum XMC_BCCU_DIM_CURVE +{ + XMC_BCCU_DIM_CURVE_COARSE = 0U, /**< Coarse curve: Slope of the linear pieces doubles every time, when it passes specific thresholds of 16, 32, 64, 128, 256, 512, 1024, 2048 */ - XMC_BCCU_DIM_CURVE_FINE = 1U, /**< Fine Curve: More pieces and different line slopes */ + XMC_BCCU_DIM_CURVE_FINE = 1U, /**< Fine Curve: More pieces and different line slopes */ } XMC_BCCU_DIM_CURVE_t; /********************************************************************************************************************* @@ -357,10 +352,10 @@ typedef BCCU_DE_Type XMC_BCCU_DIM_t; /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -368,23 +363,26 @@ typedef BCCU_DE_Type XMC_BCCU_DIM_t; */ typedef struct XMC_BCCU_GLOBAL_CONFIG { - union{ - struct{ - uint32_t trig_mode:1; /**< Selects trigger Mode. Use type @ref XMC_BCCU_TRIGMODE_t */ + union + { + struct + { + uint32_t trig_mode: 1; /**< Selects trigger Mode. Use type @ref XMC_BCCU_TRIGMODE_t */ uint32_t : 1; - uint32_t trig_delay:2; /**< Selects trigger delay between channel & module trigger. \n Use type @ref - XMC_BCCU_TRIGDELAY_t */ + uint32_t trig_delay: 2; /**< Selects trigger delay between channel & module trigger. \n Use type @ref XMC_BCCU_TRIGDELAY_t */ uint32_t : 12; - uint32_t maxzero_at_output:12; /**< Configures maximum 0's allowed at modulator output */ + uint32_t maxzero_at_output: 12; /**< Configures maximum 0's allowed at modulator output */ }; uint32_t globcon; /* Not to use */ }; - union{ - struct{ - uint32_t fclk_ps:12; /**< Configures the ratio between fast clock and module clock */ + union + { + struct + { + uint32_t fclk_ps: 12; /**< Configures the ratio between fast clock and module clock */ uint32_t : 3; - uint32_t bclk_sel:1; /**< Selects the bit clock. Use type @ref XMC_BCCU_BCLK_MODE_t */ - uint32_t dclk_ps:12; /**< Configures the ratio between dimmer clock and module clock */ + uint32_t bclk_sel: 1; /**< Selects the bit clock. Use type @ref XMC_BCCU_BCLK_MODE_t */ + uint32_t dclk_ps: 12; /**< Configures the ratio between dimmer clock and module clock */ }; uint32_t globclk; /* Not to use */ }; @@ -399,7 +397,7 @@ typedef struct XMC_BCCU_TRIG_CONFIG { XMC_BCCU_TRIGMODE_t mode; /**< Selects global trigger mode which decides when to occur BCCU trigger */ XMC_BCCU_TRIGDELAY_t delay; /**< Selects global trigger delay between channel trigger & BCCU trigger */ - uint16_t mask_chans; /**< Channel mask to configure trigger settings for multiple channels For example: + uint16_t mask_chans; /**< Channel mask to configure trigger settings for multiple channels For example: If channel 0 and 7, wants to configure then the channel mask is 01000 0001 = 0x81\n*/ uint16_t mask_trig_lines; /**< Trigger line mask */ } XMC_BCCU_TRIG_CONFIG_t; @@ -407,67 +405,69 @@ typedef struct XMC_BCCU_TRIG_CONFIG /** * Configures channel settings of the BCCU module. */ -#ifdef DOXYGEN +#ifdef DOXYGEN typedef struct XMC_BCCU_CH_CONFIG { - uint32_t pack_thresh:3; /**< Configures packer threshold value of FIFO */ - uint32_t pack_en:1; /**< Enables a packed output bitstream */ - uint32_t dim_sel:3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t */ - uint32_t dim_bypass:1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */ - uint32_t gate_en:1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */ - uint32_t flick_wd_en:1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */ - uint32_t trig_edge:1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */ - uint32_t force_trig_en:1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n for - 256 bclk cycles */ - uint32_t pack_offcmp_lev:8; /**< Configures a packer off-time compare level. When the off-time counter reaches this, the - measured on & off time counters are stored into FIFO */ - uint32_t pack_oncmp_lev:8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\n + uint32_t pack_thresh: 3; /**< Configures packer threshold value of FIFO */ + uint32_t pack_en: 1; /**< Enables a packed output bitstream */ + uint32_t dim_sel: 3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t */ + uint32_t dim_bypass: 1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */ + uint32_t gate_en: 1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */ + uint32_t flick_wd_en: 1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */ + uint32_t trig_edge: 1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */ + uint32_t force_trig_en: 1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n for 256 bclk cycles */ + uint32_t pack_offcmp_lev: 8; /**< Configures a packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters are stored into FIFO */ + uint32_t pack_oncmp_lev: 8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\n the measured on & off time counters are stored into FIFO */ - uint32_t pack_offcnt_val:8; /**< Configures an initial packer off-time counter level, only if channel is disabled.
        + uint32_t pack_offcnt_val: 8; /**< Configures an initial packer off-time counter level, only if channel is disabled.
        Controls phase shift of the modulator output */ - uint32_t pack_oncnt_val:8; /**< Configures an initial packer on-time counter level, only if channel is disabled.
        + uint32_t pack_oncnt_val: 8; /**< Configures an initial packer on-time counter level, only if channel is disabled.
        Controls phase shift of the modulator output */ -}XMC_BCCU_CH_CONFIG_t; +} XMC_BCCU_CH_CONFIG_t; #endif - + typedef struct XMC_BCCU_CH_CONFIG { - union{ - struct{ - uint32_t pack_thresh:3; /**< Configures packer threshold value of FIFO */ - uint32_t pack_en:1; /**< Enables a packed output bitstream */ - uint32_t dim_sel:3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t - */ - uint32_t dim_bypass:1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */ - uint32_t gate_en:1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */ - uint32_t flick_wd_en:1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */ - uint32_t trig_edge:1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */ - uint32_t force_trig_en:1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n - for 256 bclk cycles */ + union + { + struct + { + uint32_t pack_thresh: 3; /**< Configures packer threshold value of FIFO */ + uint32_t pack_en: 1; /**< Enables a packed output bitstream */ + uint32_t dim_sel: 3; /**< Selects a dimming engine source of the channel. \n Use type @ref XMC_BCCU_CH_DIMMING_SOURCE_t */ + uint32_t dim_bypass: 1; /**< Selects dimming engine bypass enable. \n Use type @ref XMC_BCCU_CH_DIMMING_ENGINE_BYPASS_t */ + uint32_t gate_en: 1; /**< Selects gating enable. Use type @ref XMC_BCCU_CH_GATING_FUNC_t */ + uint32_t flick_wd_en: 1; /**< Selects flicker watchdog enable. Use type @ref XMC_BCCU_CH_FLICKER_WD_t */ + uint32_t trig_edge: 1; /**< Selects trigger edge. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t */ + uint32_t force_trig_en: 1; /**< Selects force trigger enable; generates a trigger if modulator output do not change\n for 256 bclk cycles */ }; - uint32_t chconfig; /* Not to use */ + uint32_t chconfig; /* Not to use */ }; - union{ - struct{ - uint32_t pack_offcmp_lev:8; /**< Configures a packer off-time compare level. When the off-time counter reaches \n + union + { + struct + { + uint32_t pack_offcmp_lev: 8; /**< Configures a packer off-time compare level. When the off-time counter reaches \n this, the measured on & off time counters are stored into FIFO */ uint32_t : 8; - uint32_t pack_oncmp_lev:8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\n + uint32_t pack_oncmp_lev: 8; /**< Configures a packer on-time compare level. When the on-time counter reaches this,\n the measured on & off time counters are stored into FIFO */ }; uint32_t pkcmp; /* Not to use */ }; - union{ - struct{ - uint32_t pack_offcnt_val:8; /**< Configures an initial packer off-time counter level, only if channel is disabled.
        + union + { + struct + { + uint32_t pack_offcnt_val: 8; /**< Configures an initial packer off-time counter level, only if channel is disabled.
        Controls phase shift of the modulator output */ uint32_t : 8; - uint32_t pack_oncnt_val:8; /**< Configures an initial packer on-time counter level, only if channel is disabled.
        + uint32_t pack_oncnt_val: 8; /**< Configures an initial packer on-time counter level, only if channel is disabled.
        Controls phase shift of the modulator output */ }; uint32_t pkcntr; /* Not to use */ }; -}XMC_BCCU_CH_CONFIG_t; +} XMC_BCCU_CH_CONFIG_t; /** * Configures dimming engine settings of the BCCU module. @@ -475,34 +475,36 @@ typedef struct XMC_BCCU_CH_CONFIG #ifdef DOXYGEN typedef struct XMC_BCCU_DIM_CONFIG { - uint32_t dim_div:10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level
        + uint32_t dim_div: 10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level
        as same as target dimming level on shadow transfer */ - uint32_t dither_en:1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */ - uint32_t cur_sel:1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither
        + uint32_t dither_en: 1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */ + uint32_t cur_sel: 1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither
        enabled, the configuration is being ignored */ -}XMC_BCCU_DIM_CONFIG_t; +} XMC_BCCU_DIM_CONFIG_t; #endif typedef struct XMC_BCCU_DIM_CONFIG { - union{ - struct{ - uint32_t dim_div:10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level
        + union + { + struct + { + uint32_t dim_div: 10; /**< Configures a dimming clock divider, used to adjust the fade rate. If 0, the dimming level
        as same as target dimming level on shadow transfer */ uint32_t : 6; - uint32_t dither_en:1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */ - uint32_t cur_sel:1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither
        + uint32_t dither_en: 1; /**< Selects a dither enable. Dithering added for every dimming step if dimming level < 128. */ + uint32_t cur_sel: 1; /**< Selects a type of exponential curve. Use type @ref XMC_BCCU_DIM_CURVE_t. If dither
        enabled, the configuration is being ignored */ }; uint32_t dtt; /* Not to use */ }; -}XMC_BCCU_DIM_CONFIG_t; +} XMC_BCCU_DIM_CONFIG_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * API PROTOTYPES @@ -519,9 +521,9 @@ extern "C" { * @return None * * \parDescription:
        - * Initializes three main clocks (fast clock, bit clock, dimmer clock) by using \a fclk_ps \a bclk_sel \a dclk_ps parameters + * Initializes three main clocks (fast clock, bit clock, dimmer clock) by using \a fclk_ps \a bclk_sel \a dclk_ps parameters * and writing into a GLOBCLK register.\n - * And also configures a trigger mode, trigger delay, maximum 0's allowed at modulator output by writing into a GLOBCON + * And also configures a trigger mode, trigger delay, maximum 0's allowed at modulator output by writing into a GLOBCON * register.\n\n * * \parRelated APIs:
        @@ -541,11 +543,11 @@ void XMC_BCCU_GlobalInit (XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t * @return None * * \parDescription:
        - * Configures trigger mode and trigger delay by writing register bits GLOBCON.TM, GLOBCON.TRDEL. \a mode and \a delay + * Configures trigger mode and trigger delay by writing register bits GLOBCON.TM, GLOBCON.TRDEL. \a mode and \a delay * parameters which decides when to trigger a conversion of vadc module for voltage measurement. \n\n * * \parRelated APIs:
        - * XMC_BCCU_EnableChannelTrigger(), XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(), XMC_BCCU_GlobalInit(), + * XMC_BCCU_EnableChannelTrigger(), XMC_BCCU_ReadGlobalTrigger(), XMC_BCCU_ConcurrentConfigTrigger(), XMC_BCCU_GlobalInit(), * XMC_BCCU_ReadLastTrigChanNr(), XMC_BCCU_GetChannelOutputLvlAtLastTrigger(), XMC_BCCU_CH_ConfigTrigger()\n\n\n */ void XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mode, XMC_BCCU_TRIGDELAY_t delay); @@ -558,7 +560,7 @@ void XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mo * 0 - Trigger mode 0 (Trigger on Any Channel) \n * 1 - Trigger mode 1 (Trigger on Active Channel)\n\n * \parDescription:
        - * Retrieves global trigger mode of the BCCU module by reading the register bit GLOBCON_TM. Use XMC_BCCU_TRIGMODE_t type to + * Retrieves global trigger mode of the BCCU module by reading the register bit GLOBCON_TM. Use XMC_BCCU_TRIGMODE_t type to * validate a returned value.\n\n * * \parRelated APIs:
        @@ -566,19 +568,19 @@ void XMC_BCCU_ConfigGlobalTrigger(XMC_BCCU_t *const bccu, XMC_BCCU_TRIGMODE_t mo */ __STATIC_INLINE uint32_t XMC_BCCU_ReadGlobalTrigger (XMC_BCCU_t *const bccu) { - return (uint32_t)(bccu->GLOBCON & BCCU_GLOBCON_TM_Msk); + return (uint32_t)(bccu->GLOBCON & BCCU_GLOBCON_TM_Msk); } /** * * @param bccu Base address of the bccu module. \b Range: BCCU0 - * @param input Trap input selection. Use type @ref XMC_BCCU_TRIGDELAY_t. + * @param input Trap input selection. Use type @ref XMC_BCCU_TRIGDELAY_t. * \b Range: XMC_BCCU_TRIGDELAY_NO_DELAY, XMC_BCCU_TRIGDELAY_QUARTER_BIT, XMC_BCCU_TRIGDELAY_HALF_BIT. * * @return None * * \parDescription:
        - * Selects input of trap functionality by writing register bit GLOBCON_TRAPIS. The trap functionality is used to switch + * Selects input of trap functionality by writing register bit GLOBCON_TRAPIS. The trap functionality is used to switch * off the connected power devices when trap input becomes active.\n\n * * \parRelated APIs:
        @@ -594,7 +596,7 @@ void XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t inp * 0 - TRAPINA \n * 1 - TRAPINB and so on. \n * \parDescription:
        - * Retrieves trap input of the channel by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_CH_TRAP_IN_t type to + * Retrieves trap input of the channel by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_CH_TRAP_IN_t type to * validate a returned value.\n\n * * \parRelated APIs:
        @@ -602,7 +604,7 @@ void XMC_BCCU_SelectTrapInput (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_IN_t inp */ __STATIC_INLINE uint32_t XMC_BCCU_ReadTrapInput (XMC_BCCU_t *const bccu) { - return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPIS_Msk) >> BCCU_GLOBCON_TRAPIS_Pos); + return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPIS_Msk) >> BCCU_GLOBCON_TRAPIS_Pos); } /** @@ -629,7 +631,7 @@ void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge) * 0 - XMC_BCCU_CH_TRAP_EDGE_RISING \n * 1 - XMC_BCCU_CH_TRAP_EDGE_FALLING. \n * \parDescription:
        - * Retrieves trap edge by reading the register bit GLOBCON_TRAPED. Use XMC_BCCU_CH_TRAP_EDGE_t type to + * Retrieves trap edge by reading the register bit GLOBCON_TRAPED. Use XMC_BCCU_CH_TRAP_EDGE_t type to * validate a returned value.\n\n * * \parRelated APIs:
        @@ -637,7 +639,7 @@ void XMC_BCCU_SetTrapEdge (XMC_BCCU_t *const bccu, XMC_BCCU_CH_TRAP_EDGE_t edge) */ __STATIC_INLINE uint32_t XMC_BCCU_ReadTrapEdge (XMC_BCCU_t *const bccu) { - return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPED_Msk) >> BCCU_GLOBCON_TRAPED_Pos); + return (uint32_t)(( (bccu->GLOBCON) & BCCU_GLOBCON_TRAPED_Msk) >> BCCU_GLOBCON_TRAPED_Pos); } /** @@ -665,7 +667,7 @@ void XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t * 1 - XMC_BCCU_SUSPEND_MODE_FREEZE. \n * 2 - XMC_BCCU_USPEND_MODE_SAFE_FREEZE. \n * \parDescription:
        - * Retrieves the state of suspend mode by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_SUSPEND_MODE_t type to + * Retrieves the state of suspend mode by reading the register bit GLOBCON_TRAPIS. Use XMC_BCCU_SUSPEND_MODE_t type to * validate a returned value.\n\n * * \parRelated APIs:
        @@ -673,7 +675,7 @@ void XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t */ __STATIC_INLINE uint32_t XMC_BCCU_ReadSuspendMode (XMC_BCCU_t *const bccu) { - return (uint32_t)( ((bccu->GLOBCON) & BCCU_GLOBCON_SUSCFG_Msk) >> BCCU_GLOBCON_SUSCFG_Pos); + return (uint32_t)( ((bccu->GLOBCON) & BCCU_GLOBCON_SUSCFG_Msk) >> BCCU_GLOBCON_SUSCFG_Pos); } /** @@ -703,7 +705,7 @@ __STATIC_INLINE uint32_t XMC_BCCU_ReadLastTrigChanNr (XMC_BCCU_t *const bccu) * @return None * * \parDescription:
        - * Configures number of consecutive zeroes allowed at modulator output (flicker watch-dog number) by writing register + * Configures number of consecutive zeroes allowed at modulator output (flicker watch-dog number) by writing register * bit GLOBCON_WDMBN.\n\n * * \parRelated APIs:
        @@ -717,7 +719,7 @@ void XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_ * * @return Number of consecutive zeroes at modulator output. \b Range: 0 to 4095 \n * \parDescription:
        - * Retrieves number of consecutive zeroes at modulator output (flicker watchdog number) by reading the register bit + * Retrieves number of consecutive zeroes at modulator output (flicker watchdog number) by reading the register bit * GLOBCON_WDMBN.\n\n * * \parRelated APIs:
        @@ -931,7 +933,7 @@ void XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask); /** * * @param bccu Base address of the bccu module. \b Range: BCCU0 - * @param trig Pointer to a trigger configuration data structure. Use type @ref XMC_BCCU_TRIG_CONFIG_t. + * @param trig Pointer to a trigger configuration data structure. Use type @ref XMC_BCCU_TRIG_CONFIG_t. * * @return None * @@ -979,7 +981,7 @@ void XMC_BCCU_ConcurrentStartLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask); * @return None * * \parDescription:
        - * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change) + * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change) * immediately for multiple channels at a same time using \a mask by writing a register CHSTRCON.\n\n * * \parRelated APIs:
        @@ -991,7 +993,7 @@ void XMC_BCCU_ConcurrentAbortLinearWalk (XMC_BCCU_t *const bccu, uint32_t mask); * * @param bccu Base address of the bccu module. \b Range: BCCU0 * @param mask Dimming engine mask to enable multiple dimming engine at a same time.\n - * For example: If dimming engine 0, channel 2 wants to enable a dimming at a same time, + * For example: If dimming engine 0, channel 2 wants to enable a dimming at a same time, * then dimming engine mask is 0101 = 0x03\n * --------------------------\n * | DE2 | DE1 | DE0 |\n @@ -1011,7 +1013,7 @@ void XMC_BCCU_ConcurrentEnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t ma * * @param bccu Base address of the bccu module. \b Range: BCCU0 * @param mask Dimming engine mask to disable multiple dimming engine at a same time.\n - * For example: If dimming engine 0, channel 2 wants to disable a dimming at a same time, + * For example: If dimming engine 0, channel 2 wants to disable a dimming at a same time, * then dimming engine mask is 0101 = 0x03\n * --------------------------\n * | DE2 | DE1 | DE0 |\n @@ -1031,7 +1033,7 @@ void XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t m * * @param bccu Base address of the bccu module. \b Range: BCCU0 * @param mask Dimming engine mask to start a dimming for multiple dimming engines at a same time.\n - * For example: If dimming engine 0, channel 2 wants to start a dimming at a same time, + * For example: If dimming engine 0, channel 2 wants to start a dimming at a same time, * then dimming engine mask is 0101 = 0x03\n * --------------------------\n * | DE2 | DE1 | DE0 |\n @@ -1040,7 +1042,7 @@ void XMC_BCCU_ConcurrentDisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t m * @return None * * \parDescription:
        - * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target + * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target * for multiple dimming engines at a same time using \a mask by writing a register DESTRCON.\n\n * * \parRelated APIs:
        @@ -1052,7 +1054,7 @@ void XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask); * * @param bccu Base address of the bccu module. \b Range: BCCU0 * @param mask Dimming engine mask to abort a dimming for multiple dimming engines at a same time.\n - * For example: If dimming engine 0, channel 2 wants to abort a dimming at a same time, + * For example: If dimming engine 0, channel 2 wants to abort a dimming at a same time, * then dimming engine mask is 0101 = 0x03\n * --------------------------\n * | DE2 | DE1 | DE0 |\n @@ -1061,7 +1063,7 @@ void XMC_BCCU_ConcurrentStartDimming (XMC_BCCU_t *const bccu, uint32_t mask); * @return None * * \parDescription:
        - * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading) + * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading) * immediately for specific dimming engine number \a dim_no by writing a register DESTRCON.\n\n * * \parRelated APIs:
        @@ -1077,7 +1079,7 @@ void XMC_BCCU_ConcurrentAbortDimming (XMC_BCCU_t *const bccu, uint32_t mask); * @return None * * \parDescription:
        - * Configures a global dimming level by writing a register GLOBDIM. This is useful only if global dimming engine selected. + * Configures a global dimming level by writing a register GLOBDIM. This is useful only if global dimming engine selected. * Otherwise the configuration is ignored. \n\n * * \parRelated APIs:
        @@ -1089,8 +1091,8 @@ void XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level); * * @param bccu Base address of the bccu module. \b Range: BCCU0 * @param event Event mask to enable multiple events at a time using ORed values of @ref XMC_BCCU_EVENT_t.\n - * For example: If XMC_BCCU_EVENT_TRIGGER0, XMC_BCCU_EVENT_TRIGGER1, XMC_BCCU_EVENT_FIFOEMPTY wants to enable - * at a same time,\n then event mask is = (XMC_BCCU_EVENT_TRIGGER0 | XMC_BCCU_EVENT_TRIGGER1 | + * For example: If XMC_BCCU_EVENT_TRIGGER0, XMC_BCCU_EVENT_TRIGGER1, XMC_BCCU_EVENT_FIFOEMPTY wants to enable + * at a same time,\n then event mask is = (XMC_BCCU_EVENT_TRIGGER0 | XMC_BCCU_EVENT_TRIGGER1 | * XMC_BCCU_EVENT_FIFOEMPTY) \n * * @return None @@ -1111,7 +1113,7 @@ __STATIC_INLINE void XMC_BCCU_EnableInterrupt (XMC_BCCU_t *const bccu, uint32_t * @param bccu Base address of the bccu module. \b Range: BCCU0 * @param event Event mask to disable multiple events at a time using ORed values of @ref XMC_BCCU_EVENT_t.\n * For example: If XMC_BCCU_EVENT_TRIGGER0, XMC_BCCU_EVENT_TRIGGER1, XMC_BCCU_EVENT_FIFOEMPTY wants to disable\n - * at a same time, then event mask is = (XMC_BCCU_EVENT_TRIGGER0 | XMC_BCCU_EVENT_TRIGGER1 | + * at a same time, then event mask is = (XMC_BCCU_EVENT_TRIGGER0 | XMC_BCCU_EVENT_TRIGGER1 | * XMC_BCCU_EVENT_FIFOEMPTY) \n * * @return None @@ -1147,10 +1149,10 @@ __STATIC_INLINE uint32_t XMC_BCCU_ReadEventFlag (XMC_BCCU_t *const bccu) /** * * @param bccu Base address of the bccu module. \b Range: BCCU0 - * @param flag_type Event flag mask to configure multiple events at a time using ORed values of @ref + * @param flag_type Event flag mask to configure multiple events at a time using ORed values of @ref * XMC_BCCU_EVENT_STATUS_t.\n - * For example: If XMC_BCCU_EVENT_STATUS_TRIGGER0, XMC_BCCU_EVENT_STATUS_TRIGGER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY - * wants to configure at a same time, then event mask is = (XMC_BCCU_EVENT_STATUS_TRIGGER0 | XMC_BCCU_EVENT_STATUS_TRIGGER1 | + * For example: If XMC_BCCU_EVENT_STATUS_TRIGGER0, XMC_BCCU_EVENT_STATUS_TRIGGER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY + * wants to configure at a same time, then event mask is = (XMC_BCCU_EVENT_STATUS_TRIGGER0 | XMC_BCCU_EVENT_STATUS_TRIGGER1 | * XMC_BCCU_EVENT_STATUS_FIFOEMPTY) \n * * @return None @@ -1169,16 +1171,16 @@ __STATIC_INLINE void XMC_BCCU_SetEventFlag (XMC_BCCU_t *const bccu, uint32_t fla /** * * @param bccu Base address of the bccu module. \b Range: BCCU0 - * @param flag_type event flag mask to clear multiple events at a time using ORed values of @ref + * @param flag_type event flag mask to clear multiple events at a time using ORed values of @ref * XMC_BCCU_EVENT_STATUS_t.\n - * For example: If XMC_BCCU_EVENT_STATUS_TRIGGER0, XMC_BCCU_EVENT_STATUS_TRIGGER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY - * wants to clear at a same time, then event mask is = (XMC_BCCU_EVENT_STATUS_TRIGGER0 | XMC_BCCU_EVENT_STATUS_TRIGGER1 | + * For example: If XMC_BCCU_EVENT_STATUS_TRIGGER0, XMC_BCCU_EVENT_STATUS_TRIGGER1, XMC_BCCU_EVENT_STATUS_FIFOEMPTY + * wants to clear at a same time, then event mask is = (XMC_BCCU_EVENT_STATUS_TRIGGER0 | XMC_BCCU_EVENT_STATUS_TRIGGER1 | * XMC_BCCU_EVENT_STATUS_FIFOEMPTY) \n * * @return None * * \parDescription:
        - * Clears multiple interrupt event flags at a same time using ORed values of @ref XMC_BCCU_EVENT_STATUS_t by writing a + * Clears multiple interrupt event flags at a same time using ORed values of @ref XMC_BCCU_EVENT_STATUS_t by writing a * register EVFSR.\n\n * * \parRelated APIs:
        @@ -1306,9 +1308,9 @@ void XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no); * @return None * * \parDescription:
        - * Configures dimming engine source, dimming bypass selection, channel trigger edge, flicker watchdog selection and force - * trigger selection by using \a dim_sel, \a dim_bypass, \a trig_edge, \a flick_wd_en, \a force_trig_en by writing into a - * CHCONFIG register. And also configures packer settings: threshold, off and on compare levels, initial values of off & on + * Configures dimming engine source, dimming bypass selection, channel trigger edge, flicker watchdog selection and force + * trigger selection by using \a dim_sel, \a dim_bypass, \a trig_edge, \a flick_wd_en, \a force_trig_en by writing into a + * CHCONFIG register. And also configures packer settings: threshold, off and on compare levels, initial values of off & on * counters, by writing into a CHCONFIG, PKCMP and PKCNTR registers.\n\n * * \parRelated APIs:
        @@ -1322,12 +1324,12 @@ void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t * @param edge Output transition selection. Use type @ref XMC_BCCU_CH_TRIG_EDGE_t. \n * \b Range: XMC_BCCU_CH_TRIG_EDGE_PASS_TO_ACT or XMC_BCCU_CH_TRIG_EDGE_ACT_TO_PASS\n * @param force_trig_en Forcing a trigger at output. \b Range: 0 or 1\n - * Generates a trigger if modulator output do not change for 256 bclk cycles\n + * Generates a trigger if modulator output do not change for 256 bclk cycles\n * * @return None * * \parDescription:
        - * Configures global trigger settings: trigger edge, force trigger enable by writing a register CHCONFIG. + * Configures global trigger settings: trigger edge, force trigger enable by writing a register CHCONFIG. * And also configures force trigger enable, generates a trigger if modulator output do not change for 256 bclk cycles * * \parRelated APIs:
        @@ -1343,7 +1345,7 @@ void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_E * @return None * * \parDescription:
        - * After channel initialization, the outcome of executing the API starts changing the color smoothly towards to target + * After channel initialization, the outcome of executing the API starts changing the color smoothly towards to target * by writing a register bit CHSTRCON_CHyS.\n\n * * \parRelated APIs:
        @@ -1363,7 +1365,7 @@ __STATIC_INLINE void XMC_BCCU_StartLinearWalk (XMC_BCCU_t *const bccu, uint32_t * @return None * * \parDescription:
        - * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change) + * When the linear walk in progress, the outcome of executing the API is stopping the linear walk (i.e. color change) * immediately for specific channels number using \a mask by writing a register CHSTRCON_CHyA.\n\n * * \parRelated APIs:
        @@ -1430,7 +1432,7 @@ __STATIC_INLINE uint32_t XMC_BCCU_IsLinearWalkComplete (XMC_BCCU_t *const bccu, * @return None * * \parDescription:
        - * Configures target channel intensity by writing register INTS, only be written if no shadow transfer of linear walk. + * Configures target channel intensity by writing register INTS, only be written if no shadow transfer of linear walk. * Use XMC_BCCU_IsLinearWalkComplete() to know shadow transfer finished \n\n * * \parRelated APIs:
        @@ -1454,11 +1456,11 @@ uint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel); /** * * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. - * @param thresh Packer threshold value of FIFO. It defines number of queue stages must be filled before output generator + * @param thresh Packer threshold value of FIFO. It defines number of queue stages must be filled before output generator * starts generating the pulses. Until that, only off-bits are generated at the output.\n - * @param off_comp Packer off-time compare level. When the off-time counter reaches this, the measured on off time + * @param off_comp Packer off-time compare level. When the off-time counter reaches this, the measured on off time * counters are stored into FIFO - * @param on_comp Packer on-time compare level. When the on-time counter reaches this, the measured on & off time + * @param on_comp Packer on-time compare level. When the on-time counter reaches this, the measured on & off time * counters are stored into FIFO * * @return None @@ -1491,7 +1493,7 @@ void XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val) /** * * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. - * @param level Packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters + * @param level Packer off-time compare level. When the off-time counter reaches this, the measured on & off time counters * are stored into FIFO * * @return None @@ -1500,7 +1502,7 @@ void XMC_BCCU_CH_SetPackerThreshold (XMC_BCCU_CH_t *const channel, uint32_t val) * Configures packer off compare level by writing register bit PKCMP_OFFCMP\n\n * * \parRelated APIs:
        - * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOnCompare(), XMC_BCCU_CH_SetPackerOffCounter(), + * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOnCompare(), XMC_BCCU_CH_SetPackerOffCounter(), * XMC_BCCU_CH_ReadPackerOffCompare()\n\n\n */ void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t level); @@ -1508,7 +1510,7 @@ void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t lev /** * * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. - * @param level Packer on-time compare level. When the on-time counter reaches this, the measured on & off time counters + * @param level Packer on-time compare level. When the on-time counter reaches this, the measured on & off time counters * are stored into FIFO * * @return None @@ -1517,7 +1519,7 @@ void XMC_BCCU_CH_SetPackerOffCompare (XMC_BCCU_CH_t *const channel, uint32_t lev * Configures packer on compare level by writing register bit PKCMP_ONCMP\n\n * * \parRelated APIs:
        - * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCounter(), + * XMC_BCCU_CH_SetPackerThreshold(), XMC_BCCU_CH_SetPackerOffCompare(), XMC_BCCU_CH_SetPackerOnCounter(), * XMC_BCCU_CH_ReadPackerOnCompare()\n\n\n */ void XMC_BCCU_CH_SetPackerOnCompare (XMC_BCCU_CH_t *const channel, uint32_t level); @@ -1589,7 +1591,7 @@ void XMC_BCCU_CH_DisablePacker (XMC_BCCU_CH_t *const channel); /** * * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. - * @param cnt_val Configures an initial packer off-time counter level, only if channel is disabled. Controls phase + * @param cnt_val Configures an initial packer off-time counter level, only if channel is disabled. Controls phase * shift of the modulator output * * @return None @@ -1606,7 +1608,7 @@ void XMC_BCCU_CH_SetPackerOffCounter (XMC_BCCU_CH_t *const channel, uint32_t cnt /** * * @param channel Base address of the bccu channel. \b Range: BCCU0_CH0, BCCU0_CH1.. - * @param cnt_val Configures an initial packer on-time counter level, only if channel is disabled. Controls phase shift + * @param cnt_val Configures an initial packer on-time counter level, only if channel is disabled. Controls phase shift * of the modulator output * * @return None @@ -1670,7 +1672,7 @@ void XMC_BCCU_CH_DisableDimmingBypass (XMC_BCCU_CH_t *const channel); * @return None * * \parDescription:
        - * Enables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable fast control schemes, + * Enables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable fast control schemes, * such as peak-current control and this has been controlled by Analog Comparator module.\n\n * * \parRelated APIs:
        @@ -1688,7 +1690,7 @@ __STATIC_INLINE void XMC_BCCU_CH_EnableGating (XMC_BCCU_CH_t *const channel) * @return None * * \parDescription:
        - * Disables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable/disable fast control + * Disables gating feature by writing register bit CHCONFIG_GEN. The gating feature is used to enable/disable fast control * schemes, such as peak-current control and this has been controlled by Analog Comparator module. \n\n * * \parRelated APIs:
        @@ -1710,7 +1712,7 @@ __STATIC_INLINE void XMC_BCCU_CH_DisableGating (XMC_BCCU_CH_t *const channel) * according to Watchdog threshold\n\n * * \parRelated APIs:
        - * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), + * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), * XMC_BCCU_CH_DisableFlickerWatchdog()\n\n\n */ __STATIC_INLINE void XMC_BCCU_CH_EnableFlickerWatchdog (XMC_BCCU_CH_t *const channel) @@ -1729,7 +1731,7 @@ __STATIC_INLINE void XMC_BCCU_CH_EnableFlickerWatchdog (XMC_BCCU_CH_t *const cha * according to Watchdog threshold\n\n * * \parRelated APIs:
        - * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), + * XMC_BCCU_SetFlickerWDThreshold(), XMC_BCCU_ReadFlickerWDThreshold(), XMC_BCCU_CH_Init(), * XMC_BCCU_CH_EnableFlickerWatchdog()\n\n\n */ __STATIC_INLINE void XMC_BCCU_CH_DisableFlickerWatchdog (XMC_BCCU_CH_t *const channel) @@ -1745,7 +1747,7 @@ __STATIC_INLINE void XMC_BCCU_CH_DisableFlickerWatchdog (XMC_BCCU_CH_t *const ch * @return None * * \parDescription:
        - * Configures dimming clock divider to adjust the fade rate, dither selection and exponential curve selection using \a + * Configures dimming clock divider to adjust the fade rate, dither selection and exponential curve selection using \a * dim_div, \a dither_en, \a cur_sel parameters and by writing into a DTT register.\n\n * * \parRelated APIs:
        @@ -1768,7 +1770,7 @@ void XMC_BCCU_DIM_Init (XMC_BCCU_DIM_t *const dim_engine, const XMC_BCCU_DIM_CON */ __STATIC_INLINE void XMC_BCCU_EnableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t dim_no) { - bccu->DEEN |= (uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no); + bccu->DEEN |= (uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no); } /** @@ -1786,7 +1788,7 @@ __STATIC_INLINE void XMC_BCCU_EnableDimmingEngine (XMC_BCCU_t *const bccu, uint3 */ __STATIC_INLINE void XMC_BCCU_DisableDimmingEngine (XMC_BCCU_t *const bccu, uint32_t dim_no) { - bccu->DEEN &= ~(uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no); + bccu->DEEN &= ~(uint32_t)(BCCU_DEEN_EDE0_Msk << dim_no); } /** @@ -1797,7 +1799,7 @@ __STATIC_INLINE void XMC_BCCU_DisableDimmingEngine (XMC_BCCU_t *const bccu, uint * @return None * * \parDescription:
        - * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target + * After dimming engine initialization, the outcome of executing the API starts changing the brightness towards to target * by writing a register bit DESTRCON_DEyS.\n\n * * \parRelated APIs:
        @@ -1805,7 +1807,7 @@ __STATIC_INLINE void XMC_BCCU_DisableDimmingEngine (XMC_BCCU_t *const bccu, uint */ __STATIC_INLINE void XMC_BCCU_StartDimming (XMC_BCCU_t *const bccu, uint32_t dim_no) { - bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0S_Msk << dim_no); + bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0S_Msk << dim_no); } /** @@ -1816,7 +1818,7 @@ __STATIC_INLINE void XMC_BCCU_StartDimming (XMC_BCCU_t *const bccu, uint32_t dim * @return None * * \parDescription:
        - * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading) + * When the dimming in progress, the outcome of executing the API is stopping the dimming (i.e. fading) * immediately for specific dimming engine number \a dim_no by writing a register bit DESTRCON_DEyA.\n\n * * \parRelated APIs:
        @@ -1824,7 +1826,7 @@ __STATIC_INLINE void XMC_BCCU_StartDimming (XMC_BCCU_t *const bccu, uint32_t dim */ __STATIC_INLINE void XMC_BCCU_AbortDimming (XMC_BCCU_t *const bccu, uint32_t dim_no) { - bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0A_Msk << dim_no); + bccu->DESTRCON = (uint32_t)(BCCU_DESTRCON_DE0A_Msk << dim_no); } /** @@ -1834,7 +1836,7 @@ __STATIC_INLINE void XMC_BCCU_AbortDimming (XMC_BCCU_t *const bccu, uint32_t dim * * @return Dimming completion status. \b Range: 0-Completed or 1-start change towards the target * \parDescription:
        - * Retrieves dimming completion status for specific dimming engine number using \a dim_no by reading the register bit + * Retrieves dimming completion status for specific dimming engine number using \a dim_no by reading the register bit * DESTRCON_DEyS. \n\n * * \parRelated APIs:
        @@ -1905,7 +1907,7 @@ void XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div) * \parRelated APIs:
        * XMC_BCCU_DIM_SetDimDivider()\n\n\n */ - __STATIC_INLINE uint32_t XMC_BCCU_DIM_ReadDimDivider(XMC_BCCU_DIM_t *const dim_engine) +__STATIC_INLINE uint32_t XMC_BCCU_DIM_ReadDimDivider(XMC_BCCU_DIM_t *const dim_engine) { return (uint32_t)(dim_engine->DTT & BCCU_DE_DTT_DIMDIV_Msk); } @@ -1963,9 +1965,6 @@ __STATIC_INLINE uint32_t XMC_BCCU_IsDitherEnable(XMC_BCCU_DIM_t *const dim_engin * @} */ -/** - * @} - */ #ifdef __cplusplus } diff --git a/cores/xmc_lib/XMCLib/inc/xmc_can.h b/cores/xmc_lib/XMCLib/inc/xmc_can.h index ac4e1729..63875298 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_can.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_can.h @@ -1,91 +1,42 @@ /** * @file xmc_can.h - * @date 2016-06-07 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
        - * - Documentation improved
        - * - * 2015-05-20: - * - New elements have added in XMC_CAN_MO_t data structure
        - * - XMC_CAN_MO_Config() signature has changed
        - * - XMC_CAN_STATUS_t enum structure has updated.
        - * - * 2015-06-20: - * - New APIs added: XMC_CAN_NODE_ClearStatus(),XMC_CAN_MO_ReceiveData(), XMC_CAN_GATEWAY_InitDesObject().
        - * - Removed version macros and declaration of GetDriverVersion API - * - * 2015-07-09: - * - New API added: XMC_CAN_NODE_Enable.
        - * - * 2015-09-01: - * - Removed fCANB clock support
        - * - * 2015-09-15: - * - Added "xmc_can_map.h" include
        - * - * 2016-06-07: - * - Added XMC_CAN_IsPanelControlReady() - * - * Details of use for node configuration related APIs
        - * Please use the XMC_CAN_NODE_SetInitBit() and XMC_CAN_NODE_EnableConfigurationChange() before calling node configuration - * related APIs. - * XMC_CAN_NODE_DisableConfigurationChange() and XMC_CAN_NODE_ResetInitBit() can be called for disable the configuration - * change and enable the node for communication afterwards. - * Do not use this when configuring the nominal bit time with XMC_CAN_NODE_NominalBitTimeConfigure(). In this case the - * Enable/Disable node configuration change is taken in account. - * - * Example Usage: - * @code - * //disabling the Node - * XMC_CAN_NODE_SetInitBit(CAN_NODE0) - * //allowing the configuration change - * XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE0) - * //Node configuration - * XMC_CAN_NODE_FrameCounterConfigure(CAN_NODE0,&can_node_frame_counter); - * XMC_CAN_NODE_EnableLoopBack(CAN_NODE0) - * //disable configuration - * XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE0) - * //Enabling node for communication - * XMC_CAN_NODE_ResetInitBit(CAN_NODE0) - * @endcode - * - * 2016-06-20: - * - Fixed bug in XMC_CAN_MO_Config()
        + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * * @endcond * */ @@ -98,36 +49,32 @@ ********************************************************************************************************************/ #include "xmc_common.h" -#if defined(CAN) +#if defined(CAN_xmc) #include "xmc_scu.h" #include "xmc_can_map.h" #include -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup CAN * @brief Controller Area Network Controller (CAN) driver for the XMC microcontroller family. * - * CAN driver provides transfer of CAN frames in accordance with CAN specificetion V2.0 B (active). Each CAN node + * CAN driver provides transfer of CAN frames in accordance with CAN specificetion V2.0 B (active). Each CAN node * can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. * All CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the - * CAN nodes. + * CAN nodes. * Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build - * gateways between + * gateways between * the CAN nodes or to setup a FIFO buffer. The CAN module provides Analyzer mode,Loop-back mode and bit timming for * node analysis. - * + * * The driver is divided into five sections: * \par CAN Global features: * -# Allows to configure module frequency using function XMC_CAN_Init(). * -# Allows to configure Module interrupt using configuration structure XMC_CAN_NODE_INTERRUPT_TRIGGER_t and function * XMC_CAN_EventTrigger(). - * + * * \par CAN_NODE features: * -# Allows to set baud rate by configuration structure XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t and Baudrate Configuration * function XMC_CAN_NODE_NominalBitTimeConfigure(). @@ -136,21 +83,21 @@ * -# Allows CAN node events enable/ disable by enum structure XMC_CAN_NODE_EVENT_t and functions XMC_CAN_NODE_EnableEvent() * and XMC_CAN_NODE_DisableEvent(). * -# Provides bit timming analysis, configuration structure XMC_CAN_NODE_FRAME_COUNTER_t and function - * XMC_CAN_NODE_FrameCounterConfigure(). + * XMC_CAN_NODE_FrameCounterConfigure(). * * \par CAN_MO features: * -# Allows message object initialization by configuration structure XMC_CAN_MO_t and function XMC_CAN_MO_Config(). * -# Allows transfer of message objects using functions XMC_CAN_MO_Transmit() and XMC_CAN_MO_Receive(). - * -# Allows to configure Single Data Transfer and Single Transmit Trial using functions + * -# Allows to configure Single Data Transfer and Single Transmit Trial using functions * XMC_CAN_MO_EnableSingleTransmitTrial() and XMC_CAN_MO_EnableSingleTransmitTrial(). - * -# Allows to configure MO events using function XMC_CAN_MO_EnableEvent(). + * -# Allows to configure MO events using function XMC_CAN_MO_EnableEvent(). * * \par CAN_FIFO features: - * -# Allows message object FIFO structure by configuration structure XMC_CAN_FIFO_CONFIG_t and functions - * XMC_CAN_TXFIFO_ConfigMOBaseObject() , XMC_CAN_RXFIFO_ConfigMOBaseObject() and XMC_CAN_TXFIFO_Transmit(). + * -# Allows message object FIFO structure by configuration structure XMC_CAN_FIFO_CONFIG_t and functions + * XMC_CAN_TXFIFO_ConfigMOBaseObject() , XMC_CAN_RXFIFO_ConfigMOBaseObject() and XMC_CAN_TXFIFO_Transmit(). * * \par CAN_GATEWAY features: - * -# Provides Gateway mode, configuration structure XMC_CAN_GATEWAY_CONFIG_t and function XMC_CAN_GATEWAY_InitSourceObject(). + * -# Provides Gateway mode, configuration structure XMC_CAN_GATEWAY_CONFIG_t and function XMC_CAN_GATEWAY_InitSourceObject(). * * @{ */ @@ -158,13 +105,13 @@ /********************************************************************************************************************* * MACROS ********************************************************************************************************************/ -#define XMC_CAN_MO_MOAR_STDID_Pos (18U) /**< Standard Identifier bitposition */ +#define XMC_CAN_MO_MOAR_STDID_Pos (18U) /**< Standard Identifier bitposition */ #define XMC_CAN_MO_MOAR_STDID_Msk ((0x000007FFUL) << XMC_CAN_MO_MOAR_STDID_Pos) /**< Standard Identifier bitMask */ -#define CAN_NODE_NIPR_Msk (0x7UL) /**< Node event mask */ +#define CAN_NODE_NIPR_Msk (0x7UL) /**< Node event mask */ -#define CAN_MO_MOIPR_Msk (0x7U) /**< Message Object event mask */ +#define CAN_MO_MOIPR_Msk (0x7U) /**< Message Object event mask */ /********************************************************************************************************************* * ENUMS @@ -190,7 +137,7 @@ typedef enum XMC_CAN_PANCMD XMC_CAN_PANCMD_STATIC_ALLOCATE = 2U, /**< Command to activate static allocation */ XMC_CAN_PANCMD_DYNAMIC_ALLOCATE = 3U, /**< Command to activate dynamic allocation */ - XMC_CAN_PANCMD_STATIC_INSERT_BEFORE = 4U, /**< Remove a message object from the list and insert it before a given object.*/ + XMC_CAN_PANCMD_STATIC_INSERT_BEFORE = 4U, /**< Remove a message object from the list and insert it before a given object.*/ XMC_CAN_PANCMD_DYNAMIC_INSERT_BEFORE = 5U, /**< Command to activate dynamic allocation */ XMC_CAN_PANCMD_STATIC_INSERT_BEHIND = 6U, /**< Command to activate dynamic allocation */ XMC_CAN_PANCMD_DYNAMIC_INSERT_BEHIND = 7U /**< Command to activate dynamic allocation */ @@ -240,7 +187,7 @@ typedef enum XMC_CAN_ARBITRATION_MODE */ typedef enum XMC_CAN_FRAME_COUNT_MODE { - XMC_CAN_FRAME_COUNT_MODE = 0U, /**< Frame Count Mode */ + XMC_CAN_FRAME_COUNT_MODE = 0U, /**< Frame Count Mode */ XMC_CAN_FRAME_COUNT_MODE_TIME_STAMP = 1U, /**< The frame counter is incremented with the beginning of a new bit time*/ XMC_CAN_FRAME_COUNT_MODE_BIT_TIMING = 2U /**< Used for baud rate detection and analysis of the bit timing */ } XMC_CAN_FRAME_COUNT_MODE_t; @@ -311,7 +258,7 @@ typedef enum XMC_CAN_MO_STATUS XMC_CAN_MO_STATUS_TX_ENABLE1 = CAN_MO_MOSTAT_TXEN1_Msk, /**< Transmit enable 1 */ XMC_CAN_MO_STATUS_MESSAGE_DIRECTION = CAN_MO_MOSTAT_DIR_Msk, /**< Message direction */ XMC_CAN_MO_STATUS_LIST = CAN_MO_MOSTAT_LIST_Msk, /**< List allocation */ - XMC_CAN_MO_STATUS_POINTER_TO_PREVIOUS_MO = CAN_MO_MOSTAT_PPREV_Msk, /**< Pointer to previous Message Object */ + XMC_CAN_MO_STATUS_POINTER_TO_PREVIOUS_MO = CAN_MO_MOSTAT_PPREV_Msk, /**< Pointer to previous Message Object */ XMC_CAN_MO_STATUS_POINTER_TO_NEXT_MO = (int32_t)CAN_MO_MOSTAT_PNEXT_Msk /**< Pointer to next Message Object */ } XMC_CAN_MO_STATUS_t; @@ -325,7 +272,7 @@ typedef enum XMC_CAN_NODE_STATUS XMC_CAN_NODE_STATUS_RX_OK = CAN_NODE_NSR_RXOK_Msk, /**< Message received successfully */ XMC_CAN_NODE_STATUS_ALERT_WARNING = CAN_NODE_NSR_ALERT_Msk, /**< Alert warning */ XMC_CAN_NODE_STATUS_ERROR_WARNING_STATUS = CAN_NODE_NSR_EWRN_Msk, /**< Error warning status */ - XMC_CAN_NODE_STATUS_BUS_OFF= CAN_NODE_NSR_BOFF_Msk, /**< Bus-off status */ + XMC_CAN_NODE_STATUS_BUS_OFF = CAN_NODE_NSR_BOFF_Msk, /**< Bus-off status */ XMC_CAN_NODE_STATUS_LIST_LENGTH_ERROR = CAN_NODE_NSR_LLE_Msk, /**< List length error */ XMC_CAN_NODE_STATUS_LIST_OBJECT_ERROR = CAN_NODE_NSR_LOE_Msk, /**< List object error */ #if !defined(MULTICAN_PLUS) @@ -344,7 +291,7 @@ typedef enum XMC_CAN_NODE_CONTROL XMC_CAN_NODE_CONTROL_LEC_INT_ENABLE = CAN_NODE_NCR_LECIE_Msk, /**< LEC Indicated Error Event Enable */ XMC_CAN_NODE_CONTROL_ALERT_INT_ENABLE = CAN_NODE_NCR_ALIE_Msk, /**< Alert Event Enable */ XMC_CAN_NODE_CONTROL_CAN_DISABLE = CAN_NODE_NCR_CANDIS_Msk, /**< CAN disable */ - XMC_CAN_NODE_CONTROL_CONF_CHANGE_ENABLE= CAN_NODE_NCR_CCE_Msk, /**< Configuration change enable */ + XMC_CAN_NODE_CONTROL_CONF_CHANGE_ENABLE = CAN_NODE_NCR_CCE_Msk, /**< Configuration change enable */ XMC_CAN_NODE_CONTROL_CAN_ANALYZER_NODEDE = CAN_NODE_NCR_CALM_Msk, /**< CAN Analyzer mode */ #if !defined(MULTICAN_PLUS) XMC_CAN_NODE_CONTROL_SUSPENDED_ENABLE = CAN_NODE_NCR_SUSEN_Msk /**< Suspend Enable */ @@ -397,14 +344,14 @@ typedef enum XMC_CAN_MO_EVENT */ typedef enum XMC_CAN_NODE_RECEIVE_INPUT { - XMC_CAN_NODE_RECEIVE_INPUT_RXDCA, /**< CAN Receive Input A */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCB, /**< CAN Receive Input B */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCC, /**< CAN Receive Input C */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCD, /**< CAN Receive Input D */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCE, /**< CAN Receive Input E */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCF, /**< CAN Receive Input F */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCG, /**< CAN Receive Input G */ - XMC_CAN_NODE_RECEIVE_INPUT_RXDCH /**< CAN Receive Input H */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCA, /**< CAN Receive Input A */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCB, /**< CAN Receive Input B */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCC, /**< CAN Receive Input C */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCD, /**< CAN Receive Input D */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCE, /**< CAN Receive Input E */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCF, /**< CAN Receive Input F */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCG, /**< CAN Receive Input G */ + XMC_CAN_NODE_RECEIVE_INPUT_RXDCH /**< CAN Receive Input H */ } XMC_CAN_NODE_RECEIVE_INPUT_t; /** @@ -441,21 +388,22 @@ typedef enum XMC_CAN_NODE_INTERRUPT_TRIGGER XMC_CAN_NODE_INTR_TRIGGER_7 = 0x128U, } XMC_CAN_NODE_INTERRUPT_TRIGGER_t; -#if defined(MULTICAN_PLUS) || defined(DOXYGEN) /** - * Defines the Clock source used for the MCAN peripheral. @note Only available for XMC1400, XMC4800 and XMC4700 series + * Defines the Clock source used for the MCAN baudrate generator */ typedef enum XMC_CAN_CANCLKSRC { -#if UC_FAMILY == XMC4 - XMC_CAN_CANCLKSRC_FPERI = 0x1U, - XMC_CAN_CANCLKSRC_FOHP = 0x2U, +#if defined(MULTICAN_PLUS) || defined(DOXYGEN) +#if (UC_FAMILY == XMC4) + XMC_CAN_CANCLKSRC_FPERI = 0x1U, /**< Use peripheral clock as MCAN baudrate generator input clock. */ #else - XMC_CAN_CANCLKSRC_MCLK = 0x1U, - XMC_CAN_CANCLKSRC_FOHP = 0x2U + XMC_CAN_CANCLKSRC_MCLK = 0x1U, /**< Use peripheral clock as MCAN baudrate generator input clock. */ #endif -} XMC_CAN_CANCLKSRC_t; + XMC_CAN_CANCLKSRC_FOHP = 0x2U, /**< Use high performance oscillator (fOHP) as MCAN baudrate generator input clock. @note Only available for XMC1400, XMC4800 and XMC4700 series*/ +#else + XMC_CAN_CANCLKSRC_FPERI = 0x1U, /**< Use peripheral clock as MCAN baudrate generator input clock. */ #endif +} XMC_CAN_CANCLKSRC_t; /********************************************************************************************************************* * DATA STRUCTURES @@ -465,11 +413,11 @@ typedef enum XMC_CAN_CANCLKSRC */ typedef struct XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG { - uint32_t can_frequency; /**< Frequency of the CAN module(fCAN). \a can_frequency shall be range of 5MHz to 120MHz */ - uint32_t baudrate; /**< Specifies the node baud rate. Unit: baud \a baudrate shall be range of 100Kbps to 1000Kbps*/ - uint16_t sample_point; /**< Sample point is used to compensate mismatch between transmitter and receiver clock phases detected in - the synchronization segment. Sample point. Range = [0, 10000] with respect [0%, 100%] of the total bit time.*/ - uint16_t sjw; /**< (Re) Synchronization Jump Width. Range:0-3 */ + uint32_t can_frequency; /**< Frequency of the CAN module(fCAN). \a can_frequency shall be range of 5MHz to 144MHz */ + uint32_t baudrate; /**< Specifies the node baud rate. Unit: baud \a baudrate shall be range of 100Kbps to 1000Kbps*/ + uint16_t sample_point; /**< Sample point is used to compensate mismatch between transmitter and receiver clock phases detected in + the synchronization segment. Sample point. Range = [0, 10000] with respect [0%, 100%] of the total bit time.*/ + uint16_t sjw; /**< (Re) Synchronization Jump Width. Range:0-3 */ } XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t; /** @@ -478,9 +426,9 @@ typedef struct XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG */ typedef struct XMC_CAN_FIFO_CONFIG { - uint8_t fifo_bottom; /**< points to the first element(slave object) in a FIFO structure.Range :0-63*/ - uint8_t fifo_top; /**< points to the last element(slave object) in a FIFO structure. Range :0-63*/ - uint8_t fifo_base; /**< points to the actual target object(Base object) within a FIFO/Gateway structure. Range :0-63*/ + uint8_t fifo_bottom; /**< points to the first element(slave object) in a FIFO structure.Range :0-63*/ + uint8_t fifo_top; /**< points to the last element(slave object) in a FIFO structure. Range :0-63*/ + uint8_t fifo_base; /**< points to the actual target object(Base object) within a FIFO/Gateway structure. Range :0-63*/ } XMC_CAN_FIFO_CONFIG_t; /** @@ -489,18 +437,18 @@ typedef struct XMC_CAN_FIFO_CONFIG */ typedef struct XMC_CAN_GATEWAY_CONFIG { - uint8_t gateway_bottom; /**< points to the first element(gateway destination object) in a FIFO structure. Range :0-63*/ - uint8_t gateway_top; /**< points to the last element(gateway destination object) in a FIFO structure. Range :0-63*/ - uint8_t gateway_base; /**< points to the actual target object within a FIFO/Gateway structure. Range :0-63*/ - bool gateway_data_frame_send; /**< TXRQ updated in the gateway destination object after the internal transfer from the gateway source - to the gateway destination object */ - bool gateway_identifier_copy; /**< The identifier of the gateway source object (after storing the received frame in the source) is copied - to the gateway destination object. */ + uint8_t gateway_bottom; /**< points to the first element(gateway destination object) in a FIFO structure. Range :0-63*/ + uint8_t gateway_top; /**< points to the last element(gateway destination object) in a FIFO structure. Range :0-63*/ + uint8_t gateway_base; /**< points to the actual target object within a FIFO/Gateway structure. Range :0-63*/ + bool gateway_data_frame_send; /**< TXRQ updated in the gateway destination object after the internal transfer from the gateway source + to the gateway destination object */ + bool gateway_identifier_copy; /**< The identifier of the gateway source object (after storing the received frame in the source) is copied + to the gateway destination object. */ bool gateway_data_length_code_copy; /**< Data length code of the gateway source object (after storing the received frame in the source) is copied to the - gateway destination object */ + gateway destination object */ bool gateway_data_copy; /**< Data fields in registers MODATALn and MODATAHn of the gateway source object (after storing the received frame in the source) - are copied to the gateway destination.*/ + are copied to the gateway destination.*/ } XMC_CAN_GATEWAY_CONFIG_t; @@ -511,10 +459,10 @@ typedef CAN_GLOBAL_TypeDef XMC_CAN_t; /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -525,14 +473,16 @@ typedef CAN_GLOBAL_TypeDef XMC_CAN_t; typedef struct XMC_CAN_NODE_FRAME_COUNTER { - union{ - struct{ - uint32_t : 16; - uint32_t can_frame_count_selection:3; /**< Defines function of the frame counter */ - uint32_t can_frame_count_mode:2; /**< Determines the operation mode of the frame counter */ - uint32_t : 11; - }; - uint32_t nfcr; + union + { + struct + { + uint32_t : 16; + uint32_t can_frame_count_selection: 3; /**< Defines function of the frame counter */ + uint32_t can_frame_count_mode: 2; /**< Determines the operation mode of the frame counter */ + uint32_t : 11; + }; + uint32_t nfcr; }; } XMC_CAN_NODE_FRAME_COUNTER_t; @@ -547,41 +497,46 @@ typedef CAN_NODE_TypeDef XMC_CAN_NODE_t; /**< pointer to the Node C */ typedef struct XMC_CAN_MO { - CAN_MO_TypeDef *can_mo_ptr; /**< Pointer to the Message Object CAN register */ - union{ - struct{ - uint32_t can_identifier:29; /**< standard (11 bit)/Extended (29 bit) message identifier */ - uint32_t can_id_mode:1; /**< Standard/Extended identifier support */ - uint32_t can_priority:2; /**< Arbitration Mode/Priority */ - }; - uint32_t mo_ar; - }; - union{ - struct{ - uint32_t can_id_mask:29; /**< CAN Identifier of Message Object */ - uint32_t can_ide_mask:1; /**< Identifier Extension Bit of Message Object */ - }; - uint32_t mo_amr; - }; + CAN_MO_TypeDef *can_mo_ptr; /**< Pointer to the Message Object CAN register */ + union + { + struct + { + uint32_t can_identifier: 29; /**< standard (11 bit)/Extended (29 bit) message identifier */ + uint32_t can_id_mode: 1; /**< Standard/Extended identifier support */ + uint32_t can_priority: 2; /**< Arbitration Mode/Priority */ + }; + uint32_t mo_ar; + }; + union + { + struct + { + uint32_t can_id_mask: 29; /**< CAN Identifier of Message Object */ + uint32_t can_ide_mask: 1; /**< Identifier Extension Bit of Message Object */ + }; + uint32_t mo_amr; + }; uint8_t can_data_length; /**< Message data length, Range:0-8 */ - union{ + union + { - uint8_t can_data_byte[8]; /**< Each position of the array represents a data byte*/ - uint16_t can_data_word[4]; /**< Each position of the array represents a 16 bits data word*/ - uint32_t can_data[2]; /**< can_data[0] lower 4 bytes of the data. can_data[1], higher 4 bytes - of the data */ - uint64_t can_data_long; /** Data of the Message Object*/ - }; + uint8_t can_data_byte[8]; /**< Each position of the array represents a data byte*/ + uint16_t can_data_word[4]; /**< Each position of the array represents a 16 bits data word*/ + uint32_t can_data[2]; /**< can_data[0] lower 4 bytes of the data. can_data[1], higher 4 bytes + of the data */ + uint64_t can_data_long; /** Data of the Message Object*/ + }; XMC_CAN_MO_TYPE_t can_mo_type; /**< Message Type */ } XMC_CAN_MO_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * API Prototypes @@ -592,8 +547,8 @@ extern "C" { /** * - * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef - * for details. + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. * * @return None * @@ -610,7 +565,7 @@ void XMC_CAN_Disable(XMC_CAN_t *const obj); /** * * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef - * for details. + * for details. * * @return None * @@ -628,10 +583,10 @@ void XMC_CAN_Enable(XMC_CAN_t *const obj); /** * * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef - * for details. + * for details. * - * @param node_num CAN node number,Range : 0-2 - * @param mo_num CAN Message Object number,Range : 0-63 + * @param node_num CAN node number,Range : 0-2 + * @param mo_num CAN Message Object number,Range : 0-63 * * @return None * @@ -669,11 +624,11 @@ __STATIC_INLINE bool XMC_CAN_IsPanelControlReady(XMC_CAN_t *const obj) /** * * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef - * for details. + * for details. * * @param pancmd panal command selection. Refer @ref XMC_CAN_PANCMD_t for valid values. - * @param arg1 Panel Argument 1,Range : 0-2 - * @param arg2 Panel Argument 2, Range : 0-63 + * @param arg1 Panel Argument 1,Range : 0-2 + * @param arg2 Panel Argument 2, Range : 0-63 * * @return None * @@ -690,23 +645,23 @@ __STATIC_INLINE bool XMC_CAN_IsPanelControlReady(XMC_CAN_t *const obj) */ __STATIC_INLINE void XMC_CAN_PanelControl(XMC_CAN_t *const obj, - const XMC_CAN_PANCMD_t pancmd, - const uint8_t arg1, - const uint8_t arg2) + const XMC_CAN_PANCMD_t pancmd, + const uint8_t arg1, + const uint8_t arg2) { obj->PANCTR = (((uint32_t)pancmd << CAN_PANCTR_PANCMD_Pos) & (uint32_t)CAN_PANCTR_PANCMD_Msk) | - (((uint32_t)arg1 << CAN_PANCTR_PANAR1_Pos) & (uint32_t)CAN_PANCTR_PANAR1_Msk) | - (((uint32_t)arg2 << CAN_PANCTR_PANAR2_Pos) & (uint32_t)CAN_PANCTR_PANAR2_Msk); + (((uint32_t)arg1 << CAN_PANCTR_PANAR1_Pos) & (uint32_t)CAN_PANCTR_PANAR1_Msk) | + (((uint32_t)arg2 << CAN_PANCTR_PANAR2_Pos) & (uint32_t)CAN_PANCTR_PANAR2_Msk); } /** * * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef - * for details. + * for details. * - * @param service_requestr Interrupt trigger number selection. Refer @ref XMC_CAN_NODE_INTERRUPT_TRIGGER_t for valid values. - * Multiple interrupt trigger events can be ORed. + * @param service_requestr Interrupt trigger number selection. Refer @ref XMC_CAN_NODE_INTERRUPT_TRIGGER_t for valid values. + * Multiple interrupt trigger events can be ORed. * * @return None * @@ -719,48 +674,110 @@ __STATIC_INLINE void XMC_CAN_PanelControl(XMC_CAN_t *const obj, * */ -__STATIC_INLINE void XMC_CAN_EventTrigger(XMC_CAN_t *const obj,const XMC_CAN_NODE_INTERRUPT_TRIGGER_t service_requestr) +__STATIC_INLINE void XMC_CAN_EventTrigger(XMC_CAN_t *const obj, const XMC_CAN_NODE_INTERRUPT_TRIGGER_t service_requestr) { obj->MITR = ((uint32_t)service_requestr << CAN_MITR_IT_Pos) & (uint32_t)CAN_MITR_IT_Msk; } - - /*INIT APIs*/ - /** * * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef - * for details. + * for details. * - * @param can_frequency CAN module frequency(fCAN). Range : 5MHz to 120MHz + * @param clksrc CAN module frequency clock source + * @param can_frequency CAN module frequency(fCAN). + * The can_frequency shall be an integer divisor of the CAN clock source frequency (fPERI/fMCLK or fOHP) and + * it should be selected such that if fulfills the minimum operating frequency specified in the clock control section of the reference manual. + * In addition the can_frequency shall be an integer multiple of the baudrate. + * Max. value: Max. clock source frequency, i.e. if using fOHP and using a XTAL of 20MHz then fCAN max. value is 20MHz. * - * @return None + * @return Actual frequency * * \parDescription:
        - * Configures clock rate of the module timer clock fCAN. Altering CAN module \a can_frequency shall affects baud rate, - * call XMC_CAN_NODE_NominalBitTimeConfigure() to configure baud rate for current CAN frequency.It configures FDR register. + * Similar to XMC_CAN_Init() configures clock rate of the module timer clock fCAN. + * The difference being that only the normal divider is used to avoid jitter. + * In addition the actual achievable frequency is returned. + * @note Use XMC_CAN_InitEx() for new projects. XMC_CAN_Init() is kept for backward compatibility reasons. + * + * Altering CAN module \a can_frequency shall affects baud rate, call XMC_CAN_NODE_NominalBitTimeConfigureEx() to configure baud rate for current CAN frequency. + * It configures FDR register. * * \parRelated APIs:
        - * XMC_CAN_NODE_NominalBitTimeConfigure()\n\n\n + * XMC_CAN_NODE_NominalBitTimeConfigure(), XMC_CAN_NODE_NominalBitTimeConfigureEx()\n\n\n * */ +uint32_t XMC_CAN_InitEx(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency); - -#if defined(MULTICAN_PLUS) -void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency); /** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. * + * @return Baudrate generator clock source + * + * \parDescription:
        + * Returns CAN baudrate generator clock source */ XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj); + /** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. * + * @return None + * + * \parDescription:
        + * Sets CAN baudrate generator clock source */ -void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source); +void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj, const XMC_CAN_CANCLKSRC_t source); + /** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return baudrate generator input clock frequency * + * \parDescription:
        + * Gets CAN baudrate generator input clock frequency */ uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj); + +/** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @return fCAN clock frequency + * + * \parDescription:
        + * Gets CAN base clock frequency + * + */ +uint32_t XMC_CAN_GetClockFrequency(XMC_CAN_t *const obj); + +#if defined(MULTICAN_PLUS) || defined(DOXYGEN) +/** + * + * @param obj Pointer pointing to XMC_CAN Global Initialization structure. Defines CAN global registers,refer CAN_NODE_TypeDef + * for details. + * + * @param clksrc CAN module frequency clock source. + * @param can_frequency CAN module frequency(fCAN). Max. value: Max. clock source frequency, i.e. if using fOHP and using a XTAL of 20MHz then fCAN max. value is 20MHz. + * @note Use clksrc parameter only for XMC1400 series and XMC47/4800 series projects, otherwise omit this parameter. + * + * @return None + * + * \parDescription:
        + * Configures clock rate of the module timer clock fCAN. Altering CAN module \a can_frequency shall affects baud rate, + * call XMC_CAN_NODE_NominalBitTimeConfigure() or XMC_CAN_NODE_NominalBitTimeConfigureEx() to configure baud rate for current CAN frequency. + * It configures FDR register. + * + * @note Use XMC_CAN_InitEx() for new projects. XMC_CAN_Init() is kept for backward compatibility reasons. + * + * \parRelated APIs:
        + * XMC_CAN_NODE_NominalBitTimeConfigure(), XMC_CAN_NODE_NominalBitTimeConfigureEx(), XMC_CAN_InitEx()\n\n\n + * + */ +void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency); #else void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency); #endif @@ -779,17 +796,14 @@ void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency); * None * */ - void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo); - - /*NODE APIs*/ - +/* NODE APIs */ /** * - * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. - * @param ptr_event CAN_NODE interrupt pointer position. Refer @ref XMC_CAN_NODE_POINTER_EVENT_t structure for valid values. + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. + * @param ptr_event CAN_NODE interrupt pointer position. Refer @ref XMC_CAN_NODE_POINTER_EVENT_t structure for valid values. * @param service_request Interrupt service request number. Range : 0-7 * * @return None @@ -803,8 +817,8 @@ void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo); */ __STATIC_INLINE void XMC_CAN_NODE_SetEventNodePointer(XMC_CAN_NODE_t *const can_node, - const XMC_CAN_NODE_POINTER_EVENT_t ptr_event, - const uint32_t service_request) + const XMC_CAN_NODE_POINTER_EVENT_t ptr_event, + const uint32_t service_request) { can_node->NIPR = (uint32_t)((can_node->NIPR) & ~(uint32_t)(CAN_NODE_NIPR_Msk << (uint32_t)ptr_event)) | (service_request << (uint32_t)ptr_event); } @@ -812,8 +826,8 @@ __STATIC_INLINE void XMC_CAN_NODE_SetEventNodePointer(XMC_CAN_NODE_t *const can_ /** * - * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. Range :CAN_NODE0-CAN_NODE2 - * @param can_bit_time Nominal bit time configuration data structure. Refer @ref XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for details. + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. Range :CAN_NODE0-CAN_NODE2 + * @param can_bit_time Nominal bit time configuration data structure. Refer @ref XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for details. * * @return None * @@ -825,8 +839,30 @@ __STATIC_INLINE void XMC_CAN_NODE_SetEventNodePointer(XMC_CAN_NODE_t *const can_ * None * */ -void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, - const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time); +void XMC_CAN_NODE_NominalBitTimeConfigure(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time); + +/** + * + * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers. Range :CAN_NODE0-CAN_NODE2 + * @param can_bit_time Nominal bit time configuration data structure. Refer @ref XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t for details. + * + * @return Status on the sucess setting the desired bitrate XMC_CAN_STATUS_t + * + * \parDescription:
        + * Similar to XMC_CAN_NODE_NominalBitTimeConfigure() configures the CAN node baudrate. + * The difference being that allows bitrates below 100kpbs. + * @note Consider using the new API for new projects. XMC_CAN_NODE_NominalBitTimeConfigure() is kept for backward compatibility reasons. + * + * Configures CAN node Baudrate. \a can_bit_time specifies required baudrate for a specified \a can_node. + * It configures NBTR register. + * + * \parRelated APIs:
        + * XMC_CAN_InitEx() + * + */ +int32_t XMC_CAN_NODE_NominalBitTimeConfigureEx(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time); /** * @param can_node Pointer pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. @@ -849,7 +885,7 @@ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, */ __STATIC_INLINE void XMC_CAN_NODE_SetReceiveInput(XMC_CAN_NODE_t *const can_node, - const XMC_CAN_NODE_RECEIVE_INPUT_t input) + const XMC_CAN_NODE_RECEIVE_INPUT_t input) { can_node->NPCR = ((can_node->NPCR) & ~(uint32_t)(CAN_NODE_NPCR_RXSEL_Msk)) | (((uint32_t)input << CAN_NODE_NPCR_RXSEL_Pos) & (uint32_t)CAN_NODE_NPCR_RXSEL_Msk); @@ -857,7 +893,7 @@ __STATIC_INLINE void XMC_CAN_NODE_SetReceiveInput(XMC_CAN_NODE_t *const can_node /** - * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. + * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. * * @return None * @@ -910,8 +946,8 @@ __STATIC_INLINE void XMC_CAN_NODE_DisableLoopBack(XMC_CAN_NODE_t *const can_node /** * * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. - * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. - * multiple events can be ORed. + * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. + * multiple events can be ORed. * * @return None * @@ -929,8 +965,8 @@ void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE /** * * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. - * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. - * multiple events can be ORed. + * @param event CAN node event mask value. Refer @ref XMC_CAN_NODE_EVENT_t structure for valid values. + * multiple events can be ORed. * * @return None * @@ -981,14 +1017,14 @@ __STATIC_INLINE XMC_CAN_NODE_LAST_ERROR_DIR_t XMC_CAN_NODE_GetLastErrTransferDir __STATIC_INLINE XMC_CAN_NODE_LAST_ERROR_INC_t XMC_CAN_NODE_GetLastErrTransferInc(XMC_CAN_NODE_t *const node) { - return (XMC_CAN_NODE_LAST_ERROR_INC_t)(((node->NECNT) & CAN_NODE_NECNT_LEINC_Msk)>> CAN_NODE_NECNT_LEINC_Pos); + return (XMC_CAN_NODE_LAST_ERROR_INC_t)(((node->NECNT) & CAN_NODE_NECNT_LEINC_Msk) >> CAN_NODE_NECNT_LEINC_Pos); } /** * * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. - * @param error_warning_level Error Warning level value. Range :0-255. + * @param error_warning_level Error Warning level value. Range :0-255. * * @return None * @@ -1059,8 +1095,8 @@ __STATIC_INLINE void XMC_CAN_NODE_SetTransmitErrorCounter(XMC_CAN_NODE_t *const __STATIC_INLINE void XMC_CAN_NODE_SetReceiveErrorCounter(XMC_CAN_NODE_t *const can_node, uint8_t can_rec) { - can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_REC_Msk)) | - (((uint32_t)can_rec << CAN_NODE_NECNT_REC_Pos) & (uint32_t)CAN_NODE_NECNT_REC_Msk); + can_node->NECNT = ((can_node->NECNT) & ~(uint32_t)(CAN_NODE_NECNT_REC_Msk)) | + (((uint32_t)can_rec << CAN_NODE_NECNT_REC_Pos) & (uint32_t)CAN_NODE_NECNT_REC_Msk); } @@ -1071,8 +1107,8 @@ __STATIC_INLINE void XMC_CAN_NODE_SetReceiveErrorCounter(XMC_CAN_NODE_t *const c * @return uint8_t Error Warning Level. Range :0 - 255 * * \parDescription:
        - * Returns error warning level. This determines the threshold value (warning level, default 96) to be reached in order - * to set the corresponding error warning bit EWRN. It reads NECNT register. + * Returns error warning level. This determines the threshold value (warning level, default 96) to be reached in order + * to set the corresponding error warning bit EWRN. It reads NECNT register. * * \parRelated APIs:
        * XMC_CAN_NODE_SetErrorWarningLevel()\n\n\n @@ -1082,7 +1118,7 @@ __STATIC_INLINE void XMC_CAN_NODE_SetReceiveErrorCounter(XMC_CAN_NODE_t *const c __STATIC_INLINE uint8_t XMC_CAN_NODE_GetErrorWarningLevel(XMC_CAN_NODE_t *const can_node) { - return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_EWRNLVL_Msk) >> CAN_NODE_NECNT_EWRNLVL_Pos); + return (uint8_t)((uint32_t)((can_node->NECNT) & CAN_NODE_NECNT_EWRNLVL_Msk) >> CAN_NODE_NECNT_EWRNLVL_Pos); } @@ -1093,9 +1129,9 @@ __STATIC_INLINE uint8_t XMC_CAN_NODE_GetErrorWarningLevel(XMC_CAN_NODE_t *const * @return uint8_t transmit error counter value. Range :0 - 255 * * \parDescription:
        - * Returns Transmit Error Counter value. If the Bitstream Processor detects an error while a transmit operation is - * running, the Transmit Error Counter is incremented by 8. An increment of 1 is used when the error condition was - * reported by an external CAN node via an Error Frame generation. It reads NECNT register. + * Returns Transmit Error Counter value. If the Bitstream Processor detects an error while a transmit operation is + * running, the Transmit Error Counter is incremented by 8. An increment of 1 is used when the error condition was + * reported by an external CAN node via an Error Frame generation. It reads NECNT register. * * \parRelated APIs:
        * XMC_CAN_NODE_SetTransmitErrorCounter() @@ -1115,10 +1151,10 @@ __STATIC_INLINE uint8_t XMC_CAN_NODE_GetTransmitErrorCounter(XMC_CAN_NODE_t *con * * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. * - * @return uint8_t receive error counter value. + * @return uint8_t receive error counter value. * * \parDescription:
        - * Returns Receive Error Counter value. It reads NECNT register. + * Returns Receive Error Counter value. It reads NECNT register. * * \parRelated APIs:
        * XMC_CAN_NODE_SetReceiveErrorCounter() @@ -1165,9 +1201,9 @@ __STATIC_INLINE uint32_t XMC_CAN_NODE_GetStatus(XMC_CAN_NODE_t *const can_node) * */ -__STATIC_INLINE void XMC_CAN_NODE_ClearStatus(XMC_CAN_NODE_t *const can_node,XMC_CAN_NODE_STATUS_t can_node_status) +__STATIC_INLINE void XMC_CAN_NODE_ClearStatus(XMC_CAN_NODE_t *const can_node, XMC_CAN_NODE_STATUS_t can_node_status) { - can_node->NSR &= ~(uint32_t)can_node_status; + can_node->NSR &= ~(uint32_t)can_node_status; } @@ -1199,7 +1235,7 @@ __STATIC_INLINE void XMC_CAN_NODE_EnableConfigurationChange(XMC_CAN_NODE_t *cons * @return None * * \parDescription:
        - * Forbid to change the configuration of the CAN node. It configures NCRx.CCE bit. + * Forbid to change the configuration of the CAN node. It configures NCRx.CCE bit. * * \parRelated API's:
        * XMC_CAN_NODE_EnableConfigurationChange() @@ -1379,7 +1415,7 @@ __STATIC_INLINE void XMC_CAN_NODE_DisableTransmit(XMC_CAN_NODE_t *const can_node /** * * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. - * @param can_node_init frame counter mode selection. Refer @ref XMC_CAN_NODE_FRAME_COUNTER_t for valid values. + * @param can_node_init frame counter mode selection. Refer @ref XMC_CAN_NODE_FRAME_COUNTER_t for valid values. * * @return None * @@ -1394,11 +1430,11 @@ __STATIC_INLINE void XMC_CAN_NODE_DisableTransmit(XMC_CAN_NODE_t *const can_node */ __STATIC_INLINE void XMC_CAN_NODE_FrameCounterConfigure(XMC_CAN_NODE_t *const can_node, - const XMC_CAN_NODE_FRAME_COUNTER_t *const can_node_init) + const XMC_CAN_NODE_FRAME_COUNTER_t *const can_node_init) { can_node->NFCR = (can_node->NFCR & ~(uint32_t)(CAN_NODE_NFCR_CFMOD_Msk | - CAN_NODE_NFCR_CFSEL_Msk)) | - can_node_init->nfcr; + CAN_NODE_NFCR_CFSEL_Msk)) | + can_node_init->nfcr; } @@ -1406,7 +1442,7 @@ __STATIC_INLINE void XMC_CAN_NODE_FrameCounterConfigure(XMC_CAN_NODE_t *const ca * * @param can_node Pointer Pointing to CAN_NODE Structure. Defines CAN_NODE registers, Range :CAN_NODE0-CAN_NODE2. * - * @return uint16_t current value of the CAN frame counter. Range :0-65535 + * @return uint16_t current value of the CAN frame counter. Range :0-65535 * * \parDescription:
        * Returns the frame counter value \a can_node of the CAN node. In Frame Count Mode (CFMOD = 00B), this API returns the frame @@ -1424,13 +1460,13 @@ __STATIC_INLINE uint16_t XMC_CAN_NODE_GetCANFrameCounter(XMC_CAN_NODE_t *const c return (uint16_t)(((uint32_t)(can_node->NFCR & CAN_NODE_NFCR_CFC_Msk) >> CAN_NODE_NFCR_CFC_Pos)); } - /*MO APIs*/ +/*MO APIs*/ /** * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * - * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. * * @return None * @@ -1449,7 +1485,7 @@ XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo); * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * - * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. * * \parDescription:
        * Configures transmit request for sending data frame. It configures MOCTR register. Data shall be updated @@ -1466,7 +1502,7 @@ XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo); /** * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * - * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. * * \parDescription:
        * Reads the Message Object data bytes, into message pointer passed as input parameter \a can_mo. @@ -1483,7 +1519,7 @@ XMC_CAN_STATUS_t XMC_CAN_MO_Receive(XMC_CAN_MO_t *can_mo); /** * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * - * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. + * @return XMC_CAN_STATUS_t CAN Node status. Refer @ref XMC_CAN_STATUS_t structure for details. * * \parDescription:
        * Reads the Message Object data bytes, into message pointer passed as input parameter \a can_mo. @@ -1495,10 +1531,10 @@ XMC_CAN_STATUS_t XMC_CAN_MO_Receive(XMC_CAN_MO_t *can_mo); */ XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo); /** - * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param can_mo_ptr_int Message Object event node pointer selection. Refer @ref XMC_CAN_MO_POINTER_EVENT_t structure - * for valid values. - * @param service_request interrupt output line of multiCAN module. + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_mo_ptr_int Message Object event node pointer selection. Refer @ref XMC_CAN_MO_POINTER_EVENT_t structure + * for valid values. + * @param service_request interrupt output line of multiCAN module. * * @return None * @@ -1511,17 +1547,17 @@ XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo); */ __STATIC_INLINE void XMC_CAN_MO_SetEventNodePointer(const XMC_CAN_MO_t *const can_mo, - const XMC_CAN_MO_POINTER_EVENT_t can_mo_ptr_int, - const uint32_t service_request) + const XMC_CAN_MO_POINTER_EVENT_t can_mo_ptr_int, + const uint32_t service_request) { can_mo->can_mo_ptr->MOIPR = ((can_mo->can_mo_ptr->MOIPR ) & ~(uint32_t)((uint32_t)CAN_MO_MOIPR_Msk << (uint32_t)can_mo_ptr_int)) | - (service_request << (uint32_t)can_mo_ptr_int); + (service_request << (uint32_t)can_mo_ptr_int); } /** * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * - * @return uint32_t Current Message Object status. + * @return uint32_t Current Message Object status. * * \parDescription:
        * Returns Message Object status, that indicates message object transfer status and message object list status @@ -1542,7 +1578,7 @@ __STATIC_INLINE uint32_t XMC_CAN_MO_GetStatus(const XMC_CAN_MO_t *const can_mo) * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * @param mask Message Object set status selection. Refer @ref XMC_CAN_MO_SET_STATUS_t for details. - * Multiple enums can be ORed. + * Multiple enums can be ORed. * @return None * * \parDescription:
        @@ -1562,7 +1598,7 @@ __STATIC_INLINE void XMC_CAN_MO_SetStatus(const XMC_CAN_MO_t *const can_mo, cons * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * @param mask Message Object set status selection. Refer @ref XMC_CAN_MO_RESET_STATUS_t for details. - * Multiple enums can be ORed. + * Multiple enums can be ORed. * @return None * * \parDescription:
        @@ -1573,7 +1609,7 @@ __STATIC_INLINE void XMC_CAN_MO_SetStatus(const XMC_CAN_MO_t *const can_mo, cons * */ -__STATIC_INLINE void XMC_CAN_MO_ResetStatus(const XMC_CAN_MO_t *const can_mo,const uint32_t mask) +__STATIC_INLINE void XMC_CAN_MO_ResetStatus(const XMC_CAN_MO_t *const can_mo, const uint32_t mask) { can_mo->can_mo_ptr->MOCTR = mask; } @@ -1582,7 +1618,7 @@ __STATIC_INLINE void XMC_CAN_MO_ResetStatus(const XMC_CAN_MO_t *const can_mo,con /** * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param event CAN node Message Object event selection. Refer @ref XMC_CAN_MO_EVENT_t for details. + * @param event CAN node Message Object event selection. Refer @ref XMC_CAN_MO_EVENT_t for details. * * @return None * @@ -1595,7 +1631,7 @@ __STATIC_INLINE void XMC_CAN_MO_ResetStatus(const XMC_CAN_MO_t *const can_mo,con */ __STATIC_INLINE void XMC_CAN_MO_EnableEvent(const XMC_CAN_MO_t *const can_mo, - const uint32_t event) + const uint32_t event) { can_mo->can_mo_ptr->MOFCR |= event; } @@ -1617,7 +1653,7 @@ __STATIC_INLINE void XMC_CAN_MO_EnableEvent(const XMC_CAN_MO_t *const can_mo, */ __STATIC_INLINE void XMC_CAN_MO_DisableEvent(const XMC_CAN_MO_t *const can_mo, - const uint32_t event) + const uint32_t event) { can_mo->can_mo_ptr->MOFCR &= ~event; } @@ -1665,7 +1701,7 @@ __STATIC_INLINE void XMC_CAN_MO_DisableSingleTransmitTrial(const XMC_CAN_MO_t *c /** * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param data_length_code transfer data length. Range:0-8 + * @param data_length_code transfer data length. Range:0-8 * * @return None * @@ -1677,7 +1713,7 @@ __STATIC_INLINE void XMC_CAN_MO_DisableSingleTransmitTrial(const XMC_CAN_MO_t *c * */ -__STATIC_INLINE void XMC_CAN_MO_DataLengthCode(const XMC_CAN_MO_t *const can_mo,const uint8_t data_length_code) +__STATIC_INLINE void XMC_CAN_MO_DataLengthCode(const XMC_CAN_MO_t *const can_mo, const uint8_t data_length_code) { can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | (((uint32_t)data_length_code << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk); @@ -1686,7 +1722,7 @@ __STATIC_INLINE void XMC_CAN_MO_DataLengthCode(const XMC_CAN_MO_t *const can_mo, /** * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param data_length_code transfer data length. Range:0-8 + * @param data_length_code transfer data length. Range:0-8 * * @return None * @@ -1698,7 +1734,7 @@ __STATIC_INLINE void XMC_CAN_MO_DataLengthCode(const XMC_CAN_MO_t *const can_mo, * */ -__STATIC_INLINE void XMC_CAN_MO_SetDataLengthCode(XMC_CAN_MO_t *const can_mo,const uint8_t data_length_code) +__STATIC_INLINE void XMC_CAN_MO_SetDataLengthCode(XMC_CAN_MO_t *const can_mo, const uint8_t data_length_code) { can_mo->can_data_length = data_length_code; can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) | @@ -1727,7 +1763,7 @@ __STATIC_INLINE uint8_t XMC_CAN_MO_GetDataLengthCode(const XMC_CAN_MO_t *const c /** * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param can_identifier Identifier. + * @param can_identifier Identifier. * * @return None * @@ -1776,7 +1812,7 @@ uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo); /** * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param can_id_mask CAN MO acceptance mask. + * @param can_id_mask CAN MO acceptance mask. * * @return None * @@ -1788,7 +1824,7 @@ uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo); * */ -void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask); +void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo, const uint32_t can_id_mask); /** * @@ -1807,7 +1843,7 @@ void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_ __STATIC_INLINE void XMC_CAN_MO_AcceptOnlyMatchingIDE(XMC_CAN_MO_t *const can_mo) { can_mo->can_ide_mask = 1U; - can_mo->can_mo_ptr->MOAMR |=(uint32_t)(CAN_MO_MOAMR_MIDE_Msk); + can_mo->can_mo_ptr->MOAMR |= (uint32_t)(CAN_MO_MOAMR_MIDE_Msk); } /** @@ -1868,7 +1904,7 @@ __STATIC_INLINE void XMC_CAN_MO_SetStandardID(XMC_CAN_MO_t *const can_mo) * After setting the identifier type user has to set the identifier value by using @ref XMC_CAN_MO_SetIdentifier() API. * */ - + __STATIC_INLINE void XMC_CAN_MO_SetExtendedID(XMC_CAN_MO_t *const can_mo) { can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS; @@ -1930,7 +1966,7 @@ __STATIC_INLINE void XMC_CAN_FIFO_DisableForeingRemoteRequest(const XMC_CAN_MO_t * XMC_CAN_FIFO_DisableRemoteMonitoring()\n\n\n * * \parNote:
        - * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. + * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. * */ __STATIC_INLINE void XMC_CAN_FIFO_EnableRemoteMonitoring(const XMC_CAN_MO_t *const can_mo) @@ -1953,7 +1989,7 @@ __STATIC_INLINE void XMC_CAN_FIFO_EnableRemoteMonitoring(const XMC_CAN_MO_t *con * XMC_CAN_FIFO_EnableRemoteMonitoring()\n\n\n * * \parNote:
        - * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. + * Remote monitoring(RMM) applies only to transmit objects and has no effect on receive objects. * */ @@ -1964,7 +2000,7 @@ __STATIC_INLINE void XMC_CAN_FIFO_DisableRemoteMonitoring(const XMC_CAN_MO_t *co /** - * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * @param select_pointer Selected Message Object number. Range:0-63 * * @return None @@ -1978,7 +2014,7 @@ __STATIC_INLINE void XMC_CAN_FIFO_DisableRemoteMonitoring(const XMC_CAN_MO_t *co * */ -__STATIC_INLINE void XMC_CAN_FIFO_SetSELMO(const XMC_CAN_MO_t *const can_mo,const uint8_t select_pointer) +__STATIC_INLINE void XMC_CAN_FIFO_SetSELMO(const XMC_CAN_MO_t *const can_mo, const uint8_t select_pointer) { can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_SEL_Msk)) | (((uint32_t)select_pointer << CAN_MO_MOFGPR_SEL_Pos) & (uint32_t)CAN_MO_MOFGPR_SEL_Msk); @@ -1989,7 +2025,7 @@ __STATIC_INLINE void XMC_CAN_FIFO_SetSELMO(const XMC_CAN_MO_t *const can_mo,cons * * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * - * @return uint8_t Current Message Object Number. Range:0-63 + * @return uint8_t Current Message Object Number. Range:0-63 * * \parDescription:
        * Returns the current FIFO Message Object,points to the actual target object within a FIFO/Gateway structure. @@ -2064,7 +2100,7 @@ __STATIC_INLINE void XMC_CAN_FIFO_DisableSingleDataTransfer(const XMC_CAN_MO_t * * */ -void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); +void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_FIFO_CONFIG_t can_fifo); /** @@ -2081,13 +2117,13 @@ void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XM * None */ -void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); +void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_FIFO_CONFIG_t can_fifo); /** * - * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. - * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_fifo CAN FIFO configuration data structure. Refer @ref XMC_CAN_FIFO_CONFIG_t data structure for details. * * @return None * @@ -2098,7 +2134,7 @@ void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XM * None * */ -void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo); +void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_FIFO_CONFIG_t can_fifo); /** @@ -2123,7 +2159,7 @@ __STATIC_INLINE void XMC_CAN_RXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *cons /** * - * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * @param can_gateway CAN gateway configuration data structure. Refer XMC_CAN_GATEWAY_CONFIG_t data structure for details. * * @return None @@ -2138,12 +2174,12 @@ __STATIC_INLINE void XMC_CAN_RXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *cons * */ -void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway); +void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_GATEWAY_CONFIG_t can_gateway); /** * - * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. + * @param can_mo Pointer to Message Object structure. Refer @ref XMC_CAN_MO_t data structure for details. * * @return None * @@ -2160,7 +2196,7 @@ void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC __STATIC_INLINE void XMC_CAN_GATEWAY_InitDesObject(const XMC_CAN_MO_t *const can_mo) { can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESRXEN_Msk | - CAN_MO_MOCTR_RESNEWDAT_Msk; + CAN_MO_MOCTR_RESNEWDAT_Msk; } /** @@ -2178,18 +2214,89 @@ __STATIC_INLINE void XMC_CAN_GATEWAY_InitDesObject(const XMC_CAN_MO_t *const can */ XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo); -#ifdef __cplusplus +/** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure + * @param list_idx List index + * + * @return List empty status. + * + * \parDescription:
        + * This function returns false in case at least one message object is allocated to list list_idx. + */ +__STATIC_INLINE bool XMC_CAN_IsListEmpty(XMC_CAN_t *const obj, uint8_t list_idx) +{ + return (bool)(obj->LIST[list_idx + 1] & CAN_LIST_EMPTY_Msk); } + +/** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure + * @param list_idx List index + * + * @return Object index of the first message object in the list list_idx. + * + * \parDescription:
        + * This function returns object index of the first message object in the list list_idx. + */ +__STATIC_INLINE uint32_t XMC_CAN_GetListBegin(XMC_CAN_t *const obj, uint8_t list_idx) +{ + return ((obj->LIST[list_idx + 1] & CAN_LIST_BEGIN_Msk) >> CAN_LIST_BEGIN_Pos); +} + +/** + * @param obj Pointer pointing to XMC_CAN Global Initialization structure + * @param list_idx List index + * + * @return Number of message objects allocated to list list_idx + * + * \parDescription:
        + * This function returns number of message objects allocated to list list_idx + */ +__STATIC_INLINE uint32_t XMC_CAN_GetListSize(XMC_CAN_t *const obj, uint8_t list_idx) +{ + return ((obj->LIST[list_idx + 1] & CAN_LIST_SIZE_Msk) >> CAN_LIST_SIZE_Pos) + 1; +} + +/** + * @param can_mo Pointer to Message Object structure. + * @param mo_idx Message object index. + * + * @return None. + * + * \parDescription:
        + * This function updates the hardware message object pointer to message object with index mo_idx + */ +__STATIC_INLINE void XMC_CAN_MO_GetMessageObject(XMC_CAN_MO_t *const can_mo, uint8_t mo_idx) +{ +#if defined(CAN_MO0) + CAN_MO_TypeDef *can_mo_ptr = &CAN_MO0[mo_idx]; +#elif defined(CAN_MO) + CAN_MO_TypeDef *can_mo_ptr = &CAN_MO->MO[mo_idx]; #endif + can_mo->can_mo_ptr = can_mo_ptr; +} /** - * @} - */ + * @param can_mo Pointer to Message Object structure. + * + * @return object index of next linked message object. + * + * \parDescription:
        + * This function returns the object index of next linked message object. + */ +__STATIC_INLINE uint32_t XMC_CAN_MO_GetNextMessageObjectIdx(XMC_CAN_MO_t *can_mo) +{ + return ((can_mo->can_mo_ptr->MOSTAT & CAN_MO_MOSTAT_PNEXT_Msk) >> CAN_MO_MOSTAT_PNEXT_Pos); +} + +#ifdef __cplusplus +} +#endif /** * @} */ + #endif /* defined(CAN) */ #endif /* XMC_CAN_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_can_map.h b/cores/xmc_lib/XMCLib/inc/xmc_can_map.h index 15240b26..967f8b5f 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_can_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_can_map.h @@ -1,47 +1,41 @@ /** * @file xmc_can_map.h - * @date 2015-10-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-10-20: - * - Removed "const" in the MOs for avoiding compiler warnings - * - * 2015-09-15: - * - Initial version + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * @endcond * */ @@ -89,6 +83,23 @@ #define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC +#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD +#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA +#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB +#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE +#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF +#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG +#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH +#endif + #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) #define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA #define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB @@ -289,7 +300,7 @@ #define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF #endif -#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144) +#if ((UC_DEVICE == XMC4800) || (UC_SERIES == XMC47)) && (UC_PACKAGE == LQFP144) #define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA #define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB #define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC @@ -310,7 +321,7 @@ #define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB #endif -#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100) +#if ((UC_DEVICE == XMC4800) || (UC_SERIES == XMC47)) && (UC_PACKAGE == LQFP100) #define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA #define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB #define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC @@ -327,7 +338,7 @@ #define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB #endif -#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LFBGA196) +#if ((UC_DEVICE == XMC4800) || (UC_SERIES == XMC47)) && (UC_PACKAGE == BGA196) #define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA #define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB #define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ccu4.h b/cores/xmc_lib/XMCLib/inc/xmc_ccu4.h index 63ebcf68..da6a91db 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_ccu4.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_ccu4.h @@ -1,82 +1,47 @@ /** * @file xmc_ccu4.h - * @date 2017-04-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
        - * - Documentation updates
        - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
        - * - * 2015-07-22: - * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
        - * - * 2015-08-17: - * - XMC_CCU4_SLICE_PRESCALER_t enum is added to set the prescaler divider.
        - * - XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum item names are updated according to the guidelines.
        - * - XMC_CCU4_EnableShadowTransfer() API is made as inline, to improve the speed.
        - * - * 2015-09-29: - * - In XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction - * settings. - * - * 2015-10-07: - * - XMC_CCU4_SLICE_GetEvent() is made as inline. - * - XMC_CCU4_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU4_SLICE_EnableMultipleEvents() and - * XMC_CCU4_SLICE_DisableMultipleEvents() APIs. - * - DOC updates for the newly added APIs. - * - * 2016-03-09: - * - Optimization of write only registers - * - * 2016-05-20: - * - Added XMC_CCU4_SLICE_StopClearTimer() - * - Changed implementation of XMC_CCU4_SLICE_StopTimer() and XMC_CCU4_SLICE_ClearTimer() to avoid RMW access - * - * 2017-04-27: - * - XMC_CCU4_SLICE_SetPrescaler() changed div_val parameter to type XMC_CCU4_SLICE_PRESCALER_t - * + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * @endcond */ #ifndef XMC_CCU4_H #define XMC_CCU4_H - + /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ @@ -84,27 +49,23 @@ #if defined(CCU40) #if UC_FAMILY == XMC1 - #include "xmc1_ccu4_map.h" +#include "xmc1_ccu4_map.h" #endif #if UC_FAMILY == XMC4 - #include "xmc4_ccu4_map.h" +#include "xmc4_ccu4_map.h" #endif -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - + /** * @addtogroup CCU4 * @brief Capture Compare Unit 4 (CCU4) low level driver for XMC family of microcontrollers
        * - * The CCU4 peripheral is a major component for systems that need general purpose timers for signal - * monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like + * The CCU4 peripheral is a major component for systems that need general purpose timers for signal + * monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like * switched mode power supplies or interruptible power supplies, can easily be implemented with the functions inside the * CCU4 peripheral.\n - * Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y (where y = [0..4]). Each + * Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y (where y = [0..4]). Each * timer slice can work in compare mode or in capture mode. * * APIs provided in this file cover the following functional blocks of CCU4:\n @@ -114,16 +75,16 @@ * 2. Module (APIs are not having any prefix e.g. XMC_CCU4_) * * \par Timer(Compare mode) configuration: - * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_COMPARE_CONFIG_t and the initialization + * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_COMPARE_CONFIG_t and the initialization * function XMC_CCU4_SLICE_CompareInit(). * * It can be used to: * -# Start and Stop the timer. (XMC_CCU4_SLICE_StartTimer(), XMC_CCU4_SLICE_StopTimer()) - * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU4_SLICE_SetTimerPeriodMatch(), - * XMC_CCU4_SLICE_SetTimerCompareMatch(), XMC_CCU4_SLICE_SetPrescaler(), XMC_CCU4_SLICE_SetDitherCompareValue(), + * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU4_SLICE_SetTimerPeriodMatch(), + * XMC_CCU4_SLICE_SetTimerCompareMatch(), XMC_CCU4_SLICE_SetPrescaler(), XMC_CCU4_SLICE_SetDitherCompareValue(), * XMC_CCU4_SLICE_SetPassiveLevel()) * -# Enable the slices to support multichannel mode. (XMC_CCU4_SLICE_EnableMultiChannelMode()) - * + * * \par Capture configuration: * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_CAPTURE_CONFIG_t and the initialization * function XMC_CCU4_SLICE_CaptureInit(). @@ -132,14 +93,14 @@ * -# Configure the capture functionality. (XMC_CCU4_SLICE_Capture0Config(), XMC_CCU4_SLICE_Capture1Config()) * -# Read the captured values along with the status, which indicate the value is latest or not. * (XMC_CCU4_SLICE_GetCaptureRegisterValue()) - * + * * \par Function/Event configuration: * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_EVENT_CONFIG_t.\n - * + * * It can be used to: * -# Enable and Disable the events. (XMC_CCU4_SLICE_EnableEvent(), XMC_CCU4_SLICE_DisableEvent()) * -# Configure to start and stop the timer on external events.(XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_StopConfig()) - * -# Modulation, external load and Gating of the timer output.(XMC_CCU4_SLICE_ModulationConfig(), + * -# Modulation, external load and Gating of the timer output.(XMC_CCU4_SLICE_ModulationConfig(), * XMC_CCU4_SLICE_LoadConfig(), XMC_CCU4_SLICE_GateConfig()) * -# Control the count direction of the timer based on the external event. (XMC_CCU4_SLICE_DirectionConfig()) * -# Count the external events.(XMC_CCU4_SLICE_CountConfig()) @@ -148,9 +109,11 @@ * * \par Interrupt configuration: * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU4_SLICE_SetInterruptNode()) + * + * Also, the CCU4 block can be configured from the ModusToolbox™ Device Configurator: \ref section_personality_ccu4 * @{ */ - + /********************************************************************************************************************* * MACROS ********************************************************************************************************************/ @@ -181,23 +144,23 @@ typedef CCU4_CC4_TypeDef XMC_CCU4_SLICE_t; /** * Return Value of an API - */ + */ typedef enum XMC_CCU4_STATUS { XMC_CCU4_STATUS_OK = 0U, /**< API fulfils request */ - XMC_CCU4_STATUS_ERROR , /**< API cannot fulfil the request */ - XMC_CCU4_STATUS_RUNNING , /**< The timer slice is currently running */ + XMC_CCU4_STATUS_ERROR, /**< API cannot fulfil the request */ + XMC_CCU4_STATUS_RUNNING, /**< The timer slice is currently running */ XMC_CCU4_STATUS_IDLE /**< The timer slice is currently idle */ } XMC_CCU4_STATUS_t; /** * CCU4 module clock - */ + */ typedef enum XMC_CCU4_CLOCK { XMC_CCU4_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */ - XMC_CCU4_CLOCK_EXTERNAL_A , /**< External clock-A */ - XMC_CCU4_CLOCK_EXTERNAL_B , /**< External clock-B */ + XMC_CCU4_CLOCK_EXTERNAL_A, /**< External clock-A */ + XMC_CCU4_CLOCK_EXTERNAL_B, /**< External clock-B */ XMC_CCU4_CLOCK_EXTERNAL_C /**< External clock-C */ } XMC_CCU4_CLOCK_t; @@ -206,13 +169,13 @@ typedef enum XMC_CCU4_CLOCK */ typedef enum XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER { - XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software only for slice 0*/ - XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software and hardware for slice 0 */ - XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software only for slice 1*/ - XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software + XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software and hardware for slice 1 */ XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software only for slice 2 */ @@ -226,7 +189,7 @@ typedef enum XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER /** * Operational modes of CCU4 slice - */ + */ typedef enum XMC_CCU4_SLICE_MODE { XMC_CCU4_SLICE_MODE_COMPARE = 0U, /**< slice(CC4y) operates in Compare Mode */ @@ -235,7 +198,7 @@ typedef enum XMC_CCU4_SLICE_MODE /** * Timer counting modes for the slice - */ + */ typedef enum XMC_CCU4_SLICE_TIMER_COUNT_MODE { XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */ @@ -244,7 +207,7 @@ typedef enum XMC_CCU4_SLICE_TIMER_COUNT_MODE /** * Timer repetition mode for the slice - */ + */ typedef enum XMC_CCU4_SLICE_TIMER_REPEAT_MODE { XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */ @@ -254,7 +217,7 @@ typedef enum XMC_CCU4_SLICE_TIMER_REPEAT_MODE /** * Timer counting direction for the CCU4 slice - */ + */ typedef enum XMC_CCU4_SLICE_TIMER_COUNT_DIR { XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */ @@ -263,7 +226,7 @@ typedef enum XMC_CCU4_SLICE_TIMER_COUNT_DIR /** * Capture mode register sets - */ + */ typedef enum XMC_CCU4_SLICE_CAP_REG_SET { XMC_CCU4_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */ @@ -272,7 +235,7 @@ typedef enum XMC_CCU4_SLICE_CAP_REG_SET /** * Prescaler mode - */ + */ typedef enum XMC_CCU4_SLICE_PRESCALER_MODE { XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */ @@ -281,7 +244,7 @@ typedef enum XMC_CCU4_SLICE_PRESCALER_MODE /** * Timer output passive level - */ + */ typedef enum XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL { XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */ @@ -294,108 +257,108 @@ typedef enum XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL typedef enum XMC_CCU4_SLICE_PRESCALER { XMC_CCU4_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu4 */ - XMC_CCU4_SLICE_PRESCALER_2 , /**< Slice Clock = fccu4/2 */ - XMC_CCU4_SLICE_PRESCALER_4 , /**< Slice Clock = fccu4/4 */ - XMC_CCU4_SLICE_PRESCALER_8 , /**< Slice Clock = fccu4/8 */ - XMC_CCU4_SLICE_PRESCALER_16 , /**< Slice Clock = fccu4/16 */ - XMC_CCU4_SLICE_PRESCALER_32 , /**< Slice Clock = fccu4/32 */ - XMC_CCU4_SLICE_PRESCALER_64 , /**< Slice Clock = fccu4/64 */ - XMC_CCU4_SLICE_PRESCALER_128 , /**< Slice Clock = fccu4/128 */ - XMC_CCU4_SLICE_PRESCALER_256 , /**< Slice Clock = fccu4/256 */ - XMC_CCU4_SLICE_PRESCALER_512 , /**< Slice Clock = fccu4/512 */ - XMC_CCU4_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu4/1024 */ - XMC_CCU4_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu4/2048 */ - XMC_CCU4_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu4/4096 */ - XMC_CCU4_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu4/8192 */ - XMC_CCU4_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu4/16384 */ + XMC_CCU4_SLICE_PRESCALER_2, /**< Slice Clock = fccu4/2 */ + XMC_CCU4_SLICE_PRESCALER_4, /**< Slice Clock = fccu4/4 */ + XMC_CCU4_SLICE_PRESCALER_8, /**< Slice Clock = fccu4/8 */ + XMC_CCU4_SLICE_PRESCALER_16, /**< Slice Clock = fccu4/16 */ + XMC_CCU4_SLICE_PRESCALER_32, /**< Slice Clock = fccu4/32 */ + XMC_CCU4_SLICE_PRESCALER_64, /**< Slice Clock = fccu4/64 */ + XMC_CCU4_SLICE_PRESCALER_128, /**< Slice Clock = fccu4/128 */ + XMC_CCU4_SLICE_PRESCALER_256, /**< Slice Clock = fccu4/256 */ + XMC_CCU4_SLICE_PRESCALER_512, /**< Slice Clock = fccu4/512 */ + XMC_CCU4_SLICE_PRESCALER_1024, /**< Slice Clock = fccu4/1024 */ + XMC_CCU4_SLICE_PRESCALER_2048, /**< Slice Clock = fccu4/2048 */ + XMC_CCU4_SLICE_PRESCALER_4096, /**< Slice Clock = fccu4/4096 */ + XMC_CCU4_SLICE_PRESCALER_8192, /**< Slice Clock = fccu4/8192 */ + XMC_CCU4_SLICE_PRESCALER_16384, /**< Slice Clock = fccu4/16384 */ XMC_CCU4_SLICE_PRESCALER_32768 /**< Slice Clock = fccu4/32768 */ } XMC_CCU4_SLICE_PRESCALER_t; /** * External Function list - */ + */ typedef enum XMC_CCU4_SLICE_FUNCTION { XMC_CCU4_SLICE_FUNCTION_START = 0U, /**< Start function */ - XMC_CCU4_SLICE_FUNCTION_STOP , /**< Stop function */ - XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event + XMC_CCU4_SLICE_FUNCTION_STOP, /**< Stop function */ + XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0, /**< Capture Event-0 function, CCycapt0 signal is used for event generation */ - XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event + XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1, /**< Capture Event-1 function, CCycapt1 signal is used for event generation */ - XMC_CCU4_SLICE_FUNCTION_GATING , /**< Gating function */ - XMC_CCU4_SLICE_FUNCTION_DIRECTION , /**< Direction function */ - XMC_CCU4_SLICE_FUNCTION_LOAD , /**< Load function */ - XMC_CCU4_SLICE_FUNCTION_COUNT , /**< Counting function */ - XMC_CCU4_SLICE_FUNCTION_OVERRIDE , /**< Override function */ - XMC_CCU4_SLICE_FUNCTION_MODULATION , /**< Modulation function */ + XMC_CCU4_SLICE_FUNCTION_GATING, /**< Gating function */ + XMC_CCU4_SLICE_FUNCTION_DIRECTION, /**< Direction function */ + XMC_CCU4_SLICE_FUNCTION_LOAD, /**< Load function */ + XMC_CCU4_SLICE_FUNCTION_COUNT, /**< Counting function */ + XMC_CCU4_SLICE_FUNCTION_OVERRIDE, /**< Override function */ + XMC_CCU4_SLICE_FUNCTION_MODULATION, /**< Modulation function */ XMC_CCU4_SLICE_FUNCTION_TRAP /**< Trap function */ } XMC_CCU4_SLICE_FUNCTION_t; /** * External Event list - */ + */ typedef enum XMC_CCU4_SLICE_EVENT { XMC_CCU4_SLICE_EVENT_NONE = 0U, /**< None */ - XMC_CCU4_SLICE_EVENT_0 , /**< Event-0 */ - XMC_CCU4_SLICE_EVENT_1 , /**< Event-1 */ + XMC_CCU4_SLICE_EVENT_0, /**< Event-0 */ + XMC_CCU4_SLICE_EVENT_1, /**< Event-1 */ XMC_CCU4_SLICE_EVENT_2 /**< Event-2 */ } XMC_CCU4_SLICE_EVENT_t; /** * External Event trigger criteria - Edge sensitivity - */ + */ typedef enum XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY { XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */ - XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates event trigger*/ - XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE, /**< Rising Edge of the input signal generates event trigger*/ + XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE, /**< Falling Edge of the input signal generates event trigger */ XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger*/ } XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t; /** * External Event trigger criteria - Level sensitivity - */ + */ typedef enum XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY { XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/ XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level*/ /* Below enum items can be utilised specific to the functionality */ - XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ - XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ + XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ } XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t; /** * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles. - */ + */ typedef enum XMC_CCU4_SLICE_EVENT_FILTER { XMC_CCU4_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filter */ - XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES , /**< 3 clock cycles */ - XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES , /**< 5 clock cycles */ + XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES, /**< 3 clock cycles */ + XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES, /**< 5 clock cycles */ XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES /**< 7 clock cycles */ } XMC_CCU4_SLICE_EVENT_FILTER_t; /** * External Event Input list. This list depicts the possible input connections to the CCU4 slice. * Interconnects are specific to each device. - */ + */ typedef uint8_t XMC_CCU4_SLICE_INPUT_t; /** * Actions that can be performed upon detection of an external Timer STOP event - */ + */ typedef enum XMC_CCU4_SLICE_END_MODE { XMC_CCU4_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */ - XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */ + XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR, /**< Without stopping timer, clears the TIMER register */ XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */ } XMC_CCU4_SLICE_END_MODE_t; /** * Actions that can be performed upon detection of an external Timer START event - */ + */ typedef enum XMC_CCU4_SLICE_START_MODE { XMC_CCU4_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */ @@ -404,7 +367,7 @@ typedef enum XMC_CCU4_SLICE_START_MODE /** * Modulation of timer output signals - */ + */ typedef enum XMC_CCU4_SLICE_MODULATION_MODE { XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */ @@ -413,7 +376,7 @@ typedef enum XMC_CCU4_SLICE_MODULATION_MODE /** * Trap exit mode - */ + */ typedef enum XMC_CCU4_SLICE_TRAP_EXIT_MODE { XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */ @@ -422,41 +385,41 @@ typedef enum XMC_CCU4_SLICE_TRAP_EXIT_MODE /** * Timer clear on capture - */ + */ typedef enum XMC_CCU4_SLICE_TIMER_CLEAR_MODE { XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */ - XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */ - XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH, /**< Clear only when timer value has been captured in C3V and C2V */ + XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW, /**< Clear only when timer value has been captured in C1V and C0V */ XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */ } XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t; /** * Multi Channel Shadow transfer request configuration options - */ + */ typedef enum XMC_CCU4_SLICE_MCMS_ACTION { XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to the actual registers upon MCS xfer request */ XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow - register values to the actual registers upon MCS xfer + register values to the actual registers upon MCS xfer request */ - XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither - Compare register values to the actual registers upon + XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither + Compare register values to the actual registers upon MCS xfer request */ } XMC_CCU4_SLICE_MCMS_ACTION_t; /** * Available Interrupt Event Ids - */ + */ typedef enum XMC_CCU4_SLICE_IRQ_ID { - XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */ - XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< Period match -> One match counting down */ - XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP = 2U , /**< Compare match counting up */ - XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN = 3U , /**< Compare match counting down */ - XMC_CCU4_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */ - XMC_CCU4_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH = 0U, /**< Period match counting up */ + XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH = 1U, /**< Period match -> One match counting down */ + XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP = 2U, /**< Compare match counting up */ + XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN = 3U, /**< Compare match counting down */ + XMC_CCU4_SLICE_IRQ_ID_EVENT0 = 8U, /**< Event-0 occurrence */ + XMC_CCU4_SLICE_IRQ_ID_EVENT1 = 9U, /**< Event-1 occurrence */ XMC_CCU4_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */ XMC_CCU4_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */ } XMC_CCU4_SLICE_IRQ_ID_t; @@ -477,12 +440,12 @@ typedef enum XMC_CCU4_SLICE_MULTI_IRQ_ID /** * Service Request Lines for CCU4. Event are mapped to these SR lines and these are used to generate the interrupt. - */ + */ typedef enum XMC_CCU4_SLICE_SR_ID { XMC_CCU4_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */ - XMC_CCU4_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */ - XMC_CCU4_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */ + XMC_CCU4_SLICE_SR_ID_1, /**< Service Request Line-1 selected */ + XMC_CCU4_SLICE_SR_ID_2, /**< Service Request Line-2 selected */ XMC_CCU4_SLICE_SR_ID_3 /**< Service Request Line-3 selected */ } XMC_CCU4_SLICE_SR_ID_t; @@ -491,28 +454,28 @@ typedef enum XMC_CCU4_SLICE_SR_ID */ typedef enum XMC_CCU4_SHADOW_TRANSFER { - XMC_CCU4_SHADOW_TRANSFER_SLICE_0 = CCU4_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU4_SHADOW_TRANSFER_SLICE_0 = CCU4_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-0 */ XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU4_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value to actual register for SLICE-0 */ XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU4_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to actual register for SLICE-0 */ - XMC_CCU4_SHADOW_TRANSFER_SLICE_1 = CCU4_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU4_SHADOW_TRANSFER_SLICE_1 = CCU4_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-1 */ XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU4_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value to actual registers for SLICE-1 */ XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU4_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to actual register for SLICE-1 */ - XMC_CCU4_SHADOW_TRANSFER_SLICE_2 = CCU4_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU4_SHADOW_TRANSFER_SLICE_2 = CCU4_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-2 */ XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU4_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value to actual register for SLICE-2 */ XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU4_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to actual register for SLICE-2 */ - XMC_CCU4_SHADOW_TRANSFER_SLICE_3 = CCU4_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU4_SHADOW_TRANSFER_SLICE_3 = CCU4_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-3 */ XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU4_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value @@ -521,7 +484,7 @@ typedef enum XMC_CCU4_SHADOW_TRANSFER actual register for SLICE-3 */ } XMC_CCU4_SHADOW_TRANSFER_t; -#if defined(CCU4V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */ +#if defined(CCU4V3) || defined(DOXYGEN_XMC1)/* Defined for XMC1400 devices only */ /** * Slice shadow transfer mode options. * @note Only available for XMC1400 series @@ -532,29 +495,29 @@ typedef enum XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE One match. */ XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */ XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */ -} XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t; - - +} XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t; + + /** * Immediate write into configuration register * @note Only available for XMC1400 series */ typedef enum XMC_CCU4_SLICE_WRITE_INTO { - XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU4_CC4_STC_IRPC_Msk, /**< Immediate or Coherent - Write into Period + XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU4_CC4_STC_IRPC_Msk, /**< Immediate or Coherent + Write into Period Configuration */ - XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION = CCU4_CC4_STC_IRCC_Msk, /**< Immediate or Coherent - Write into Compare + XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION = CCU4_CC4_STC_IRCC_Msk, /**< Immediate or Coherent + Write into Compare Configuration */ - XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU4_CC4_STC_IRLC_Msk, /**< Immediate or Coherent + XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU4_CC4_STC_IRLC_Msk, /**< Immediate or Coherent Write into Passive Level Configuration */ - XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRDC_Msk, /**< Immediate or Coherent + XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRDC_Msk, /**< Immediate or Coherent Write into Dither Value Configuration */ - XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRFC_Msk /**< Immediate or Coherent - Write into Floating Prescaler + XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRFC_Msk /**< Immediate or Coherent + Write into Floating Prescaler Value Configuration */ } XMC_CCU4_SLICE_WRITE_INTO_t; @@ -591,12 +554,33 @@ typedef enum XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO */ typedef enum XMC_CCU4_SLICE_MASK { - XMC_CCU4_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */ - XMC_CCU4_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */ - XMC_CCU4_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */ + XMC_CCU4_SLICE_MASK_SLICE_0 = 1U, /**< SLICE-0 */ + XMC_CCU4_SLICE_MASK_SLICE_1 = 2U, /**< SLICE-1 */ + XMC_CCU4_SLICE_MASK_SLICE_2 = 4U, /**< SLICE-2 */ XMC_CCU4_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */ } XMC_CCU4_SLICE_MASK_t; +/** + * Selects suspend mode + */ +typedef enum XMC_CCU4_SUSPEND_MODE +{ + XMC_CCU4_SUSPEND_MODE_IGNORE = 0 << CCU4_GCTRL_SUSCFG_Pos, /**< Suspend request ignored. The module never enters in suspend */ + XMC_CCU4_SUSPEND_MODE_STOPS_INMEDIATELLY = 1 << CCU4_GCTRL_SUSCFG_Pos, /**< Stops all the running slices immediately. Safe stop is not applied. */ + XMC_CCU4_SUSPEND_MODE_SAFE_STOP = 2 << CCU4_GCTRL_SUSCFG_Pos, /**< Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. */ + XMC_CCU4_SUSPEND_MODE_WAIT_ROLL_OVER = 3 << CCU4_GCTRL_SUSCFG_Pos /**< Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. */ +} XMC_CCU4_SUSPEND_MODE_t; + + +/** + * CCU4 slice status bit + */ +typedef enum XMC_CCU4_SLICE_STATUS_BIT +{ + XMC_CCU4_SLICE_STATUS_BIT_PASSIVE = false, /**< Passive */ + XMC_CCU4_SLICE_STATUS_BIT_ACTIVE = true /**< Active */ +} XMC_CCU4_SLICE_STATUS_BIT_t; + /********************************************************************************************************************* * DATA STRUCTURES @@ -606,7 +590,7 @@ typedef enum XMC_CCU4_SLICE_MASK * Configuration data structure of an External Event(Event-0/1/2). * Needed to configure the various aspects of an External Event. * This structure will not connect the external event with an external function. - */ + */ typedef struct XMC_CCU4_SLICE_EVENT_CONFIG { XMC_CCU4_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event */ @@ -619,16 +603,16 @@ typedef struct XMC_CCU4_SLICE_EVENT_CONFIG /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to compare mode operation. * This excludes event and function configuration. - */ + */ typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG { union @@ -652,7 +636,7 @@ typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG }; uint32_t tc; }; - uint32_t prescaler_initval : 4; /**< Initial prescaler divider value + uint32_t prescaler_initval : 4; /**< Initial prescaler divider value Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t */ uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */ uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering */ @@ -664,7 +648,7 @@ typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG /** * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to capture mode operation. * This excludes event and function configuration. - */ + */ typedef struct XMC_CCU4_SLICE_CAPTURE_CONFIG { union @@ -690,9 +674,9 @@ typedef struct XMC_CCU4_SLICE_CAPTURE_CONFIG } XMC_CCU4_SLICE_CAPTURE_CONFIG_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * API Prototypes @@ -705,10 +689,10 @@ extern "C" { __STATIC_INLINE bool XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t *const module) { bool tmp = false; - + tmp = (module == CCU40); - -#if defined(CCU41) + +#if defined(CCU41) tmp = tmp || (module == CCU41); #endif @@ -719,63 +703,63 @@ __STATIC_INLINE bool XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t *const modul #if defined(CCU43) tmp = tmp || (module == CCU43); #endif - - return tmp; -} + + return tmp; +} __STATIC_INLINE bool XMC_CCU4_IsValidSlice(const XMC_CCU4_SLICE_t *const slice) { bool tmp = false; - + tmp = (slice == CCU40_CC40); -#if defined(CCU40_CC41) +#if defined(CCU40_CC41) tmp = tmp || (slice == CCU40_CC41); #endif -#if defined(CCU40_CC42) +#if defined(CCU40_CC42) tmp = tmp || (slice == CCU40_CC42); #endif -#if defined(CCU40_CC43) +#if defined(CCU40_CC43) tmp = tmp || (slice == CCU40_CC43); #endif -#if defined(CCU41) +#if defined(CCU41) tmp = tmp || (slice == CCU41_CC40); -#if defined(CCU41_CC41) +#if defined(CCU41_CC41) tmp = tmp || (slice == CCU41_CC41); #endif -#if defined(CCU41_CC42) +#if defined(CCU41_CC42) tmp = tmp || (slice == CCU41_CC42); #endif -#if defined(CCU41_CC43) +#if defined(CCU41_CC43) tmp = tmp || (slice == CCU41_CC43); #endif -#endif -#if defined(CCU42) +#endif +#if defined(CCU42) tmp = tmp || (slice == CCU42_CC40); -#if defined(CCU42_CC41) +#if defined(CCU42_CC41) tmp = tmp || (slice == CCU42_CC41); #endif -#if defined(CCU42_CC42) +#if defined(CCU42_CC42) tmp = tmp || (slice == CCU42_CC42); #endif -#if defined(CCU42_CC43) +#if defined(CCU42_CC43) tmp = tmp || (slice == CCU42_CC43); #endif #endif -#if defined(CCU43) +#if defined(CCU43) tmp = tmp || (slice == CCU43_CC40); -#if defined(CCU43_CC41) +#if defined(CCU43_CC41) tmp = tmp || (slice == CCU43_CC41); #endif -#if defined(CCU43_CC42) +#if defined(CCU43_CC42) tmp = tmp || (slice == CCU43_CC42); #endif -#if defined(CCU43_CC43) +#if defined(CCU43_CC43) tmp = tmp || (slice == CCU43_CC43); #endif -#endif - - return tmp; -} +#endif + + return tmp; +} /** * @param module Constant pointer to CCU4 module @@ -860,7 +844,7 @@ void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module); __STATIC_INLINE void XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t *const module) { XMC_ASSERT("XMC_CCU4_StartPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); - module->GIDLC |= (uint32_t) CCU4_GIDLC_SPRB_Msk; + module->GIDLC = (uint32_t) CCU4_GIDLC_SPRB_Msk; } /** @@ -880,7 +864,7 @@ __STATIC_INLINE void XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t *const module) __STATIC_INLINE void XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t *const module) { XMC_ASSERT("XMC_CCU4_StopPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); - module->GIDLS |= (uint32_t) CCU4_GIDLS_CPRB_Msk; + module->GIDLS = (uint32_t) CCU4_GIDLS_CPRB_Msk; } /** @@ -899,7 +883,7 @@ __STATIC_INLINE void XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t *const module) __STATIC_INLINE bool XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t *const module) { XMC_ASSERT("XMC_CCU4_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); - return((bool)((module->GSTAT & (uint32_t) CCU4_GSTAT_PRB_Msk) == (uint32_t)CCU4_GSTAT_PRB_Msk)); + return ((bool)((module->GSTAT & (uint32_t) CCU4_GSTAT_PRB_Msk) == (uint32_t)CCU4_GSTAT_PRB_Msk)); } /** @@ -911,9 +895,9 @@ __STATIC_INLINE bool XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t *const module * None
        * * \parDescription:
        - * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, * GIDLC.CS3I bits.\n\n - * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out + * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out * of the idle state simultaneously. * * \parRelated APIs:
        @@ -923,8 +907,8 @@ __STATIC_INLINE void XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t *const modu { XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Wrong clock mask", (clock_mask < 16U)); - - module->GIDLC |= (uint32_t) clock_mask; + + module->GIDLC = (uint32_t) clock_mask; } /** @@ -935,7 +919,7 @@ __STATIC_INLINE void XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t *const modu * None
        * * \parDescription:
        - * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, * GIDLC.CS3I bits according to the selected \a slice_number.\n\n * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the * slice whose clock needs to be enabled. @@ -948,7 +932,7 @@ __STATIC_INLINE void XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t *const module, const XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Slice Number", (slice_number < 4U)); - module->GIDLC |= ((uint32_t) 1) << slice_number; + module->GIDLC = ((uint32_t) 1) << slice_number; } /** @@ -957,9 +941,9 @@ __STATIC_INLINE void XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t *const module, const * Range: [0x0 to 0x3] * @return
        * None
        - * + * * \parDescription:
        - * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, + * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n * It is possible to disable clock at slice level using the module pointer. * \b slice_number is used to disable the clock to a given slice of the module. @@ -973,7 +957,25 @@ __STATIC_INLINE void XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t *const module, cons XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Slice Number", (slice_number < 4U)); - module->GIDLS |= ((uint32_t) 1) << slice_number; + module->GIDLS = ((uint32_t) 1) << slice_number; +} + +/** + * @param module Constant pointer to CCU8 module + * @param mode Selects suspend mode + * @return
        + * None
        + * + * \parDescription:
        + * Configures the entering in suspend mode for all the CCU8 slices. + * + * \parRelated APIs:
        + * None. + */ +__STATIC_INLINE void XMC_CCU4_SetSuspendMode(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SUSPEND_MODE_t mode) +{ + XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module)); + module->GCTRL = (module->GCTRL & (uint32_t)~CCU4_GCTRL_SUSCFG_Msk) | mode; } /** @@ -983,8 +985,8 @@ __STATIC_INLINE void XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t *const module, cons * None
        * * \parDescription:
        - * Initialization of a CC4 slice to compare mode, by configuring CC4yTC, CC4yCMC, CC4yPSC, CC4yDITH, CC4yPSL, - * CC4yFPCS, CC4yCHC registers.\n\n + * Initialization of a CC4 slice to compare mode, by configuring CC4yTC, CC4yCMC, CC4yPSC, CC4yDITH, CC4yPSL, + * CC4yFPCS, CC4yCHC registers.\n\n * CC4 slice is configured with Timer configurations in this routine. * After initialization user has to explicitly enable the shadow transfer for the required values by calling * XMC_CCU4_EnableShadowTransfer() with appropriate mask. @@ -1078,9 +1080,9 @@ void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLI * Pass \b true if the modulation needs to be synchronized with PWM signal. * @return
        * None
        - * + * * \parDescription:
        - * Configures the Output Modulation Function of the slice, by configuring CCeyCMC.MOS, CC4yTC.EMT and + * Configures the Output Modulation Function of the slice, by configuring CCeyCMC.MOS, CC4yTC.EMT and * CC4yTC.EMS bits.\n\n * Modulation function is mapped with one of the 3 events. The output signal of the CCU can * be modulated according to a external input. Additionally, the behaviour of the slice upon activation @@ -1099,7 +1101,7 @@ void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, * @param event Map an External event to the External Count Function * @return
        * None
        - * + * * \parDescription:
        * Configures the Count Function of the slice, by configuring CC4yCMC.CNTS bit.\n\n * Count function is mapped with one of the 3 events. CCU4 slice can take an external @@ -1116,7 +1118,7 @@ void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SL * @param event Map an External event to the External Gating Function * @return
        * None
        - * + * * \parDescription:
        * Configures the Gating Function of the slice, by configuring CC4yCMC.GATES bit.\n\n * Gating function is mapped with one of the 3 events. A CCU4 slice can use an input signal that would @@ -1132,7 +1134,7 @@ void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLI * @param event Map an External event to the Capture-0 Function * @return
        * None
        - * + * * \parDescription:
        * Configures the Capture-0 Function of the slice, by configuring CC4yCMC.CAP0S bit.\n\n * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-0 mode @@ -1148,7 +1150,7 @@ void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4 * @param event Map an External event to the Capture-1 Function * @return
        * None
        - * + * * \parDescription:
        * Configures the Capture-1 Function of the slice, by configuring CC4yCMC.CAP1S bit.\n\n * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-1 @@ -1170,15 +1172,15 @@ void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4 * Individual capture registers can still be accessed in this mode. * * \parRelated APIs:
        - * XMC_CCU4_GetCapturedValueFromFifo(). + * \if XMC4 XMC_CCU4_GetCapturedValueFromFifo()
        \endif XMC_CCU4_SLICE_GetCapturedValueFromFifo(). */ __STATIC_INLINE bool XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_IsExtendedCapReadEnabled:Invalid Module Pointer", XMC_CCU4_IsValidSlice(slice)); - return((bool)((slice->TC & (uint32_t) CCU4_CC4_TC_ECM_Msk) == (uint32_t)CCU4_CC4_TC_ECM_Msk)); + return ((bool)((slice->TC & (uint32_t) CCU4_CC4_TC_ECM_Msk) == (uint32_t)CCU4_CC4_TC_ECM_Msk)); } -#if defined(CCU4V1) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +#if defined(CCU4V1) || defined(DOXYGEN_XMC4) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */ /** * @param module Constant pointer to CCU4 module * @param slice_number to check whether read value belongs to required slice or not @@ -1189,17 +1191,19 @@ __STATIC_INLINE bool XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLIC * * \parDescription:
        * Read captured value from FIFO(ECRD register).\n\n - * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured - * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the - * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be * derived/inferred from the captured values. * * \parRelated APIs:
        * XMC_CCU4_SLICE_IsExtendedCapReadEnabled(). - * @note Only available for XMC4500, XMC4400, XMC4200 and XMC4100 series + * @note Only available for XMC4500, XMC4400, XMC4200 and XMC4100 series. For other devices use XMC_CCU4_SLICE_GetCapturedValueFromFifo() API. */ int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number); -#else +#endif + +#if defined(CCU4V2) || defined(CCU4V3) || defined(DOXYGEN) /* Defined for XMC4800, XMC4700, XMC4300, XMC1400, XMC1300, XMC1200, XMC1100 devices only */ /** * @param slice Constant pointer to CC4 Slice * @param set The capture register set from which the captured value is to be retrieved @@ -1209,17 +1213,17 @@ int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, * * \parDescription:
        * Read captured value from FIFO(CC4yECRD0 and CC4yECRD1).\n\n - * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured - * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the - * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be * derived/inferred from the captured values. * * \parRelated APIs:
        * XMC_CCU4_SLICE_IsExtendedCapReadEnabled(). - * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU4_GetCapturedValueFromFifo() API + * \if XMC4 @note Only available for XMC4800, XMC4700, XMC4300 series. For other devices use XMC_CCU4_GetCapturedValueFromFifo() API. \endif */ uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_CAP_REG_SET_t set); + const XMC_CCU4_SLICE_CAP_REG_SET_t set); #endif /** @@ -1227,10 +1231,10 @@ uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const s * @param event Map an External event to the External Count Direction Function * @return
        * None
        - * + * * \parDescription:
        * Configures the Count Direction of the slice, by configuring CC4yCMC.UDS bit.\n\n - * Count direction function is mapped with one of the 3 events. A slice can be configured to change the + * Count direction function is mapped with one of the 3 events. A slice can be configured to change the * CC4yTIMER count direction depending on an external signal. * * \parRelated APIs:
        @@ -1246,7 +1250,7 @@ void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU * \parDescription:
        * Configures the status bit override Function of the slice, by configuring CC4yCMC.OFS bit.\n\n * Status bit override function is mapped with one of the 3 events. A slice can be configured to change the - * output of the timer's CC4yST signal depending on an external signal. + * output of the timer's CC4yST signal depending on an external signal. * * \parRelated APIs:
        * XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(). @@ -1293,8 +1297,8 @@ void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, * XMC_CCU4_SLICE_StatusBitOverrideConfig(). */ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, - const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config); + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config); /** * @param slice Constant pointer to CC4 Slice @@ -1326,7 +1330,7 @@ void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, * @return
        * None
        * - * + * * \parDescription:
        * Selects an input for an external event, by configuring CC4yINS register.\n\n * It is possible to select one of the possible 16 input signals for a given Event. @@ -1416,7 +1420,7 @@ __STATIC_INLINE bool XMC_CCU4_SLICE_IsTimerRunning(const XMC_CCU4_SLICE_t *const __STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_DIR_t XMC_CCU4_SLICE_GetCountingDir(const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((XMC_CCU4_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU4_CC4_TCST_CDIR_Msk) >> CCU4_CC4_TCST_CDIR_Pos)); + return ((XMC_CCU4_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU4_CC4_TCST_CDIR_Msk) >> CCU4_CC4_TCST_CDIR_Pos)); } /** @@ -1499,7 +1503,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t *const slice * returns XMC_CCU4_SLICE_MODE_CAPTURE if the slice is operating in capture mode * * \parDescription:
        - * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading + * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading * CC4yTC.CMOD bit.\n\n * Ensure that before invoking this API the CCU4 slice should be configured otherwise the output of this API is * invalid. @@ -1510,7 +1514,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t *const slice __STATIC_INLINE XMC_CCU4_SLICE_MODE_t XMC_CCU4_SLICE_GetSliceMode(const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((XMC_CCU4_SLICE_MODE_t)(((slice->TC) & CCU4_CC4_TC_CMOD_Msk) >> CCU4_CC4_TC_CMOD_Pos)); + return ((XMC_CCU4_SLICE_MODE_t)(((slice->TC) & CCU4_CC4_TC_CMOD_Msk) >> CCU4_CC4_TC_CMOD_Pos)); } /** * @param slice Constant pointer to CC4 Slice @@ -1545,10 +1549,10 @@ void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_ * XMC_CCU4_SLICE_SetTimerRepeatMode(). */ __STATIC_INLINE XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t XMC_CCU4_SLICE_GetTimerRepeatMode( - const XMC_CCU4_SLICE_t *const slice) + const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TSSM_Msk) >> CCU4_CC4_TC_TSSM_Pos)); + return ((XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TSSM_Msk) >> CCU4_CC4_TC_TSSM_Pos)); } /** * @param slice Constant pointer to CC4 Slice @@ -1561,7 +1565,7 @@ __STATIC_INLINE XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t XMC_CCU4_SLICE_GetTimerRepeat * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0. - * During this upward and downward counting, the timer status output stays asserted as long as the timer value is + * During this upward and downward counting, the timer status output stays asserted as long as the timer value is * greater than the compare value. * * \parRelated APIs:
        @@ -1582,10 +1586,10 @@ void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XM * XMC_CCU4_SLICE_SetTimerCountingMode(). */ __STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_MODE_t XMC_CCU4_SLICE_GetTimerCountingMode( - const XMC_CCU4_SLICE_t *const slice) + const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((XMC_CCU4_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TCM_Msk) >> CCU4_CC4_TC_TCM_Pos)); + return ((XMC_CCU4_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TCM_Msk) >> CCU4_CC4_TC_TCM_Pos)); } /** * @param slice Constant pointer to CC4 Slice @@ -1596,7 +1600,7 @@ __STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_MODE_t XMC_CCU4_SLICE_GetTimerCountin * * \parDescription:
        * Programs the timer period, by writing CC4yPRS register.\n\n - * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow + * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow * register. Explicitly enable the shadow transfer for the the period value by calling * XMC_CCU4_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running, * a period match transfers the value from the shadow register to the actual period register. @@ -1632,7 +1636,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetTimerPeriodMatch(XMC_CCU4_SLICE_t *const __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerPeriodMatch(const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((uint16_t)slice->PR); + return ((uint16_t)slice->PR); } /** @@ -1681,7 +1685,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetTimerCompareMatch(XMC_CCU4_SLICE_t *const __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((uint16_t)slice->CR); + return ((uint16_t)slice->CR); } /** @@ -1693,7 +1697,7 @@ __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLIC * None
        * * \parDescription:
        - * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring + * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring * the GCSS register.\n\n * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the * shadow transfer trigger after the API is called. @@ -1709,7 +1713,7 @@ __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLIC __STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const module, const uint32_t shadow_transfer_msk) { XMC_ASSERT("XMC_CCU4_EnableShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module)); - module->GCSS = (uint32_t)shadow_transfer_msk; + module->GCSS = (uint32_t)shadow_transfer_msk; } /** @@ -1727,7 +1731,7 @@ __STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const modu __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU4_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - return((uint16_t)slice->TIMER); + return ((uint16_t)slice->TIMER); } /** * @param slice Constant pointer to CC4 Slice @@ -1738,7 +1742,7 @@ __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t *co * * \parDescription:
        * Loads a new timer value, by setting CC4yTIMER register.\n\n - * + * * \parNote:
        * Request to load is ignored if the timer is running. * @@ -1763,8 +1767,8 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetTimerValue(XMC_CCU4_SLICE_t *const slice, * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering * can help reduce long term errors. Dithering can be applied to period and duty individually, * this can be selected using the parameter \b period_dither and \b duty_dither. - * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then - * the period/compare values would be dithered according to the dither mode selected. This API would invoke + * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then + * the period/compare values would be dithered according to the dither mode selected. This API would invoke * XMC_CCU4_SLICE_SetDitherCompareValue(). * * \parNote:
        @@ -1852,7 +1856,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_DisableFloatingPrescaler(XMC_CCU4_SLICE_t *c * the spread value, there is no dithering. After setting the value XMC_CCU4_EnableShadowTransfer() has to be * called with appropriate mask. * - * \parRelated APIs:
        + * \parRelated APIs:
        * XMC_CCU4_SLICE_EnableDithering(). */ __STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *const slice, const uint8_t comp_val) @@ -1860,6 +1864,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *cons XMC_ASSERT("XMC_CCU4_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->DITS = comp_val; } + /** * @param slice Constant pointer to CC4 Slice * @param div_val Prescaler divider value. Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t @@ -1877,6 +1882,25 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *cons */ void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_PRESCALER_t div_val); +/** + * @param slice Constant pointer to CC4 Slice + * @return
        + * XMC_CCU4_SLICE_PRESCALER_t Prescaler divider value.
        + * + * \parDescription:
        + * Returns current prescaler value.\n\n + * Used to detrmine the clock frequency of the CCU4 slice XMC_SCU_CLOCK_GetCcuClockFrequency() / XMC_CCU4_SLICE_GetPrescaler() + * + * \parRelated APIs:
        + * XMC_CCU4_SLICE_SetPrescaler(). + */ +__STATIC_INLINE XMC_CCU4_SLICE_PRESCALER_t XMC_CCU4_SLICE_GetPrescaler(XMC_CCU4_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); + + return (XMC_CCU4_SLICE_PRESCALER_t)slice->PSC; +} + /** * @param slice Constant pointer to CC4 Slice * @param cmp_val Prescaler divider compare value @@ -1888,14 +1912,14 @@ void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_S * Programs the slice specific prescaler divider compare value, by configuring CC4yFPCS register.\n\n * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial * value and increments to the compare value steadily upon every period match. Once prescaler divider - * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting + * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting * the value, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask. * * \parRelated APIs:
        * XMC_CCU4_SLICE_SetPrescaler(). */ __STATIC_INLINE void XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SLICE_t *const slice, - const uint8_t cmp_val) + const uint8_t cmp_val) { XMC_ASSERT("XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); /* write to the shadow register */ @@ -1909,7 +1933,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SL * \parDescription:
        * Enables the multichannel mode, by setting CC4yTC.MCME bit.
        \n * The output state of the Timer slices can be controlled in parallel by a single input signal. - * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can + * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to the * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus through * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated. @@ -1950,7 +1974,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_DisableMultiChannelMode(XMC_CCU4_SLICE_t *co * None
        * * \parDescription:
        - * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring + * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n * The shadow transfer would take place either if it was requested by software or by the CCU4x.MCSS input. * @@ -1969,9 +1993,9 @@ void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, * * \parDescription:
        * Retrieves timer value which has been captured in the Capture registers, by reading CC4yCV[\b reg_num] register.\n\n - * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped + * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing - * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help + * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help * to find out if there is a new captured value present. * * \parRelated APIs:
        @@ -1999,8 +2023,8 @@ uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const sl * XMC_CCU4_SLICE_GetCaptureRegisterValue(). */ XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_CAP_REG_SET_t set, - uint32_t *val_ptr); + const XMC_CCU4_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr); /** * @param slice Constant pointer to CC4 Slice @@ -2018,7 +2042,7 @@ XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_ * XMC_CCU4_SLICE_DisableMultipleEvents(). */ __STATIC_INLINE void XMC_CCU4_SLICE_EnableEvent(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_IRQ_ID_t event) + const XMC_CCU4_SLICE_IRQ_ID_t event) { XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); @@ -2063,7 +2087,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_EnableMultipleEvents(XMC_CCU4_SLICE_t *const * XMC_CCU4_SLICE_DisableMultipleEvents(). */ __STATIC_INLINE void XMC_CCU4_SLICE_DisableEvent(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_IRQ_ID_t event) + const XMC_CCU4_SLICE_IRQ_ID_t event) { XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); @@ -2110,7 +2134,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_SetEvent(XMC_CCU4_SLICE_t *const slice, cons { XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); - slice->SWS |= ((uint32_t) 1) << ((uint32_t) event); + slice->SWS = ((uint32_t) 1) << ((uint32_t) event); } /** @@ -2129,7 +2153,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_ClearEvent(XMC_CCU4_SLICE_t *const slice, co { XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); - slice->SWR |= ((uint32_t) 1) << ((uint32_t) event); + slice->SWR = ((uint32_t) 1) << ((uint32_t) event); } /** @@ -2152,7 +2176,7 @@ __STATIC_INLINE bool XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t *const slice XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); - return(((uint32_t)(slice->INTS & ((uint32_t)1 << (uint32_t)event))) != 0U); + return (((uint32_t)(slice->INTS & ((uint32_t)1 << (uint32_t)event))) != 0U); } /** * @param slice Constant pointer to CC4 Slice @@ -2172,7 +2196,7 @@ __STATIC_INLINE bool XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t *const slice void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event, const XMC_CCU4_SLICE_SR_ID_t sr); - + /** * @param slice Constant pointer to CC4 Slice * @param level Slice output passive level @@ -2190,7 +2214,7 @@ void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level); -#if defined(CCU4V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */ +#if defined(CCU4V3) || defined(DOXYGEN_XMC1) /* Defined for XMC1400 devices only */ /** * @param slice Constant pointer to CC4 Slice * @@ -2201,14 +2225,14 @@ void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, * Cascades the shadow transfer operation throughout the CCU4 timer slices, by setting CSE bit in STC register.\n\n * * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture, - * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of - * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC40 slice is a + * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of + * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC40 slice is a * master to start the operation. - * + * * \parNote:
        * XMC_CCU4_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be * cascaded. - * + * * \parRelated APIs:
        * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_DisableCascadedShadowTransfer()
        . * @note Only available for XMC1400 series @@ -2229,7 +2253,7 @@ __STATIC_INLINE void XMC_CCU4_SLICE_EnableCascadedShadowTransfer(XMC_CCU4_SLICE_ * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n * * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. - * + * * \parRelated APIs:
        * XMC_CCU4_SLICE_EnableCascadedShadowTransfer()
        . * @note Only available for XMC1400 series @@ -2249,141 +2273,155 @@ __STATIC_INLINE void XMC_CCU4_SLICE_DisableCascadedShadowTransfer(XMC_CCU4_SLICE * * \parDescription:
        * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n - * + * * After requesting for shadow transfer mode using XMC_CCU4_EnableShadowTransfer(), actual transfer occurs based on the - * selection done using this API (i.e. on period and One match, on Period match only, on One match only). + * selection done using this API (i.e. on period and One match, on Period match only, on One match only). * * \parNote:
        * This is effective when the timer is configured in centre aligned mode. - * + * * \parRelated APIs:
        * XMC_CCU4_EnableShadowTransfer()
        * @note Only available for XMC1400 series */ __STATIC_INLINE void XMC_CCU4_SLICE_SetShadowTransferMode(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) + const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) { XMC_ASSERT("XMC_CCU4_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU4_CC4_STC_STM_Msk << (uint32_t)CCU4_CC4_STC_STM_Pos)) | + slice->STC = ((slice->STC) & (uint32_t)~CCU4_CC4_STC_STM_Msk) | ((shadow_transfer_mode << CCU4_CC4_STC_STM_Pos) & (uint32_t)CCU4_CC4_STC_STM_Msk); } - /** - * @param slice Constant pointer to CC4 Slice - * @param coherent_write specifies for what fields this mode has to be applied - * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by - * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n - * - * When coherent shadow is enabled, after calling XMC_CCU4_EnableShadowTransfer(), the value which are written in the - * respective shadow registers get updated according the configuration done using XMC_CCU4_SLICE_SetShadowTransferMode() - * API. \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_SetShadowTransferMode()
        - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC4 Slice +* @param coherent_write specifies for what fields this mode has to be applied +* Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by +* clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n +* +* When coherent shadow is enabled, after calling XMC_CCU4_EnableShadowTransfer(), the value which are written in the +* respective shadow registers get updated according the configuration done using XMC_CCU4_SLICE_SetShadowTransferMode() +* API. \parNote:
        +* +* \parRelated APIs:
        +* XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_SetShadowTransferMode()
        +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU4_SLICE_t *const slice, - const uint32_t coherent_write) + const uint32_t coherent_write) { XMC_ASSERT("XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->STC &= ~(uint32_t)coherent_write; } - /** - * @param slice Constant pointer to CC4 Slice - * @param immediate_write specifies for what fields this mode has to be applied - * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting - * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n - * - * When immediate shadow is enabled, by calling XMC_CCU4_EnableShadowTransfer() the value which are written in the - * shadow registers get updated to the actual registers immediately. \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU4_EnableShadowTransfer()
        - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC4 Slice +* @param immediate_write specifies for what fields this mode has to be applied +* Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting +* IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n +* +* When immediate shadow is enabled, by calling XMC_CCU4_EnableShadowTransfer() the value which are written in the +* shadow registers get updated to the actual registers immediately. \parNote:
        +* +* \parRelated APIs:
        +* XMC_CCU4_EnableShadowTransfer()
        +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU4_SLICE_t *const slice, - const uint32_t immediate_write) + const uint32_t immediate_write) { XMC_ASSERT("XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->STC |= immediate_write; } - /** - * @param slice Constant pointer to CC4 Slice - * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated - * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a - * bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting - * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n - * - * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. - * \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(). - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC4 Slice +* @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated +* Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a +* bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting +* ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n +* +* By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. +* \parNote:
        +* Automatic shadow transfer feature does not work when system PCLK is faster than MCLK. +* +* \parRelated APIs:
        +* XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(). +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice, - const uint32_t automatic_shadow_transfer) + const uint32_t automatic_shadow_transfer) { XMC_ASSERT("XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->STC |= automatic_shadow_transfer; } - /** - * @param slice Constant pointer to CC4 Slice - * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be - * generated - * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a - * bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By - * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n - * - * This disables the generation of automatic shadow transfer request for the specified register update. - * \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(). - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC4 Slice +* @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be +* generated +* Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a +* bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By +* clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n +* +* This disables the generation of automatic shadow transfer request for the specified register update. +* \parNote:
        +* +* \parRelated APIs:
        +* XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(). +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice, - const uint32_t automatic_shadow_transfer) + const uint32_t automatic_shadow_transfer) { XMC_ASSERT("XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); slice->STC &= ~(uint32_t)automatic_shadow_transfer; } #endif + +/** + * @param module Constant pointer to CCU4 module + * @param slice_number Slice for which the status bit should be obtained. + * Range: [0x0 to 0x3] + * @return status bit of slice passive (false) or active (true) + * + * \parDescription:
        + * Returns CCU4 slice status bit (passive or active) + * + */ +__STATIC_INLINE XMC_CCU4_SLICE_STATUS_BIT_t XMC_CCU4_GetSliceStatusBit(XMC_CCU4_MODULE_t *const module, uint8_t slice_number) +{ + return (XMC_CCU4_SLICE_STATUS_BIT_t)((module->GCST & (CCU4_GCST_CC40ST_Msk << slice_number)) ? 1 : 0); +} + #ifdef __cplusplus } #endif - -/** - * @} - */ - + /** * @} */ - + + #endif /* defined(CCU40) */ #endif /* CCU4_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ccu8.h b/cores/xmc_lib/XMCLib/inc/xmc_ccu8.h index 74390795..7f0fbb75 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_ccu8.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_ccu8.h @@ -1,90 +1,41 @@ /** * @file xmc_ccu8.h - * @date 2017-04-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
        - * - Documentation updates
        - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
        - * - Added XMC_CCU8_SLICE_LoadSelector() API, to select which compare register value has to be loaded - * during external load event. - * - * 2015-07-01: - * - In XMC_CCU8_SLICE_CHECK_INTERRUPT macro, fixed the missing item for compare match down for channel 2.
        - * - * 2015-07-24: - * - XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
        - * - * 2015-08-17: - * - XMC_CCU8_SLICE_PRESCALER_t enum is added to set the prescaler divider.
        - * - XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t is added for all the devices except XMC45 devices, to set when the - * shadow transfer has to happen.
        - * - XMC_CCU8_SOURCE_OUT0_t, XMC_CCU8_SOURCE_OUT1_t, XMC_CCU8_SOURCE_OUT2_t, XMC_CCU8_SOURCE_OUT3_t enums are added - * to maps one of the ST to OUT0, OUT1, OUT3, OUT4 signals. - * - In XMC_CCU8_SLICE_COMPARE_CONFIG_t structure, selector_out0, selector_out1, selector_out2, selector_out3 are - * added to support XMC14 devices. - * - XMC_CCU8_EnableShadowTransfer() API is made as inline, to improve the speed.
        - * - XMC_CCU8_SLICE_EnableCascadedShadowTransfer(), XMC_CCU8_SLICE_DisableCascadedShadowTransfer(), - * XMC_CCU8_SLICE_SetShadowTransferMode() API are supported for all the devices except XMC45. - * - * 2015-09-29: - * - In XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction - * settings. - * - * 2015-10-07: - * - XMC_CCU8_SLICE_SetTimerCompareMatchChannel1(), XMC_CCU8_SLICE_SetTimerCompareMatchChannel2() inline APIs are - * added to update the respective compare registers directly. - * - XMC_CCU8_SLICE_GetEvent() is made as inline. - * - XMC_CCU8_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU8_SLICE_EnableMultipleEvents() and - * XMC_CCU8_SLICE_DisableMultipleEvents() APIs. - * - DOC updates for the newly added APIs. - * - * 2016-03-09: - * - Optimization of write only registers - * - * 2016-05-20: - * - Added XMC_CCU8_SLICE_StopClearTimer() - * - Changed XMC_CCU8_SLICE_StopTimer() and XMC_CCU8_SLICE_ClearTimer() - * - * 2017-04-27: - * - XMC_CCU8_SLICE_SetPrescaler() changed div_val parameter to type XMC_CCU8_SLICE_PRESCALER_t - * + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * @endcond */ @@ -99,17 +50,13 @@ #if defined(CCU80) #if UC_FAMILY == XMC1 - #include "xmc1_ccu8_map.h" +#include "xmc1_ccu8_map.h" #endif #if UC_FAMILY == XMC4 - #include "xmc4_ccu8_map.h" +#include "xmc4_ccu8_map.h" #endif -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup CCU8 @@ -117,10 +64,10 @@ * @brief Capture Compare Unit 8 (CCU8) low level driver for XMC family of microcontrollers
        * * The CCU8 peripheral functions play a major role in applications that need complex Pulse Width Modulation (PWM) signal - * generation, with complementary high side and low side switches, multi phase control. These functions in conjunction - * with a very flexible and programmable signal conditioning scheme, make the CCU8 the must have peripheral for state + * generation, with complementary high side and low side switches, multi phase control. These functions in conjunction + * with a very flexible and programmable signal conditioning scheme, make the CCU8 the must have peripheral for state * of the art motor control, multi phase and multi level power electronics systems.\n - * Each CCU8 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC8y (where y = [0..4]). Each + * Each CCU8 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC8y (where y = [0..4]). Each * timer slice can work in compare mode or in capture mode. * * APIs provided in this file cover the following functional blocks of CCU8: @@ -130,17 +77,17 @@ * 2. Module (APIs are not having any prefix e.g. XMC_CCU8_) * * \par Timer(Compare mode) configuration: - * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_COMPARE_CONFIG_t, + * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_COMPARE_CONFIG_t, * XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t and the initialization functions XMC_CCU8_SLICE_CompareInit(), XMC_CCU8_SLICE_DeadTimeInit(). * * It can be used to: * -# Start and Stop the timer. (XMC_CCU8_SLICE_StartTimer(), XMC_CCU8_SLICE_StopTimer()) - * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU8_SLICE_SetTimerPeriodMatch(), - * XMC_CCU8_SLICE_SetTimerCompareMatch(), XMC_CCU8_SLICE_SetPrescaler(), XMC_CCU8_SLICE_SetDitherCompareValue(), + * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU8_SLICE_SetTimerPeriodMatch(), + * XMC_CCU8_SLICE_SetTimerCompareMatch(), XMC_CCU8_SLICE_SetPrescaler(), XMC_CCU8_SLICE_SetDitherCompareValue(), * XMC_CCU8_SLICE_SetPassiveLevel()) * -# Configure the dead time.(XMC_CCU8_SLICE_SetDeadTimeValue(), XMC_CCU8_SLICE_SetDeadTimePrescaler()) * -# Enable the slices to support multichannel mode. (XMC_CCU8_SLICE_EnableMultiChannelMode()) - * + * * \par Capture configuration: * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_CAPTURE_CONFIG_t and the initialization * function XMC_CCU8_SLICE_CaptureInit(). @@ -149,14 +96,14 @@ * -# Configure the capture functionality. (XMC_CCU8_SLICE_Capture0Config(), XMC_CCU8_SLICE_Capture1Config()) * -# Read the captured values along with the status, which indicate the value is latest or not. * (XMC_CCU8_SLICE_GetCaptureRegisterValue()) - * + * * \par Function/Event configuration: * This section of the LLD provides the configuration structure XMC_CCU8_SLICE_EVENT_CONFIG_t. - * + * * It can be used to: * -# Enable and Disable the events. (XMC_CCU8_SLICE_EnableEvent(), XMC_CCU8_SLICE_DisableEvent()) * -# Configure to start and stop the timer on external events.(XMC_CCU8_SLICE_StartConfig(), XMC_CCU8_SLICE_StopConfig()) - * -# Modulation, external load and Gating of the timer output.(XMC_CCU8_SLICE_ModulationConfig(), + * -# Modulation, external load and Gating of the timer output.(XMC_CCU8_SLICE_ModulationConfig(), * XMC_CCU8_SLICE_LoadConfig(), XMC_CCU8_SLICE_GateConfig()) * -# Control the count direction of the timer based on the external event. (XMC_CCU8_SLICE_DirectionConfig()) * -# Count the external events.(XMC_CCU8_SLICE_CountConfig()) @@ -183,7 +130,7 @@ (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT1) || \ (interrupt == XMC_CCU8_SLICE_IRQ_ID_EVENT2) || \ (interrupt == XMC_CCU8_SLICE_IRQ_ID_TRAP)) - + /* Macro to check if the slice ptr passed is valid */ #define XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(cmp_channel) \ ((cmp_channel == XMC_CCU8_SLICE_COMPARE_CHANNEL_1) || \ @@ -209,8 +156,8 @@ typedef CCU8_CC8_TypeDef XMC_CCU8_SLICE_t; typedef enum XMC_CCU8_STATUS { XMC_CCU8_STATUS_OK = 0U, /**< API fulfils request */ - XMC_CCU8_STATUS_ERROR , /**< API cannot fulfil request */ - XMC_CCU8_STATUS_RUNNING , /**< The timer slice is currently running */ + XMC_CCU8_STATUS_ERROR, /**< API cannot fulfil request */ + XMC_CCU8_STATUS_RUNNING, /**< The timer slice is currently running */ XMC_CCU8_STATUS_IDLE /**< The timer slice is currently idle */ } XMC_CCU8_STATUS_t; @@ -220,8 +167,8 @@ typedef enum XMC_CCU8_STATUS typedef enum XMC_CCU8_CLOCK { XMC_CCU8_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */ - XMC_CCU8_CLOCK_EXTERNAL_A , /**< External clock-A */ - XMC_CCU8_CLOCK_EXTERNAL_B , /**< External clock-B */ + XMC_CCU8_CLOCK_EXTERNAL_A, /**< External clock-A */ + XMC_CCU8_CLOCK_EXTERNAL_B, /**< External clock-B */ XMC_CCU8_CLOCK_EXTERNAL_C /**< External clock-C */ } XMC_CCU8_CLOCK_t; @@ -230,13 +177,13 @@ typedef enum XMC_CCU8_CLOCK */ typedef enum XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER { - XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software only for slice 0*/ - XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software and hardware for slice 0 */ - XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software only for slice 1*/ - XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software + XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software and hardware for slice 1 */ XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software only for slice 2 */ @@ -338,20 +285,20 @@ typedef enum XMC_CCU8_SLICE_COMPARE_CHANNEL typedef enum XMC_CCU8_SLICE_PRESCALER { XMC_CCU8_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu8 */ - XMC_CCU8_SLICE_PRESCALER_2 , /**< Slice Clock = fccu8/2 */ - XMC_CCU8_SLICE_PRESCALER_4 , /**< Slice Clock = fccu8/4 */ - XMC_CCU8_SLICE_PRESCALER_8 , /**< Slice Clock = fccu8/8 */ - XMC_CCU8_SLICE_PRESCALER_16 , /**< Slice Clock = fccu8/16 */ - XMC_CCU8_SLICE_PRESCALER_32 , /**< Slice Clock = fccu8/32 */ - XMC_CCU8_SLICE_PRESCALER_64 , /**< Slice Clock = fccu8/64 */ - XMC_CCU8_SLICE_PRESCALER_128 , /**< Slice Clock = fccu8/128 */ - XMC_CCU8_SLICE_PRESCALER_256 , /**< Slice Clock = fccu8/256 */ - XMC_CCU8_SLICE_PRESCALER_512 , /**< Slice Clock = fccu8/512 */ - XMC_CCU8_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu8/1024 */ - XMC_CCU8_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu8/2048 */ - XMC_CCU8_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu8/4096 */ - XMC_CCU8_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu8/8192 */ - XMC_CCU8_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu8/16384 */ + XMC_CCU8_SLICE_PRESCALER_2, /**< Slice Clock = fccu8/2 */ + XMC_CCU8_SLICE_PRESCALER_4, /**< Slice Clock = fccu8/4 */ + XMC_CCU8_SLICE_PRESCALER_8, /**< Slice Clock = fccu8/8 */ + XMC_CCU8_SLICE_PRESCALER_16, /**< Slice Clock = fccu8/16 */ + XMC_CCU8_SLICE_PRESCALER_32, /**< Slice Clock = fccu8/32 */ + XMC_CCU8_SLICE_PRESCALER_64, /**< Slice Clock = fccu8/64 */ + XMC_CCU8_SLICE_PRESCALER_128, /**< Slice Clock = fccu8/128 */ + XMC_CCU8_SLICE_PRESCALER_256, /**< Slice Clock = fccu8/256 */ + XMC_CCU8_SLICE_PRESCALER_512, /**< Slice Clock = fccu8/512 */ + XMC_CCU8_SLICE_PRESCALER_1024, /**< Slice Clock = fccu8/1024 */ + XMC_CCU8_SLICE_PRESCALER_2048, /**< Slice Clock = fccu8/2048 */ + XMC_CCU8_SLICE_PRESCALER_4096, /**< Slice Clock = fccu8/4096 */ + XMC_CCU8_SLICE_PRESCALER_8192, /**< Slice Clock = fccu8/8192 */ + XMC_CCU8_SLICE_PRESCALER_16384, /**< Slice Clock = fccu8/16384 */ XMC_CCU8_SLICE_PRESCALER_32768 /**< Slice Clock = fccu8/32768 */ } XMC_CCU8_SLICE_PRESCALER_t; @@ -361,8 +308,8 @@ typedef enum XMC_CCU8_SLICE_PRESCALER typedef enum XMC_CCU8_SLICE_DTC_DIV { XMC_CCU8_SLICE_DTC_DIV_1 = 0U, /**< DTC clock = Slice Clock */ - XMC_CCU8_SLICE_DTC_DIV_2 , /**< DTC clock = Slice Clock/2 */ - XMC_CCU8_SLICE_DTC_DIV_4 , /**< DTC clock = Slice Clock/4 */ + XMC_CCU8_SLICE_DTC_DIV_2, /**< DTC clock = Slice Clock/2 */ + XMC_CCU8_SLICE_DTC_DIV_4, /**< DTC clock = Slice Clock/4 */ XMC_CCU8_SLICE_DTC_DIV_8 /**< DTC clock = Slice Clock/8 */ } XMC_CCU8_SLICE_DTC_DIV_t; @@ -373,12 +320,12 @@ typedef enum XMC_CCU8_SLICE_DTC_DIV typedef enum XMC_CCU8_SLICE_STATUS { XMC_CCU8_SLICE_STATUS_CHANNEL_1 = 0U, /**< Channel-1 status connected to Slice Status */ - XMC_CCU8_SLICE_STATUS_CHANNEL_2 , /**< Channel-2 status connected to Slice Status */ - XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2 , /**< \b Wired \b AND of Channel-1 and Channel-2 status connected to + XMC_CCU8_SLICE_STATUS_CHANNEL_2, /**< Channel-2 status connected to Slice Status */ + XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2, /**< \b Wired \b AND of Channel-1 and Channel-2 status connected to Slice status */ -#if ((UC_SERIES == XMC13) || (UC_SERIES == XMC14)) || defined(DOXYGEN) +#if ((UC_SERIES == XMC13) || (UC_SERIES == XMC14)) || defined(DOXYGEN_XMC1) XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2 /**< \b Wired \b OR of Channel-1 and Channel-2 status connected to Slice - status. @note Only available for XMC1300 and XMC1400 series */ + status. @note Only available for XMC1300 and XMC1400 series */ #endif } XMC_CCU8_SLICE_STATUS_t; @@ -388,8 +335,8 @@ typedef enum XMC_CCU8_SLICE_STATUS typedef enum XMC_CCU8_SLICE_MODULATION_CHANNEL { XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE = 0U, /**< No modulation */ - XMC_CCU8_SLICE_MODULATION_CHANNEL_1 , /**< Modulation for Compare Channel-1 */ - XMC_CCU8_SLICE_MODULATION_CHANNEL_2 , /**< Modulation for Compare Channel-2 */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_1, /**< Modulation for Compare Channel-1 */ + XMC_CCU8_SLICE_MODULATION_CHANNEL_2, /**< Modulation for Compare Channel-2 */ XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2 /**< Modulation for Compare Channel-1 and Compare Channel-2 */ } XMC_CCU8_SLICE_MODULATION_CHANNEL_t; @@ -399,17 +346,17 @@ typedef enum XMC_CCU8_SLICE_MODULATION_CHANNEL typedef enum XMC_CCU8_SLICE_FUNCTION { XMC_CCU8_SLICE_FUNCTION_START = 0U, /**< Start function */ - XMC_CCU8_SLICE_FUNCTION_STOP , /**< Stop function */ - XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event + XMC_CCU8_SLICE_FUNCTION_STOP, /**< Stop function */ + XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT0, /**< Capture Event-0 function, CCycapt0 signal is used for event generation */ - XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event + XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT1, /**< Capture Event-1 function, CCycapt1 signal is used for event generation */ - XMC_CCU8_SLICE_FUNCTION_GATING , /**< Gating function */ - XMC_CCU8_SLICE_FUNCTION_DIRECTION , /**< Direction function */ - XMC_CCU8_SLICE_FUNCTION_LOAD , /**< Load function */ - XMC_CCU8_SLICE_FUNCTION_COUNT , /**< Counting function */ - XMC_CCU8_SLICE_FUNCTION_OVERRIDE , /**< Override function */ - XMC_CCU8_SLICE_FUNCTION_MODULATION , /**< Modulation function */ + XMC_CCU8_SLICE_FUNCTION_GATING, /**< Gating function */ + XMC_CCU8_SLICE_FUNCTION_DIRECTION, /**< Direction function */ + XMC_CCU8_SLICE_FUNCTION_LOAD, /**< Load function */ + XMC_CCU8_SLICE_FUNCTION_COUNT, /**< Counting function */ + XMC_CCU8_SLICE_FUNCTION_OVERRIDE, /**< Override function */ + XMC_CCU8_SLICE_FUNCTION_MODULATION, /**< Modulation function */ XMC_CCU8_SLICE_FUNCTION_TRAP /**< Trap function */ } XMC_CCU8_SLICE_FUNCTION_t; @@ -419,8 +366,8 @@ typedef enum XMC_CCU8_SLICE_FUNCTION typedef enum XMC_CCU8_SLICE_EVENT { XMC_CCU8_SLICE_EVENT_NONE = 0U, /**< None */ - XMC_CCU8_SLICE_EVENT_0 , /**< Event-0 */ - XMC_CCU8_SLICE_EVENT_1 , /**< Event-1 */ + XMC_CCU8_SLICE_EVENT_0, /**< Event-0 */ + XMC_CCU8_SLICE_EVENT_1, /**< Event-1 */ XMC_CCU8_SLICE_EVENT_2 /**< Event-2 */ } XMC_CCU8_SLICE_EVENT_t; @@ -430,9 +377,9 @@ typedef enum XMC_CCU8_SLICE_EVENT typedef enum XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY { XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */ - XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE, /**< Rising Edge of the input signal generates event trigger */ - XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event + XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE, /**< Falling Edge of the input signal generates event trigger */ XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger */ } XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t; @@ -444,8 +391,8 @@ typedef enum XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY { XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/ XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level */ - /* Below enum items can be utilised specific to the functionality */ - XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ + /* Below enum items can be utilised specific to the functionality */ + XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */ XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */ } XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t; @@ -455,8 +402,8 @@ typedef enum XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY typedef enum XMC_CCU8_SLICE_EVENT_FILTER { XMC_CCU8_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filtering is applied */ - XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES , /**< Input should be stable for 3 clock cycles */ - XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES , /**< Input should be stable for 5 clock cycles */ + XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES, /**< Input should be stable for 3 clock cycles */ + XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES, /**< Input should be stable for 5 clock cycles */ XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES /**< Input should be stable for 7 clock cycles */ } XMC_CCU8_SLICE_EVENT_FILTER_t; @@ -473,7 +420,7 @@ typedef uint8_t XMC_CCU8_SLICE_INPUT_t; typedef enum XMC_CCU8_SLICE_END_MODE { XMC_CCU8_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */ - XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */ + XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR, /**< Without stopping timer, clears the TIMER register */ XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */ } XMC_CCU8_SLICE_END_MODE_t; @@ -510,8 +457,8 @@ typedef enum XMC_CCU8_SLICE_TRAP_EXIT_MODE typedef enum XMC_CCU8_SLICE_TIMER_CLEAR_MODE { XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */ - XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */ - XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH, /**< Clear only when timer value has been captured in C3V and C2V */ + XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW, /**< Clear only when timer value has been captured in C1V and C0V */ XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */ } XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t; @@ -523,10 +470,10 @@ typedef enum XMC_CCU8_SLICE_MCMS_ACTION XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to the actual registers upon MCS xfer request */ XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow - register values to the actual registers upon MCS xfer + register values to the actual registers upon MCS xfer request */ - XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither - Compare register values to the actual registers upon + XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither + Compare register values to the actual registers upon MCS xfer request */ } XMC_CCU8_SLICE_MCMS_ACTION_t; @@ -535,14 +482,14 @@ typedef enum XMC_CCU8_SLICE_MCMS_ACTION */ typedef enum XMC_CCU8_SLICE_IRQ_ID { - XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */ - XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< One match counting down */ - XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1 = 2U , /**< Compare match counting up for channel 1 */ - XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1 = 3U , /**< Compare match counting down for channel 1 */ - XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2 = 4U , /**< Compare match counting up for channel 2 */ - XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2 = 5U , /**< Compare match counting down for channel 2 */ - XMC_CCU8_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */ - XMC_CCU8_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH = 0U, /**< Period match counting up */ + XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH = 1U, /**< One match counting down */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1 = 2U, /**< Compare match counting up for channel 1 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1 = 3U, /**< Compare match counting down for channel 1 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2 = 4U, /**< Compare match counting up for channel 2 */ + XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2 = 5U, /**< Compare match counting down for channel 2 */ + XMC_CCU8_SLICE_IRQ_ID_EVENT0 = 8U, /**< Event-0 occurrence */ + XMC_CCU8_SLICE_IRQ_ID_EVENT1 = 9U, /**< Event-1 occurrence */ XMC_CCU8_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */ XMC_CCU8_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */ } XMC_CCU8_SLICE_IRQ_ID_t; @@ -569,8 +516,8 @@ typedef enum XMC_CCU8_SLICE_MULTI_IRQ_ID typedef enum XMC_CCU8_SLICE_SR_ID { XMC_CCU8_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */ - XMC_CCU8_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */ - XMC_CCU8_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */ + XMC_CCU8_SLICE_SR_ID_1, /**< Service Request Line-1 selected */ + XMC_CCU8_SLICE_SR_ID_2, /**< Service Request Line-2 selected */ XMC_CCU8_SLICE_SR_ID_3 /**< Service Request Line-3 selected */ } XMC_CCU8_SLICE_SR_ID_t; @@ -580,28 +527,28 @@ typedef enum XMC_CCU8_SLICE_SR_ID */ typedef enum XMC_CCU8_SHADOW_TRANSFER { - XMC_CCU8_SHADOW_TRANSFER_SLICE_0 = CCU8_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU8_SHADOW_TRANSFER_SLICE_0 = CCU8_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-0 */ XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU8_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value to actual register for SLICE-0 */ XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU8_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to actual register for SLICE-0 */ - XMC_CCU8_SHADOW_TRANSFER_SLICE_1 = CCU8_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU8_SHADOW_TRANSFER_SLICE_1 = CCU8_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-1 */ XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU8_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value to actual registers for SLICE-1 */ XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU8_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to actual register for SLICE-1 */ - XMC_CCU8_SHADOW_TRANSFER_SLICE_2 = CCU8_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU8_SHADOW_TRANSFER_SLICE_2 = CCU8_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-2 */ XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU8_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value to actual register for SLICE-2 */ XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU8_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to actual register for SLICE-2 */ - XMC_CCU8_SHADOW_TRANSFER_SLICE_3 = CCU8_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level + XMC_CCU8_SHADOW_TRANSFER_SLICE_3 = CCU8_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level shadow register values to actual registers for SLICE-3 */ XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU8_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value @@ -613,7 +560,7 @@ typedef enum XMC_CCU8_SHADOW_TRANSFER #if (UC_SERIES != XMC45) || defined(DOXYGEN) /** * Slice shadow transfer mode options. - * @note Not available for XMC4500 series + * \if XMC4 @note Not available for XMC4500 series \endif */ typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE { @@ -624,12 +571,12 @@ typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE } XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t; #endif -#if defined(CCU8V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */ +#if defined(CCU8V3) || defined(DOXYGEN_XMC1) /* Defined for XMC1400 devices only */ /** * Output sources for OUTy0 signal * @note Only available for XMC1400 series */ - typedef enum XMC_CCU8_SOURCE_OUT0 +typedef enum XMC_CCU8_SOURCE_OUT0 { XMC_CCU8_SOURCE_OUT0_ST1 = (uint32_t)0x0, /**< CCU8yST1 signal path is connected the CCU8x.OUT0 */ XMC_CCU8_SOURCE_OUT0_INV_ST1 = (uint32_t)0x1, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT0 */ @@ -641,7 +588,7 @@ typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE * Output sources for OUTy1 signal * @note Only available for XMC1400 series */ - typedef enum XMC_CCU8_SOURCE_OUT1 +typedef enum XMC_CCU8_SOURCE_OUT1 { XMC_CCU8_SOURCE_OUT1_ST1 = (uint32_t)0x1, /**< CCU8yST1 signal path is connected the CCU8x.OUT1 */ XMC_CCU8_SOURCE_OUT1_INV_ST1 = (uint32_t)0x0, /**< Inverted CCU8yST1 signal path is connected the CCU8x.OUT1 */ @@ -653,7 +600,7 @@ typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE * Output sources for OUTy2 signal * @note Only available for XMC1400 series */ - typedef enum XMC_CCU8_SOURCE_OUT2 +typedef enum XMC_CCU8_SOURCE_OUT2 { XMC_CCU8_SOURCE_OUT2_ST2 = (uint32_t)0x0, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ XMC_CCU8_SOURCE_OUT2_INV_ST2 = (uint32_t)0x1, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ @@ -665,7 +612,7 @@ typedef enum XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE * Output sources for OUTy3 signal * @note Only available for XMC1400 series */ - typedef enum XMC_CCU8_SOURCE_OUT3 +typedef enum XMC_CCU8_SOURCE_OUT3 { XMC_CCU8_SOURCE_OUT3_ST2 = (uint32_t)0x1, /**< CCU8yST2 signal path is connected the CCU8x.OUT2 */ XMC_CCU8_SOURCE_OUT3_INV_ST2 = (uint32_t)0x0, /**< Inverted CCU8yST2 signal path is connected the CCU8x.OUT2 */ @@ -717,23 +664,23 @@ typedef enum XMC_CCU8_OUT_PATH */ typedef enum XMC_CCU8_SLICE_WRITE_INTO { - XMC_CCU8_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU8_CC8_STC_IRPC_Msk, /**< Immediate or Coherent - Write into Period + XMC_CCU8_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU8_CC8_STC_IRPC_Msk, /**< Immediate or Coherent + Write into Period Configuration */ - XMC_CCU8_SLICE_WRITE_INTO_COMPARE1_CONFIGURATION = CCU8_CC8_STC_IRCC1_Msk, /**< Immediate or Coherent - Write into Compare 1 + XMC_CCU8_SLICE_WRITE_INTO_COMPARE1_CONFIGURATION = CCU8_CC8_STC_IRCC1_Msk, /**< Immediate or Coherent + Write into Compare 1 Configuration */ - XMC_CCU8_SLICE_WRITE_INTO_COMPARE2_CONFIGURATION = CCU8_CC8_STC_IRCC2_Msk, /**< Immediate or Coherent - Write into Compare 2 + XMC_CCU8_SLICE_WRITE_INTO_COMPARE2_CONFIGURATION = CCU8_CC8_STC_IRCC2_Msk, /**< Immediate or Coherent + Write into Compare 2 Configuration */ - XMC_CCU8_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU8_CC8_STC_IRLC_Msk, /**< Immediate or Coherent + XMC_CCU8_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU8_CC8_STC_IRLC_Msk, /**< Immediate or Coherent Write into Passive Level Configuration */ - XMC_CCU8_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRDC_Msk, /**< Immediate or Coherent + XMC_CCU8_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRDC_Msk, /**< Immediate or Coherent Write into Dither Value Configuration */ - XMC_CCU8_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRFC_Msk /**< Immediate or Coherent - Write into Floating Prescaler + XMC_CCU8_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU8_CC8_STC_IRFC_Msk /**< Immediate or Coherent + Write into Floating Prescaler Value Configuration */ } XMC_CCU8_SLICE_WRITE_INTO_t; @@ -769,17 +716,71 @@ typedef enum XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO } XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t; #endif + /** * CCU8 slice mask which can be used for the APIs as input where multi slice support is available */ typedef enum XMC_CCU8_SLICE_MASK { - XMC_CCU8_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */ - XMC_CCU8_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */ - XMC_CCU8_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */ + XMC_CCU8_SLICE_MASK_SLICE_0 = 1U, /**< SLICE-0 */ + XMC_CCU8_SLICE_MASK_SLICE_1 = 2U, /**< SLICE-1 */ + XMC_CCU8_SLICE_MASK_SLICE_2 = 4U, /**< SLICE-2 */ XMC_CCU8_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */ } XMC_CCU8_SLICE_MASK_t; +/** + * Selects which signal is controlling the delay between the change at the CCU8 outputs and effective change at the driver parity output + */ +typedef enum XMC_CCU8_PARITY_CHECKER_DELAY_INPUT +{ + XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_IGBTA = 0 << CCU8_GPCHK_PCDS_Pos, + XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_IGBTB = 1 << CCU8_GPCHK_PCDS_Pos, + XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_IGBTC = 2 << CCU8_GPCHK_PCDS_Pos, + XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_IGBTD = 3 << CCU8_GPCHK_PCDS_Pos +} XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_t; + + +/** + * Selects which signal contains the driver parity information + */ +typedef enum XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT +{ + XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_SLICE_0 = 0 << CCU8_GPCHK_PISEL_Pos, + XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_SLICE_1 = 1 << CCU8_GPCHK_PISEL_Pos, + XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_SLICE_2 = 2 << CCU8_GPCHK_PISEL_Pos, + XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_SLICE_3 = 3 << CCU8_GPCHK_PISEL_Pos, +} XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_t; + +/** + * Selects if we have an odd or even parity + */ +typedef enum XMC_CCU8_PARITY_CHECKER_TYPE +{ + XMC_CCU8_PARITY_CHECKER_TYPE_EVEN = 0 << CCU8_GPCHK_PCTS_Pos, + XMC_CCU8_PARITY_CHECKER_TYPE_ODD = 1 << CCU8_GPCHK_PCTS_Pos, +} XMC_CCU8_PARITY_CHECKER_TYPE_t; + +/** + * Selects suspend mode + */ +typedef enum XMC_CCU8_SUSPEND_MODE +{ + XMC_CCU8_SUSPEND_MODE_IGNORE = 0 << CCU8_GCTRL_SUSCFG_Pos, /**< Suspend request ignored. The module never enters in suspend */ + XMC_CCU8_SUSPEND_MODE_STOPS_INMEDIATELLY = 1 << CCU8_GCTRL_SUSCFG_Pos, /**< Stops all the running slices immediately. Safe stop is not applied. */ + XMC_CCU8_SUSPEND_MODE_SAFE_STOP = 2 << CCU8_GCTRL_SUSCFG_Pos, /**< Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. */ + XMC_CCU8_SUSPEND_MODE_WAIT_ROLL_OVER = 3 << CCU8_GCTRL_SUSCFG_Pos /**< Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. */ +} XMC_CCU8_SUSPEND_MODE_t; + +/** + * CCU8 slice status bit + */ +typedef enum XMC_CCU8_SLICE_STATUS_BIT +{ + XMC_CCU8_SLICE_STATUS_BIT_PASSIVE = false, /**< Passive */ + XMC_CCU8_SLICE_STATUS_BIT_ACTIVE = true /**< Active */ +} XMC_CCU8_SLICE_STATUS_BIT_t; + + /********************************************************************************************************************* * DATA STRUCTURES ********************************************************************************************************************/ @@ -801,10 +802,10 @@ typedef struct XMC_CCU8_SLICE_EVENT_CONFIG /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -819,10 +820,10 @@ typedef struct XMC_CCU8_SLICE_DEAD_TIME_CONFIG uint32_t enable_dead_time_channel1 : 1; /**< Enable dead time for Compare Channel-1 */ uint32_t enable_dead_time_channel2 : 1; /**< Enable dead time for Compare Channel-2 */ uint32_t channel1_st_path : 1; /**< Should dead time be applied to ST output of Compare Channel-1? */ - uint32_t channel1_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of + uint32_t channel1_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of Compare Channel-1? */ uint32_t channel2_st_path : 1; /**< Should dead time be applied to ST output of Compare Channel-2? */ - uint32_t channel2_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of + uint32_t channel2_inv_st_path : 1; /**< Should dead time be applied to inverse ST output of Compare Channel-2? */ uint32_t div : 2; /**< Dead time prescaler divider value. Accepts enum ::XMC_CCU8_SLICE_DTC_DIV_t*/ @@ -891,13 +892,13 @@ typedef struct XMC_CCU8_SLICE_COMPARE_CONFIG { struct { - uint32_t passive_level_out0 : 1; /**< ST and OUT passive levels Configuration for OUT0. + uint32_t passive_level_out0 : 1; /**< ST and OUT passive levels Configuration for OUT0. Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ - uint32_t passive_level_out1 : 1; /**< ST and OUT passive levels Configuration for OUT1. + uint32_t passive_level_out1 : 1; /**< ST and OUT passive levels Configuration for OUT1. Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ - uint32_t passive_level_out2 : 1; /**< ST and OUT passive levels Configuration for OUT2. + uint32_t passive_level_out2 : 1; /**< ST and OUT passive levels Configuration for OUT2. Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ - uint32_t passive_level_out3 : 1; /**< ST and OUT passive levels Configuration for OUT3. + uint32_t passive_level_out3 : 1; /**< ST and OUT passive levels Configuration for OUT3. Accepts enum :: XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t */ uint32_t : 28; }; @@ -909,43 +910,43 @@ typedef struct XMC_CCU8_SLICE_COMPARE_CONFIG { uint32_t asymmetric_pwm : 1; /**< Should the PWM be a function of the 2 compare channels rather than period value? */ - #if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ +#if !defined(CCU8V3) /* Defined for all devices except XMC1400 */ uint32_t invert_out0 : 1; /**< Should inverted ST of Channel-1 be connected to OUT0? */ uint32_t invert_out1 : 1; /**< Should inverted ST of Channel-1 be connected to OUT1? */ uint32_t invert_out2 : 1; /**< Should inverted ST of Channel-2 be connected to OUT2? */ uint32_t invert_out3 : 1; /**< Should inverted ST of Channel-2 be connected to OUT3? */ uint32_t : 27; - #else +#else uint32_t : 3; uint32_t selector_out0 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT0 - Accepts enum :: XMC_CCU8_SOURCE_OUT0_t - refer OCS1 bit-field of CHC register. + Accepts enum :: XMC_CCU8_SOURCE_OUT0_t + refer OCS1 bit-field of CHC register. @note Only available for XMC1400 series */ uint32_t : 2; uint32_t selector_out1 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT1 - Accepts enum :: XMC_CCU8_SOURCE_OUT1_t - refer OCS2 bit-field of CHC register. + Accepts enum :: XMC_CCU8_SOURCE_OUT1_t + refer OCS2 bit-field of CHC register. @note Only available for XMC1400 series */ uint32_t : 2; uint32_t selector_out2 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT2 - Accepts enum :: XMC_CCU8_SOURCE_OUT2_t + Accepts enum :: XMC_CCU8_SOURCE_OUT2_t refer OCS3 bit-field of CHC register. @note Only available for XMC1400 series */ uint32_t : 2; uint32_t selector_out3 : 2; /**< Connect ST or inverted ST of Channel-1 or Channel-2 be to OUT3 - Accepts enum :: XMC_CCU8_SOURCE_OUT3_t + Accepts enum :: XMC_CCU8_SOURCE_OUT3_t refer OCS4 bit-field of CHC register. @note Only available for XMC1400 series */ uint32_t : 14; - #endif +#endif }; uint32_t chc; }; - uint32_t prescaler_initval : 4; /**< Initial prescaler divider value + uint32_t prescaler_initval : 4; /**< Initial prescaler divider value Accepts enum :: XMC_CCU8_SLICE_PRESCALER_t */ uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to. Range : [0 to 15] */ - uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering + uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering Range : [0 to 15] */ uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true*/ } XMC_CCU8_SLICE_COMPARE_CONFIG_t; @@ -979,9 +980,9 @@ typedef struct XMC_CCU8_SLICE_CAPTURE_CONFIG } XMC_CCU8_SLICE_CAPTURE_CONFIG_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * API Prototypes @@ -993,45 +994,45 @@ extern "C" { __STATIC_INLINE bool XMC_CCU8_IsValidModule(const XMC_CCU8_MODULE_t *const module) { bool tmp = false; - + tmp = (module == CCU80); - + #if defined(CCU81) tmp = tmp || (module == CCU81); #endif - - return tmp; -} + + return tmp; +} __STATIC_INLINE bool XMC_CCU8_IsValidSlice(const XMC_CCU8_SLICE_t *const slice) { bool tmp = false; - + tmp = (slice == CCU80_CC80); -#if defined(CCU80_CC81) +#if defined(CCU80_CC81) tmp = tmp || (slice == CCU80_CC81); #endif -#if defined(CCU80_CC82) +#if defined(CCU80_CC82) tmp = tmp || (slice == CCU80_CC82); #endif -#if defined(CCU80_CC83) +#if defined(CCU80_CC83) tmp = tmp || (slice == CCU80_CC83); #endif -#if defined(CCU81) +#if defined(CCU81) tmp = tmp || (slice == CCU81_CC80); -#if defined(CCU81_CC81) +#if defined(CCU81_CC81) tmp = tmp || (slice == CCU81_CC81); #endif -#if defined(CCU81_CC82) +#if defined(CCU81_CC82) tmp = tmp || (slice == CCU81_CC82); #endif -#if defined(CCU81_CC83) +#if defined(CCU81_CC83) tmp = tmp || (slice == CCU81_CC83); #endif -#endif - - return tmp; -} +#endif + + return tmp; +} /** * @param module Constant pointer to CCU8 module @@ -1098,7 +1099,6 @@ void XMC_CCU8_DisableModule(XMC_CCU8_MODULE_t *const module); */ void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLOCK_t clock); - /** * @param module Constant pointer to CCU8 module * @return
        @@ -1111,13 +1111,31 @@ void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLO * (Mandatory to fully initialize the module). * * \parRelated APIs:
        - * XMC_CCU8_Init()
        XMC_CCU8_EnableClock()
        XMC_CCU8_DisableClock()
        XMC_CCU8_StartPrescaler()
        + * XMC_CCU8_Init()
        XMC_CCU8_EnableClock()
        XMC_CCU8_DisableClock()
        XMC_CCU8_StartPrescaler()
        * XMC_CCU8_StopPrescaler(). */ __STATIC_INLINE void XMC_CCU8_StartPrescaler(XMC_CCU8_MODULE_t *const module) { XMC_ASSERT("XMC_CCU8_StartPrescaler:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); - module->GIDLC |= (uint32_t) CCU8_GIDLC_SPRB_Msk; + module->GIDLC = (uint32_t) CCU8_GIDLC_SPRB_Msk; +} + +/** + * @param module Constant pointer to CCU8 module + * @return
        + * None
        + * + * \parDescription:
        + * Starts the parity function.
        \n + * Invoke this API after XMC_CCU8_Init() + * + * \parRelated APIs:
        + * XMC_CCU8_Init()
        XMC_CCU8_EnableClock()
        XMC_CCU8_DisableClock()
        XMC_CCU8_StopParityChecker(). + */ +__STATIC_INLINE void XMC_CCU8_StartParityChecker(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_StartParityChecker:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GIDLC = (uint32_t) CCU8_GIDLC_SPCH_Msk; } /** @@ -1136,7 +1154,24 @@ __STATIC_INLINE void XMC_CCU8_StartPrescaler(XMC_CCU8_MODULE_t *const module) __STATIC_INLINE void XMC_CCU8_StopPrescaler(XMC_CCU8_MODULE_t *const module) { XMC_ASSERT("XMC_CCU8_StopPrescaler:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); - module->GIDLS |= (uint32_t) CCU8_GIDLS_CPRB_Msk; + module->GIDLS = (uint32_t) CCU8_GIDLS_CPRB_Msk; +} + +/** + * @param module Constant pointer to CCU8 module + * @return
        + * None
        + * + * \parDescription:
        + * Stops the parity function.
        \n + * + * \parRelated APIs:
        + * XMC_CCU8_EnableClock()
        XMC_CCU8_DisableClock()
        XMC_CCU8_StartParityChecker()
        + */ +__STATIC_INLINE void XMC_CCU8_StopParityChecker(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_StopParityChecker:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GIDLS = (uint32_t) CCU8_GIDLS_CPCH_Msk; } /** @@ -1146,7 +1181,7 @@ __STATIC_INLINE void XMC_CCU8_StopPrescaler(XMC_CCU8_MODULE_t *const module) * * \parDescription:
        * Returns the state of the prescaler, by reading GSTAT.PRB bit.\n\n - * If clock is being supplied to the slices of the module then returns as true. + * If clock is being supplied to the slices of the module then returns as true. * * \parRelated APIs:
        * XMC_CCU8_StartPrescaler()
        XMC_CCU8_StopPrescaler()
        XMC_CCU8_EnableClock()
        XMC_CCU8_DisableClock(). @@ -1154,21 +1189,38 @@ __STATIC_INLINE void XMC_CCU8_StopPrescaler(XMC_CCU8_MODULE_t *const module) __STATIC_INLINE bool XMC_CCU8_IsPrescalerRunning(XMC_CCU8_MODULE_t *const module) { XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); - return((bool)((module->GSTAT & (uint32_t) CCU8_GSTAT_PRB_Msk) == CCU8_GSTAT_PRB_Msk)); + return ((bool)((module->GSTAT & (uint32_t) CCU8_GSTAT_PRB_Msk) == CCU8_GSTAT_PRB_Msk)); +} + +/** + * @param module Constant pointer to CCU8 module + * @return
        + * None
        + * + * \parDescription:
        + * Returns the state of the parity checker.\n\n + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker()
        XMC_CCU8_StopParityChecker()
        XMC_CCU8_EnableClock()
        XMC_CCU8_DisableClock(). + */ +__STATIC_INLINE bool XMC_CCU8_IsParityCheckerRunning(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + return ((bool)((module->GSTAT & (uint32_t) CCU8_GSTAT_PCRB_Msk) == CCU8_GSTAT_PCRB_Msk)); } /** * @param module Constant pointer to CCU8 module * @param clock_mask Slices whose clocks are to be enabled simultaneously. - * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively. + * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively. * Range: [0x1 to 0xF] * @return
        * None
        * * \parDescription:
        - * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, * GIDLC.CS3I bits.\n\n - * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out + * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out * of the idle state simultaneously. * * \parRelated APIs:
        @@ -1179,7 +1231,25 @@ __STATIC_INLINE void XMC_CCU8_EnableMultipleClocks(XMC_CCU8_MODULE_t *const modu XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid clock mask", (clock_mask < 16U)); - module->GIDLC |= (uint32_t) clock_mask; + module->GIDLC = (uint32_t) clock_mask; +} + +/** + * @param module Constant pointer to CCU8 module + * @param mode Selects suspend mode + * @return
        + * None
        + * + * \parDescription:
        + * Configures the entering in suspend mode for all the CCU8 slices. + * + * \parRelated APIs:
        + * None. + */ +__STATIC_INLINE void XMC_CCU8_SetSuspendMode(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_SUSPEND_MODE_t mode) +{ + XMC_ASSERT("XMC_CCU8_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GCTRL = (module->GCTRL & (uint32_t)~CCU8_GCTRL_SUSCFG_Msk) | mode; } /** @@ -1189,9 +1259,9 @@ __STATIC_INLINE void XMC_CCU8_EnableMultipleClocks(XMC_CCU8_MODULE_t *const modu * None
        * * \parDescription:
        - * Initialization of a CC8 slice to compare mode, by configuring CC8yTC, CC8yCMC, CC8yPSC, CC8yDITH, CC8yPSL, + * Initialization of a CC8 slice to compare mode, by configuring CC8yTC, CC8yCMC, CC8yPSC, CC8yDITH, CC8yPSL, * CC8yFPCS, CC8yCHC registers.\n\n - * CC8 slice is configured with Timer configurations in this routine. Timer is stopped before initialization + * CC8 slice is configured with Timer configurations in this routine. Timer is stopped before initialization * by calling XMC_CCU8_SLICE_StopTimer(). After initialization user has to explicitly enable * the shadow transfer for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. * @@ -1211,7 +1281,7 @@ void XMC_CCU8_SLICE_CompareInit(XMC_CCU8_SLICE_t *const slice, * Initialization of a CC8 slice to capture mode, by configuring CC8yTC, CC8yCMC, CC8yPSC,CC8yFPCS registers.\n\n * CC8 slice is configured with Capture configurations in this routine. Timer is stopped before initialization * by calling XMC_CCU8_SLICE_StopTimer(). After initialization user has to explicitly enable the shadow transfer - * for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. + * for the required values by calling XMC_CCU8_EnableShadowTransfer() with appropriate mask. * * \parRelated APIs:
        * XMC_CCU8_SLICE_Capture0Config()
        XMC_CCU8_SLICE_Capture1Config(). @@ -1227,7 +1297,7 @@ void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, * None
        * * \parDescription:
        - * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, + * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I, * GIDLC.CS3I bits according to the selected \a slice_number.\n\n * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the * slice whose clock needs to be enabled. Directly accessed register is GIDLC. @@ -1240,7 +1310,7 @@ __STATIC_INLINE void XMC_CCU8_EnableClock(XMC_CCU8_MODULE_t *const module, const XMC_ASSERT("XMC_CCU8_EnableClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); XMC_ASSERT("XMC_CCU8_EnableClock:Invalid Slice Number", (slice_number < 4U)); - module->GIDLC |= ((uint32_t) 1 << slice_number); + module->GIDLC = ((uint32_t) 1 << slice_number); } /** @@ -1251,7 +1321,7 @@ __STATIC_INLINE void XMC_CCU8_EnableClock(XMC_CCU8_MODULE_t *const module, const * None
        * * \parDescription:
        - * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, + * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I, * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n * It is possible to disable clock at slice level using the module pointer. * \b slice_number is used to disable the clock to a given slice of the module. @@ -1264,21 +1334,143 @@ __STATIC_INLINE void XMC_CCU8_DisableClock(XMC_CCU8_MODULE_t *const module, cons XMC_ASSERT("XMC_CCU8_DisableClock:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); XMC_ASSERT("XMC_CCU8_DisableClock:Invalid Slice Number", (slice_number < 4U)); - module->GIDLS |= ((uint32_t) 1 << slice_number); + module->GIDLS = ((uint32_t) 1 << slice_number); +} + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @param output Slice output. + * @return
        + * None
        + * + * \parDescription:
        + * Enables slice outputs to be used to perform the parity check. + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker()
        XMC_CCU8_SLICE_ParityCheckerDisableSliceOutput()
        + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ParityCheckerEnableSliceOutput(XMC_CCU8_MODULE_t *const module, const uint8_t slice_number, XMC_CCU8_SLICE_OUTPUT_t output) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerEnableSliceOutput:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerEnableSliceOutput:Invalid Slice Number", (slice_number < 4U)); + + module->GPCHK |= (uint32_t)(((output & (1 << slice_number)) << CCU8_GPCHK_PCSEL0_Pos) | + ((output & (2 << slice_number)) << CCU8_GPCHK_PCSEL1_Pos) | + ((output & (4 << slice_number)) << CCU8_GPCHK_PCSEL2_Pos) | + ((output & (8 << slice_number)) << CCU8_GPCHK_PCSEL3_Pos)); +} + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @param output Slice output ::XMC_CCU8_SLICE_OUTPUT_t. + * @return
        + * None
        + * + * \parDescription:
        + * Enables slice outputs to be used to perform the parity check. + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker()
        XMC_CCU8_SLICE_ParityCheckerEnableSliceOutput()
        + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ParityCheckerDisableSliceOutput(XMC_CCU8_MODULE_t *const module, const uint8_t slice_number, XMC_CCU8_SLICE_OUTPUT_t output) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerEnableSliceOutput:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerDisableSliceOutput:Invalid Slice Number", (slice_number < 4U)); + + module->GPCHK &= (uint32_t)~(((output & (1 << slice_number)) << CCU8_GPCHK_PCSEL0_Pos) | + ((output & (2 << slice_number)) << CCU8_GPCHK_PCSEL1_Pos) | + ((output & (4 << slice_number)) << CCU8_GPCHK_PCSEL2_Pos) | + ((output & (8 << slice_number)) << CCU8_GPCHK_PCSEL3_Pos)); +} + +/** + * @param module Constant pointer to CCU8 module + * @param input signal controlling the delay between the change at the CCU8 outputs and effective change at the driver parity output ::XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_t. + * @return
        + * None
        + * + * \parDescription:
        + * Selects which signal is controlling the delay between the change at the CCU8 outputs and effective change at the driver parity output + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker()
        + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ParityCheckerSetDelayInput(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_PARITY_CHECKER_DELAY_INPUT_t input) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerSetDelayInput:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GPCHK = (module->GPCHK & (uint32_t)~CCU8_GPCHK_PCDS_Msk) | input; +} + +/** + * @param module Constant pointer to CCU8 module + * @param input signal contains the driver parity information ::XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_t. + * @return
        + * None
        + * + * \parDescription:
        + * Selects which signal contains the driver parity information. + * The signal must be selected throughout the input selector mux of each slice. The signal must be mapped to the Event 1 of a slice using XMC_CCU8_SLICE_SetInput() + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker(), XMC_CCU8_SLICE_SetInput()
        . + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ParityCheckerSetDriverInput(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_PARITY_CHECKER_DRIVER_INPUT_t input) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerSetDelayInput:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GPCHK = (module->GPCHK & (uint32_t)~CCU8_GPCHK_PISEL_Msk) | input; +} + +/** + * @param module Constant pointer to CCU8 module + * @param type odd or even parity ::XMC_CCU8_PARITY_CHECKER_TYPE_t. + * @return
        + * None
        + * + * \parDescription:
        + * Selects if we have an odd or even parity. + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker()
        . + */ +__STATIC_INLINE void XMC_CCU8_SLICE_ParityCheckerSetType(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_PARITY_CHECKER_TYPE_t type) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerSetDelayInput:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + module->GPCHK = (module->GPCHK & (uint32_t)~CCU8_GPCHK_PCTS_Msk) | type; +} + + +/** + * @param module Constant pointer to CCU8 module + * @return status of parity checker. If >0 then an error is dectected + * + * \parDescription:
        + * Returns current value of the XOR chain. + * + * \parRelated APIs:
        + * XMC_CCU8_StartParityChecker()
        + */ +__STATIC_INLINE uint32_t XMC_CCU8_SLICE_ParityCheckerGetStatus(XMC_CCU8_MODULE_t *const module) +{ + XMC_ASSERT("XMC_CCU8_SLICE_ParityCheckerSetDelayInput:Invalid Module Pointer", XMC_CCU8_IsValidModule(module)); + return (module->GPCHK & CCU8_GPCHK_PCST_Msk); } /** * @param slice Constant pointer to CC8 Slice * @param out_path_msk configuration for output path selection. * combination of XMC_CCU8_OUT_PATH_t enum items can be used to create a mask. - * + * * @return
        * None
        * * \parDescription:
        - * Configure the out the path of the two compare channels with specified ST signal, by configuring the + * Configure the out the path of the two compare channels with specified ST signal, by configuring the ^ CC8yCHC register.\n\n - * + * * For the two compare channels it is possible to select either direct ST signal or inverted ST signal. * \b out_path_msk is used to set the required out put path. * @@ -1334,10 +1526,10 @@ void XMC_CCU8_SLICE_StopConfig(XMC_CCU8_SLICE_t *const slice, * \parDescription:
        * Configures the Load Function for the slice, by configuring CC8yCMC.LDS bit.\n\n * Load function is mapped with one of the 3 events. Up on occurrence of the event,\n - * if CC8yTCST.CDIR set to 0,CC8yTIMER register is reloaded with the value from compare channel 1 or + * if CC8yTCST.CDIR set to 0,CC8yTIMER register is reloaded with the value from compare channel 1 or * compare channel 2\n * if CC8yTCST.CDIR set to 1,CC8yTIMER register is reloaded with the value from period register\n - * + * * * \parRelated APIs:
        * XMC_CCU8_SLICE_ConfigureEvent()
        XMC_CCU8_SLICE_SetInput(). @@ -1372,7 +1564,7 @@ void XMC_CCU8_SLICE_LoadSelector(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_S * None
        * * \parDescription:
        - * Configures the Output Modulation Function of the slice, by configuring CC8yCMC.MOS, CC8yTC.EMT and + * Configures the Output Modulation Function of the slice, by configuring CC8yCMC.MOS, CC8yTC.EMT and * CC8yTC.EMS bits.\n\n * Modulation function is mapped with one of the 3 events. The output signal of the CCU can * be modulated according to a external input. Additionally, the behaviour of the slice upon activation @@ -1384,9 +1576,9 @@ void XMC_CCU8_SLICE_LoadSelector(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_S void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_EVENT_t event, const XMC_CCU8_SLICE_MODULATION_MODE_t mod_mode, - const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel, + const XMC_CCU8_SLICE_MODULATION_CHANNEL_t channel, const bool synch_with_pwm - ); + ); /** * @param slice Constant pointer to CC8 Slice @@ -1398,7 +1590,7 @@ void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, * Configures the Count Function of the slice, by configuring CC8yCMC.CNTS bit.\n\n * Count function is mapped with one of the 3 events. CCU8 slice can take an external * signal to act as the counting event. The CCU8 slice would count the - * edges present on the \b event selected. + * edges present on the \b event selected. * * \parRelated APIs:
        * XMC_CCU8_SLICE_ConfigureEvent()
        XMC_CCU8_SLICE_SetInput(). @@ -1464,15 +1656,15 @@ void XMC_CCU8_SLICE_Capture1Config(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8 * Individual capture registers can still be accessed in this mode. * * \parRelated APIs:
        - * XMC_CCU8_GetCapturedValueFromFifo(). + * \if XMC4 XMC_CCU8_GetCapturedValueFromFifo()
        \endif XMC_CCU8_SLICE_GetCapturedValueFromFifo(). */ __STATIC_INLINE bool XMC_CCU8_SLICE_IsExtendedCapReadEnabled(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_IsPrescalerRunning:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((bool)((slice->TC & (uint32_t) CCU8_CC8_TC_ECM_Msk) == (uint32_t)CCU8_CC8_TC_ECM_Msk)); + return ((bool)((slice->TC & (uint32_t) CCU8_CC8_TC_ECM_Msk) == (uint32_t)CCU8_CC8_TC_ECM_Msk)); } -#if defined(CCU8V1) /* Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only */ +#if defined(CCU8V1) || defined(DOXYGEN_XMC4) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */ /** * @param module Constant pointer to CCU8 module * @param slice_number to check whether read value belongs to required slice or not @@ -1483,16 +1675,19 @@ __STATIC_INLINE bool XMC_CCU8_SLICE_IsExtendedCapReadEnabled(const XMC_CCU8_SLIC * * \parDescription:
        * Read captured value from FIFO(ECRD register).\n\n - * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured - * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the - * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be * derived/inferred from the captured values. * * \parRelated APIs:
        * XMC_CCU8_SLICE_IsExtendedCapReadEnabled(). + * @note Only available for XMC4500, XMC4400, XMC4200, XMC4100 series. For other devices use XMC_CCU8_SLICE_GetCapturedValueFromFifo() API. */ int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, const uint8_t slice_number); -#else +#endif + +#if defined(CCU8V2) || defined(CCU8V3) || defined(DOXYGEN) /* Defined for XMC4800, XMC4700, XMC4300, XMC1400, XMC1300 devices only */ /** * @param slice Constant pointer to CC8 Slice * @param set The capture register set from which the captured value is to be retrieved @@ -1502,17 +1697,17 @@ int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, * * \parDescription:
        * Read captured value from FIFO(CC8yECRD0 and CC8yECRD1).\n\n - * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured - * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the - * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be + * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured + * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the + * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be * derived/inferred from the captured values. * * \parRelated APIs:
        * XMC_CCU8_SLICE_IsExtendedCapReadEnabled(). - * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU8_GetCapturedValueFromFifo() API + * \if XMC4 @note Only available for XMC4800, XMC4700, XMC4300 series. For other devices use XMC_CCU8_GetCapturedValueFromFifo() API. \endif */ uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_CAP_REG_SET_t set); + const XMC_CCU8_SLICE_CAP_REG_SET_t set); #endif /** @@ -1523,7 +1718,7 @@ uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const s * * \parDescription:
        * Configures the Count Direction of the slice, by configuring CC8yCMC.UDS bit.\n\n - * Count direction function is mapped with one of the 3 events. A slice can be configured to change the + * Count direction function is mapped with one of the 3 events. A slice can be configured to change the * CC8yTIMER count direction depending on an external signal. * * \parRelated APIs:
        @@ -1586,8 +1781,8 @@ void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, * XMC_CCU8_SLICE_StatusBitOverrideConfig(). */ void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, - const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config); + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config); /** * @param slice Constant pointer to CC8 Slice @@ -1603,9 +1798,9 @@ void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slic * the edge selection, the level selection and the Low pass filter for the event. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_StartConfig()
        XMC_CCU8_SLICE_StopConfig()
        XMC_CCU8_SLICE_LoadConfig()
        - * XMC_CCU8_SLICE_ModulationConfig()
        XMC_CCU8_SLICE_CountConfig()
        XMC_CCU8_SLICE_GateConfig()
        - * XMC_CCU8_SLICE_Capture0Config()
        XMC_CCU8_SLICE_Capture1Config()
        XMC_CCU8_SLICE_DirectionConfig()
        + * XMC_CCU8_SLICE_StartConfig()
        XMC_CCU8_SLICE_StopConfig()
        XMC_CCU8_SLICE_LoadConfig()
        + * XMC_CCU8_SLICE_ModulationConfig()
        XMC_CCU8_SLICE_CountConfig()
        XMC_CCU8_SLICE_GateConfig()
        + * XMC_CCU8_SLICE_Capture0Config()
        XMC_CCU8_SLICE_Capture1Config()
        XMC_CCU8_SLICE_DirectionConfig()
        * XMC_CCU8_SLICE_StatusBitOverrideConfig()
        XMC_CCU8_SLICE_TrapConfig(). */ void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, @@ -1626,9 +1821,9 @@ void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, * This configures the CC8yINS.EVxIS for the selected event. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_StartConfig()
        XMC_CCU8_SLICE_StopConfig()
        XMC_CCU8_SLICE_LoadConfig()
        - * XMC_CCU8_SLICE_ModulationConfig()
        XMC_CCU8_SLICE_CountConfig()
        XMC_CCU8_SLICE_GateConfig()
        - * XMC_CCU8_SLICE_Capture0Config()
        XMC_CCU8_SLICE_Capture1Config()
        XMC_CCU8_SLICE_DirectionConfig()
        + * XMC_CCU8_SLICE_StartConfig()
        XMC_CCU8_SLICE_StopConfig()
        XMC_CCU8_SLICE_LoadConfig()
        + * XMC_CCU8_SLICE_ModulationConfig()
        XMC_CCU8_SLICE_CountConfig()
        XMC_CCU8_SLICE_GateConfig()
        + * XMC_CCU8_SLICE_Capture0Config()
        XMC_CCU8_SLICE_Capture1Config()
        XMC_CCU8_SLICE_DirectionConfig()
        * XMC_CCU8_SLICE_StatusBitOverrideConfig()
        XMC_CCU8_SLICE_TrapConfig(). */ void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, @@ -1651,7 +1846,7 @@ void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, * can be the output of a sensing element which has just detected an abnormal electrical condition. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_TrapConfig()
        XMC_CCU8_SLICE_DisableTrap()
        XMC_CCU8_SLICE_ConfigureEvent()
        + * XMC_CCU8_SLICE_TrapConfig()
        XMC_CCU8_SLICE_DisableTrap()
        XMC_CCU8_SLICE_ConfigureEvent()
        * XMC_CCU8_SLICE_SetInput(). */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableTrap(XMC_CCU8_SLICE_t *const slice, const uint32_t out_mask) @@ -1681,7 +1876,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableTrap(XMC_CCU8_SLICE_t *const slice, co __STATIC_INLINE void XMC_CCU8_SLICE_DisableTrap(XMC_CCU8_SLICE_t *const slice, const uint32_t out_mask) { XMC_ASSERT("XMC_CCU8_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - + slice->TC &= ~((uint32_t)out_mask << CCU8_CC8_TC_TRAPE0_Pos); } @@ -1699,7 +1894,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_DisableTrap(XMC_CCU8_SLICE_t *const slice, c __STATIC_INLINE bool XMC_CCU8_SLICE_IsTimerRunning(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return(bool)(((slice->TCST) & CCU8_CC8_TCST_TRB_Msk) == (uint32_t)CCU8_CC8_TCST_TRB_Msk); + return (bool)(((slice->TCST) & CCU8_CC8_TCST_TRB_Msk) == (uint32_t)CCU8_CC8_TCST_TRB_Msk); } /** @@ -1717,7 +1912,7 @@ __STATIC_INLINE bool XMC_CCU8_SLICE_IsTimerRunning(const XMC_CCU8_SLICE_t *const __STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr1Running(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_IsDeadTimeCntr1Running:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return(bool)(((slice->TCST) & CCU8_CC8_TCST_DTR1_Msk) == (uint32_t)CCU8_CC8_TCST_DTR1_Msk); + return (bool)(((slice->TCST) & CCU8_CC8_TCST_DTR1_Msk) == (uint32_t)CCU8_CC8_TCST_DTR1_Msk); } /** @@ -1735,7 +1930,7 @@ __STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr1Running(const XMC_CCU8_SLICE_ __STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr2Running(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_IsDeadTimeCntr2Running:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return(bool)(((slice->TCST) & CCU8_CC8_TCST_DTR2_Msk) == (uint32_t)CCU8_CC8_TCST_DTR2_Msk); + return (bool)(((slice->TCST) & CCU8_CC8_TCST_DTR2_Msk) == (uint32_t)CCU8_CC8_TCST_DTR2_Msk); } /** @@ -1754,7 +1949,7 @@ __STATIC_INLINE bool XMC_CCU8_SLICE_IsDeadTimeCntr2Running(const XMC_CCU8_SLICE_ __STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_DIR_t XMC_CCU8_SLICE_GetCountingDir(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((XMC_CCU8_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU8_CC8_TCST_CDIR_Msk) >> CCU8_CC8_TCST_CDIR_Pos)); + return ((XMC_CCU8_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU8_CC8_TCST_CDIR_Msk) >> CCU8_CC8_TCST_CDIR_Pos)); } /** * @param slice Constant pointer to CC8 Slice @@ -1836,7 +2031,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_StopClearTimer(XMC_CCU8_SLICE_t *const slice * returns XMC_CCU8_SLICE_MODE_CAPTURE if the slice is operating in capture mode * * \parDescription:
        - * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading + * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading * CC8yTC.CMOD bit.\n\n * Ensure that before invoking this API the CCU8 slice should be configured otherwise the output of this API is * invalid. @@ -1847,7 +2042,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_StopClearTimer(XMC_CCU8_SLICE_t *const slice __STATIC_INLINE XMC_CCU8_SLICE_MODE_t XMC_CCU8_SLICE_GetSliceMode(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((XMC_CCU8_SLICE_MODE_t)(((slice->TC) & CCU8_CC8_TC_CMOD_Msk) >> CCU8_CC8_TC_CMOD_Pos)); + return ((XMC_CCU8_SLICE_MODE_t)(((slice->TC) & CCU8_CC8_TC_CMOD_Msk) >> CCU8_CC8_TC_CMOD_Pos)); } /** @@ -1883,10 +2078,10 @@ void XMC_CCU8_SLICE_SetTimerRepeatMode(XMC_CCU8_SLICE_t *const slice, const XMC_ * XMC_CCU8_SLICE_SetTimerRepeatMode(). */ __STATIC_INLINE XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t XMC_CCU8_SLICE_GetTimerRepeatMode( - const XMC_CCU8_SLICE_t *const slice) + const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TSSM_Msk) >> CCU8_CC8_TC_TSSM_Pos)); + return ((XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TSSM_Msk) >> CCU8_CC8_TC_TSSM_Pos)); } /** * @param slice Constant pointer to CC8 Slice @@ -1899,7 +2094,7 @@ __STATIC_INLINE XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t XMC_CCU8_SLICE_GetTimerRepeat * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0. - * During this upward and downward counting, the timer status output stays asserted as long as the timer value is + * During this upward and downward counting, the timer status output stays asserted as long as the timer value is * greater than the compare value. * * \parRelated APIs:
        @@ -1920,10 +2115,10 @@ void XMC_CCU8_SLICE_SetTimerCountingMode(XMC_CCU8_SLICE_t *const slice, const XM * XMC_CCU8_SLICE_SetTimerCountingMode(). */ __STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_MODE_t XMC_CCU8_SLICE_GetTimerCountingMode( - const XMC_CCU8_SLICE_t *const slice) + const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((XMC_CCU8_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TCM_Msk) >> CCU8_CC8_TC_TCM_Pos)); + return ((XMC_CCU8_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU8_CC8_TC_TCM_Msk) >> CCU8_CC8_TC_TCM_Pos)); } /** * @param slice Constant pointer to CC8 Slice @@ -1934,7 +2129,7 @@ __STATIC_INLINE XMC_CCU8_SLICE_TIMER_COUNT_MODE_t XMC_CCU8_SLICE_GetTimerCountin * * \parDescription:
        * Programs the timer period, by writing CC8yPRS register.\n\n - * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow + * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow * register. Explicitly enable the shadow transfer for the the period value by calling * XMC_CCU8_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running, * a period match transfers the value from the shadow register to the actual period register. @@ -1966,7 +2161,7 @@ void XMC_CCU8_SLICE_SetTimerPeriodMatch(XMC_CCU8_SLICE_t *const slice, const uin __STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerPeriodMatch(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((uint16_t) slice->PR); + return ((uint16_t) slice->PR); } /** * @param slice Constant pointer to CC8 Slice @@ -1987,8 +2182,8 @@ __STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerPeriodMatch(const XMC_CCU8_SLICE * XMC_CCU8_EnableShadowTransfer(). */ void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, - const uint16_t compare_val); + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint16_t compare_val); /** * @param slice Constant pointer to CC8 Slice @@ -2057,7 +2252,41 @@ __STATIC_INLINE void XMC_CCU8_SLICE_SetTimerCompareMatchChannel2(XMC_CCU8_SLICE_ * XMC_CCU8_SLICE_SetTimerCompareMatch(). */ uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel); + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel); + +/** + * @param slice Constant pointer to CC8 Slice + * @return + * uint16_t Timer compare value + * + * \parDescription:
        + * Gets the timer compare1 value, by reading CC8yCR1 register.\n\n + * + * \parRelated APIs:
        + * XMC_CCU8_SLICE_SetTimerCompareMatchChannel1(). + */ +__STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerCompareMatchChannel1(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_GetTimerCompareMatchChannel1:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return slice->CR1; +} + +/** + * @param slice Constant pointer to CC8 Slice + * @return Timer compare value + * uint16_t Timer compare value + * + * \parDescription:
        + * Gets the timer compare1 value, by reading CC8yCR2 register.\n\n + * + * \parRelated APIs:
        + * XMC_CCU8_SLICE_SetTimerCompareMatchChannel2(). + */ +__STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerCompareMatchChannel2(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatchChannel2:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + return slice->CR2; +} /** * @param module Constant pointer to CCU8 module @@ -2068,13 +2297,12 @@ uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice * None
        * * \parDescription:
        - * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring + * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring * the GCSS register.\n\n * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the - * shadow transfer trigger after the API is called. - * - * Any call to XMC_CCU8_SLICE_SetTimerPeriodMatch()
        XMC_CCU8_SLICE_SetTimerCompareMatch()
        - * XMC_XMC_CCU8_SLICE_SetPrescaler()
        XMC_CCU8_SLICE_CompareInit()
        XMC_CCU8_SLICE_CaptureInit(). + * shadow transfer trigger after the API is called.\n\n + * Any call to XMC_CCU8_SLICE_SetTimerPeriodMatch(), XMC_CCU8_SLICE_SetTimerCompareMatch(), + * XMC_CCU8_SLICE_SetPrescaler(), XMC_CCU8_SLICE_CompareInit(), XMC_CCU8_SLICE_CaptureInit() * must be succeeded by this API. * * \parRelated APIs:
        @@ -2083,7 +2311,7 @@ uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice __STATIC_INLINE void XMC_CCU8_EnableShadowTransfer(XMC_CCU8_MODULE_t *const module, const uint32_t shadow_transfer_msk) { XMC_ASSERT("XMC_CCU8_EnableShadowTransfer:Invalid module Pointer", XMC_CCU8_IsValidModule(module)); - module->GCSS = (uint32_t)shadow_transfer_msk; + module->GCSS = (uint32_t)shadow_transfer_msk; } /** @@ -2101,7 +2329,7 @@ __STATIC_INLINE void XMC_CCU8_EnableShadowTransfer(XMC_CCU8_MODULE_t *const modu __STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerValue(const XMC_CCU8_SLICE_t *const slice) { XMC_ASSERT("XMC_CCU8_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - return((uint16_t) slice->TIMER); + return ((uint16_t) slice->TIMER); } /** * @param slice Constant pointer to CC8 Slice @@ -2112,7 +2340,7 @@ __STATIC_INLINE uint16_t XMC_CCU8_SLICE_GetTimerValue(const XMC_CCU8_SLICE_t *co * * \parDescription:
        * Loads a new timer value, by setting CC8yTIMER register.\n\n - * + * * \parNote:
        * Request to load is ignored if the timer is running. * @@ -2137,8 +2365,8 @@ __STATIC_INLINE void XMC_CCU8_SLICE_SetTimerValue(XMC_CCU8_SLICE_t *const slice, * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering * can help reduce long term errors. Dithering can be applied to period and duty individually, * this can be selected using the parameter \b period_dither and \b duty_dither. - * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then - * the period/compare values would be dithered according to the dither mode selected. This API would invoke + * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then + * the period/compare values would be dithered according to the dither mode selected. This API would invoke * XMC_CCU8_SLICE_SetDitherCompareValue(). * * \parNote:
        @@ -2184,8 +2412,8 @@ __STATIC_INLINE void XMC_CCU8_SLICE_DisableDithering(XMC_CCU8_SLICE_t *const sli * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue()
        XMC_CCU8_SLICE_DisableFloatingPrescaler()
        - * XMC_XMC_CCU8_SLICE_SetPrescaler(). + * XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue()
        XMC_CCU8_SLICE_DisableFloatingPrescaler()
        + * XMC_CCU8_SLICE_SetPrescaler(). */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableFloatingPrescaler(XMC_CCU8_SLICE_t *const slice) { @@ -2254,6 +2482,25 @@ __STATIC_INLINE void XMC_CCU8_SLICE_SetDitherCompareValue(XMC_CCU8_SLICE_t *cons */ void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_PRESCALER_t div_val); +/** + * @param slice Constant pointer to CC8 Slice + * @return
        + * XMC_CCU8_SLICE_PRESCALER_t Prescaler divider value.
        + * + * \parDescription:
        + * Returns current prescaler value.\n\n + * Used to detrmine the clock frequency of the CCU8 slice XMC_SCU_CLOCK_GetCcuClockFrequency() / XMC_CCU8_SLICE_GetPrescaler() + * + * \parRelated APIs:
        + * XMC_CCU8_SLICE_SetPrescaler(). + */ +__STATIC_INLINE XMC_CCU8_SLICE_PRESCALER_t XMC_CCU8_SLICE_GetPrescaler(XMC_CCU8_SLICE_t *const slice) +{ + XMC_ASSERT("XMC_CCU8_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + + return (XMC_CCU8_SLICE_PRESCALER_t)slice->PSC; +} + /** * @param slice Constant pointer to CC8 Slice * @param cmp_val Prescaler divider compare value @@ -2265,14 +2512,14 @@ void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_S * Programs the slice specific prescaler divider compare value, by configuring CC8yFPCS register.\n\n * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial * value and increments to the compare value steadily upon every period match. Once prescaler divider - * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting + * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting * the value, XMC_CCU8_EnableShadowTransfer() has to be called with appropriate mask. * * \parRelated APIs:
        * XMC_CCU8_SLICE_SetPrescaler(). */ __STATIC_INLINE void XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU8_SLICE_t *const slice, - const uint8_t cmp_val) + const uint8_t cmp_val) { XMC_ASSERT("XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); /* First, write to the shadow register */ @@ -2297,7 +2544,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU8_SL * XMC_CCU8_SLICE_DisableMultiChannelMode()
        XMC_CCU8_SetMultiChannelShadowTransferMode(). */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableMultiChannelMode(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) { XMC_ASSERT("XMC_CCU8_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_EnableMultiChannelMode:Invalid Channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); @@ -2320,7 +2567,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableMultiChannelMode(XMC_CCU8_SLICE_t *con * XMC_CCU8_SLICE_EnableMultiChannelMode(). */ __STATIC_INLINE void XMC_CCU8_SLICE_DisableMultiChannelMode(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t ch_num) { XMC_ASSERT("XMC_CCU8_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_DisableMultiChannelMode:Invalid Channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(ch_num)); @@ -2337,7 +2584,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_DisableMultiChannelMode(XMC_CCU8_SLICE_t *co * None
        * * \parDescription:
        - * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring + * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n * The shadow transfer would take place either if it was requested by software or by the CCU8x.MCSS input. * @@ -2356,9 +2603,9 @@ void XMC_CCU8_SetMultiChannelShadowTransferMode(XMC_CCU8_MODULE_t *const module, * * \parDescription:
        * Retrieves timer value which has been captured in the Capture registers, by reading CC8yCV[\b reg_num] register.\n\n - * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped + * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing - * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help + * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help * to find out if there is a new captured value present. * * \parRelated APIs:
        @@ -2386,8 +2633,8 @@ uint32_t XMC_CCU8_SLICE_GetCaptureRegisterValue(const XMC_CCU8_SLICE_t *const sl * XMC_CCU8_SLICE_GetCaptureregisterValue(). */ XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_CAP_REG_SET_t set, - uint32_t *val_ptr); + const XMC_CCU8_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr); /** * @param slice Constant pointer to CC8 Slice @@ -2401,7 +2648,7 @@ XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_ * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableMultipleEvents()
        XMC_CCU8_SLICE_DisableEvent()
        + * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableMultipleEvents()
        XMC_CCU8_SLICE_DisableEvent()
        * XMC_CCU8_SLICE_DisableMultipleEvents(). */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) @@ -2426,7 +2673,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableEvent(XMC_CCU8_SLICE_t *const slice, c * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableEvent()
        XMC_CCU8_SLICE_DisableEvent()
        + * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableEvent()
        XMC_CCU8_SLICE_DisableEvent()
        * XMC_CCU8_SLICE_DisableMultipleEvents(). */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableMultipleEvents(XMC_CCU8_SLICE_t *const slice, const uint16_t mask) @@ -2446,7 +2693,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableMultipleEvents(XMC_CCU8_SLICE_t *const * Prevents the event from being asserted. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableEvent()
        XMC_CCU8_SLICE_EnableMultipleEvents()
        + * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableEvent()
        XMC_CCU8_SLICE_EnableMultipleEvents()
        * XMC_CCU8_SLICE_DisableMultipleEvents(). */ __STATIC_INLINE void XMC_CCU8_SLICE_DisableEvent(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_IRQ_ID_t event) @@ -2470,7 +2717,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_DisableEvent(XMC_CCU8_SLICE_t *const slice, * Prevents selected events of the slice from being asserted. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableEvent()
        XMC_CCU8_SLICE_EnableMultipleEvents()
        + * XMC_CCU8_SLICE_SetInterruptNode()
        XMC_CCU8_SLICE_EnableEvent()
        XMC_CCU8_SLICE_EnableMultipleEvents()
        * XMC_CCU8_SLICE_DisableEvent(). */ __STATIC_INLINE void XMC_CCU8_SLICE_DisableMultipleEvents(XMC_CCU8_SLICE_t *const slice, const uint16_t mask) @@ -2498,7 +2745,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_SetEvent(XMC_CCU8_SLICE_t *const slice, cons XMC_ASSERT("XMC_CCU8_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_SetEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); - slice->SWS |= ((uint32_t) 1) << ((uint32_t) event); + slice->SWS = ((uint32_t) 1) << ((uint32_t) event); } /** @@ -2518,7 +2765,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_ClearEvent(XMC_CCU8_SLICE_t *const slice, co { XMC_ASSERT("XMC_CCU8_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_ClearEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); - slice->SWR |= ((uint32_t) 1) << ((uint32_t) event); + slice->SWR = ((uint32_t) 1) << ((uint32_t) event); } /** @@ -2540,8 +2787,8 @@ __STATIC_INLINE bool XMC_CCU8_SLICE_GetEvent(const XMC_CCU8_SLICE_t *const slice { XMC_ASSERT("XMC_CCU8_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_GetEvent:Invalid SR event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); - return(((uint32_t)(slice->INTS & ((uint32_t)1 << event))) != 0U); - } + return (((uint32_t)(slice->INTS & ((uint32_t)1 << event))) != 0U); +} /** * @param slice Constant pointer to CC8 Slice @@ -2595,7 +2842,7 @@ void XMC_CCU8_SLICE_SetPassiveLevel(XMC_CCU8_SLICE_t *const slice, * programmed by this routine. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_ConfigureDeadTime()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_SetDeadTimePrescaler()
        + * XMC_CCU8_SLICE_ConfigureDeadTime()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_SetDeadTimePrescaler()
        * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
        XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). */ void XMC_CCU8_SLICE_DeadTimeInit(XMC_CCU8_SLICE_t *const slice, @@ -2619,7 +2866,7 @@ void XMC_CCU8_SLICE_DeadTimeInit(XMC_CCU8_SLICE_t *const slice, * External count direction function is enabled then the asymmetric mode of operation is not possible. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_EnableSymmetricCompareMode()
        + * XMC_CCU8_SLICE_EnableSymmetricCompareMode()
        */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableAsymmetricCompareMode(XMC_CCU8_SLICE_t *const slice) { @@ -2659,7 +2906,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableSymmetricCompareMode(XMC_CCU8_SLICE_t * Range: [0x0 to 0x3F] * * \parDescription:
        - * Activates or deactivates dead time for compare channel and ST path, by configuring CC8y.DC1R, CC8y.DC1R and + * Activates or deactivates dead time for compare channel and ST path, by configuring CC8y.DC1R, CC8y.DC1R and * CC8y.DTC registers.\n\n * Use the provided masks to enable/disable the dead time for the compare channels and the ST signals. It is possible * to deactivate the dead time for all the options by passing a 0x0 as the mask. @@ -2667,7 +2914,7 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableSymmetricCompareMode(XMC_CCU8_SLICE_t * programmed by this routine. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_DeadTimeInit()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_SetDeadTimePrescaler()
        + * XMC_CCU8_SLICE_DeadTimeInit()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_SetDeadTimePrescaler()
        * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
        XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). */ void XMC_CCU8_SLICE_ConfigureDeadTime(XMC_CCU8_SLICE_t *const slice, const uint8_t mask); @@ -2688,7 +2935,7 @@ void XMC_CCU8_SLICE_ConfigureDeadTime(XMC_CCU8_SLICE_t *const slice, const uint8 * value changes from 1 to 0(falling edge). Directly accessed registers are CC8yDC1R, CC8yDC2R. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_DeadTimeInit()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_ConfigureDeadTime()
        + * XMC_CCU8_SLICE_DeadTimeInit()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_ConfigureDeadTime()
        * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
        XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). */ void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, @@ -2703,12 +2950,12 @@ void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, * None
        * * \parDescription:
        - * Configures clock division factor for dead time generator, by configuring CC8yDTC.DTCC bit. - * The Clock divider works on the timer clock. It is possible to scale the timer clock for the dead time + * Configures clock division factor for dead time generator, by configuring CC8yDTC.DTCC bit. + * The Clock divider works on the timer clock. It is possible to scale the timer clock for the dead time * generator by a factor of 1/2/4/8. This selection is passed as an argument to the API. * * \parRelated APIs:
        - * XMC_CCU8_SLICE_DeadTimeInit()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_ConfigureDeadTime()
        + * XMC_CCU8_SLICE_DeadTimeInit()
        XMC_CCU8_SLICE_SetDeadTimeValue()
        XMC_CCU8_SLICE_ConfigureDeadTime()
        * XMC_CCU8_SLICE_IsDeadTimeCntr1Running()
        XMC_CCU8_SLICE_IsDeadTimeCntr2Running(). */ void XMC_CCU8_SLICE_SetDeadTimePrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_DTC_DIV_t div_val); @@ -2740,17 +2987,17 @@ void XMC_CCU8_SLICE_ConfigureStatusBitOutput(XMC_CCU8_SLICE_t *const slice, cons * Cascades the shadow transfer operation throughout the CCU8 timer slices, by setting CSE bit in STC register.\n\n * * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture, - * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of - * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC80 slice is a + * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of + * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC80 slice is a * master to start the operation. - * + * * \parNote:
        * XMC_CCU8_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be * cascaded. - * + * * \parRelated APIs:
        * XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_DisableCascadedShadowTransfer()
        . - * @note Not available for XMC4500 series + * \if XMC4 @note Not available for XMC4500 series \endif */ __STATIC_INLINE void XMC_CCU8_SLICE_EnableCascadedShadowTransfer(XMC_CCU8_SLICE_t *const slice) { @@ -2768,10 +3015,10 @@ __STATIC_INLINE void XMC_CCU8_SLICE_EnableCascadedShadowTransfer(XMC_CCU8_SLICE_ * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n * * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode. - * + * * \parRelated APIs:
        * XMC_CCU8_SLICE_EnableCascadedShadowTransfer()
        . - * @note Not available for XMC4500 series + * \if XMC4 @note Not available for XMC4500 series \endif */ __STATIC_INLINE void XMC_CCU8_SLICE_DisableCascadedShadowTransfer(XMC_CCU8_SLICE_t *const slice) { @@ -2788,143 +3035,160 @@ __STATIC_INLINE void XMC_CCU8_SLICE_DisableCascadedShadowTransfer(XMC_CCU8_SLICE * * \parDescription:
        * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n - * + * * After requesting for shadow transfer mode using XMC_CCU8_EnableShadowTransfer(), actual transfer occurs based on the - * selection done using this API (i.e. on period and One match, on Period match only, on One match only). + * selection done using this API (i.e. on period and One match, on Period match only, on One match only). * * \parNote:
        * This is effective when the timer is configured in centre aligned mode. - * + * * \parRelated APIs:
        * XMC_CCU8_EnableShadowTransfer()
        - * @note Not available for XMC4500 series + * \if XMC4 @note Not available for XMC4500 series \endif */ __STATIC_INLINE void XMC_CCU8_SLICE_SetShadowTransferMode(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) + const XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode) { XMC_ASSERT("XMC_CCU8_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - slice->STC = ((slice->STC) & ~(uint32_t)((uint32_t)CCU8_CC8_STC_STM_Msk << (uint32_t)CCU8_CC8_STC_STM_Pos)) | + slice->STC = ((slice->STC) & (uint32_t)~CCU8_CC8_STC_STM_Msk) | ((shadow_transfer_mode << CCU8_CC8_STC_STM_Pos) & (uint32_t)CCU8_CC8_STC_STM_Msk); } #endif -#if defined(CCU8V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */ - /** - * @param slice Constant pointer to CC8 Slice - * @param immediate_write specifies for what fields this mode has to be applied - * Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting - * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n - * - * When immediate shadow is enabled, by calling XMC_CCU8_EnableShadowTransfer() the value which are written in the - * shadow registers get updated to the actual registers immediately. \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU8_EnableShadowTransfer()
        - * @note Only available for XMC1400 series - */ +#if defined(CCU8V3) || defined(DOXYGEN_XMC1)/* Defined for XMC1400 devices only */ +/** +* @param slice Constant pointer to CC8 Slice +* @param immediate_write specifies for what fields this mode has to be applied +* Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting +* IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n +* +* When immediate shadow is enabled, by calling XMC_CCU8_EnableShadowTransfer() the value which are written in the +* shadow registers get updated to the actual registers immediately. \parNote:
        +* +* \parRelated APIs:
        +* XMC_CCU8_EnableShadowTransfer()
        +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU8_SLICE_t *const slice, - const uint32_t immediate_write) + const uint32_t immediate_write) { - XMC_ASSERT("XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); + XMC_ASSERT("XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); slice->STC |= immediate_write; } - /** - * @param slice Constant pointer to CC8 Slice - * @param coherent_write specifies for what fields this mode has to be applied - * Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by - * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n - * - * When coherent shadow is enabled, after calling XMC_CCU8_EnableShadowTransfer(), the value which are written in the - * respective shadow registers get updated according the configuration done using XMC_CCU8_SLICE_SetShadowTransferMode() - * API. \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_SetShadowTransferMode()
        - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC8 Slice +* @param coherent_write specifies for what fields this mode has to be applied +* Use :: XMC_CCU8_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by +* clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n +* +* When coherent shadow is enabled, after calling XMC_CCU8_EnableShadowTransfer(), the value which are written in the +* respective shadow registers get updated according the configuration done using XMC_CCU8_SLICE_SetShadowTransferMode() +* API. \parNote:
        +* +* \parRelated APIs:
        +* XMC_CCU8_EnableShadowTransfer(), XMC_CCU8_SLICE_SetShadowTransferMode()
        +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU8_SLICE_t *const slice, - const uint32_t coherent_write) + const uint32_t coherent_write) { XMC_ASSERT("XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); slice->STC &= ~(uint32_t)coherent_write; } - /** - * @param slice Constant pointer to CC8 Slice - * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated - * Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a - * bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting - * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n - * - * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. - * \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(). - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC8 Slice +* @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated +* Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a +* bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting +* ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n +* +* By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers. +* \parNote:
        +* Automatic shadow transfer feature does not work when system PCLK is faster than MCLK. +* +* \parRelated APIs:
        +* XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(). +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU8_SLICE_t *const slice, - const uint32_t automatic_shadow_transfer) + const uint32_t automatic_shadow_transfer) { XMC_ASSERT("XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); slice->STC |= automatic_shadow_transfer; } - /** - * @param slice Constant pointer to CC8 Slice - * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be - * generated - * Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a - * bit wise OR operation. - * @return
        - * None
        - * - * \parDescription:
        - * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By - * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n - * - * This disables the generation of automatic shadow transfer request for the specified register update. - * \parNote:
        - * - * \parRelated APIs:
        - * XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(). - * @note Only available for XMC1400 series - */ +/** +* @param slice Constant pointer to CC8 Slice +* @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be +* generated +* Use :: XMC_CCU8_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a +* bit wise OR operation. +* @return
        +* None
        +* +* \parDescription:
        +* Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By +* clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n +* +* This disables the generation of automatic shadow transfer request for the specified register update. +* \parNote:
        +* +* \parRelated APIs:
        +* XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest(). +* @note Only available for XMC1400 series +*/ __STATIC_INLINE void XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU8_SLICE_t *const slice, - const uint32_t automatic_shadow_transfer) + const uint32_t automatic_shadow_transfer) { XMC_ASSERT("XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); slice->STC &= ~(uint32_t)automatic_shadow_transfer; } #endif + +/** + * @param module Constant pointer to CCU8 module + * @param slice_number Slice for which the clock should be disabled. + * Range: [0x0 to 0x3] + * @param channel Select which compare channel + * + * @return status bit of slice passive (false) or active (true) + * + * \parDescription:
        + * Returns CCU4 slice status bit (passive or active) + * + */ +__STATIC_INLINE XMC_CCU8_SLICE_STATUS_BIT_t XMC_CCU8_GetSliceStatusBit(XMC_CCU8_MODULE_t *const module, uint8_t slice_number, XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel) +{ + return (XMC_CCU8_SLICE_STATUS_BIT_t)((module->GCST & ((CCU8_GCST_CC80ST1_Msk << slice_number) << (channel * CCU8_GCST_CC80ST2_Pos))) ? 1 : 0); +} + + #ifdef __cplusplus } #endif - -/** - * @} - */ /** * @} */ + #endif /* defined(CCU80) */ #endif /* XMC_CCU8_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_common.h b/cores/xmc_lib/XMCLib/inc/xmc_common.h index dafc9585..782ef164 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_common.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_common.h @@ -1,68 +1,43 @@ /** * @file xmc_common.h - * @date 2017-08-03 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial - * - Brief section updated - * - Added XMC_LIB_VERSION macro + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2016-02-26: - * - Updated XMC_LIB_VERSION macro to v2.1.6 - * - * 2016-05-30: - * - Updated XMC_LIB_VERSION macro to v2.1.8 + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-11-18: - * - Updated XMC_LIB_VERSION macro to v2.1.10 - * - Changed type of size in XMC_PRIOARRAY_t to fix compilation warnings + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2017-04-04: - * - Updated XMC_LIB_VERSION macro to v2.1.12 - * - * 2017-06-24: - * - Updated XMC_LIB_VERSION macro to v2.1.14 - * - * 2017-08-03: - * - Updated XMC_LIB_VERSION macro to v2.1.16 - * - Added __RAM_FUNC macro - * - * @endcond + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * + * @endcond */ #ifndef XMC_COMMON_H @@ -70,35 +45,39 @@ #include #include +#include #include #include #include "xmc_device.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup COMMON - * @brief Common APIs to all peripherals for XMC microcontroller family + * @brief Common APIs to all peripherals for XMC microcontroller family + + * The Common driver contains a set of different system functions. These functions + * can be called in the application routine. * @{ */ /********************************************************************************************************************** * MACROS *********************************************************************************************************************/ -#define XMC_LIB_MAJOR_VERSION (2U) -#define XMC_LIB_MINOR_VERSION (1U) -#define XMC_LIB_PATCH_VERSION (16U) - +#define XMC_LIB_MAJOR_VERSION (4U) +#define XMC_LIB_MINOR_VERSION (3U) +#define XMC_LIB_PATCH_VERSION (0U) + #define XMC_LIB_VERSION ((XMC_LIB_MAJOR_VERSION << 16U) + (XMC_LIB_MINOR_VERSION << 8U) + XMC_LIB_PATCH_VERSION) +#define XMC_VERSION_NUMBER(major, minor, patch) ((major << 16U) + (minor << 8U) + patch) + /* Define WEAK attribute */ #if !defined(__WEAK) #if defined ( __CC_ARM ) #define __WEAK __attribute__ ((weak)) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __WEAK __attribute__ ((weak)) #elif defined ( __ICCARM__ ) #define __WEAK __weak #elif defined ( __GNUC__ ) @@ -112,6 +91,8 @@ #if defined ( __CC_ARM ) // http://www.keil.com/support/docs/3723.htm #define __RAM_FUNC __attribute__((section("RAMCODESECTION"))) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __RAM_FUNC __attribute__((section("RAMCODESECTION"))) #elif defined ( __ICCARM__ ) // https://www.iar.com/support/tech-notes/linker/controlling-placement-of-the-section-where-__ramfunc-functions-reside-ewarm-5.x--6.x/ #define __RAM_FUNC __ramfunc @@ -123,65 +104,56 @@ #endif #ifdef XMC_ASSERT_ENABLE - #define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} } +#define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} } #else - #define XMC_ASSERT(msg, exp) { ; } +#define XMC_ASSERT(msg, exp) #endif #ifdef XMC_DEBUG_ENABLE - #include - #define XMC_DEBUG(...) { printf(__VA_ARGS__); } +#include +#define XMC_DEBUG(...) { printf(__VA_ARGS__); } #else - #define XMC_DEBUG(...) { ; } +#define XMC_DEBUG(...) #endif #define XMC_UNUSED_ARG(x) (void)x #define XMC_STRUCT_INIT(m) memset(&m, 0, sizeof(m)) -#define XMC_PRIOARRAY_DEF(name, size) \ -XMC_PRIOARRAY_ITEM_t prioarray_m_##name[size + 2]; \ -XMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)}; +/*************************************************************************************************** + * Macro Name: XMC_DIV_ROUND + ***********************************************************************************************//** + * + * Calculates a / b with rounding to the nearest integer, + * a and b must have the same sign. + * + **************************************************************************************************/ +#define XMC_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) -#define XMC_PRIOARRAY(name) \ -&prioarray_def_##name +/*************************************************************************************************** + * Macro Name: XMC_DIV_ROUNDUP + ***********************************************************************************************//** + * + * Calculates a / b with rounding up if remainder != 0, + * both a and b must be positive. + * + **************************************************************************************************/ +#define XMC_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) +/** @cond */ /********************************************************************************************************************** * DATA STRUCTURES *********************************************************************************************************************/ /* * */ -typedef struct XMC_DRIVER_VERSION +typedef struct XMC_DRIVER_VERSION { uint8_t major; uint8_t minor; uint8_t patch; } XMC_DRIVER_VERSION_t; - -/* - * - */ -typedef void *XMC_LIST_t; - -/* - * - */ -typedef struct XMC_PRIOARRAY_ITEM -{ - int32_t priority; - int32_t previous; - int32_t next; -} XMC_PRIOARRAY_ITEM_t; - -/* - * - */ -typedef struct XMC_PRIOARRAY -{ - int32_t size; - XMC_PRIOARRAY_ITEM_t *items; -} XMC_PRIOARRAY_t; +/** @endcond */ /********************************************************************************************************************** * API PROTOTYPES @@ -196,111 +168,95 @@ extern "C" { */ void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line); -/* - * - */ -void XMC_LIST_Init(XMC_LIST_t *list); - -/* - * - */ -void XMC_LIST_Add(XMC_LIST_t *list, void *const item); - -/* - * - */ -void XMC_LIST_Remove(XMC_LIST_t *list, void *const item); - -/* - * - */ -uint32_t XMC_LIST_GetLength(XMC_LIST_t *list); - -/* - * - */ -void *XMC_LIST_GetHead(XMC_LIST_t *list); - -/* - * - */ -void *XMC_LIST_GetTail(XMC_LIST_t *list); - -/* - * - */ -void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item); - -/* - * - */ -void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray); - -/* - * - */ -void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority); - -/* - * - */ -void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item); - -/* - * - */ -__STATIC_INLINE int32_t XMC_PRIOARRAY_GetHead(XMC_PRIOARRAY_t *prioarray) -{ - XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); - return prioarray->items[prioarray->size].next; -} - -/* - * - */ -__STATIC_INLINE int32_t XMC_PRIOARRAY_GetTail(XMC_PRIOARRAY_t *prioarray) -{ - XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); - return prioarray->items[prioarray->size + 1].previous; -} - -/* - * - */ -__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPriority(XMC_PRIOARRAY_t *prioarray, int32_t item) -{ - XMC_ASSERT("XMC_PRIOARRAY_GetItemPriority: item out of range", (item >= 0) && (item < prioarray->size)); - return prioarray->items[item].priority; -} - -/* - * - */ -__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemNext(XMC_PRIOARRAY_t *prioarray, int32_t item) -{ - XMC_ASSERT("XMC_PRIOARRAY_GetItemNext: item out of range", (item >= 0) && (item < prioarray->size)); - return prioarray->items[item].next; -} - -/* - * - */ -__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPrevious(XMC_PRIOARRAY_t *prioarray, int32_t item) -{ - XMC_ASSERT("XMC_PRIOARRAY_GetItemPrevious: item out of range", (item >= 0) && (item < prioarray->size)); - return prioarray->items[item].previous; -} +/******************************************************************************* +* Function Name: XMC_DelayCycles +****************************************************************************//** +* +* The function delays by the specified number of CPU clock cycles. +* +* \note There is memory reading timing limitation in XMC1xxx device family +* (see section Memory Read in the device TRM) +* this may significantly stretch this function execution, +* especially at high CPU speeds. +* +* @param cycles The number of CPU clock cycles to delay. +* Valid range: 0x0 .. 0xFFFFFFFD. +* +*******************************************************************************/ +void XMC_DelayCycles(uint32_t cycles); + +/******************************************************************************* +* Function Name: XMC_Delay +****************************************************************************//** +* +* The function delays by the specified number of milliseconds. +* The number of cycles to delay is calculated based on the +* \ref SystemCoreClock. +* +* @param milliseconds The number of milliseconds to delay. +* +* \note The function calls \ref XMC_DelayCycles() API to generate a delay. +* If the desired delay is bigger than 0xFFFFFFFD CPU cycles, +* then an additional loop runs to prevent +* an overflow in parameter passed to \ref XMC_DelayCycles() API. +* +*******************************************************************************/ +void XMC_Delay(uint32_t milliseconds); + +/******************************************************************************* +* Function Name: XMC_DelayUs +****************************************************************************//** +* +* The function delays by the specified number of microseconds. +* The number of cycles to delay is calculated based on the +* \ref SystemCoreClock. +* +* @param microseconds The number of microseconds to delay. +* +* \note If the CPU frequency in MHz is a small number, +* the actual delay can be significantly bigger than the desired value. +* The actual delay cannot be shorter than the desired one. +* +*******************************************************************************/ +void XMC_DelayUs(uint16_t microseconds); + +/******************************************************************************* +* Function Name: XMC_EnterCriticalSection +****************************************************************************//** +* +* XMC_EnterCriticalSection disables interrupts and returns a value +* indicating whether the interrupts were previously enabled. +* +* \return Returns the current interrupt status. Returns 0 if the interrupts +* were previously enabled or 1 if the interrupts were previously +* disabled. +* +* \note Implementation of XMC_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +*******************************************************************************/ +uint32_t XMC_EnterCriticalSection(void); + +/******************************************************************************* +* Function Name: XMC_ExitCriticalSection +****************************************************************************//** +* +* Re-enables the interrupts if they were enabled before +* XMC_EnterCriticalSection() was called. The argument should be the value +* returned from \ref XMC_EnterCriticalSection(). +* +* \param savedIntrStatus Puts the saved interrupts status returned by +* the \ref XMC_EnterCriticalSection(). +* +*******************************************************************************/ +void XMC_ExitCriticalSection(uint32_t savedIntrStatus); #ifdef __cplusplus } #endif /** - * @} - */ - -/** - * @} + * @} (end addtogroup COMMON) */ #endif /* XMC_COMMON_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dac.h b/cores/xmc_lib/XMCLib/inc/xmc_dac.h index 6d479b7e..8eff4142 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_dac.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_dac.h @@ -1,60 +1,43 @@ /** * @file xmc_dac.h - * @date 2015-08-31 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** - * - * Change History - * -------------- - * - * 2015-02-18: - * - Initial version - * - * 2015-02-20: - * - Driver description added - * - * 2015-06-19: - * - Removed version macros and declaration of GetDriverVersion API - * - * 2015-08-31: - * - Help document updated - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -65,15 +48,11 @@ * HEADER FILES *******************************************************************************/ -#include +#include "xmc_common.h" /* DAC peripheral is not available on XMC1X devices. */ #if defined(DAC) -/** - * @addtogroup XMClib - * @{ - */ /** * @addtogroup DAC @@ -121,7 +100,7 @@ #define XMC_DAC_NO_CHANNELS (2U) /**< DAC maximum channels */ #define XMC_DAC_SAMPLES_PER_PERIOD (32U) /**< DAC samples per period in pattern mode */ -#define XMC_DAC_PATTERN_TRIANGLE {0U, 4U, 8U, 12U, 16U, 19U, 23U, 27U, 31U} /**< First quarter Triangle waveform samples */ +#define XMC_DAC_PATTERN_TRIANGLE {0U, 4U, 8U, 12U, 16U, 19U, 23U, 27U, 31U} /**< First quarter Triangle waveform samples */ #define XMC_DAC_PATTERN_SINE {0U, 6U, 12U, 17U, 22U, 26U, 29U, 30U, 31U} /**< First quarter Sine waveform samples */ #define XMC_DAC_PATTERN_RECTANGLE {31U, 31U, 31U, 31U, 31U, 31U, 31U, 31U, 31U} /**< First quarter Rectangle waveform samples */ @@ -157,7 +136,7 @@ (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_32) ||\ (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_64) ||\ (SCALE == XMC_DAC_CH_OUTPUT_SCALE_DIV_128)) - + /******************************************************************************* * ENUMS @@ -195,23 +174,23 @@ typedef enum XMC_DAC_CH_MODE typedef enum XMC_DAC_CH_TRIGGER { XMC_DAC_CH_TRIGGER_INTERNAL = - (0x0U << DAC_DAC0CFG1_TRIGMOD_Pos), /**< Internal trigger as per frequency divider value */ + (0x0U << DAC_DAC0CFG1_TRIGMOD_Pos), /**< Internal trigger as per frequency divider value */ XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1 = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | 0x0U, /**< External trigger from CCU80 Interrupt SR1 */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | 0x0U, /**< External trigger from CCU80 Interrupt SR1 */ XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1 = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x2U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU40 Interrupt SR1 */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x2U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU40 Interrupt SR1 */ XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1 = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x3U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU41 Interrupt SR1 */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x3U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from CCU41 Interrupt SR1 */ XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9 = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x4U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.9 */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x4U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.9 */ XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8 = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x5U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.8 */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x5U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from pin 2.8 */ XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x6U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-0 DX1 Input Signal */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x6U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-0 DX1 Input Signal */ XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS = - (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x7U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-1 DX1 Input Signal */ + (0x1U << DAC_DAC0CFG1_TRIGMOD_Pos) | (0x7U << DAC_DAC0CFG1_TRIGSEL_Pos), /**< External trigger from USIC-1 DX1 Input Signal */ XMC_DAC_CH_TRIGGER_SOFTWARE = - (0x2U << DAC_DAC0CFG1_TRIGMOD_Pos) /**< Software trigger */ + (0x2U << DAC_DAC0CFG1_TRIGMOD_Pos) /**< Software trigger */ } XMC_DAC_CH_TRIGGER_t; /** @@ -219,7 +198,7 @@ typedef enum XMC_DAC_CH_TRIGGER */ typedef enum XMC_DAC_CH_DATA_TYPE { - XMC_DAC_CH_DATA_TYPE_UNSIGNED = 0U , /**< input data is unsigned */ + XMC_DAC_CH_DATA_TYPE_UNSIGNED = 0U, /**< input data is unsigned */ XMC_DAC_CH_DATA_TYPE_SIGNED = 1U /**< input data is signed */ } XMC_DAC_CH_DATA_TYPE_t; @@ -229,35 +208,35 @@ typedef enum XMC_DAC_CH_DATA_TYPE typedef enum XMC_DAC_CH_OUTPUT_SCALE { XMC_DAC_CH_OUTPUT_SCALE_NONE = - 0x0U, /**< No scaling */ + 0x0U, /**< No scaling */ XMC_DAC_CH_OUTPUT_SCALE_MUL_2 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x1U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 2 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x1U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 2 */ XMC_DAC_CH_OUTPUT_SCALE_MUL_4 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x2U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 4 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x2U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 4 */ XMC_DAC_CH_OUTPUT_SCALE_MUL_8 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x3U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 8 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x3U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 8 */ XMC_DAC_CH_OUTPUT_SCALE_MUL_16 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x4U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 16 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x4U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 16 */ XMC_DAC_CH_OUTPUT_SCALE_MUL_32 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x5U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 32 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x5U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 32 */ XMC_DAC_CH_OUTPUT_SCALE_MUL_64 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x6U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 64 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x6U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 64 */ XMC_DAC_CH_OUTPUT_SCALE_MUL_128 = - (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x7U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 128 */ + (0x1U << DAC_DAC0CFG1_MULDIV_Pos) | (0x7U << DAC_DAC0CFG1_SCALE_Pos), /**< multiplied by 128 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_2 = - 0x1U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 2 */ + 0x1U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 2 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_4 = - 0x2U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 4 */ + 0x2U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 4 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_8 = - 0x3U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 8 */ + 0x3U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 8 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_16 = - 0x4U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 16 */ + 0x4U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 16 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_32 = - 0x5U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 32 */ + 0x5U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 32 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_64 = - 0x6U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 64 */ + 0x6U << DAC_DAC0CFG1_SCALE_Pos, /**< divided by 64 */ XMC_DAC_CH_OUTPUT_SCALE_DIV_128 = - 0x7U << DAC_DAC0CFG1_SCALE_Pos /**< divided by 128 */ + 0x7U << DAC_DAC0CFG1_SCALE_Pos /**< divided by 128 */ } XMC_DAC_CH_OUTPUT_SCALE_t; /** @@ -290,8 +269,8 @@ typedef struct struct { - __IO uint32_t low; - __IO uint32_t high; + __IO uint32_t low; + __IO uint32_t high; } DACCFG[XMC_DAC_NO_CHANNELS]; __IO uint32_t DACDATA[XMC_DAC_NO_CHANNELS]; @@ -299,18 +278,18 @@ typedef struct struct { - __IO uint32_t low; - __IO uint32_t high; + __IO uint32_t low; + __IO uint32_t high; } DACPAT[XMC_DAC_NO_CHANNELS]; } XMC_DAC_t; /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -320,32 +299,32 @@ typedef struct XMC_DAC_CH_CONFIG { union { - struct - { - uint32_t :23; /**< Not used bits */ - uint32_t data_type:1; /**< input data type - unsigned / signed */ - uint32_t :4; /**< Not used bits */ - uint32_t output_negation:1; /**< Negation of the output waveform enabled/disabled */ - uint32_t :3; - }; - uint32_t cfg0; + struct + { + uint32_t : 23; /**< Not used bits */ + uint32_t data_type: 1; /**< input data type - unsigned / signed */ + uint32_t : 4; /**< Not used bits */ + uint32_t output_negation: 1; /**< Negation of the output waveform enabled/disabled */ + uint32_t : 3; + }; + uint32_t cfg0; }; union { - struct - { - uint32_t output_scale:4; /**< Scale value of type XMC_DAC_CH_OUTPUT_SCALE_t. It includes scaling + mul/div bit */ - uint32_t output_offset:8; /**< offset value */ - uint32_t :20; - }; - uint32_t cfg1; + struct + { + uint32_t output_scale: 4; /**< Scale value of type XMC_DAC_CH_OUTPUT_SCALE_t. It includes scaling + mul/div bit */ + uint32_t output_offset: 8; /**< offset value */ + uint32_t : 20; + }; + uint32_t cfg1; }; } XMC_DAC_CH_CONFIG_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /******************************************************************************* * API PROTOTYPES @@ -432,7 +411,7 @@ bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac); __STATIC_INLINE void XMC_DAC_EnableSimultaneousDataMode(XMC_DAC_t *const dac) { XMC_ASSERT("XMC_DAC_EnableSimultaneousDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); - + dac->DACCFG[0].high |= DAC_DAC0CFG1_DATMOD_Msk; } @@ -455,7 +434,7 @@ __STATIC_INLINE void XMC_DAC_EnableSimultaneousDataMode(XMC_DAC_t *const dac) __STATIC_INLINE void XMC_DAC_DisableSimultaneousDataMode(XMC_DAC_t *const dac) { XMC_ASSERT("XMC_DAC_DisableSimultaneousDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); - + dac->DACCFG[0].high &= ~DAC_DAC0CFG1_DATMOD_Msk; } @@ -480,7 +459,7 @@ __STATIC_INLINE void XMC_DAC_DisableSimultaneousDataMode(XMC_DAC_t *const dac) __STATIC_INLINE void XMC_DAC_SimultaneousWrite(XMC_DAC_t *const dac, const uint16_t data0, const uint16_t data1) { XMC_ASSERT("XMC_DAC_SimultaneousWrite: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); - + dac->DAC01DATA = (data0 << DAC_DAC01DATA_DATA0_Pos) | (data1 << DAC_DAC01DATA_DATA1_Pos); } @@ -522,7 +501,7 @@ __STATIC_INLINE void XMC_DAC_CH_EnableOutput(XMC_DAC_t *const dac, const uint8_t { XMC_ASSERT("XMC_DAC_CH_EnableOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_EnableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].high |= DAC_DAC0CFG1_ANAEN_Msk; } @@ -546,7 +525,7 @@ __STATIC_INLINE void XMC_DAC_CH_DisableOutput(XMC_DAC_t *const dac, const uint8_ { XMC_ASSERT("XMC_DAC_CH_DisableOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_DisableOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].high &= ~DAC_DAC0CFG1_ANAEN_Msk; } @@ -572,7 +551,7 @@ __STATIC_INLINE bool XMC_DAC_CH_IsOutputEnabled(const XMC_DAC_t *const dac, cons { XMC_ASSERT("XMC_DAC_CH_IsOutputEnabled: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_IsOutputEnabled: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + return (bool)(dac->DACCFG[channel].high & DAC_DAC0CFG1_ANAEN_Msk); } @@ -604,7 +583,7 @@ __STATIC_INLINE void XMC_DAC_CH_Write(XMC_DAC_t *const dac, const uint8_t channe { XMC_ASSERT("XMC_DAC_CH_Write: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_Write: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACDATA[channel] = data; } @@ -645,9 +624,9 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const * */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, - const uint8_t channel, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency); + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); /** * @param dac Pointer to an instance of DAC module @@ -662,7 +641,7 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, * \parDescription:
        * Sets the \e channel to Ramp mode. Trigger, frequency, start and stop values are configured. * On a \e trigger ramp values are converted and driven to \e channel output. - * Start and stop have the range of [0-4095]. Stop should be equal or greater than start. + * Start and stop have the range of [0-4095]. Stop should be equal or greater than start. * * \parNote:
        * If the ramp counter reaches its \e stop value, it restarts from the \e start value with the next trigger pulse. @@ -672,11 +651,11 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, * */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, - const uint8_t channel, - const uint16_t start, - const uint16_t stop, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency); + const uint8_t channel, + const uint16_t start, + const uint16_t stop, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); /** * @param dac Pointer to an instance of DAC module @@ -697,11 +676,11 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, * */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, - const uint8_t channel, - const uint8_t *const pattern, - const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency); + const uint8_t channel, + const uint8_t *const pattern, + const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); /** * @param dac Pointer to an instance of DAC module @@ -720,9 +699,9 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, * */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac, - const uint8_t channel, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency); + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency); /** * @param dac Pointer to an instance of DAC module @@ -764,11 +743,11 @@ void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, const uint8_t channel, const ui * */ __STATIC_INLINE void XMC_DAC_CH_EnablePatternSignOutput(XMC_DAC_t *const dac, - const uint8_t channel) + const uint8_t channel) { XMC_ASSERT("XMC_DAC_CH_EnablePatternSignOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_EnablePatternSignOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low |= DAC_DAC0CFG0_SIGNEN_Msk; } @@ -792,11 +771,11 @@ __STATIC_INLINE void XMC_DAC_CH_EnablePatternSignOutput(XMC_DAC_t *const dac, * */ __STATIC_INLINE void XMC_DAC_CH_DisablePatternSignOutput(XMC_DAC_t *const dac, - const uint8_t channel) + const uint8_t channel) { XMC_ASSERT("XMC_DAC_CH_DisablePatternSignOutput: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_DisablePatternSignOutput: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low &= ~DAC_DAC0CFG0_SIGNEN_Msk; } @@ -824,7 +803,7 @@ __STATIC_INLINE void XMC_DAC_CH_SetRampStart(XMC_DAC_t *const dac, const uint8_t { XMC_ASSERT("XMC_DAC_CH_SetRampStart: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetRampStart: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACDATA[channel] = start; } @@ -849,7 +828,7 @@ __STATIC_INLINE uint16_t XMC_DAC_CH_GetRampStart(XMC_DAC_t *const dac, const uin { XMC_ASSERT("XMC_DAC_CH_GetRampStart: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_GetRampStart: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + return (uint16_t)(dac->DACDATA[channel]); } @@ -877,9 +856,9 @@ __STATIC_INLINE void XMC_DAC_CH_SetRampStop(XMC_DAC_t *const dac, const uint8_t { XMC_ASSERT("XMC_DAC_CH_SetRampStop: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetRampStop: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DAC01DATA = (dac->DAC01DATA & ~(DAC_DAC01DATA_DATA0_Msk << (channel * DAC_DAC01DATA_DATA1_Pos))) | - (stop << (channel * DAC_DAC01DATA_DATA1_Pos)); + (stop << (channel * DAC_DAC01DATA_DATA1_Pos)); } /** @@ -904,7 +883,7 @@ __STATIC_INLINE uint16_t XMC_DAC_CH_GetRampStop(XMC_DAC_t *const dac, const uint XMC_ASSERT("XMC_DAC_CH_GetRampStop: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_GetRampStop: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - return((dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & DAC_DAC01DATA_DATA0_Msk); + return ((dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & DAC_DAC01DATA_DATA0_Msk); } /** @@ -1001,8 +980,8 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac, const uint * */ __STATIC_INLINE XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetPatternFrequency(XMC_DAC_t *const dac, - const uint8_t channel, - const uint32_t frequency) + const uint8_t channel, + const uint32_t frequency) { XMC_ASSERT("XMC_DAC_CH_SetPatternFrequency: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetPatternFrequency: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); @@ -1027,7 +1006,7 @@ __STATIC_INLINE void XMC_DAC_CH_SetMode(XMC_DAC_t *const dac, const uint8_t chan XMC_ASSERT("XMC_DAC_CH_SetMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); XMC_ASSERT("XMC_DAC_CH_SetMode: trigger parameter not valid\n", XMC_DAC_IS_MODE_VALID(mode)); - + dac->DACCFG[channel].low = (dac->DACCFG[channel].low & ~DAC_DAC0CFG0_MODE_Msk) | mode; } @@ -1053,7 +1032,7 @@ __STATIC_INLINE void XMC_DAC_CH_SetSignedDataType(XMC_DAC_t *const dac, const ui { XMC_ASSERT("XMC_DAC_CH_SetSignedDataType: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetSignedDataType: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low |= (DAC_DAC0CFG0_SIGN_Msk); } @@ -1078,7 +1057,7 @@ __STATIC_INLINE void XMC_DAC_CH_SetUnsignedDataType(XMC_DAC_t *const dac, const { XMC_ASSERT("XMC_DAC_CH_SetUnsignedDataType: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetUnsignedDataType: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low &= ~(DAC_DAC0CFG0_SIGN_Msk); } @@ -1104,7 +1083,7 @@ __STATIC_INLINE void XMC_DAC_CH_SoftwareTrigger(XMC_DAC_t *const dac, const uint { XMC_ASSERT("XMC_DAC_CH_SoftwareTrigger: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SoftwareTrigger: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].high |= DAC_DAC0CFG1_SWTRIG_Msk; } @@ -1129,7 +1108,7 @@ __STATIC_INLINE void XMC_DAC_CH_EnableEvent(XMC_DAC_t *const dac, const uint8_t { XMC_ASSERT("XMC_DAC_CH_EnableEvent: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_EnableEvent: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low |= DAC_DAC0CFG0_SREN_Msk; } @@ -1150,7 +1129,7 @@ __STATIC_INLINE void XMC_DAC_CH_DisableEvent(XMC_DAC_t *const dac, const uint8_t { XMC_ASSERT("XMC_DAC_CH_DisableEvent: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_DisableEvent: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low &= ~DAC_DAC0CFG0_SREN_Msk; } @@ -1180,7 +1159,7 @@ __STATIC_INLINE void XMC_DAC_CH_SetOutputOffset(XMC_DAC_t *const dac, const uint { XMC_ASSERT("XMC_DAC_CH_SetOutputOffset: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_SetOutputOffset: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].high = (dac->DACCFG[channel].high & ~DAC_DAC0CFG1_OFFS_Msk) | offset << DAC_DAC0CFG1_OFFS_Pos; } @@ -1232,7 +1211,7 @@ __STATIC_INLINE XMC_DAC_CH_OUTPUT_SCALE_t XMC_DAC_CH_GetOutputScale(XMC_DAC_t *c { XMC_ASSERT("XMC_DAC_CH_GetOutputScale: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_GetOutputScale: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + return (XMC_DAC_CH_OUTPUT_SCALE_t)(dac->DACCFG[channel].high & (DAC_DAC0CFG1_MULDIV_Msk | DAC_DAC0CFG1_SCALE_Msk)); } @@ -1259,7 +1238,7 @@ __STATIC_INLINE void XMC_DAC_CH_EnableOutputNegation(XMC_DAC_t *const dac, const { XMC_ASSERT("XMC_DAC_CH_EnableOutputNegation: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_EnableOutputNegation: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low |= XMC_DAC_DACCFG_NEGATE_Msk; } @@ -1284,7 +1263,7 @@ __STATIC_INLINE void XMC_DAC_CH_DisableOutputNegation(XMC_DAC_t *const dac, cons { XMC_ASSERT("XMC_DAC_CH_DisableOutputNegation: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_DisableOutputNegation: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + dac->DACCFG[channel].low &= ~XMC_DAC_DACCFG_NEGATE_Msk; } @@ -1310,7 +1289,7 @@ __STATIC_INLINE bool XMC_DAC_CH_IsFifoFull(const XMC_DAC_t *const dac, const uin { XMC_ASSERT("XMC_DAC_CH_IsFifoFull: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_IsFifoFull: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + return (bool)(dac->DACCFG[channel].low & DAC_DAC0CFG0_FIFOFUL_Msk); } @@ -1336,7 +1315,7 @@ __STATIC_INLINE bool XMC_DAC_CH_IsFifoEmpty(const XMC_DAC_t *const dac, const ui { XMC_ASSERT("XMC_DAC_CH_IsFifoEmpty: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac)); XMC_ASSERT("XMC_DAC_CH_IsFifoEmpty: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel)); - + return (bool)(dac->DACCFG[channel].low & DAC_DAC0CFG0_FIFOEMP_Msk); } @@ -1344,10 +1323,6 @@ __STATIC_INLINE bool XMC_DAC_CH_IsFifoEmpty(const XMC_DAC_t *const dac, const ui } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_device.h b/cores/xmc_lib/XMCLib/inc/xmc_device.h index b2853204..89325d77 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_device.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_device.h @@ -1,70 +1,49 @@ /** * @file xmc_device.h - * @date 2018-03-08 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-09-23: - * - Added XMC14 and XMC48/47 + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-11-19: - * - Added XMC43 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-02-26: - * - Fixed CCU8 version for XMC43/47/48 + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2016-06-14: - * - Added XMC1201_T028x0016, XMC1202_T016x0064, XMC1301_T016x0032, XMC1302_Q040x0200, - * XMC1302_T028x0016, XMC1402_T038x0032, XMC1402_T038x0064, XMC1402_T038x0128, - * XMC1403_Q040x0064, XMC1403_Q040x0128, XMC1403_Q040x0200, XMC1402_T038x0200 - * XMC1402_Q040x0200, XMC1402_Q048x0200, XMC1201_T028x0032 - * - * 2018-03-08: - * - Added defines for XMC1 and XMC47 and XMC48 series to give RAM totals in - * UC_RAm and UC_ALL_RAM - * - * @endcond + * @endcond * */ #ifndef XMC_DEVICE_H #define XMC_DEVICE_H - + /* Family definitions */ #define XMC4 (4) #define XMC1 (1) @@ -99,13 +78,11 @@ #define XMC1402 (1402) #define XMC1403 (1403) #define XMC1404 (1404) -#define XMC1300 (1300) #define XMC1301 (1301) #define XMC1302 (1302) #define XMC1200 (1200) #define XMC1201 (1201) #define XMC1202 (1202) -#define XMC1203 (1203) #define XMC1100 (1100) /* Package definitions */ @@ -117,20 +94,18 @@ #define VQFN48 (6) #define TSSOP38 (7) #define TSSOP28 (8) -#define TSSOP16 (9) +#define TSSOP16 (9) #define VQFN24 (10) #define VQFN40 (11) #define VQFN64 (12) #define BGA196 (13) -#if defined(XMC4800_E196x2048) +#if defined(XMC4800_E196x2048) #define UC_FAMILY XMC4 #define UC_SERIES XMC48 #define UC_DEVICE XMC4800 #define UC_PACKAGE BGA196 #define UC_FLASH (2048UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (352UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -141,8 +116,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE LQFP144 #define UC_FLASH (2048UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (352UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -153,8 +126,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE LQFP100 #define UC_FLASH (2048UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (352UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -165,8 +136,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE BGA196 #define UC_FLASH (1536UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -177,8 +146,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE LQFP144 #define UC_FLASH (1536UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -189,8 +156,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE LQFP100 #define UC_FLASH (1536UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -201,8 +166,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE BGA196 #define UC_FLASH (1024UL) -#define UC_RAM (72UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -213,8 +176,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE LQFP144 #define UC_FLASH (1024UL) -#define UC_RAM (72UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -225,8 +186,6 @@ #define UC_DEVICE XMC4800 #define UC_PACKAGE LQFP100 #define UC_FLASH (1024UL) -#define UC_RAM (72UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -237,8 +196,6 @@ #define UC_DEVICE XMC4700 #define UC_PACKAGE BGA196 #define UC_FLASH (2048UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (352UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -249,8 +206,6 @@ #define UC_DEVICE XMC4700 #define UC_PACKAGE LQFP144 #define UC_FLASH (2048UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (352UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -261,8 +216,6 @@ #define UC_DEVICE XMC4700 #define UC_PACKAGE LQFP100 #define UC_FLASH (2048UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (352UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -273,8 +226,6 @@ #define UC_DEVICE XMC4700 #define UC_PACKAGE BGA196 #define UC_FLASH (1536UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -285,8 +236,6 @@ #define UC_DEVICE XMC4700 #define UC_PACKAGE LQFP144 #define UC_FLASH (1536UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -297,8 +246,6 @@ #define UC_DEVICE XMC4700 #define UC_PACKAGE LQFP100 #define UC_FLASH (1536UL) -#define UC_RAM (96UL) -#define UC_ALL_RAM (276UL) #define MULTICAN_PLUS #define CCU4V2 #define CCU8V2 @@ -309,89 +256,73 @@ #define UC_DEVICE XMC4500 #define UC_PACKAGE BGA144 #define UC_FLASH (1024UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (80UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4500_F144x1024) +#elif defined(XMC4500_F144x1024) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4500 #define UC_PACKAGE LQFP144 #define UC_FLASH (1024UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (80UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4500_F100x1024) +#elif defined(XMC4500_F100x1024) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4500 #define UC_PACKAGE LQFP100 #define UC_FLASH (1024UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (80UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4500_F144x768) +#elif defined(XMC4500_F144x768) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4500 #define UC_PACKAGE LQFP144 #define UC_FLASH (768UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (80UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4500_F100x768) +#elif defined(XMC4500_F100x768) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4500 #define UC_PACKAGE LQFP100 #define UC_FLASH (768UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (80UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4502_F100x768) +#elif defined(XMC4502_F100x768) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4502 #define UC_PACKAGE LQFP100 #define UC_FLASH (768UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (80UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4504_F100x512) +#elif defined(XMC4504_F100x512) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4504 #define UC_PACKAGE LQFP100 #define UC_FLASH (512UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (64UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4504_F144x512) +#elif defined(XMC4504_F144x512) #define UC_FAMILY XMC4 #define UC_SERIES XMC45 #define UC_DEVICE XMC4504 #define UC_PACKAGE LQFP144 #define UC_FLASH (512UL) -#define UC_RAM (64UL) -#define UC_ALL_RAM (64UL) #define CCU4V1 #define CCU8V1 -#elif defined(XMC4400_F100x512) +#elif defined(XMC4400_F100x512) #define UC_FAMILY XMC4 #define UC_SERIES XMC44 #define UC_DEVICE XMC4400 @@ -400,7 +331,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4400_F64x512) +#elif defined(XMC4400_F64x512) #define UC_FAMILY XMC4 #define UC_SERIES XMC44 #define UC_DEVICE XMC4400 @@ -409,7 +340,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4400_F100x256) +#elif defined(XMC4400_F100x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC44 #define UC_DEVICE XMC4400 @@ -418,7 +349,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4400_F64x256) +#elif defined(XMC4400_F64x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC44 #define UC_DEVICE XMC4400 @@ -427,7 +358,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4402_F100x256) +#elif defined(XMC4402_F100x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC44 #define UC_DEVICE XMC4402 @@ -436,7 +367,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4402_F64x256) +#elif defined(XMC4402_F64x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC44 #define UC_DEVICE XMC4402 @@ -445,7 +376,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4300_F100x256) +#elif defined(XMC4300_F100x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC43 #define UC_DEVICE XMC4300 @@ -455,7 +386,7 @@ #define CCU4V2 #define CCU8V2 -#elif defined(XMC4200_E64x256) +#elif defined(XMC4200_E64x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC42 #define UC_DEVICE XMC4200 @@ -464,7 +395,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4200_F64x256) +#elif defined(XMC4200_F64x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC42 #define UC_DEVICE XMC4200 @@ -473,7 +404,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4200_Q48x256) +#elif defined(XMC4200_Q48x256) #define UC_FAMILY XMC4 #define UC_SERIES XMC42 #define UC_DEVICE XMC4200 @@ -482,7 +413,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4100_E64x128) +#elif defined(XMC4100_E64x128) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4100 @@ -491,7 +422,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4100_F64x128) +#elif defined(XMC4100_F64x128) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4100 @@ -500,7 +431,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4100_Q48x128) +#elif defined(XMC4100_Q48x128) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4100 @@ -509,7 +440,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4104_E64x64) +#elif defined(XMC4104_E64x64) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4104 @@ -518,7 +449,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4104_F64x64) +#elif defined(XMC4104_F64x64) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4104 @@ -527,7 +458,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4104_Q48x64) +#elif defined(XMC4104_Q48x64) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4104 @@ -536,7 +467,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4104_E64x128) +#elif defined(XMC4104_E64x128) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4104 @@ -545,7 +476,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4104_F64x128) +#elif defined(XMC4104_F64x128) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4104 @@ -554,7 +485,7 @@ #define CCU4V1 #define CCU8V1 -#elif defined(XMC4104_Q48x128) +#elif defined(XMC4104_Q48x128) #define UC_FAMILY XMC4 #define UC_SERIES XMC41 #define UC_DEVICE XMC4104 @@ -964,8 +895,6 @@ #define UC_DEVICE XMC1301 #define UC_PACKAGE TSSOP38 #define UC_FLASH (16UL) -#define UC_RAM (16UL) -#define UC_ALL_RAM (16UL) #define CCU4V2 #define CCU8V2 @@ -1081,8 +1010,6 @@ #define UC_DEVICE XMC1302 #define UC_PACKAGE TSSOP38 #define UC_FLASH (64UL) -#define UC_RAM (16UL) -#define UC_ALL_RAM (16UL) #define CCU4V2 #define CCU8V2 @@ -1104,6 +1031,42 @@ #define CCU4V2 #define CCU8V2 +#elif defined(XMC1302_T028x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (200UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T028x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (128UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T028x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (64UL) +#define CCU4V2 +#define CCU8V2 + +#elif defined(XMC1302_T028x0032) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC13 +#define UC_DEVICE XMC1302 +#define UC_PACKAGE TSSOP28 +#define UC_FLASH (32UL) +#define CCU4V2 +#define CCU8V2 + #elif defined(XMC1302_T028x0016) #define UC_FAMILY XMC1 #define UC_SERIES XMC13 @@ -1416,6 +1379,36 @@ #define MULTICAN_PLUS #define CCU4V3 +#elif defined(XMC1404_Q040x0064) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (64UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q040x0128) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (128UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + +#elif defined(XMC1404_Q040x0200) +#define UC_FAMILY XMC1 +#define UC_SERIES XMC14 +#define UC_DEVICE XMC1404 +#define UC_PACKAGE VQFN40 +#define UC_FLASH (200UL) +#define MULTICAN_PLUS +#define CCU4V3 +#define CCU8V3 + #elif defined(XMC1404_Q048x0064) #define UC_FAMILY XMC1 #define UC_SERIES XMC14 @@ -1508,44 +1501,25 @@ #else #error "xmc_device.h: device not supported" -#endif -#if UC_FAMILY == XMC1 -#define UC_RAM (16UL) -#define UC_ALL_RAM (16UL) -#endif - -#if UC_FAMILY == XMC41 -#define UC_RAM (8UL) -#define UC_ALL_RAM (20UL) -#endif - -#if UC_FAMILY == XMC42 -#define UC_RAM (16UL) -#define UC_ALL_RAM (40UL) -#endif - -#if UC_FAMILY == XMC43 -#define UC_RAM (64UL) -#define UC_ALL_RAM (128UL) -#endif - -#if UC_FAMILY == XMC44 -#define UC_RAM (16UL) -#define UC_ALL_RAM (80UL) -#endif - -#if UC_FAMILY == XMC45 -#define UC_RAM (8UL) -#define UC_ALL_RAM (20UL) #endif #if UC_SERIES == XMC45 +#if UC_DEVICE == XMC4502 +#include "XMC4502.h" +#elif UC_DEVICE == XMC4504 +#include "XMC4504.h" +#else #include "XMC4500.h" +#endif #define PERIPHERAL_RESET_SUPPORTED #define USB_OTG_SUPPORTED #elif UC_SERIES == XMC44 +#if UC_DEVICE == XMC4402 +#include "XMC4402.h" +#else #include "XMC4400.h" +#endif #define CLOCK_GATING_SUPPORTED #define PERIPHERAL_RESET_SUPPORTED #define USB_OTG_SUPPORTED @@ -1562,7 +1536,13 @@ #define PERIPHERAL_RESET_SUPPORTED #elif UC_SERIES == XMC41 +#if UC_DEVICE == XMC4104 +#include "XMC4104.h" +#elif UC_DEVICE == XMC4108 +#include "XMC4108.h" +#else #include "XMC4100.h" +#endif #define CLOCK_GATING_SUPPORTED #define PERIPHERAL_RESET_SUPPORTED diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dma.h b/cores/xmc_lib/XMCLib/inc/xmc_dma.h index 7330996d..7170fd92 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_dma.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_dma.h @@ -1,55 +1,41 @@ - /** * @file xmc_dma.h - * @date 2016-10-28 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
        - * - * 2015-06-20: - * - Add the declarations for the following APIs:
        - * XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine,
        - * XMC_DMA_CH_ClearSourcePeripheralRequest,
        - * XMC_DMA_CH_ClearDestinationPeripheralRequest
        - * - Documentation updates
        - * - Removed version macros and declaration of GetDriverVersion API
        - * - * 2016-10-28: - * - Fix documentation on maximum block size + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -67,10 +53,6 @@ #include "xmc_dma_map.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup DMA @@ -261,8 +243,9 @@ typedef enum XMC_DMA_CH_STATUS * like source address, destination address, block size, incrementation * modes and the like. */ - -typedef struct { + +typedef struct GPDMA_CH +{ __IO uint32_t SAR; __I uint32_t RESERVED0; __IO uint32_t DAR; @@ -294,7 +277,8 @@ typedef struct { * to configure the GPDMA peripheral on the XMC4000 series of microcontrollers. * The registers can be accessed with ::XMC_DMA0 and ::XMC_DMA1. */ -typedef struct { +typedef struct XMC_DMA +{ GPDMA_CH_t CH[8]; __IO uint32_t RAWCHEV[10]; @@ -327,10 +311,10 @@ typedef struct { /* Anonymous structure/union guard start */ #if defined (__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined (__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -347,16 +331,16 @@ typedef struct XMC_DMA_LLI struct { uint32_t enable_interrupt: 1; /**< Enable interrupts? */ - uint32_t dst_transfer_width: 3; /**< Destination transfer width */ - uint32_t src_transfer_width: 3; /**< Source transfer width */ - uint32_t dst_address_count_mode: 2; /**< Destination address count mode */ - uint32_t src_address_count_mode: 2; /**< Source address count mode */ - uint32_t dst_burst_length: 3; /**< Destination burst length */ - uint32_t src_burst_length: 3; /**< Source burst length */ + uint32_t dst_transfer_width: 3; /**< Destination transfer width (:: XMC_DMA_CH_TRANSFER_WIDTH_t) */ + uint32_t src_transfer_width: 3; /**< Source transfer width (:: XMC_DMA_CH_TRANSFER_WIDTH_t) */ + uint32_t dst_address_count_mode: 2; /**< Destination address count mode (:: XMC_DMA_CH_ADDRESS_COUNT_MODE_t) */ + uint32_t src_address_count_mode: 2; /**< Source address count mode (:: XMC_DMA_CH_ADDRESS_COUNT_MODE_t) */ + uint32_t dst_burst_length: 3; /**< Destination burst length (:: XMC_DMA_CH_BURST_LENGTH_t) */ + uint32_t src_burst_length: 3; /**< Source burst length (:: XMC_DMA_CH_BURST_LENGTH_t) */ uint32_t enable_src_gather: 1; /**< Enable source gather? */ uint32_t enable_dst_scatter: 1; /**< Enable destination scatter? */ uint32_t : 1; /**< Reserved bits */ - uint32_t transfer_flow: 3; /**< DMA transfer flow */ + uint32_t transfer_flow: 3; /**< DMA transfer flow (:: XMC_DMA_CH_TRANSFER_FLOW_t) */ uint32_t : 4; /**< Reserved bits */ uint32_t enable_dst_linked_list: 1; /**< Enable destination linked list? */ uint32_t enable_src_linked_list: 1; /**< Enable source linked list? */ @@ -382,24 +366,24 @@ typedef struct XMC_DMA_CH_CONFIG struct { uint32_t enable_interrupt: 1; /**< Enable interrupts? */ - uint32_t dst_transfer_width: 3; /**< Destination transfer width */ - uint32_t src_transfer_width: 3; /**< Source transfer width */ - uint32_t dst_address_count_mode: 2; /**< Destination address count mode */ - uint32_t src_address_count_mode: 2; /**< Source address count mode */ - uint32_t dst_burst_length: 3; /**< Destination burst length */ - uint32_t src_burst_length: 3; /**< Source burst length */ + uint32_t dst_transfer_width: 3; /**< Destination transfer width (:: XMC_DMA_CH_TRANSFER_WIDTH_t) */ + uint32_t src_transfer_width: 3; /**< Source transfer width (:: XMC_DMA_CH_TRANSFER_WIDTH_t) */ + uint32_t dst_address_count_mode: 2; /**< Destination address count mode (:: XMC_DMA_CH_ADDRESS_COUNT_MODE_t) */ + uint32_t src_address_count_mode: 2; /**< Source address count mode (:: XMC_DMA_CH_ADDRESS_COUNT_MODE_t) */ + uint32_t dst_burst_length: 3; /**< Destination burst length (:: XMC_DMA_CH_BURST_LENGTH_t) */ + uint32_t src_burst_length: 3; /**< Source burst length (:: XMC_DMA_CH_BURST_LENGTH_t) */ uint32_t enable_src_gather: 1; /**< Enable source gather? */ uint32_t enable_dst_scatter: 1; /**< Enable destination scatter? */ - uint32_t : 1; - uint32_t transfer_flow: 3; /**< DMA transfer flow */ - uint32_t : 9; + uint32_t : 1; + uint32_t transfer_flow: 3; /**< DMA transfer flow (:: XMC_DMA_CH_TRANSFER_FLOW_t) */ + uint32_t : 9; }; }; uint32_t src_addr; /**< Source address */ uint32_t dst_addr; /**< Destination address */ XMC_DMA_LLI_t *linked_list_pointer; /**< Linked list pointer */ - + union { uint32_t src_gather_control; @@ -419,21 +403,21 @@ typedef struct XMC_DMA_CH_CONFIG uint32_t dst_scatter_count: 12; /**< Destination scatter count */ }; }; - - uint16_t block_size; /**< Block size for DMA controlled transfers [max. 4095]*/ - XMC_DMA_CH_TRANSFER_TYPE_t transfer_type; /**< DMA transfer type */ - XMC_DMA_CH_PRIORITY_t priority; /**< DMA channel priority */ - XMC_DMA_CH_SRC_HANDSHAKING_t src_handshaking; /**< DMA source handshaking interface */ - uint8_t src_peripheral_request; /**< Source peripheral request */ - XMC_DMA_CH_DST_HANDSHAKING_t dst_handshaking; /**< DMA destination handshaking interface */ - uint8_t dst_peripheral_request; /**< Destination peripheral request */ + + uint16_t block_size; /**< Block size for DMA controlled transfers [max. 4095] */ + XMC_DMA_CH_TRANSFER_TYPE_t transfer_type; /**< DMA transfer type (:: XMC_DMA_CH_TRANSFER_TYPE_t) */ + XMC_DMA_CH_PRIORITY_t priority; /**< DMA channel priority (::XMC_DMA_CH_PRIORITY_t) */ + XMC_DMA_CH_SRC_HANDSHAKING_t src_handshaking; /**< DMA source handshaking interface (:: XMC_DMA_CH_SRC_HANDSHAKING_t) */ + uint8_t src_peripheral_request; /**< Source peripheral request. See xmc_dma_map.h */ + XMC_DMA_CH_DST_HANDSHAKING_t dst_handshaking; /**< DMA destination handshaking interface (:: XMC_DMA_CH_DST_HANDSHAKING_t) */ + uint8_t dst_peripheral_request; /**< Destination peripheral request. See xmc_dma_map.h */ } XMC_DMA_CH_CONFIG_t; /* Anonymous structure/union guard end */ #if defined (__CC_ARM) - #pragma pop +#pragma pop #elif defined (__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** @@ -736,7 +720,7 @@ XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, */ __STATIC_INLINE void XMC_DMA_CH_Enable(XMC_DMA_t *const dma, const uint8_t channel) { - dma->CHENREG = (uint32_t)(0x101UL << channel); + dma->CHENREG = (uint32_t)(0x101UL << channel); } /** @@ -1234,6 +1218,67 @@ void XMC_DMA_CH_ClearSourcePeripheralRequest(XMC_DMA_t *const dma, uint8_t chann */ void XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_DMA_t *const dma, uint8_t channel); +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The destination peripheral request for which DMA channel is to be cleared? + * @return None + * + * \parDescription:
        + * Enable FIFO mode
        + * + * \par + * Special mode to improve bandwidth. When enabled, the channel waits until the FIFO
        + * is less than half full to fetch the data from the source peripheral, and waits until the FIFO is greater
        + * than or equal to half full in order to send data to the destination peripheral. Because of this, the
        + * channel can transfer the data using bursts, which eliminates the need to arbitrate for the AHB master
        + * interface in each single AHB transfer. + * + * \parRelated APIs:
        + * XMC_DMA_CH_DisableFifoMode()\n\n + */ +__STATIC_INLINE void XMC_DMA_CH_EnableFifoMode(XMC_DMA_t *const dma, uint8_t channel) +{ + dma->CH[channel].CFGH |= GPDMA0_CH_CFGH_FIFO_MODE_Msk; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The destination peripheral request for which DMA channel is to be cleared? + * @return None + * + * \parDescription:
        + * Disable FIFO mode
        + * + * \par + * When the FIFO mode is not enabled, the channel waits only until
        + * the FIFO can transmit or accept a single AHB transfer before it requests the master bus interface.
        + * + * \parRelated APIs:
        + * XMC_DMA_CH_EnableFifoMode()\n\n + */ +__STATIC_INLINE void XMC_DMA_CH_DisableFifoMode(XMC_DMA_t *const dma, uint8_t channel) +{ + dma->CH[channel].CFGH &= ~GPDMA0_CH_CFGH_FIFO_MODE_Msk; +} + +/** + * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address + * @param channel The destination peripheral request for which DMA channel is to be cleared? + * @return Total number of data items already read from the source peripheral + * + * \parDescription:
        + * Obtain the total number of data items already read from the source peripheral
        + * + * \parNote:
        + * The width of the single transaction is determined by src_transfer_width. + * + */ +__STATIC_INLINE uint32_t XMC_DMA_CH_GetTransferredData(XMC_DMA_t *const dma, const uint8_t channel) +{ + return (dma->CH[channel].CTLH & GPDMA0_CH_CTLH_BLOCK_TS_Msk); + +} + /** * @param dma A constant pointer to XMC_DMA_t, pointing to the GPDMA base address * @return None @@ -1261,9 +1306,6 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma); * @} (end addtogroup DMA) */ -/** - * @} (end addtogroup XMClib) - */ #endif /* defined (GPDMA0) */ #endif /* XMC_DMA_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dma_map.h b/cores/xmc_lib/XMCLib/inc/xmc_dma_map.h index 90bdfc53..f635de25 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_dma_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_dma_map.h @@ -1,47 +1,42 @@ /** * @file xmc_dma_map.h - * @date 2015-05-07 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-05-07: - * - Change line numbering for DMA1
        + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_dsd.h b/cores/xmc_lib/XMCLib/inc/xmc_dsd.h index 6c28b3a1..358db9af 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_dsd.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_dsd.h @@ -1,55 +1,42 @@ /** * @file xmc_dsd.h - * @date 2015-09-18 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-03-30: - * - Initial version - * - * 2015-06-19: - * - Removed version macros and declaration of GetDriverVersion API
        - * - Added API XMC_DSD_CH_GetRectifyDelay
        - * - * 2015-07-16: - * - Renamed API “XMC_DSD_CH_AuxFilter_SetBoudary()†to “XMC_DSD_CH_AuxFilter_SetBoundary()â€
        - * - * 2015-09-18: - * - Added APIs "XMC_DSD_SetResultEventFlag()","XMC_DSD_ClearResultEventFlag()" - * "XMC_DSD_SetAlarmEventFlag()" and "XMC_DSD_ClearAlarmEventFlag()"
        - * - Support added for XMC4800 microcontroller family
        + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * * @endcond * */ @@ -62,15 +49,11 @@ /********************************************************************************************************************** * HEADER FILES *********************************************************************************************************************/ -#include +#include "xmc_common.h" #if defined(DSD) -#include +#include "xmc_scu.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup DSD @@ -78,7 +61,7 @@ * @brief Delta Sigma Demodulator (DSD) driver for the XMC4500, XMC4400 and XMC4800 microcontroller family
        * * The DSD unit provides a series of digital input channels accepting data streams from external modulators - * using the Delta/Sigma (DS) conversion principle. The on-chip demodulator channels convert these inputs to + * using the Delta/Sigma (DS) conversion principle. The on-chip demodulator channels convert these inputs to * discrete digital values. * DSD unit can be used for isolated current/voltage measurement and for sensor interfaces.
        * @@ -98,14 +81,16 @@ * -# Configuration structure XMC_DSD_CH_INTEGRATOR_CONFIG_t and initialization function XMC_DSD_CH_Integrator_Init() to configure integrator * -# Configuration structure XMC_DSD_CH_TIMESTAMP_CONFIG_t and initialization function XMC_DSD_CH_Timestamp_Init() to configure timestamp * -# Configuration structure XMC_DSD_CH_RECTIFY_CONFIG_t and initialization function XMC_DSD_CH_Rectify_Init() to configure rectifier + * + * Also, the DSD block can be configured from the ModusToolbox™ Device Configurator: \ref section_personality_dsd */ - - /********************************************************************************************************************* - * MACROS - ********************************************************************************************************************/ - #define XMC_DSD_CHECK_MODULE_PTR(PTR) ( ((PTR)== DSD)) - #define XMC_DSD_CHECK_CHANNEL_PTR(PTR) ( ((PTR) == DSD_CH0) || ((PTR) == DSD_CH1) || ((PTR) == DSD_CH2) || ((PTR) == DSD_CH3)) - + +/********************************************************************************************************************* +* MACROS +********************************************************************************************************************/ +#define XMC_DSD_CHECK_MODULE_PTR(PTR) ( ((PTR)== DSD)) +#define XMC_DSD_CHECK_CHANNEL_PTR(PTR) ( ((PTR) == DSD_CH0) || ((PTR) == DSD_CH1) || ((PTR) == DSD_CH2) || ((PTR) == DSD_CH3)) + /********************************************************************************************************************** * ENUMS *********************************************************************************************************************/ @@ -365,8 +350,8 @@ typedef enum XMC_DSD_CH_AUX_EVENT */ typedef enum XMC_DSD_CH_RESULT_EVENT { - XMC_DSD_CH_RESULT_EVENT_DISABLE = 0U, /**< Disable service request */ - XMC_DSD_CH_RESULT_EVENT_ENABLE = 3U /**< Enable service request for each new result value */ + XMC_DSD_CH_RESULT_EVENT_DISABLE = 0U, /**< Disable service request */ + XMC_DSD_CH_RESULT_EVENT_ENABLE = 3U /**< Enable service request for each new result value */ } XMC_DSD_CH_RESULT_EVENT_t; @@ -376,10 +361,10 @@ typedef enum XMC_DSD_CH_RESULT_EVENT ********************************************************************************************************************/ /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -397,7 +382,7 @@ typedef struct XMC_DSD_GENERATOR_CONFIG uint32_t bit_reverse: 1; /**< should PWM signal be bit-reversed? 0: Normal mode, 1:Bit-reverse mode */ uint32_t inverted_polarity: 1; /**< should PWM signal start from negative max. 0: Normal, 1: Inverted */ uint32_t frequency: 4; /**< Frequency divider value of PWM signal. This parameter can take a value of XMC_DSD_GENERATOR_CLKDIV_t */ - uint32_t :24; + uint32_t : 24; }; uint32_t generator_conf; /**< Carrier generator configuration register(CGCFG)*/ }; @@ -422,7 +407,7 @@ typedef struct XMC_DSD_CH_FILTER_CONFIG uint32_t : 12; uint32_t clock_source: 4; /**< This parameter can take a value of XMC_DSD_CH_CLOCK_SOURCE_t */ uint32_t strobe: 4; /**< This parameter can take a value of XMC_DSD_CH_STROBE_t */ - uint32_t :8; + uint32_t : 8; }; uint32_t demodulator_conf; /*Demodulator Input Configuration Register*/ }; @@ -453,21 +438,21 @@ typedef struct XMC_DSD_CH_INTEGRATOR_CONFIG { union { - struct - { - uint32_t :8; - uint32_t start_condition: 2; /**< Can take a value of XMC_DSD_CH_INTEGRATOR_START_t.Bitfields \a ITRMODE of \a DICFG.*/ - uint32_t :2; - uint32_t trigger_source: 3; /**< Can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t.Bitfields \a TRSEL of \a DICFG. */ - uint32_t :17; - }; - uint32_t integrator_trigger; /**< Demodulator Input Configuration Register(\a DICFG).*/ + struct + { + uint32_t : 8; + uint32_t start_condition: 2; /**< Can take a value of XMC_DSD_CH_INTEGRATOR_START_t.Bitfields \a ITRMODE of \a DICFG.*/ + uint32_t : 2; + uint32_t trigger_source: 3; /**< Can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t.Bitfields \a TRSEL of \a DICFG. */ + uint32_t : 17; + }; + uint32_t integrator_trigger; /**< Demodulator Input Configuration Register(\a DICFG).*/ }; - uint32_t integration_loop; /**< Integration loops to see stop condition. Bitfields \a REPVAL of \a IWCTR.*/ - uint32_t discarded_values; /**< Number of mainfilter results,discarded before integration starts.Bitfields \a NVALDIS of \a IWCTR.*/ - uint32_t stop_condition; /**< Integrator stop condition. Can take a value of XMC_DSD_CH_INTEGRATOR_STOP_t.Bitfields \a IWS of \a IWCTR.*/ - uint32_t counted_values; /**< Number of mainfilter results, integrated to a integrator result.Bitfields \a NVALINT of \a IWCTR.*/ + uint32_t integration_loop; /**< Integration loops to see stop condition. Bitfields \a REPVAL of \a IWCTR.*/ + uint32_t discarded_values; /**< Number of mainfilter results,discarded before integration starts.Bitfields \a NVALDIS of \a IWCTR.*/ + uint32_t stop_condition; /**< Integrator stop condition. Can take a value of XMC_DSD_CH_INTEGRATOR_STOP_t.Bitfields \a IWS of \a IWCTR.*/ + uint32_t counted_values; /**< Number of mainfilter results, integrated to a integrator result.Bitfields \a NVALINT of \a IWCTR.*/ } XMC_DSD_CH_INTEGRATOR_CONFIG_t; @@ -482,8 +467,8 @@ typedef struct XMC_DSD_CH_TIMESTAMP_CONFIG { struct { - uint32_t :10; - uint32_t trigger_mode:2; /**< This parameter can take a value of XMC_DSD_CH_TIMESTAMP_TRIGGER_t */ + uint32_t : 10; + uint32_t trigger_mode: 2; /**< This parameter can take a value of XMC_DSD_CH_TIMESTAMP_TRIGGER_t */ uint32_t trigger_source: 3; /**< This parameter can take a value of XMC_DSD_CH_TRIGGER_SOURCE_t */ uint32_t : 17; }; @@ -534,9 +519,9 @@ typedef struct XMC_DSD_CH_RECTIFY_CONFIG { struct { - uint32_t :4; + uint32_t : 4; uint32_t sign_source: 2; /**< Can take a value of XMC_DSD_CH_SIGN_SOURCE_t.Bitfields \a SSRC of \a RECTCFG.*/ - uint32_t :26; + uint32_t : 26; }; uint32_t rectify_config; /**< Rectification configuration register(\a RECTCFG)*/ }; @@ -549,9 +534,9 @@ typedef struct XMC_DSD_CH_RECTIFY_CONFIG /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** @@ -771,7 +756,7 @@ __STATIC_INLINE bool XMC_DSD_IsChannelStarted(XMC_DSD_t *const dsd, const XMC_DS * \parRelated APIs:
        * XMC_DSD_CH_GetResult_TS()\n\n\n */ -__STATIC_INLINE void XMC_DSD_CH_GetResult(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) +__STATIC_INLINE void XMC_DSD_CH_GetResult(XMC_DSD_CH_t *const channel, int16_t *dsd_Result) { uint16_t result; result = (uint16_t)((uint32_t)channel->RESM & DSD_CH_RESM_RESULT_Msk); @@ -794,10 +779,10 @@ __STATIC_INLINE void XMC_DSD_CH_GetResult(XMC_DSD_CH_t *const channel, int16_t* * XMC_DSD_CH_GetResult(),XMC_DSD_CH_GetResult_TS_Time()\n\n\n */ void XMC_DSD_CH_GetResult_TS( - XMC_DSD_CH_t *const channel, - int16_t* dsd_Result, - uint8_t* dsd_filter_loop, - uint8_t* dsd_integration_loop); + XMC_DSD_CH_t *const channel, + int16_t *dsd_Result, + uint8_t *dsd_filter_loop, + uint8_t *dsd_integration_loop); /** * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t\n @@ -811,7 +796,7 @@ void XMC_DSD_CH_GetResult_TS( * \parRelated APIs:
        * XMC_DSD_CH_GetResult(),XMC_DSD_CH_GetResult_TS()\n\n\n */ -void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t *const channel, int16_t* dsd_Result, uint32_t* time); +void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t *const channel, int16_t *dsd_Result, uint32_t *time); /** * @param channel Pointer to an instance of DSD channel of type @ref XMC_DSD_CH_t @@ -825,7 +810,7 @@ void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t *const channel, int16_t* dsd_Resu * \parRelated APIs:
        * XMC_DSD_CH_GetResult_TS()\n\n\n */ -__STATIC_INLINE void XMC_DSD_CH_GetResult_AUX(XMC_DSD_CH_t *const channel, int16_t* dsd_Result) +__STATIC_INLINE void XMC_DSD_CH_GetResult_AUX(XMC_DSD_CH_t *const channel, int16_t *dsd_Result) { uint16_t result; result = (uint16_t) (channel->RESA & DSD_CH_RESA_RESULT_Msk); @@ -988,13 +973,13 @@ void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX * XMC_DSD_CH_AuxFilter_Init()\n\n\n */ __STATIC_INLINE void XMC_DSD_CH_AuxFilter_SetBoundary( - XMC_DSD_CH_t *const channel, - const int16_t lower_boundary, - const int16_t upper_boundary) + XMC_DSD_CH_t *const channel, + const int16_t lower_boundary, + const int16_t upper_boundary) { XMC_ASSERT("XMC_DSD_CH_AuxFilter_SetBoundary:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); channel->BOUNDSEL = (((uint32_t)upper_boundary << (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYU_Pos) - | ((uint32_t)lower_boundary & (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYL_Msk)); + | ((uint32_t)lower_boundary & (uint32_t)DSD_CH_BOUNDSEL_BOUNDARYL_Msk)); } /** @@ -1011,7 +996,7 @@ __STATIC_INLINE void XMC_DSD_CH_AuxFilter_SetBoundary( __STATIC_INLINE void XMC_DSD_CH_AuxFilter_EnableEvent(XMC_DSD_CH_t *const channel, XMC_DSD_CH_AUX_EVENT_t event) { XMC_ASSERT("XMC_DSD_CH_AuxFilter_EnableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); - channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk|(uint32_t)DSD_CH_FCFGA_SRGA_Msk); + channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk | (uint32_t)DSD_CH_FCFGA_SRGA_Msk); channel->FCFGA |= ((uint32_t)event << DSD_CH_FCFGA_SRGA_Pos); } @@ -1027,7 +1012,7 @@ __STATIC_INLINE void XMC_DSD_CH_AuxFilter_EnableEvent(XMC_DSD_CH_t *const channe __STATIC_INLINE void XMC_DSD_CH_AuxFilter_DisableEvent(XMC_DSD_CH_t *const channel) { XMC_ASSERT("XMC_DSD_CH_AuxFilter_DisableEvent:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); - channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk|(uint32_t)DSD_CH_FCFGA_SRGA_Msk); + channel->FCFGA &= ~((uint32_t)DSD_CH_FCFGA_ESEL_Msk | (uint32_t)DSD_CH_FCFGA_SRGA_Msk); } /** @@ -1079,7 +1064,7 @@ void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTI * Read bit field \a SDCAP of register \a CGSYNC * */ -__STATIC_INLINE void XMC_DSD_CH_GetRectifyDelay(XMC_DSD_CH_t *const channel, uint8_t* delay) +__STATIC_INLINE void XMC_DSD_CH_GetRectifyDelay(XMC_DSD_CH_t *const channel, uint8_t *delay) { XMC_ASSERT("XMC_DSD_CH_GetRectifyDelay:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); *delay = (uint8_t)((channel->CGSYNC & DSD_CH_CGSYNC_SDCAP_Msk ) >> DSD_CH_CGSYNC_SDCAP_Pos); @@ -1145,7 +1130,7 @@ __STATIC_INLINE void XMC_DSD_ClearResultEventFlag(XMC_DSD_t *const dsd, const ui __STATIC_INLINE void XMC_DSD_SetAlarmEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) { XMC_ASSERT("XMC_DSD_SetAlarmEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); - dsd->EVFLAG = (channel_id<< DSD_EVFLAGCLR_ALEC0_Pos); + dsd->EVFLAG = (channel_id << DSD_EVFLAGCLR_ALEC0_Pos); } /** * @param dsd Pointer to an instance of DSD module of type @ref XMC_DSD_t @@ -1166,7 +1151,7 @@ __STATIC_INLINE void XMC_DSD_SetAlarmEventFlag(XMC_DSD_t *const dsd, const uint3 __STATIC_INLINE void XMC_DSD_ClearAlarmEventFlag(XMC_DSD_t *const dsd, const uint32_t channel_id) { XMC_ASSERT("XMC_DSD_ClearAlarmEventFlag:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); - dsd->EVFLAGCLR = (channel_id<EVFLAGCLR = (channel_id << DSD_EVFLAGCLR_ALEC0_Pos); } #ifdef __cplusplus } @@ -1176,9 +1161,6 @@ __STATIC_INLINE void XMC_DSD_ClearAlarmEventFlag(XMC_DSD_t *const dsd, const uin * @} */ -/** - * @} - */ #endif /* DSD_PRESENT */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ebu.h b/cores/xmc_lib/XMCLib/inc/xmc_ebu.h index e0a96d3e..1e7e9240 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_ebu.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_ebu.h @@ -1,85 +1,72 @@ /** * @file xmc_ebu.h - * @date 2017-06-24 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-06-20: - * - Initial - * - * 2016-03-30: - * - Added ebu_data_hold_cycles_for_read_accesses to XMC_EBU_BUS_READ_CONFIG_t - * - Added ebu_device_addressing_mode and ebu_data_hold_cycles_for_write_accesses to XMC_EBU_BUS_WRITE_CONFIG_t - * - * 2017-06-24: - * - Changed XMC_EBU_AddressSelectEnable() to make sure arbitartion mode is active - * - * @endcond - * - */ - + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond + * + */ + #ifndef XMC_EBU_H #define XMC_EBU_H /********************************************************************************************************************** * HEADER FILES *********************************************************************************************************************/ - -#include + +#include "xmc_common.h" #if defined (EBU) -#include +#include "xmc_scu.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup EBU * @brief External Bus Unit (EBU) driver for the XMC45/XMC47/XMC48 microcontroller * - * The External Bus Unit (EBU) controls the transactions between external memories or - * peripheral units, and the internal memories and peripheral units. Several external - * device configurations are supported; e.g. Asynchronous static memories, SDRAM - * and various flash memory types. It supports multiple programmable address regions. + * The External Bus Unit (EBU) controls the transactions between external memories or + * peripheral units, and the internal memories and peripheral units. Several external + * device configurations are supported; e.g. Asynchronous static memories, SDRAM + * and various flash memory types. It supports multiple programmable address regions. * * The EBU low level driver provides functions to configure and initialize the EBU - * hardware peripheral. + * hardware peripheral. * @{ */ - + /********************************************************************************************************************** * MACROS **********************************************************************************************************************/ @@ -102,10 +89,10 @@ /********************************************************************************************************************** * ENUMS **********************************************************************************************************************/ - + /** * Status return values for EBU low level driver - */ + */ typedef enum XMC_EBU_STATUS { XMC_EBU_STATUS_OK = 0U, /**< Operation successful */ @@ -309,11 +296,11 @@ typedef enum XMC_EBU_DEVICE_ADDRESSING_MODE */ typedef enum XMC_EBU_WAIT_CONTROL { - XMC_EBU_WAIT_CONTROL_OFF = 0U, /**< Default after reset; Wait control off */ + XMC_EBU_WAIT_CONTROL_OFF = 0U, /**< Default after reset; Wait control off */ XMC_EBU_WAIT_CONTROL_SYNC_EARLY_WAIT_ASYNC_ASYNC_INPUT_AT_WAIT = 1U, /**< SYNC: Wait for page load (Early WAIT); - ASYNC: Asynchronous input at WAIT */ + ASYNC: Asynchronous input at WAIT */ XMC_EBU_WAIT_CONTROL_SYNC_WAIT_WITH_DATA_ASYNC_SYNC_INPUT_AT_WAIT = 2U, /**< SYNC: Wait for page load (WAIT with data); - ASYNC: Synchronous input at WAIT; */ + ASYNC: Synchronous input at WAIT; */ XMC_EBU_WAIT_CONTROL_SYNC_ABORT_AND_RETRY_ACCESS = 3U /**< SYNC: Abort and retry access; */ } XMC_EBU_WAIT_CONTROL_t; @@ -482,13 +469,13 @@ typedef enum XMC_EBU_SDRAM_RFRSH_STATUS /********************************************************************************************************************** * DATA STRUCTURES *********************************************************************************************************************/ - + /* Anonymous structure/union guard start */ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined (__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -498,11 +485,11 @@ typedef enum XMC_EBU_SDRAM_RFRSH_STATUS * values for clock mode, div2 clock mode and clock divide ratio of EBU. * The XMC_EBU_Init() can be used to populate the structure with the clock * configuration values of the EBU module. - */ + */ typedef struct XMC_EBU_CLK_CONFIG { union - { + { uint32_t raw0; struct { @@ -522,9 +509,9 @@ typedef struct XMC_EBU_CLK_CONFIG * SDRAM tristate, external clock, arbitration, timeout control and ALE mode for * EBU. The XMC_EBU_Init() can be used to populate the structure with the * clock configuration values of the EBU module. - */ + */ typedef struct XMC_EBU_MODE_CONFIG -{ +{ union { uint32_t raw0; @@ -551,7 +538,7 @@ typedef struct XMC_EBU_MODE_CONFIG * Configuring this structure frees the allocated EBU ports for GPIO * functionality. The XMC_EBU_Init() is used to populate the structure * with the GPIO mode for the allocated EBU ports. - */ + */ typedef struct XMC_EBU_FREE_PINS_TO_GPIO { union @@ -573,7 +560,7 @@ typedef struct XMC_EBU_FREE_PINS_TO_GPIO * The structure presents a convenient way to set/obtain the read and read timing * configuration for a region for EBU. The XMC_EBU_ConfigureRegion() can be * used to populate the structure with the read configuration values for EBU. - */ + */ typedef struct XMC_EBU_BUS_READ_CONFIG { /* EBU read configuration parameters */ @@ -600,7 +587,7 @@ typedef struct XMC_EBU_BUS_READ_CONFIG uint32_t : 1; uint32_t ebu_device_type : 4; /**< Device type for region (::XMC_EBU_DEVICE_TYPE_t) */ }; - }; + }; /* EBU read access parameters */ union { @@ -660,27 +647,27 @@ typedef struct XMC_EBU_BUS_READ_CONFIG * 1110B: 14 clock cycles selected
        * 1111B: 15 clock cycles selected
        */ - uint32_t command_delay_lines : 4; - /** - * Address hold cycles:
        - * This bit field determines the number of clock cycles of the address hold phase.
        - * 0000B: 0 clock cycle selected
        - * 0001B: 1 clock cycle selected
        - * ...
        - * 1110B: 14 clock cycles selected
        - * 1111B: 15 clock cycles selected
        - */ - uint32_t address_hold_cycles : 4; - /** - * Address Cycles: - * This bit field determines the number of clock cycles of the address phase.
        - * 0000B: 1 clock cycle selected
        - * 0001B: 1 clock cycle selected
        - * ...
        - * 1110B: 14 clock cycles selected
        - * 1111B: 15 clock cycles selected
        - */ - uint32_t address_cycles : 4; + uint32_t command_delay_lines : 4; + /** + * Address hold cycles:
        + * This bit field determines the number of clock cycles of the address hold phase.
        + * 0000B: 0 clock cycle selected
        + * 0001B: 1 clock cycle selected
        + * ...
        + * 1110B: 14 clock cycles selected
        + * 1111B: 15 clock cycles selected
        + */ + uint32_t address_hold_cycles : 4; + /** + * Address Cycles: + * This bit field determines the number of clock cycles of the address phase.
        + * 0000B: 1 clock cycle selected
        + * 0001B: 1 clock cycle selected
        + * ...
        + * 1110B: 14 clock cycles selected
        + * 1111B: 15 clock cycles selected
        + */ + uint32_t address_cycles : 4; }; }; } XMC_EBU_BUS_READ_CONFIG_t; @@ -691,7 +678,7 @@ typedef struct XMC_EBU_BUS_READ_CONFIG * The structure presents a convenient way to set/obtain the write and write timing * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be used * to populate the structure with the write configuration values of EBU. - */ + */ typedef struct XMC_EBU_BUS_WRITE_CONFIG { /* EBU write configuration parameters */ @@ -736,7 +723,7 @@ typedef struct XMC_EBU_BUS_WRITE_CONFIG * Recovery cycles after write accesses:
        * This bit field determines the basic number of clock cycles of the Recovery Phase at the end of write accesses.
        * 000B: No recovery phase clock cycles available
        - * 001B: 1 clock cycle selected
        + * 001B: 1 clock cycle selected
        * ...
        * 110B: 6 clock cycles selected
        * 111B: 7 clock cycles selected
        @@ -801,10 +788,10 @@ typedef struct XMC_EBU_BUS_WRITE_CONFIG * 1110B: 14 clock cycles selected
        * 1111B: 15 clock cycles selected
        */ - uint32_t address_cycles : 4; + uint32_t address_cycles : 4; }; }; -}XMC_EBU_BUS_WRITE_CONFIG_t; +} XMC_EBU_BUS_WRITE_CONFIG_t; /** * SDRAM configuration structure
        @@ -824,22 +811,22 @@ typedef struct XMC_EBU_SDRAM_CONFIG { /** * Number of clock cycles between row activate command and a precharge - * command + * command */ uint32_t ebu_row_precharge_delay_counter : 4; - /** + /** * (CRFSH) Number of refresh commands issued during powerup init sequence: * Perform CRFSH + 1 refresh cycles */ uint32_t ebu_init_refresh_commands_counter : 4; /** * (CRSC) Number of NOP cycles after a mode register set command: - * Insert CRSC + 1 NOP cycles + * Insert CRSC + 1 NOP cycles */ uint32_t ebu_mode_register_set_up_time : 2; /** * (CRP) Number of NOP cycles inserted after a precharge command: - * Insert CRP + 1 NOP cycles + * Insert CRP + 1 NOP cycles */ uint32_t ebu_row_precharge_time_counter : 2; /** @@ -916,7 +903,7 @@ typedef struct XMC_EBU_SDRAM_CONFIG }; /* EBU SDRAM refresh parameters */ union - { + { uint32_t raw2; struct { @@ -974,9 +961,9 @@ typedef struct XMC_EBU_SDRAM_CONFIG /* Anonymous structure/union guard end */ #if defined (__CC_ARM) - #pragma pop +#pragma pop #elif defined (__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** @@ -984,8 +971,8 @@ typedef struct XMC_EBU_SDRAM_CONFIG * * The structure presents a convenient way to set/obtain the read and read timing * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be - * used to populate the structure with the read configuration values of EBU - */ + * used to populate the structure with the read configuration values of EBU + */ typedef struct XMC_EBU_REGION_READ_CONFIG { const uint32_t ebu_region_no; /**< Number of region*/ @@ -999,7 +986,7 @@ typedef struct XMC_EBU_REGION_READ_CONFIG * timing configurations for a region of EBU. The XMC_EBU_ConfigureRegion() * can be used to populate the structure with the write configuration * values of EBU. - */ + */ typedef struct XMC_EBU_REGION_WRITE_CONFIG { const uint32_t ebu_region_no; /**< Number of refresh counter period */ @@ -1013,7 +1000,7 @@ typedef struct XMC_EBU_REGION_WRITE_CONFIG * write and write timing configurations for a region of EBU. The * XMC_EBU_ConfigureRegion() can be used to populate the structure with the * region read and write configuration values of EBU. - */ + */ typedef struct XMC_EBU_REGION { XMC_EBU_REGION_READ_CONFIG_t read_config; @@ -1027,14 +1014,14 @@ typedef struct XMC_EBU_REGION * of the EBU like clock, mode and GPIO mode. The XMC_EBU_Init() can be * used to populate the structure with the region read and write configuration * values of EBU. - */ + */ typedef struct XMC_EBU_CONFIG { XMC_EBU_CLK_CONFIG_t ebu_clk_config; /**< Clock configuration structure */ XMC_EBU_MODE_CONFIG_t ebu_mode_config; /**< Mode configuration structure */ XMC_EBU_FREE_PINS_TO_GPIO_t ebu_free_pins_to_gpio; /**< Free allocated EBU ports for GPIO */ } XMC_EBU_CONFIG_t; - + /** * External Bus Unit (EBU) device structure
        * @@ -1066,7 +1053,7 @@ typedef struct /********************************************************************************************************************** * API PROTOTYPES **********************************************************************************************************************/ - + #ifdef __cplusplus extern "C" { #endif @@ -1165,7 +1152,7 @@ __STATIC_INLINE void XMC_EBU_Disable(XMC_EBU_t *const ebu) /** * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address - * @param clk_status Constant structure ::XMC_EBU_CLK_STATUS_t, containing the + * @param clk_status Constant structure ::XMC_EBU_CLK_STATUS_t, containing the * disable status, clock mode status, DIV2 clock mode status * and clock divide ratio * @return Status Returns clock status, disable status, clock mode status, DIV2 clock @@ -1184,7 +1171,7 @@ __STATIC_INLINE void XMC_EBU_Disable(XMC_EBU_t *const ebu) * * \parRelated APIs:
        * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_CLKDivideRatio() - */ + */ __STATIC_INLINE uint32_t XMC_EBU_GetCLKStatus(XMC_EBU_t *const ebu, const XMC_EBU_CLK_STATUS_t clk_status) { XMC_ASSERT("XMC_EBU_GetCLKStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); @@ -1193,8 +1180,8 @@ __STATIC_INLINE uint32_t XMC_EBU_GetCLKStatus(XMC_EBU_t *const ebu, const XMC_EB /** * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address - * @param clock_divide_ratio Structure ::XMC_EBU_CLOCK_DIVIDE_RATIO_t, containing the - * clock division factors of 1, 2, 3 and 4 respectively + * @param clock_divide_ratio Structure ::XMC_EBU_CLOCK_DIVIDE_RATIO_t, containing the + * clock division factors of 1, 2, 3 and 4 respectively * @return None * * \parDescription:
        @@ -1214,7 +1201,7 @@ __STATIC_INLINE void XMC_EBU_CLKDivideRatio(XMC_EBU_t *ebu, XMC_EBU_CLOCK_DIVIDE } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1232,7 +1219,7 @@ __STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshExit(XMC_EBU_t *const ebu) } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1251,7 +1238,7 @@ __STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshEntry(XMC_EBU_t *const ebu) } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1270,7 +1257,7 @@ __STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshExit(XMC_EBU_t *const ebu) } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1289,7 +1276,7 @@ __STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshEntry(XMC_EBU_t *const ebu) } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1309,7 +1296,7 @@ __STATIC_INLINE void XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit(XMC_EBU_t *co } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1330,7 +1317,7 @@ __STATIC_INLINE void XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit(XMC_EBU_t *c } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1338,13 +1325,13 @@ __STATIC_INLINE void XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit(XMC_EBU_t *c * * \par * The function sets the SDRMREF.AUTOSELFR bit-field. When set, the memory controller - * automatically issues the self refresh entry command to all SDRAM units + * automatically issues the self refresh entry command to all SDRAM units * devices when it gives up control of the external bus. It will also automatically * issue the self refresh exit command when it regains control of the bus. * * \parRelated APIs:
        * XMC_EBU_SdramDisableAutomaticSelfRefresh() - */ + */ __STATIC_INLINE void XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t *const ebu) { XMC_ASSERT("XMC_EBU_SdramEnableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); @@ -1352,7 +1339,7 @@ __STATIC_INLINE void XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t *const eb } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return None * * \parDescription:
        @@ -1366,7 +1353,7 @@ __STATIC_INLINE void XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t *const eb * * \parRelated APIs:
        * XMC_EBU_SdramEnableAutomaticSelfRefresh() - */ + */ __STATIC_INLINE void XMC_EBU_SdramDisableAutomaticSelfRefresh(XMC_EBU_t *const ebu) { XMC_ASSERT("XMC_EBU_SdramDisableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); @@ -1374,7 +1361,7 @@ __STATIC_INLINE void XMC_EBU_SdramDisableAutomaticSelfRefresh(XMC_EBU_t *const e } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return bool Returns if the arbitration mode is selected or not * * \parDescription:
        @@ -1417,10 +1404,10 @@ __STATIC_INLINE bool XMC_EBU_IsBusAribitrationSelected(XMC_EBU_t *const ebu) * * \parRelated APIs:
        * XMC_EBU_AddressSelectDisable() - */ + */ __STATIC_INLINE void XMC_EBU_AddressSelectEnable(XMC_EBU_t *const ebu, - uint32_t ebu_addr_select_en, - const uint32_t ebu_region_n) + uint32_t ebu_addr_select_en, + const uint32_t ebu_region_n) { XMC_ASSERT("XMC_EBU_AddressSelectEnable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); ebu->ADDRSEL[ebu_region_n] |= ebu_addr_select_en; @@ -1428,7 +1415,7 @@ __STATIC_INLINE void XMC_EBU_AddressSelectEnable(XMC_EBU_t *const ebu, } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @param ebu_addr_select_dis Choose between a memory region disable or an alternate * region disable * @param ebu_region_n A valid region number for which disable and protection @@ -1446,17 +1433,17 @@ __STATIC_INLINE void XMC_EBU_AddressSelectEnable(XMC_EBU_t *const ebu, * * \parRelated APIs:
        * XMC_EBU_AddressSelectEnable() - */ + */ __STATIC_INLINE void XMC_EBU_AddressSelectDisable(XMC_EBU_t *const ebu, - uint32_t ebu_addr_select_dis, - const uint32_t ebu_region_n) + uint32_t ebu_addr_select_dis, + const uint32_t ebu_region_n) { XMC_ASSERT("XMC_EBU_AddressSelectDisable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); ebu->ADDRSEL[ebu_region_n] &= ~ebu_addr_select_dis; } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @param ebu_buswcon_status Enumeration of type ::XMC_EBU_BUSWCON_SELECT_t, representing * values for non-array access and device addressing modes. * @param ebu_region_n A valid region number for which status pertaining to WRITE is required @@ -1472,22 +1459,22 @@ __STATIC_INLINE void XMC_EBU_AddressSelectDisable(XMC_EBU_t *const ebu, * * \parRelated APIs:
        * XMC_EBU_ConfigureRegion() - */ + */ __STATIC_INLINE uint32_t XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t *const ebu, - const XMC_EBU_BUSWCON_SELECT_t ebu_buswcon_status, - const uint32_t ebu_region_n) + const XMC_EBU_BUSWCON_SELECT_t ebu_buswcon_status, + const uint32_t ebu_region_n) { XMC_ASSERT("XMC_EBU_GetBusWriteConfStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); return (ebu->BUS[ebu_region_n].WRCON & ebu_buswcon_status); } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @return Status SDRAM error or busy states * * \parDescription:
        * Gets SDRAM error or busy states
        - * + * * \par * The function gets SDRAM read error, refresh error and busy states. The bit-fields of SDRSTAT * indicate the various states. REFERR reflects a failed previous refresh request collision @@ -1497,7 +1484,7 @@ __STATIC_INLINE uint32_t XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t *const ebu, * * \parRelated APIs:
        * XMC_EBU_ConfigureSdram() - */ + */ __STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu) { XMC_ASSERT("XMC_EBU_SdramGetStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); @@ -1505,13 +1492,13 @@ __STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu) } /** - * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address + * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address * @param sdram_rfrsh_status Constant enum of type ::XMC_EBU_SDRAM_RFRSH_STATUS_t * @return Status Status of self refresh entry and exit command issue * * \parDescription:
        * Gets SDRAM refresh status
        - * + * * \par * The function gets SDRAM refresh status for self refresh entry/exit command successful issue. * The bit-fields of SDRMREF indicate various states:
        @@ -1520,9 +1507,9 @@ __STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu) * * \parRelated APIs:
        * XMC_EBU_SdramResetSelfRefreshEntry(), XMC_EBU_SdramResetSelfRefreshExit() - */ + */ __STATIC_INLINE uint32_t XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t *const ebu, - const XMC_EBU_SDRAM_RFRSH_STATUS_t sdram_rfrsh_status) + const XMC_EBU_SDRAM_RFRSH_STATUS_t sdram_rfrsh_status) { XMC_ASSERT("XMC_EBU_SdramGetRefreshStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); return (uint32_t)(ebu->SDRMREF & sdram_rfrsh_status); @@ -1533,10 +1520,6 @@ __STATIC_INLINE uint32_t XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t *const ebu, } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ecat.h b/cores/xmc_lib/XMCLib/inc/xmc_ecat.h index 4a800b65..dad90650 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_ecat.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_ecat.h @@ -1,52 +1,46 @@ /** * @file xmc_ecat.h - * @date 2015-12-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-12-27: - * - Initial Version
        + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup ECAT @@ -62,7 +56,7 @@ * Slave Controller processes the frame in hardware. Thus, communication performance is independent from processor * power. * - * The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral. + * The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral. * For EHTERCAT stack integration, the necessary hardware accees layer APIs shall be explicitly implemented depending * upon the stack provider. The XMC_ECAT lld layer provides only the hardware initialization functions for start up and * basic functionalities. @@ -139,7 +133,7 @@ typedef enum XMC_ECAT_EVENT */ typedef struct XMC_ECAT_PORT_CTRL { - union + union { struct { @@ -158,8 +152,8 @@ typedef struct XMC_ECAT_PORT_CTRL uint32_t raw; } common; - union - { + union + { struct { uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT0_CTRL_RXD0_t) */ @@ -179,8 +173,8 @@ typedef struct XMC_ECAT_PORT_CTRL uint32_t raw; } port0; - union - { + union + { struct { uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT_CTRL_RXD0_t) */ @@ -199,7 +193,7 @@ typedef struct XMC_ECAT_PORT_CTRL uint32_t raw; } port1; - + } XMC_ECAT_PORT_CTRL_t; /** @@ -448,15 +442,12 @@ __STATIC_INLINE void XMC_ECAT_SetALEventMask(uint16_t intMask) #ifdef __cplusplus } #endif - -/** - * @} - */ - + /** * @} */ - + + #endif /* defined (ECAT) */ #endif /* XMC_ECAT_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ecat_map.h b/cores/xmc_lib/XMCLib/inc/xmc_ecat_map.h index 4d7997f6..734e97a5 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_ecat_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_ecat_map.h @@ -1,46 +1,41 @@ /** * @file xmc_ecat_map.h - * @date 2016-07-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-09-09: - * - Initial + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-07-20: - * - Added XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 and XMC_ECAT_PORT_CTRL_LATCHIN0_P9_1 + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -50,42 +45,46 @@ /** * ECAT PORT 0 receive data 0 line - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_RXD0 { XMC_ECAT_PORT0_CTRL_RXD0_P1_4 = 0U, /**< RXD0A receive data line */ XMC_ECAT_PORT0_CTRL_RXD0_P5_0 = 1U, /**< RXD0B receive data line */ XMC_ECAT_PORT0_CTRL_RXD0_P7_4 = 2U, /**< RXD0C receive data line */ + XMC_ECAT_PORT0_CTRL_RXD0_GND = 3U, /**< RXD0D receive data line */ } XMC_ECAT_PORT0_CTRL_RXD0_t; /** * ECAT PORT 0 receive data 1 line - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_RXD1 { XMC_ECAT_PORT0_CTRL_RXD1_P1_5 = 0U, /**< RXD1A receive data line */ XMC_ECAT_PORT0_CTRL_RXD1_P5_1 = 1U, /**< RXD1B receive data line */ XMC_ECAT_PORT0_CTRL_RXD1_P7_5 = 2U, /**< RXD1C receive data line */ + XMC_ECAT_PORT0_CTRL_RXD1_GND = 3U, /**< RXD1D receive data line */ } XMC_ECAT_PORT0_CTRL_RXD1_t; /** * ECAT PORT 0 receive data 2 line - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_RXD2 { XMC_ECAT_PORT0_CTRL_RXD2_P1_10 = 0U, /**< RXD2A receive data line */ XMC_ECAT_PORT0_CTRL_RXD2_P5_2 = 1U, /**< RXD2B receive data line */ - XMC_ECAT_PORT0_CTRL_RXD2_P7_6 = 2U /**< RXD2C receive data line */ + XMC_ECAT_PORT0_CTRL_RXD2_P7_6 = 2U, /**< RXD2C receive data line */ + XMC_ECAT_PORT0_CTRL_RXD2_GND = 3U /**< RXD2D receive data line */ } XMC_ECAT_PORT0_CTRL_RXD2_t; /** * ECAT PORT 0 receive data 3 line - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_RXD3 { XMC_ECAT_PORT0_CTRL_RXD3_P1_11 = 0U, /**< RXD3A Receive data line */ XMC_ECAT_PORT0_CTRL_RXD3_P5_7 = 1U, /**< RXD3B Receive data line */ - XMC_ECAT_PORT0_CTRL_RXD3_P7_7 = 2U /**< RXD3C Receive data line */ + XMC_ECAT_PORT0_CTRL_RXD3_P7_7 = 2U, /**< RXD3C Receive data line */ + XMC_ECAT_PORT0_CTRL_RXD3_GND = 3U /**< RXD3D Receive data line */ } XMC_ECAT_PORT0_CTRL_RXD3_t; /** @@ -95,27 +94,30 @@ typedef enum XMC_ECAT_PORT0_CTRL_RX_ERR { XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0 = 0U, /**< RX_ERRA Receive error line */ XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6 = 1U, /**< RX_ERRB Receive error line */ - XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9 = 2U /**< RX_ERRC Receive error line */ + XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9 = 2U, /**< RX_ERRC Receive error line */ + XMC_ECAT_PORT0_CTRL_RX_ERR_GND = 3U /**< RX_ERRD Receive error line */ } XMC_ECAT_PORT0_CTRL_RX_ERR_t; /** * ECAT PORT 0 receive clock line - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_RX_CLK { XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1 = 0U, /**< RX_CLKA Recevive clock */ XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4 = 1U, /**< RX_CLKB Recevive clock */ XMC_ECAT_PORT0_CTRL_RX_CLK_P7_10 = 2U, /**< RX_CLKC Recevive clock */ + XMC_ECAT_PORT0_CTRL_RX_CLK_GND = 3U, /**< RX_CLKD Recevive clock */ } XMC_ECAT_PORT0_CTRL_RX_CLK_t; /** * ECAT PORT 0 data valid - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_RX_DV { XMC_ECAT_PORT0_CTRL_RX_DV_P1_9 = 0U, /**< RX_DVA Receive data valid */ XMC_ECAT_PORT0_CTRL_RX_DV_P5_6 = 1U, /**< RX_DVB Receive data valid */ XMC_ECAT_PORT0_CTRL_RX_DV_P7_11 = 2U, /**< RX_DVC Receive data valid */ + XMC_ECAT_PORT0_CTRL_RX_DV_GND = 3U, /**< RX_DVD Receive data valid */ } XMC_ECAT_PORT0_CTRL_RX_DV_t; /** @@ -126,16 +128,18 @@ typedef enum XMC_ECAT_PORT0_CTRL_LINK XMC_ECAT_PORT0_CTRL_LINK_P4_1 = 0U, /**< LINKA Link status */ XMC_ECAT_PORT0_CTRL_LINK_P1_15 = 1U, /**< LINKB Link status */ XMC_ECAT_PORT0_CTRL_LINK_P9_10 = 2U, /**< LINKC Link status */ + XMC_ECAT_PORT0_CTRL_LINK_GND = 3U, /**< LINKD Link status */ } XMC_ECAT_PORT0_CTRL_LINK_t; /** * ECAT PORT 0 transmit clock - */ + */ typedef enum XMC_ECAT_PORT0_CTRL_TX_CLK { XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0 = 0U, /**< TX_CLKA transmit clock */ XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5 = 1U, /**< TX_CLKB transmit clock */ XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1 = 2U, /**< TX_CLKC transmit clock */ + XMC_ECAT_PORT0_CTRL_TX_CLK_GND = 3U, /**< TX_CLKD transmit clock */ } XMC_ECAT_PORT0_CTRL_TX_CLK_t; /** @@ -146,6 +150,7 @@ typedef enum XMC_ECAT_PORT1_CTRL_RXD0 XMC_ECAT_PORT1_CTRL_RXD0_P0_11 = 0U, /**< RXD0A receive data line */ XMC_ECAT_PORT1_CTRL_RXD0_P14_7 = 1U, /**< RXD0B receive data line */ XMC_ECAT_PORT1_CTRL_RXD0_P8_4 = 2U, /**< RXD0C receive data line */ + XMC_ECAT_PORT1_CTRL_RXD0_GND = 3U, /**< RXD0D receive data line */ } XMC_ECAT_PORT1_CTRL_RXD0_t; /** @@ -156,6 +161,7 @@ typedef enum XMC_ECAT_PORT1_CTRL_RXD1 XMC_ECAT_PORT1_CTRL_RXD1_P0_6 = 0U, /**< RXD1A receive data line */ XMC_ECAT_PORT1_CTRL_RXD1_P14_12 = 1U, /**< RXD1B receive data line */ XMC_ECAT_PORT1_CTRL_RXD1_P8_5 = 2U, /**< RXD1C receive data line */ + XMC_ECAT_PORT1_CTRL_RXD1_GND = 3U, /**< RXD1D receive data line */ } XMC_ECAT_PORT1_CTRL_RXD1_t; /** @@ -165,7 +171,8 @@ typedef enum XMC_ECAT_PORT1_CTRL_RXD2 { XMC_ECAT_PORT1_CTRL_RXD2_P0_5 = 0U, /**< RXD2A receive data line */ XMC_ECAT_PORT1_CTRL_RXD2_P14_13 = 1U, /**< RXD2B receive data line */ - XMC_ECAT_PORT1_CTRL_RXD2_P8_6 = 2U /**< RXD2C receive data line */ + XMC_ECAT_PORT1_CTRL_RXD2_P8_6 = 2U, /**< RXD2C receive data line */ + XMC_ECAT_PORT1_CTRL_RXD2_GND = 3U /**< RXD2D receive data line */ } XMC_ECAT_PORT1_CTRL_RXD2_t; /** @@ -175,7 +182,8 @@ typedef enum XMC_ECAT_PORT1_CTRL_RXD3 { XMC_ECAT_PORT1_CTRL_RXD3_P0_4 = 0U, /**< RXD3A Receive data line */ XMC_ECAT_PORT1_CTRL_RXD3_P14_14 = 1U, /**< RXD3B Receive data line */ - XMC_ECAT_PORT1_CTRL_RXD3_P8_7 = 2U /**< RXD3C Receive data line */ + XMC_ECAT_PORT1_CTRL_RXD3_P8_7 = 2U, /**< RXD3C Receive data line */ + XMC_ECAT_PORT1_CTRL_RXD3_GND = 3U /**< RXD3D Receive data line */ } XMC_ECAT_PORT1_CTRL_RXD3_t; /** @@ -185,7 +193,8 @@ typedef enum XMC_ECAT_PORT1_CTRL_RX_ERR { XMC_ECAT_PORT1_CTRL_RX_ERR_P3_5 = 0U, /**< RX_ERRA Receive error line */ XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2 = 1U, /**< RX_ERRB Receive error line */ - XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9 = 2U /**< RX_ERRC Receive error line */ + XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9 = 2U, /**< RX_ERRC Receive error line */ + XMC_ECAT_PORT1_CTRL_RX_ERR_GND = 3U /**< RX_ERRD Receive error line */ } XMC_ECAT_PORT1_CTRL_RX_ERR_t; /** @@ -196,6 +205,7 @@ typedef enum XMC_ECAT_PORT1_CTRL_RX_CLK XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1 = 0U, /**< RX_CLKA Recevive clock */ XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6 = 1U, /**< RX_CLKB Recevive clock */ XMC_ECAT_PORT1_CTRL_RX_CLK_P8_10 = 2U, /**< RX_CLKC Recevive clock */ + XMC_ECAT_PORT1_CTRL_RX_CLK_GND = 3U, /**< RX_CLKD Recevive clock */ } XMC_ECAT_PORT1_CTRL_RX_CLK_t; /** @@ -206,6 +216,7 @@ typedef enum XMC_ECAT_PORT1_CTRL_RX_DV XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */ XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */ XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */ + XMC_ECAT_PORT1_CTRL_RX_DV_GND = 3U, /**< RX_DVD Receive data valid */ } XMC_ECAT_PORT1_CTRL_RX_DV_t; /** @@ -216,6 +227,7 @@ typedef enum XMC_ECAT_PORT1_CTRL_LINK XMC_ECAT_PORT1_CTRL_LINK_P3_4 = 0U, /**< LINKA Link status */ XMC_ECAT_PORT1_CTRL_LINK_P15_3 = 1U, /**< LINKB Link status */ XMC_ECAT_PORT1_CTRL_LINK_P9_11 = 2U, /**< LINKC Link status */ + XMC_ECAT_PORT1_CTRL_LINK_GND = 3U, /**< LINKD Link status */ } XMC_ECAT_PORT1_CTRL_LINK_t; /** @@ -226,16 +238,18 @@ typedef enum XMC_ECAT_PORT1_CTRL_TX_CLK XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10 = 0U, /**< TX_CLKA transmit clock */ XMC_ECAT_PORT1_CTRL_TX_CLK_P5_9 = 1U, /**< TX_CLKB transmit clock */ XMC_ECAT_PORT1_CTRL_TX_CLK_P9_0 = 2U, /**< TX_CLKC transmit clock */ + XMC_ECAT_PORT1_CTRL_TX_CLK_GND = 3U, /**< TX_CLKD transmit clock */ } XMC_ECAT_PORT1_CTRL_TX_CLK_t; /** * ECAT management data I/O - */ + */ typedef enum XMC_ECAT_PORT_CTRL_MDIO { XMC_ECAT_PORT_CTRL_MDIO_P0_12 = 0U, /**< MDIOA management data I/O */ XMC_ECAT_PORT_CTRL_MDIO_P4_2 = 1U, /**< MDIOB management data I/O */ - XMC_ECAT_PORT_CTRL_MDIO_P9_7 = 2U /**< MDIOC management data I/O */ + XMC_ECAT_PORT_CTRL_MDIO_P9_7 = 2U, /**< MDIOC management data I/O */ + XMC_ECAT_PORT_CTRL_MDIO_GND = 3U /**< MDIOD management data I/O */ } XMC_ECAT_PORT_CTRL_MDIO_t; /** @@ -247,7 +261,7 @@ typedef enum XMC_ECAT_PORT_CTRL_LATCHIN0 XMC_ECAT_PORT_CTRL_LATCHIN0_9_0 = 1U, /**< LATCH0B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 */ XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 = 1U, /**< LATCH0B line */ XMC_ECAT_PORT_CTRL_LATCHIN0_ERU0_PDOUT0 = 2U, /**< LATCH0C line */ - XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0 = 3U, /**< LATCH0D line */ + XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0 = 3U, /**< LATCH0D line */ } XMC_ECAT_PORT_CTRL_LATCHIN0_t; /** @@ -259,7 +273,7 @@ typedef enum XMC_ECAT_PORT_CTRL_LATCHIN1 XMC_ECAT_PORT_CTRL_LATCHIN1_9_1 = 1U, /**< LATCH1 B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 */ XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 = 1U, /**< LATCH1 B line */ XMC_ECAT_PORT_CTRL_LATCHIN1_ERU0_PDOUT1 = 2U, /**< LATCH1C line */ - XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1 = 3U, /**< LATCH1D line */ + XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1 = 3U, /**< LATCH1D line */ } XMC_ECAT_PORT_CTRL_LATCHIN1_t; /** diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eru.h b/cores/xmc_lib/XMCLib/inc/xmc_eru.h index c2291cdb..c2fd2f4b 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_eru.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_eru.h @@ -1,53 +1,41 @@ /** * @file xmc_eru.h - * @date 2016-03-10 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
        - * - Documentation updates
        - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
        - * - * 2015-10-07: - * - Doc update for XMC_ERU_ETL_CONFIG_t field
        - * - * 2016-03-10: - * - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation.
        + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -61,25 +49,22 @@ #include "xmc_common.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** + * \anchor brief_pdlapi_eru * @addtogroup ERU * @brief Event Request Unit (ERU) driver for the XMC microcontroller family. * * The Event Request Unit (ERU) is a versatile multiple input event detection and processing unit. - * The ERU module can be used to expand the P-to-P connections of the device: ports-to-peripherals, - * peripherals-to-peripherals and ports-to-ports. It also offers configurable logic, that allows the generation of + * The ERU module can be used to expand the P-to-P connections of the device: ports-to-peripherals, + * peripherals-to-peripherals and ports-to-ports. It also offers configurable logic, that allows the generation of * triggers, pattern detection and real-time signal monitoring. * * @image html "eru_overview.png" * * The driver is divided into two sections: * \par Event trigger logic (ERU_ETL): - * This section of the LLD provides the configuration structure XMC_ERU_ETL_CONFIG_t and the initialization function + * This section of the LLD provides the configuration structure XMC_ERU_ETL_CONFIG_t and the initialization function * XMC_ERU_ETL_Init().\n * It can be used to: * -# Select one out of two inputs (A and B). For each of these two inputs, a vector of 4 possible signals is available. @@ -93,7 +78,7 @@ * This section of the LLD provides the provides the configuration structure XMC_ERU_OGU_CONFIG_t and the initialization * function XMC_ERU_ETL_OGU_Init(). * It can be used to: - * -# Combine the trigger events and status information and gates the output depending on a gating signal. + * -# Combine the trigger events and status information and gates the output depending on a gating signal. * (XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_SetServiceRequestMode()) * @{ */ @@ -111,11 +96,11 @@ #endif #if UC_FAMILY == XMC1 - #include "xmc1_eru_map.h" +#include "xmc1_eru_map.h" #endif #if UC_FAMILY == XMC4 - #include "xmc4_eru_map.h" +#include "xmc4_eru_map.h" #endif #if defined(XMC_ERU0) && defined(XMC_ERU1) @@ -220,23 +205,23 @@ typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER typedef enum XMC_ERU_ETL_STATUS_FLAG_MODE { XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL = 0U, /**< Status flag is in sticky mode. Retain the same state until - cleared by software. In case of pattern match this mode + cleared by software. In case of pattern match this mode is used. */ XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL = 1U /**< Status flag is in non-sticky mode. Automatically cleared by the opposite edge detection.\n - eg. if positive edge is selected as trigger event, for the + eg. if positive edge is selected as trigger event, for the negative edge event the status flag is cleared. */ } XMC_ERU_ETL_STATUS_FLAG_MODE_t; /** * Defines pattern detection feature to be enabled or not in OGUy(Output gating unit, y = [0 to 3]). - * + * */ typedef enum XMC_ERU_OGU_PATTERN_DETECTION { XMC_ERU_OGU_PATTERN_DETECTION_DISABLED = 0U, /**< Pattern match is disabled */ XMC_ERU_OGU_PATTERN_DETECTION_ENABLED = 1U /**< Pattern match is enabled, the selected status flags of - ETLx(Event Trigger Logic, x = [0 to 3]) unit, are + ETLx(Event Trigger Logic, x = [0 to 3]) unit, are used in pattern detection. */ } XMC_ERU_OGU_PATTERN_DETECTION_t; @@ -273,10 +258,10 @@ typedef enum XMC_ERU_OGU_SERVICE_REQUEST XMC_ERU_OGU_SERVICE_REQUEST_DISABLED = 0U, /**< Service request blocked, ERUx_GOUTy = 0 */ XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER = 1U, /**< Service request generated enabled, ERUx_GOUTy = 1 */ XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH = 2U, /**< Service request generated on trigger - event and input pattern match, + event and input pattern match, ERUx_GOUTy = ~pattern matching result*/ XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH = 3U/**< Service request generated on trigger - event and input pattern mismatch, + event and input pattern mismatch, ERUx_GOUTy = pattern matching result*/ } XMC_ERU_OGU_SERVICE_REQUEST_t; @@ -285,20 +270,23 @@ typedef enum XMC_ERU_OGU_SERVICE_REQUEST ********************************************************************************************************************/ /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** * ERU module */ -typedef struct { - union { +typedef struct XMC_ERU +{ + union + { __IO uint32_t EXISEL; - struct { + struct + { __IO uint32_t EXS0A : 2; __IO uint32_t EXS0B : 2; __IO uint32_t EXS1A : 2; @@ -311,10 +299,12 @@ typedef struct { }; __I uint32_t RESERVED0[3]; - union { - __IO uint32_t EXICON[4]; + union + { + __IO uint32_t EXICON[4]; - struct { + struct + { __IO uint32_t PE : 1; __IO uint32_t LD : 1; __IO uint32_t ED : 2; @@ -322,21 +312,23 @@ typedef struct { __IO uint32_t FL : 1; __IO uint32_t SS : 4; __I uint32_t RESERVED1 : 20; - } EXICON_b[4]; + } EXICON_b[4]; }; - union { - __IO uint32_t EXOCON[4]; + union + { + __IO uint32_t EXOCON[4]; - struct { + struct + { __IO uint32_t ISS : 2; __IO uint32_t GEEN : 1; __I uint32_t PDR : 1; __IO uint32_t GP : 2; - uint32_t : 6; + uint32_t : 6; __IO uint32_t IPEN : 4; __I uint32_t RESERVED2 : 16; - } EXOCON_b[4]; + } EXOCON_b[4]; }; } XMC_ERU_t; @@ -366,13 +358,13 @@ typedef struct XMC_ERU_ETL_CONFIG uint32_t raw; struct { - uint32_t enable_output_trigger: 1; /**< Enables the generation of trigger pulse(PE), for the configured edge + uint32_t enable_output_trigger: 1; /**< Enables the generation of trigger pulse(PE), for the configured edge detection. This accepts boolean values as input. */ - uint32_t status_flag_mode: 1; /**< Enables the status flag auto clear(LD), for the opposite edge of the + uint32_t status_flag_mode: 1; /**< Enables the status flag auto clear(LD), for the opposite edge of the configured event edge. This accepts boolean values as input. */ - uint32_t edge_detection: 2; /**< Configure the event trigger edge(FE, RE). + uint32_t edge_detection: 2; /**< Configure the event trigger edge(FE, RE). Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t for valid values. */ - uint32_t output_trigger_channel: 3; /**< Output channel select(OCS) for ETLx output trigger pulse. + uint32_t output_trigger_channel: 3; /**< Output channel select(OCS) for ETLx output trigger pulse. Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid values. */ uint32_t : 1; uint32_t source: 4; /**< Input path combination along with polarity for event generation. @@ -392,30 +384,30 @@ typedef struct XMC_ERU_ETL_CONFIG */ typedef union XMC_ERU_OGU_CONFIG { - uint32_t raw; - - struct - { - uint32_t peripheral_trigger: 2; /**< peripheral trigger(ISS) input selection. + uint32_t raw; + + struct + { + uint32_t peripheral_trigger: 2; /**< peripheral trigger(ISS) input selection. Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for valid values. */ - uint32_t enable_pattern_detection: 1; /**< Enable generation of(GEEN) event for pattern detection result change. + uint32_t enable_pattern_detection: 1; /**< Enable generation of(GEEN) event for pattern detection result change. This accepts boolean values as input. */ - uint32_t : 1; - uint32_t service_request: 2; /**< Gating(GP) on service request generation for pattern detection result. + uint32_t : 1; + uint32_t service_request: 2; /**< Gating(GP) on service request generation for pattern detection result. Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. */ - uint32_t : 6; - uint32_t pattern_detection_input: 4; /**< Enable input for the pattern detection(IPENx, x = [0 to 3]). - Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. + uint32_t : 6; + uint32_t pattern_detection_input: 4; /**< Enable input for the pattern detection(IPENx, x = [0 to 3]). + Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. OR combination of the enum items given as input */ - uint32_t : 16; - }; + uint32_t : 16; + }; } XMC_ERU_OGU_CONFIG_t; /*Anonymous structure/union guard end */ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * API PROTOTYPES @@ -438,13 +430,13 @@ extern "C" { * Abstract API, not mandatory to call.
        * \endif * \par - * This API is called by XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init() and therefore no need to call it explicitly during - * initialization sequence. Call this API to enable ERU1 module once again if the module is disabled by calling + * This API is called by XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init() and therefore no need to call it explicitly during + * initialization sequence. Call this API to enable ERU1 module once again if the module is disabled by calling * XMC_ERU_Disable(). For ERU0 module clock gating and reset features are not available. - * + * * \parNote:
        * \if XMC4 - * 1. Required to configure ERU1 module again after calling XMC_ERU_Disable(). Since the all the registers are + * 1. Required to configure ERU1 module again after calling XMC_ERU_Disable(). Since the all the registers are * reset with default values. * \endif * \parRelated APIs:
        @@ -481,15 +473,15 @@ void XMC_ERU_Disable(XMC_ERU_t *const eru); * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address * @param channel ERU_ETLx(Event trigger logic unit) channel * Range : [0 to 3] - * @param config pointer to a constant ERU_ETLx configuration data structure. + * @param config pointer to a constant ERU_ETLx configuration data structure. * Refer data structure XMC_ERU_ETL_CONFIG_t for detail. * * @return None * * Description:
        - * Initializes the selected ERU_ETLx \a channel with the \a config structure.
        + * Initializes the selected ERU_ETLx \a channel with the \a config structure.
        * - * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures + * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures *
          *
        • Input signal for path A and Path B,
          • *
        • Trigger pulse generation,
          • @@ -506,11 +498,11 @@ void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU * @param channel ERU_ETLx(Event trigger logic unit) channel. * Range : [0 to 3] * @param input_a input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.\n - * Refer XMC_ERU_ETL_INPUT_A_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of + * Refer XMC_ERU_ETL_INPUT_A_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of * the input is done based on selected signal.\n * e.g: ERU0_ETL3_INPUTA_P2_7. * @param input_b input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.\n - * Refer XMC_ERU_ETL_INPUT_B_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of + * Refer XMC_ERU_ETL_INPUT_B_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of * the input is done based on selected signal.\n * e.g: ERU0_ETL0_INPUTB_P2_0. * @@ -519,14 +511,14 @@ void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU * \parDescription:
          * Configures the event source for path A and path B in with selected \a input_a and \a input_b respectively.
          * \par - * These values are set during initialization in XMC_ERU_ETL_Init(). Call this to change the input, as needed later in - * the program. According to the ports/peripheral selected, the event source has to be changed. + * These values are set during initialization in XMC_ERU_ETL_Init(). Call this to change the input, as needed later in + * the program. According to the ports/peripheral selected, the event source has to be changed. */ void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_INPUT_A_t input_a, const XMC_ERU_ETL_INPUT_B_t input_b); - + /** * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. * @param channel ERU_ETLx(Event trigger logic unit) channel. @@ -537,11 +529,11 @@ void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, * @return None * * \parDescription:
          - * Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits in + * Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits in * ERSx(Event request source) unit
          * \par - * The signal ERSxO is generated from the selection and this is connected to ETLx(Event trigger logic, - * x = [0 to 3]) for further action. These values are set during initialization in XMC_ERU_ETL_Init(). Call this to + * The signal ERSxO is generated from the selection and this is connected to ETLx(Event trigger logic, + * x = [0 to 3]) for further action. These values are set during initialization in XMC_ERU_ETL_Init(). Call this to * change the source, as needed later in the program. */ void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, @@ -560,7 +552,7 @@ void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, * \parDescription:
          * Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.
          * \par - * Rising edge, falling edge or either edges can be selected to generate the event.These values are set during + * Rising edge, falling edge or either edges can be selected to generate the event.These values are set during * initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. */ void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru, @@ -578,9 +570,9 @@ void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru, * Return event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register.
          * \par * Rising edge, falling edge or either edges can be selected to generate the event. - * Call this to get the configured trigger edge. */ + * Call this to get the configured trigger edge. */ XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, - const uint8_t channel); + const uint8_t channel); /** * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. * @param channel ERU_ETLx(Event trigger logic unit) channel. @@ -613,7 +605,7 @@ __STATIC_INLINE void XMC_ERU_ETL_SetStatusFlag(XMC_ERU_t *const eru, const uint8 * @return None * * \parDescription:
          - * Set the status flag bit(FL) in EXICONx(x = [0 to 3]).
          + * Clear the status flag bit(FL) in EXICONx(x = [0 to 3]).
          * \par * If auto clear of the status flag is not enabled by detection of the opposite edge of the event edge, this API clears * the Flag. SO that next event is considered as new event. @@ -655,7 +647,7 @@ __STATIC_INLINE uint32_t XMC_ERU_ETL_GetStatusFlag(XMC_ERU_t *const eru, const u * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. * @param channel ERU_ETLx(Event trigger logic unit) channel. * Range : [0 to 3]. - * @param mode Set whether status flag has to be cleared by software or hardware. + * @param mode Set whether status flag has to be cleared by software or hardware. * Refer @ref XMC_ERU_ETL_STATUS_FLAG_MODE_t for valid value. * * @return None @@ -663,8 +655,8 @@ __STATIC_INLINE uint32_t XMC_ERU_ETL_GetStatusFlag(XMC_ERU_t *const eru, const u * \parDescription:
          * Set the mode for status flag mode by setting (LD) bit in EXICONx(x = \a channel) register.
          * \par - * If SWCTRL is selected, status flag has to be cleared by software. This is typically used for pattern match detection. - * If HWCTRL is selected, status flag is cleared by hardware. If Positive edge is selected as event edge, for negative + * If SWCTRL is selected, status flag has to be cleared by software. This is typically used for pattern match detection. + * If HWCTRL is selected, status flag is cleared by hardware. If Positive edge is selected as event edge, for negative * edge status flag is cleared and vice versa.This is typically used for continuous event detection.These values are set * during initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. * @@ -679,19 +671,19 @@ void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru, * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address. * @param channel ERU_ETLx(Event trigger logic unit) channel. * Range : [0 to 3]. - * @param trigger Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse + * @param trigger Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse * Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid value. * * @return None * * \parDescription:
          - * Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by + * Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by * ETLx(Event Trigger Logic, x = \a channel) by setting (OCS and PE) bit fields. * \par - * The trigger pulse is generated for one clock pulse along with the flag status update. This is typically used to - * trigger the ISR for the external events. The configured OGUy(Output gating unit y = [0 to 3]), generates the event + * The trigger pulse is generated for one clock pulse along with the flag status update. This is typically used to + * trigger the ISR for the external events. The configured OGUy(Output gating unit y = [0 to 3]), generates the event * based on the trigger pulse.If output trigger pulse generation is disabled by XMC_ERU_ETL_DisableOutputTrigger(), - * XMC_ERU_ETL_EnableOutputTrigger() can called to reconfigure. These values are set during initialization in + * XMC_ERU_ETL_EnableOutputTrigger() can called to reconfigure. These values are set during initialization in * XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program. * * \parRelated APIs:
          @@ -712,7 +704,7 @@ void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru, * Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = \a channel). * \par * Typically this can used when only pattern match is being used for event generation. - * + * * \parRelated APIs:
          * XMC_ERU_ETL_EnableOutputTrigger() */ @@ -724,15 +716,15 @@ void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channe * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address * @param channel ERU_OGUy(Output gating unit) channel * Range : [0 to 3] - * @param config pointer to constant ERU_OGUy configuration data structure. + * @param config pointer to constant ERU_OGUy configuration data structure. * Refer data structure XMC_ERU_OGU_CONFIG_t for detail. * * @return None * * Description:
          - * Initializes the selected ERU_OGUy \a channel with the \a config structure.
          + * Initializes the selected ERU_OGUy \a channel with the \a config structure.
          * - * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures + * Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures *
            *
          • Pattern detection,
            • *
          • Peripheral trigger input,
            • @@ -748,15 +740,15 @@ void XMC_ERU_OGU_Init(XMC_ERU_t *const eru, * @param channel ERU_OGUy(Output gating unit) channel * Range : [0 to 3] * @param input ERU_ETLx(x = [0 to 3]), for pattern match detection. - * Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. Logical OR combination of the - * enum items can be passed as the input. + * Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. Logical OR combination of the + * enum items can be passed as the input. * * @return None * * \parDescription:
            * Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3]) and GEEN bits. * \par - * These bits are dedicated to each channel of the ERU_ETLx(x = [0 to 3]). These values are set during initialization in + * These bits are dedicated to each channel of the ERU_ETLx(x = [0 to 3]). These values are set during initialization in * XMC_ERU_OGU_Init(). Call this to change the pattern, as needed later in the program. * * \parRelated APIs:
            @@ -797,7 +789,7 @@ void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t cha * XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePatternDetection() */ __STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const eru, - const uint8_t channel) + const uint8_t channel) { XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Channel Number", (channel < 4U)); @@ -810,8 +802,8 @@ __STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const * @param channel ERU_OGUy(Output gating unit) channel * Range : [0 to 3] * @param peripheral_trigger which peripheral trigger signal is used for event generation. - * Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for the valid values, or - xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of the peripheral input is done based + * Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for the valid values, or + xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of the peripheral input is done based on input. e.g: ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0. * * @return None @@ -819,15 +811,15 @@ __STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const * \parDescription:
            * Configures peripheral trigger input, by setting (ISS) bit. * \par - * Based on the peripheral the input signal has to be selected. These values are set during initialization in + * Based on the peripheral the input signal has to be selected. These values are set during initialization in * XMC_ERU_OGU_Init(). Call this to change the input, as needed later in the program. * * \parRelated APIs:
            * XMC_ERU_OGU_DisablePeripheralTrigger() */ void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, - const uint8_t channel, - const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger); + const uint8_t channel, + const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger); /** * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address @@ -839,15 +831,15 @@ void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, * \parDescription:
            * Disables event generation based on peripheral trigger by clearing (ISS) bit. * \par - * This is typically used when peripheral trigger is no longer need. After calling - * XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_EnablePeripheralTrigger() has to be called to reconfigure the + * This is typically used when peripheral trigger is no longer need. After calling + * XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_EnablePeripheralTrigger() has to be called to reconfigure the * signals again. * * \parRelated APIs:
            * XMC_ERU_OGU_EnablePeripheralTrigger() */ void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, - const uint8_t channel); + const uint8_t channel); /** * @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address @@ -861,9 +853,9 @@ void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, * \parDescription:
            * Configures the gating scheme for service request generation by setting (GP) bit.
            * \par - * Typically this function is used to change the service request generation scheme. These values are set during - * initialization in XMC_ERU_OGU_Init(). Call this to change the gating mode, as needed later in the program. - * + * Typically this function is used to change the service request generation scheme. These values are set during + * initialization in XMC_ERU_OGU_Init(). Call this to change the gating mode, as needed later in the program. + * */ void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru, const uint8_t channel, @@ -877,8 +869,5 @@ void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru, * @} (end addtogroup ERU) */ -/** - * @} (end addtogroup XMClib) - */ #endif /* XMC_ERU_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eth_mac.h b/cores/xmc_lib/XMCLib/inc/xmc_eth_mac.h index 73533693..88a3b9ae 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_eth_mac.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_eth_mac.h @@ -1,79 +1,46 @@ /** * @file xmc_eth_mac.h - * @date 2017-08-07 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-06-20: - * - Initial - * - * 2016-04-25: - * - Change XMC_ETH_MAC_BUF_SIZE to 1524 to allow for Tagged MAC frame format - * - * 2016-05-19: - * - Added XMC_ETH_MAC_GetTxBuffer() and XMC_ETH_MAC_GetRxBuffer() - * - Added XMC_ETH_MAC_SetTxBufferSize() - * - * 2016-06-08: - * - Added XMC_ETH_MAC_IsRxDescriptorOwnedByDma() - * - * 2017-02-25: - * - XMC_ETH_MAC_SetPortControl() fixed compilation warning - * - * 2017-04-02: - * - Added XMC_ETH_MAC_InitPTPEx() - * - Added XMC_ETH_MAC_SetPTPTime() - * - Added XMC_ETH_MAC_UpdateAddend() - * - * 2017-04-11: - * - Added XMC_ETH_MAC_EnablePTPAlarm() and XMC_ETH_MAC_DisablePTPAlarm - * - * 2017-04-17: - * - Fixed ordering of PTP nanoseconds and seconds in XMC_ETH_MAC_DMA_DESC_t - * - * 2017-08-07: - * - Added XMC_ETH_MAC_TIMESTAMP_STATUS_t + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup ETH_MAC @@ -341,14 +308,14 @@ typedef union XMC_ETH_MAC_PORT_CTRL */ typedef struct XMC_ETH_MAC_DMA_DESC { - uint32_t status; /**< DMA descriptor status */ - uint32_t length; /**< Descriptor length */ - uint32_t buffer1; /**< Buffer 1 */ - uint32_t buffer2; /**< Buffer 2 */ - uint32_t extended_status; /**< Extended status */ - uint32_t reserved; /**< Reserved */ - uint32_t time_stamp_nanoseconds; /**< Time stamp low */ - uint32_t time_stamp_seconds; /**< Time stamp high */ + volatile uint32_t status; /**< DMA descriptor status */ + volatile uint32_t length; /**< Descriptor length */ + volatile uint32_t buffer1; /**< Buffer 1 */ + volatile uint32_t buffer2; /**< Buffer 2 */ + volatile uint32_t extended_status; /**< Extended status */ + volatile uint32_t reserved; /**< Reserved */ + volatile uint32_t time_stamp_nanoseconds; /**< Time stamp low */ + volatile uint32_t time_stamp_seconds; /**< Time stamp high */ } XMC_ETH_MAC_DMA_DESC_t; /** @@ -407,6 +374,21 @@ extern "C" { */ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac); +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return None + * + * \parDescription:
            + * Initialize the Ethernet MAC peripheral.
            + * Required when initializing the PHY, to deliver the clocks to the MAC, before MAC is reseted. + * \note The module needs to be enabled before using XMC_ETH_MAC_Enable()
            + * + * \par + * The function sets the link speed, applies the duplex mode, sets auto-negotiation + * and loop-back settings. + */ +void XMC_ETH_MAC_InitEx(XMC_ETH_MAC_t *const eth_mac); + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return None @@ -432,7 +414,7 @@ void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac); * up the status bit, control bit, buffer length and the buffer pointer. */ void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac); - + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return None @@ -457,19 +439,6 @@ void XMC_ETH_MAC_Enable(XMC_ETH_MAC_t *const eth_mac); */ void XMC_ETH_MAC_Disable(XMC_ETH_MAC_t *const eth_mac); -/** - * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address - * @return bool - * - * \parDescription:
            - * Check if the ETH MAC is enabled
            - * - * \par - * The function checks if the ETH MAC is enabled or not. It returns "true" if the - * peripheral is enabled, "false" otherwise. - */ -bool XMC_ETH_MAC_IsEnabled(const XMC_ETH_MAC_t *const eth_mac); - /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return None @@ -576,6 +545,20 @@ __STATIC_INLINE void XMC_ETH_MAC_SetAddress(XMC_ETH_MAC_t *const eth_mac, uint64 eth_mac->regs->MAC_ADDRESS0_LOW = (uint32_t)addr; } +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addr Pointer to 6 byte MAC address + * @return None + * + * \parDescription:
            + * Set MAC address
            + * + * \par + * The function sets the MAC address by writing to the MAC_ADDRESS0_HIGH and + * MAC_ADDRESS0_LOW registers. + */ +void XMC_ETH_MAC_SetAddressEx(XMC_ETH_MAC_t *const eth_mac, const uint8_t *const addr); + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return uint64_t The MAC address which has been set @@ -588,14 +571,28 @@ __STATIC_INLINE void XMC_ETH_MAC_SetAddress(XMC_ETH_MAC_t *const eth_mac, uint64 */ __STATIC_INLINE uint64_t XMC_ETH_MAC_GetAddress(XMC_ETH_MAC_t *const eth_mac) { - return ((((uint64_t)eth_mac->regs->MAC_ADDRESS0_HIGH << 32)) | (uint64_t)eth_mac->regs->MAC_ADDRESS0_LOW); + uint32_t mac_addr_high = eth_mac->regs->MAC_ADDRESS0_HIGH; + uint32_t mac_addr_low = eth_mac->regs->MAC_ADDRESS0_HIGH; + return ((((uint64_t)mac_addr_high << 32)) | (uint64_t)mac_addr_low); } +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return uint64_t The MAC address which has been set + * + * \parDescription:
            + * Get MAC address
            + * + * \par + * The function returns the current ETH MAC address. + */ +void XMC_ETH_MAC_GetAddressEx(XMC_ETH_MAC_t *const eth_mac, uint8_t *const addr); + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @param index Table entry index * @param addr Address value - * @param flags Compare control. OR'ed combination of @ref XMC_ETH_MAC_ADDR_FILTER_t or zero. + * @param flags Compare control. OR'ed combination of @ref XMC_ETH_MAC_ADDR_FILTER_t or zero. * * @return None * @@ -607,6 +604,22 @@ __STATIC_INLINE uint64_t XMC_ETH_MAC_GetAddress(XMC_ETH_MAC_t *const eth_mac) */ void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, uint8_t index, const uint64_t addr, uint32_t flags); +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param index Table entry index + * @param addr Pointer to 6 byte MAC address + * @param flags Compare control. OR'ed combination of @ref XMC_ETH_MAC_ADDR_FILTER_t or zero. + * + * @return None + * + * \parDescription:
            + * Set perfect filter for address filtering
            + * + * \par + * The function can be used to set perfect filter for address filtering. + */ +void XMC_ETH_MAC_SetAddressPerfectFilterEx(XMC_ETH_MAC_t *const eth_mac, uint8_t index, uint8_t *const addr, uint32_t flags); + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @param hash The hash to be used for filtering @@ -874,9 +887,9 @@ __STATIC_INLINE void XMC_ETH_MAC_DisableUnicastHashFilter(XMC_ETH_MAC_t *const e * the ETH MAC's dedicated DMA unit. */ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, - const uint8_t *frame, - uint32_t len, - uint32_t flags); + const uint8_t *frame, + uint32_t len, + uint32_t flags); /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address @@ -1064,7 +1077,7 @@ __STATIC_INLINE void XMC_ETH_MAC_EnableTxJabber(XMC_ETH_MAC_t *const eth_mac) __STATIC_INLINE void XMC_ETH_MAC_DisableTxJabber(XMC_ETH_MAC_t *const eth_mac) { eth_mac->regs->MAC_CONFIGURATION |= (uint32_t)ETH_MAC_CONFIGURATION_JD_Msk; -} +} /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address @@ -1204,8 +1217,8 @@ __STATIC_INLINE void XMC_ETH_MAC_DisableLoopback(XMC_ETH_MAC_t *const eth_mac) * The function sets the link speed and duplex settings. */ __STATIC_INLINE void XMC_ETH_MAC_SetLink(XMC_ETH_MAC_t *const eth_mac, - XMC_ETH_LINK_SPEED_t speed, - XMC_ETH_LINK_DUPLEX_t duplex) + XMC_ETH_LINK_SPEED_t speed, + XMC_ETH_LINK_DUPLEX_t duplex) { eth_mac->regs->MAC_CONFIGURATION = (eth_mac->regs->MAC_CONFIGURATION & (uint32_t)~(ETH_MAC_CONFIGURATION_DM_Msk | ETH_MAC_CONFIGURATION_FES_Msk)) | @@ -1266,6 +1279,21 @@ __STATIC_INLINE bool XMC_ETH_MAC_IsTxDescriptorOwnedByDma(XMC_ETH_MAC_t *const e return ((eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN) != 0U); } +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return bool true if TX descriptor is owned by DMA, false otherwise + * + * \parDescription:
            + * Is TX descriptor owned by DMA?
            + * + * \par + * The function checks if the TX descriptor is owned by the DMA. + */ +__STATIC_INLINE bool XMC_ETH_MAC_IsTxDescriptorOwnedByDmaEx(XMC_ETH_MAC_t *const eth_mac, uint8_t index) +{ + return ((eth_mac->tx_desc[index].status & ETH_MAC_DMA_TDES0_OWN) != 0U); +} + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return None @@ -1396,6 +1424,30 @@ __STATIC_INLINE void XMC_ETH_MAC_ResumeRx(XMC_ETH_MAC_t *const eth_mac) eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; } +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current TX buffer + * + * \parDescription:
            + * Returns the current TX buffer. + */ +__STATIC_INLINE uint8_t XMC_ETH_MAC_GetCurrentTxDescIndex(XMC_ETH_MAC_t *const eth_mac) +{ + return eth_mac->tx_index; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current TX buffer + * + * \parDescription:
            + * Returns the current TX buffer. + */ +__STATIC_INLINE uint8_t XMC_ETH_MAC_GetCurrentRxDescIndex(XMC_ETH_MAC_t *const eth_mac) +{ + return eth_mac->rx_index; +} + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return Pointer to current TX buffer @@ -1408,6 +1460,70 @@ __STATIC_INLINE uint8_t *XMC_ETH_MAC_GetTxBuffer(XMC_ETH_MAC_t *const eth_mac) return (uint8_t *)(eth_mac->tx_desc[eth_mac->tx_index].buffer1); } +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @return Pointer to current TX buffer + * + * \parDescription:
            + * Returns the current TX buffer. + */ +__STATIC_INLINE uint8_t *XMC_ETH_MAC_GetTxBufferEx(XMC_ETH_MAC_t *const eth_mac, uint8_t index) +{ + return (uint8_t *)(eth_mac->tx_desc[index].buffer1); +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addresss Buffer address + * @return None + * + * \parDescription:
            + * Sets the buffer address of the current TX buffer. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetTxBuffer(XMC_ETH_MAC_t *const eth_mac, const uint8_t *const address) +{ + eth_mac->tx_desc[eth_mac->tx_index].buffer1 = (uint32_t)address; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addresss Buffer address + * @return None + * + * \parDescription:
            + * Sets the buffer address of the current TX buffer. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetTxBufferEx(XMC_ETH_MAC_t *const eth_mac, uint8_t index, const uint8_t *const address) +{ + eth_mac->tx_desc[index].buffer1 = (uint32_t)address; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addresss Buffer address + * @return None + * + * \parDescription:
            + * Sets the buffer address of the current TX buffer. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetRxBuffer(XMC_ETH_MAC_t *const eth_mac, const uint8_t *const address) +{ + eth_mac->rx_desc[eth_mac->rx_index].buffer1 = (uint32_t)address; +} + +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param addresss Buffer address + * @return None + * + * \parDescription:
            + * Sets the buffer address of the current TX buffer. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetRxBufferEx(XMC_ETH_MAC_t *const eth_mac, uint8_t index, const uint8_t *const address) +{ + eth_mac->rx_desc[index].buffer1 = (uint32_t)address; +} + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @return Pointer to current RX buffer @@ -1417,7 +1533,7 @@ __STATIC_INLINE uint8_t *XMC_ETH_MAC_GetTxBuffer(XMC_ETH_MAC_t *const eth_mac) */ __STATIC_INLINE uint8_t *XMC_ETH_MAC_GetRxBuffer(XMC_ETH_MAC_t *const eth_mac) { - return (uint8_t *)(eth_mac->rx_desc[eth_mac->rx_index].buffer1); + return (uint8_t *)(eth_mac->rx_desc[eth_mac->rx_index].buffer1); } /** @@ -1433,6 +1549,19 @@ __STATIC_INLINE void XMC_ETH_MAC_SetTxBufferSize(XMC_ETH_MAC_t *const eth_mac, u eth_mac->tx_desc[eth_mac->tx_index].length = size; } +/** + * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address + * @param size Size of buffer + * @return None + * + * \parDescription:
            + * Sets the current TX buffer size. + */ +__STATIC_INLINE void XMC_ETH_MAC_SetTxBufferSizeEx(XMC_ETH_MAC_t *const eth_mac, uint8_t index, uint32_t size) +{ + eth_mac->tx_desc[index].length = size; +} + /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address * @param event A valid ETH PMT event (XMC_ETH_MAC_PMT_EVENT_t) or a valid combination @@ -1552,7 +1681,7 @@ __STATIC_INLINE void XMC_ETH_MAC_DisablePowerDownMode(XMC_ETH_MAC_t *const eth_m * \par * The function sets the VLAN tag to identify the VLAN frames. */ -void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag); +void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint32_t tag); /** * @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address @@ -1678,7 +1807,7 @@ __STATIC_INLINE void XMC_ETH_MAC_DisablePTPAlarm(XMC_ETH_MAC_t *const eth_mac) * Adjust PTP clock
            * * \par - * The function is used to adjust the PTP clock (time synchronization) to compensate a reference clock drift. + * The function is used to adjust the PTP clock (time synchronization) to compensate a reference clock drift. */ void XMC_ETH_MAC_UpdateAddend(XMC_ETH_MAC_t *const eth_mac, uint32_t addend); @@ -1791,15 +1920,12 @@ uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac); #ifdef __cplusplus } #endif - -/** - * @} - */ - + /** * @} */ - + + #endif /* defined (ETH0) */ #endif /* XMC_ETH_MAC_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h b/cores/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h index f10474f1..2586bb54 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_eth_mac_map.h @@ -1,43 +1,41 @@ /** * @file xmc_eth_mac_map.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial
            + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -47,16 +45,16 @@ /** * ETH MAC interface mode - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_MODE { XMC_ETH_MAC_PORT_CTRL_MODE_MII = 0x0U, /**< MII mode */ XMC_ETH_MAC_PORT_CTRL_MODE_RMII = 0x1U /**< RMII mode */ } XMC_ETH_MAC_PORT_CTRL_MODE_t; - + /** * ETH MAC receive data 0 line - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0 { XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2 = 0U, /**< RXD0A receive data line */ @@ -67,7 +65,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0 /** * ETH MAC receive data 1 line - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1 { XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3 = 0U, /**< RXD1A receive data line */ @@ -78,7 +76,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1 /** * ETH MAC receive data 2 line - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2 { XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8 = 0U, /**< RXD2A receive data line */ @@ -87,7 +85,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2 /** * ETH MAC receive data 3 line - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3 { XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9 = 0U, /**< RXD3A Receive data line */ @@ -96,7 +94,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3 /** * ETH MAC PHY clock - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII { XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1 = 0U, /**< XMC_ETH_RMIIA PHY clock */ @@ -107,7 +105,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII /** * ETH MAC carrier sense data valid - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV { XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5 = 0U, /**< XMC_ETH_CRS_DVA carrier sense data valid */ @@ -118,7 +116,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV /** * ETH MAC carrier sense - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_CRS { XMC_ETH_MAC_PORT_CTRL_CRS_P5_11 = 0U, /**< XMC_ETH_CRSA carrier sense */ @@ -127,7 +125,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_CRS /** * ETH MAC receive error - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_RXER { XMC_ETH_MAC_PORT_CTRL_RXER_P2_4 = 0U, /**< XMC_ETH_RXERA carrier sense */ @@ -137,7 +135,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_RXER /** * ETH MAC collision detection - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_COL { XMC_ETH_MAC_PORT_CTRL_COL_P2_15 = 0U, /**< XMC_ETH_COLA collision detection */ @@ -146,7 +144,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_COL /** * ETH PHY transmit clock - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX { XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10 = 0U, /**< XMC_ETH_CLK_TXA PHY transmit clock */ @@ -155,7 +153,7 @@ typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX /** * ETH management data I/O - */ + */ typedef enum XMC_ETH_MAC_PORT_CTRL_MDIO { XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9 = 0U, /**< XMC_ETH_MDIOA management data I/O */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_eth_phy.h b/cores/xmc_lib/XMCLib/inc/xmc_eth_phy.h index 358369ec..c75c5a0f 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_eth_phy.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_eth_phy.h @@ -1,54 +1,45 @@ /** * @file xmc_eth_phy.h - * @date 2015-12-15 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-06-20: - * - Initial - * - * 2015-12-15: - * - Added XMC_ETH_PHY_ExitPowerDown and XMC_ETH_PHY_Reset + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup ETH_PHY @@ -65,7 +56,7 @@ * INCLUDES *******************************************************************************/ -#include +#include "xmc_eth_mac.h" /******************************************************************************* * ENUMS @@ -214,9 +205,6 @@ bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_ /** * @} */ - -/** - * @} - */ + #endif /* XMC_ETH_PHY_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_fce.h b/cores/xmc_lib/XMCLib/inc/xmc_fce.h index e227fdd7..c7daf6a7 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_fce.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_fce.h @@ -1,50 +1,43 @@ /** * @file xmc_fce.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial - * - * 2015-05-20: - * - Description updated
            - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -54,15 +47,11 @@ /********************************************************************************************************************** * HEADER FILES *********************************************************************************************************************/ - -#include + +#include "xmc_common.h" #if defined (FCE) -/** - * @addtogroup XMClib - * @{ - */ /** * @addtogroup FCE @@ -74,31 +63,31 @@ * The primary target of FCE is to be used as an hardware acceleration engine for software * applications or operating systems services using CRC signatures. * - * @image html fce_overview.png - * @image latex ../images/fce_overview.png + * @image html fce_overview.png + * @image latex ../images/fce_overview.png * FCE Features:
            * @image html fce_polynomials.png * @image latex ../images/fce_polynomials.png * * CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB71
            * * CRC kernel 2: CCITT CRC16 polynomial: 0x1021
            * * CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D
            - * * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at + * * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at * the end of a message.
            * * Extended register interface to control reliability of FCE execution in safety applications.
            * * Error notification scheme via dedicated interrupt node for:
            - a)Transient error detection: Error interrupt generation (maskable) with local status register + a)Transient error detection: Error interrupt generation (maskable) with local status register (cleared by software)
            b)Checksum failure: Error interrupt generation (maskable) with local status register (cleared by software)
            - + FCE provides one interrupt line to the interrupt system. Each CRC engine has its own set of flag registers.
            * @{ */ - + /********************************************************************************************************************** * MACROS *********************************************************************************************************************/ - + #define XMC_FCE_CRC32_0 FCE_KE0 /**< Kernel 0
            */ #define XMC_FCE_CRC32_1 FCE_KE1 /**< Kernel 1
            */ #define XMC_FCE_CRC16 FCE_KE2 /**< Kernel 2
            */ @@ -114,7 +103,7 @@ /********************************************************************************************************************** * ENUMS *********************************************************************************************************************/ - + /** * FCE interrupt configuration */ @@ -182,15 +171,15 @@ typedef enum XMC_FCE_STATUS /** * FCE kernel - */ + */ typedef FCE_KE_TypeDef XMC_FCE_Kernel_t; /* Anonymous structure/union guard start */ #if defined (__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined (__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -203,20 +192,20 @@ typedef struct XMC_FCE_CONFIG uint32_t regval; struct { - uint32_t : 8; + uint32_t : 8; uint32_t config_refin : 1; /**< Enables byte-wise reflection */ uint32_t config_refout : 1; /**< Enables bit-wise reflection */ uint32_t config_xsel : 1; /**< Enables output inversion */ - uint32_t : 21; /**< Reserved bits */ + uint32_t : 21; /**< Reserved bits */ }; }; } XMC_FCE_CONFIG_t; /* Anonymous structure/union guard end */ #if defined (__CC_ARM) - #pragma pop +#pragma pop #elif defined (__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** @@ -232,18 +221,18 @@ typedef struct XMC_FCE /********************************************************************************************************************** * API PROTOTYPES *********************************************************************************************************************/ - + #ifdef __cplusplus extern "C" { #endif - + /** * @param None * @return uint32_t Module revision number * * \parDescription:
            * Read FCE module revision number
            - * + * * \par * The value of a module revision starts with 0x01 (first revision). The current revision * number is 0x01. @@ -259,7 +248,7 @@ __STATIC_INLINE uint32_t XMC_FCE_ReadModuleRev(void) * * \parDescription:
            * Read the FCE module type
            - * + * * \par * The return value is currently 0xC0. It defines the module as a 32-bit module. */ @@ -274,7 +263,7 @@ __STATIC_INLINE uint32_t XMC_FCE_ReadModuleType(void) * * \parDescription:
            * Read FCE module number
            - * + * * \par * The return value for FCE module is currently 0x00CA. */ @@ -306,7 +295,7 @@ __STATIC_INLINE bool XMC_FCE_Get_DisableStatus(void) * * \parDescription:
            * Disable the FCE module
            - * + * * \par * The function asserts the FCE peripheral reset and sets the DISR bit in the CLC * register. @@ -335,7 +324,7 @@ void XMC_FCE_Enable(void); * * \parDescription:
            * Initialize the FCE engine
            - * + * * \par * The function sets to the CFG and CRC registers with the FCE configuration and * seeds values. The function always returns XMC_FCE_STATUS_SUCCESS. @@ -437,7 +426,7 @@ __STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_S * Enable CRC operations
            * * \par - * The function enables FRC operations by writing to the CFG register. + * The function enables FRC operations by writing to the CFG register. * * \parNote:
            * CRC comparison check (at the end of message) can be enabled using the CCE bit-field. @@ -570,8 +559,8 @@ __STATIC_INLINE void XMC_FCE_UpdateLength(const XMC_FCE_t *const engine, const u */ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, const uint8_t *data, - uint32_t length, - uint8_t *result); + uint32_t length, + uint8_t *result); /** * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address @@ -594,8 +583,27 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, */ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, const uint16_t *data, - uint32_t length, - uint16_t *result); + uint32_t length, + uint16_t *result); + +/** + * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Length of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription:
            + * Calculate and update the RC16 checksum in the result pointer
            + * + * \parNote:
            + * Alternative to XMC_FCE_CalculateCRC16() where a uint8_t data array can be used + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16Ex(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint16_t *const result); /** * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address @@ -617,8 +625,27 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, */ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, const uint32_t *data, - uint32_t length, - uint32_t *result); + uint32_t length, + uint32_t *result); + +/** + * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address + * @param data Pointer to the data buffer + * @param length Total number of bytes of data buffer + * @param result Pointer to computed CRC result + * @return XMC_FCE_STATUS_ERROR on error + * @return XMC_FCE_STATUS_SUCCESS otherwise. + * + * \parDescription
            + * Calculate and update the calculated CRC32 checksum in the result pointer
            + * + * \parNote:
            + * Alternative to XMC_FCE_CalculateCRC32() where a uint8_t data array can be used + */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32Ex(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint32_t *const result); /** * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address @@ -630,7 +657,7 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, */ __STATIC_INLINE void XMC_FCE_GetCRCResult(const XMC_FCE_t *const engine, uint32_t *result) { - *result= engine->kernel_ptr->RES; + *result = engine->kernel_ptr->RES; } /** @@ -660,7 +687,7 @@ void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t t * This function should be invoked before using ::XMC_FCE_CalculateCRC16() to compute * the CRC value. */ -void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length); +void XMC_FCE_LittleEndian16bit(uint8_t *inbuffer, uint16_t *outbuffer, uint16_t length); /** * @param inbuffer Pointer to input data buffer @@ -678,7 +705,7 @@ void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t * This function should be invoked before using ::XMC_FCE_CalculateCRC32() to compute * the CRC value. */ -void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length); +void XMC_FCE_LittleEndian32bit(uint8_t *inbuffer, uint32_t *outbuffer, uint16_t length); #ifdef __cplusplus } @@ -688,10 +715,7 @@ void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t * @} */ -/** - * @} - */ - + #endif /* defined (FCE) */ #endif /* XMC_FCE_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_flash.h b/cores/xmc_lib/XMCLib/inc/xmc_flash.h index 963d1239..b6a61dd2 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_flash.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_flash.h @@ -1,48 +1,43 @@ /** * @file xmc_flash.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2014-12-10: - * - Initial
            - * 2015-02-20: - * - Updated for Documentation related changes
            - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -57,17 +52,13 @@ #include "xmc_common.h" #if UC_FAMILY == XMC1 - #include "xmc1_flash.h" +#include "xmc1_flash.h" #endif - + #if UC_FAMILY == XMC4 - #include "xmc4_flash.h" +#include "xmc4_flash.h" #endif -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup FLASH @@ -78,17 +69,17 @@ *
              * \if XMC4 *
            1. Provides function to program a page. ( XMC_FLASH_ProgramPage() )

              2. - *
            2. Provides functions to support read and write protection. ( XMC_FLASH_InstallProtection(), - * XMC_FLASH_ConfirmProtection(), XMC_FLASH_VerifyReadProtection(), XMC_FLASH_VerifyWriteProtection() )

              3. - *
            3. Provides function to erase sector. ( XMC_FLASH_EraseSector() )

              4. + *
            4. Provides functions to support read and write protection. ( XMC_FLASH_InstallProtection(), + * XMC_FLASH_ConfirmProtection(), XMC_FLASH_VerifyReadProtection(), XMC_FLASH_VerifyWriteProtection() )

              5. + *
            5. Provides function to erase sector. ( XMC_FLASH_EraseSector() )

              6. * \endif * \if XMC1 - *
            6. Provides functions to program and verify pages. ( XMC_FLASH_ProgramPage(), XMC_FLASH_ProgramPages() + *
            7. Provides functions to program and verify pages. ( XMC_FLASH_ProgramPage(), XMC_FLASH_ProgramPages() * XMC_FLASH_ProgramVerifyPage() )

              8. *
            8. Provides functions to write and verify blocks. ( XMC_FLASH_WriteBlocks(), XMC_FLASH_VerifyBlocks() )

              9. *
            9. Provides functions to read data in terms of word and blocks. ( XMC_FLASH_ReadBlocks(), XMC_FLASH_ReadWord() ) - *

              10. - *
            10. Provides function to erase page. ( XMC_FLASH_ErasePage() )

              11. + *
              + *
            11. Provides function to erase page. ( XMC_FLASH_ErasePage() )

              12. * \endif *
            * @{ @@ -118,7 +109,7 @@ extern "C" { * \endif * * \parRelated APIs:
            - * None + * None * */ void XMC_FLASH_ClearStatus(void); @@ -179,68 +170,6 @@ void XMC_FLASH_EnableEvent(const uint32_t event_msk); */ void XMC_FLASH_DisableEvent(const uint32_t event_msk); -/** - * - * @param address Pointer to the starting address of flash page from where the programming starts. - * @param data Pointer to the source address where targeted data is located. - * - * @return None - * - * \parDescription:
            - * \if XMC1 - * Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one - * page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr) - * to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines - * (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation. - * \endif - * \if XMC4 - * Programs a single flash page associated with the specified \a address.\n\n XMC4000 flash can be programmed with a - * granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status - * bits inside status register. It starts the write process by issuing the page mode command followed by the load page - * command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page - * command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the - * programming operation.\n - * \endif - * - * \parNote:
            - * Flash will be busy state during write is ongoing, hence no operations allowed until it completes. - * - * \parRelated APIs:
            - * None - * - */ -void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data); - -/** - * - * @param address Pointer to the starting address of the page to be erased. - * - * @return None - * - * \parDescription:
            - * \if XMC1 - * Erases a complete sector starting from the \a address specified.\n\n XMC1000 Flash can be erased with granularity - * of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls XMC_FLASH_ErasePages API 16 - * times starting from the first page of the sector.. Call XMC_FLASH_GetStatus() API after calling this API, - * to verify the erase operation.\n - * \endif - * - * \if XMC4 - * Erases a sector associated with the specified \a address.\n\n Before erase, it clears the error status bits inside - * FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash - * erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n - * \endif - * \if XMC1 - * \parRelated APIs:
            - * XMC_FLASH_ErasePages() \n\n\n - * \endif - * \if XMC4 - * \parRelated APIs:
            - * None - * \endif - */ -void XMC_FLASH_EraseSector(uint32_t *address); - /** * * @param None @@ -268,9 +197,6 @@ __STATIC_INLINE bool XMC_FLASH_IsBusy(void) * @} */ -/** - * @} - */ #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_gpio.h b/cores/xmc_lib/XMCLib/inc/xmc_gpio.h index dd0dd249..262030c6 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_gpio.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_gpio.h @@ -1,47 +1,41 @@ /** * @file xmc_gpio.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial draft
            - * - Documentation improved
            - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -56,31 +50,27 @@ #include "xmc_common.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup GPIO * @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family. * - * GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins. - * Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the - * connectivity to the on-chip periphery and the control for the pad characteristics. + * GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins. + * Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the + * connectivity to the on-chip periphery and the control for the pad characteristics. * * The driver is divided into Input and Output mode. * * Input mode features: * -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init() - * -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() + * -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() * \if XMC1 * -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis() * \endif * - * + * * Output mode features: - * -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() + * -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode() * \if XMC4 * -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength() * \endif @@ -90,7 +80,6 @@ *@{ */ - /********************************************************************************************************************** * MACROS *********************************************************************************************************************/ @@ -99,19 +88,20 @@ #define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk #define PORT_IOCR_PC_Size (8U) - + #define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \ (level == XMC_GPIO_OUTPUT_LEVEL_HIGH)) - + #define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \ (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \ - (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2)) - + (hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2)) + /********************************************************************************************************************** * ENUMS *********************************************************************************************************************/ + /** * Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum. */ @@ -126,17 +116,16 @@ typedef enum XMC_GPIO_OUTPUT_LEVEL */ typedef enum XMC_GPIO_HWCTRL { - XMC_GPIO_HWCTRL_DISABLED = 0x0, /**< Software control only */ - XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1, /**< HWI0/HWO0 control path can override the software configuration */ - XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2 /**< HWI1/HWO1 control path can override the software configuration */ + XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */ + XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */ + XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */ } XMC_GPIO_HWCTRL_t; - /********************************************************************************************************************** * DEVICE FAMILY EXTENSIONS *********************************************************************************************************************/ - #if UC_FAMILY == XMC1 +#if UC_FAMILY == XMC1 #include "xmc1_gpio.h" #elif UC_FAMILY == XMC4 #include "xmc4_gpio.h" @@ -144,7 +133,6 @@ typedef enum XMC_GPIO_HWCTRL #error "xmc_gpio.h: family device not supported" #endif - /********************************************************************************************************************** * API PROTOTYPES *********************************************************************************************************************/ @@ -179,10 +167,13 @@ extern "C" { * \parNote:
            * This API is called in definition of DAVE_init by code generation and therefore should not be explicitly called * for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS). + * + * */ + + void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config); - /** * * @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR. @@ -198,7 +189,9 @@ void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPI * * \parRelated APIs:
            * None + * */ + void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode); @@ -219,12 +212,15 @@ void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_ * * \parNote:
            * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). + * */ + + __STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level) { XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level)); - + port->OMR = (uint32_t)level << pin; } @@ -244,7 +240,9 @@ __STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const * \parNote:
            * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\n * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0. + * */ + __STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); @@ -252,7 +250,6 @@ __STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const u port->OMR = (uint32_t)0x1U << pin; } - /** * * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. @@ -269,7 +266,9 @@ __STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const u *\parNote:
            * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). * Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n + * */ + __STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); @@ -277,7 +276,6 @@ __STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const ui port->OMR = 0x10000U << pin; } - /** * * @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR. @@ -294,7 +292,9 @@ __STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const ui * \parNote:
            * Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtual * and does not contain any flip-flop. A read action delivers the value of 0. + * */ + __STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); @@ -302,7 +302,6 @@ __STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const ui port->OMR = 0x10001U << pin; } - /** * * @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN. @@ -320,6 +319,7 @@ __STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const ui * Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode(). * */ + __STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port)); @@ -327,7 +327,6 @@ __STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const ui return (((port->IN) >> pin) & 0x1U); } - /** * @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS. * @param pin port pin number. @@ -345,7 +344,10 @@ __STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const ui * Note:
            * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * */ + + __STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); @@ -372,7 +374,9 @@ __STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, c *\parNote:
            * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so * may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * */ + __STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); @@ -398,7 +402,9 @@ __STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, *\parNote:
            * Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). * Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state. + * */ + void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl); @@ -414,11 +420,12 @@ void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, * \parDescription:
            * Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for * analog port pins. + * */ __STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); - + port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); } @@ -437,10 +444,11 @@ __STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, co * for analog port pins. * */ + __STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin) { XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port)); - + port->PDISC |= (uint32_t)0x1U << pin; } @@ -452,9 +460,5 @@ __STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, c * @} (end addtogroup GPIO) */ -/** - * @} (end addtogroup XMClib) - */ - #endif /* XMC_GPIO_H */ - \ No newline at end of file + diff --git a/cores/xmc_lib/XMCLib/inc/xmc_hrpwm.h b/cores/xmc_lib/XMCLib/inc/xmc_hrpwm.h index f8b5dffa..95144754 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_hrpwm.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_hrpwm.h @@ -1,66 +1,44 @@ /** * @file xmc_hrpwm.h - * @date 2015-06-20 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** - * - * Change History - * -------------- - * - * 2015-02-18: - * - Driver description updated
            - * - API's are renamed
            - * XMC_HRPWM_HRC_SetResolutionCR1() -> XMC_HRPWM_HRC_SetCompare1()
            - * XMC_HRPWM_HRC_SetResolutionCR2() -> XMC_HRPWM_HRC_SetCompare2()
            - * XMC_HRPWM_HRC_SetDeadTimeDCF() -> XMC_HRPWM_HRC_SetDeadTimeFalling()
            - * XMC_HRPWM_HRC_SetDeadTimeDCR() -> XMC_HRPWM_HRC_SetDeadTimeRising()
            - * - * 2015-05-12: - * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input
            - * - Enum XMC_HRPWM_SHADOW_TX_t is renamed to XMC_HRPWM_SHADOW_TX_DAC_t to represent that shadow transfer is for DAC
            - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
            - * - Updated copyright and change history section. - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -74,16 +52,12 @@ extern "C" { /*********************************************************************************************************************** * HEADER FILES **********************************************************************************************************************/ -#include +#include "xmc_common.h" #if defined(HRPWM0) -#include +#include "xmc_hrpwm_map.h" + -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - /** * @addtogroup HRPWM * @brief High Resolution PWM Unit (HRPWM) driver for the XMC microcontroller family.
            @@ -131,6 +105,8 @@ extern "C" { *
          • Dead time insertion on complementary signals
            *
          • Passive level selection on outputs.
            *
      + * + * Also, the HRPWM block can be configured from the ModusToolbox™ Device Configurator: \ref section_personality_hrpwm * @{ */ /*********************************************************************************************************************** @@ -317,7 +293,7 @@ typedef enum XMC_HRPWM_HRC_OUT_PASSIVE_LVL /** * CSG power modes */ - typedef enum XMC_HRPWM_CSG_POWER_MODE +typedef enum XMC_HRPWM_CSG_POWER_MODE { XMC_HRPWM_CSG_POWER_MODE_OFF = 0U << HRPWM0_CSGCFG_C0PM_Pos, /**< Comparator slope generator turned off */ XMC_HRPWM_CSG_POWER_MODE_LOW_SPEED = 1U << HRPWM0_CSGCFG_C0PM_Pos, /**< Comparator slope generator in low speed mode */ @@ -382,7 +358,7 @@ typedef enum XMC_HRPWM_CSG_PRESCALER_STOP } XMC_HRPWM_CSG_PRESCALER_STOP_t; /** - * Clear prescaler in CSG + * Clear prescaler in CSG */ typedef enum XMC_HRPWM_CSG_PRESCALER_CLR { @@ -617,13 +593,13 @@ typedef enum XMC_HRPWM_CSG_SLICE XMC_HRPWM_CSG_SLICE_1, /**< CSG slice number is 1 */ XMC_HRPWM_CSG_SLICE_2 /**< CSG slice number is 2 */ } XMC_HRPWM_CSG_SLICE_t; - + /** * HRPWM CSG - Comparator output filter window */ typedef enum XMC_HRPWM_CSG_CMP_FILTER_WINDOW { - XMC_HRPWM_CSG_CMP_FILTER_WINDOW_2_CLK_CYCLES = 0U , /**< Needs to be stable for 2 clk cycles */ + XMC_HRPWM_CSG_CMP_FILTER_WINDOW_2_CLK_CYCLES = 0U, /**< Needs to be stable for 2 clk cycles */ XMC_HRPWM_CSG_CMP_FILTER_WINDOW_3_CLK_CYCLES, /**< Needs to be stable for 3 clk cycles */ XMC_HRPWM_CSG_CMP_FILTER_WINDOW_4_CLK_CYCLES, /**< Needs to be stable for 4 clk cycles */ XMC_HRPWM_CSG_CMP_FILTER_WINDOW_5_CLK_CYCLES, /**< Needs to be stable for 5 clk cycles */ @@ -640,12 +616,12 @@ typedef enum XMC_HRPWM_CSG_CMP_FILTER_WINDOW XMC_HRPWM_CSG_CMP_FILTER_WINDOW_16_CLK_CYCLES, /**< Needs to be stable for 16 clk cycles */ XMC_HRPWM_CSG_CMP_FILTER_WINDOW_32_CLK_CYCLES /**< Needs to be stable for 32 clk cycles */ } XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t; - + /** * HRPWM CSG - Slope step gain */ typedef enum XMC_HRPWM_CSG_SLOPE_STEP_GAIN -{ +{ XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_1 = 0U, /**< slope step has an increment/decrement of 1 */ XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_2, /**< slope step has an increment/decrement of 2 */ XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_4, /**< slope step has an increment/decrement of 4 */ @@ -699,10 +675,10 @@ typedef struct XMC_HRPWM_HRC_SRC_CONFIG /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -729,7 +705,7 @@ typedef struct XMC_HRPWM_HRC_CONFIG uint32_t : 1; uint32_t dt_trigger_sel: 1; /**< Selection of trigger for dead time shadow transfer. Accepts enum XMC_HRPWM_HRC_DT_TR_SEL_t */ uint32_t : 15; - }; + }; uint32_t gc; /**< General high resolution channel configuration */ }; @@ -846,15 +822,15 @@ typedef struct XMC_HRPWM_CSG_SGEN uint32_t : 6; }; uint32_t sc; /**< Slope Generation Configuration */ - }; + }; uint32_t pulse_swallow_val; /**< Pulse swallow value */ } XMC_HRPWM_CSG_SGEN_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** @@ -868,7 +844,7 @@ typedef struct XMC_HRPWM_CSG_CONFIG } XMC_HRPWM_CSG_CONFIG_t; /*********************************************************************************************************************** - * API PROTOTYPES + * API PROTOTYPES **********************************************************************************************************************/ /** * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address @@ -1059,28 +1035,28 @@ __STATIC_INLINE void XMC_HRPWM_EnableLowResolutionPath(XMC_HRPWM_t *const hrpwm, * XMC_HRPWM_EnableLowResolutionPath()
      * */ - __STATIC_INLINE void XMC_HRPWM_DisableLowResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) +__STATIC_INLINE void XMC_HRPWM_DisableLowResolutionPath(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { XMC_ASSERT("XMC_HRPWM_DisableLowResolutionPath:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); hrpwm->HRCCFG &= ~mask; } - /** - * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address - * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. - * @return None - * - * \parDescription - *
      Enables the high resolution shadow transfer
      \n - * - * Enables the high resolution shadow transfer determined by passed mask value, by setting HRCSTRG.H0ES, HRCSTRG.H0DES bits. - * The input for trigger for shadow transfer needs to be configured correctly. - * - * \parRelated APIs:
      - * XMC_HRPWM_DisableHighResolutionShadowTransfer()
      - * XMC_HRPWM_GetHighResolutionShadowTransferStatus()
      - * - */ +/** + * @param hrpwm Constant pointer to XMC_HRPWM_t, pointing to the HRPWM module base address + * @param mask masked values of selected HRC modules. Use the enum type @ref XMC_HRPWM_HRC_SHADOW_TX_t to generate the mask. + * @return None + * + * \parDescription + *
      Enables the high resolution shadow transfer
      \n + * + * Enables the high resolution shadow transfer determined by passed mask value, by setting HRCSTRG.H0ES, HRCSTRG.H0DES bits. + * The input for trigger for shadow transfer needs to be configured correctly. + * + * \parRelated APIs:
      + * XMC_HRPWM_DisableHighResolutionShadowTransfer()
      + * XMC_HRPWM_GetHighResolutionShadowTransferStatus()
      + * + */ __STATIC_INLINE void XMC_HRPWM_EnableHighResolutionShadowTransfer(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { @@ -1189,7 +1165,7 @@ __STATIC_INLINE void XMC_HRPWM_DisableHRPowerMode(XMC_HRPWM_t *const hrpwm) __STATIC_INLINE void XMC_HRPWM_ModuleClkFreq(XMC_HRPWM_t *const hrpwm, const XMC_HRPWM_CLK_FREQ_t clk_freq) { XMC_ASSERT("XMC_HRPWM_ModuleClkFreq:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + hrpwm->HRCCFG &= ~(HRPWM0_HRCCFG_CLKC_Msk); hrpwm->HRCCFG |= (clk_freq << HRPWM0_HRCCFG_CLKC_Pos); } @@ -1256,10 +1232,10 @@ __STATIC_INLINE void XMC_HRPWM_StopComparator(XMC_HRPWM_t *const hrpwm, const ui __STATIC_INLINE bool XMC_HRPWM_IsComparatorRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { bool status; - + XMC_ASSERT("XMC_HRPWM_IsComparatorRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - if(hrpwm->CSGSTATG & mask) + if (hrpwm->CSGSTATG & mask) { status = true; } @@ -1267,7 +1243,7 @@ __STATIC_INLINE bool XMC_HRPWM_IsComparatorRunning(XMC_HRPWM_t *const hrpwm, con { status = false; } - + return (status); } @@ -1353,7 +1329,7 @@ __STATIC_INLINE uint32_t XMC_HRPWM_IsDacRunning(XMC_HRPWM_t *const hrpwm, const __STATIC_INLINE void XMC_HRPWM_ClampComparatorOutput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { XMC_ASSERT("XMC_HRPWM_ClampComparatorOutput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + hrpwm->CSGSETG = mask; } @@ -1375,7 +1351,7 @@ __STATIC_INLINE void XMC_HRPWM_ClampComparatorOutput(XMC_HRPWM_t *const hrpwm, c __STATIC_INLINE void XMC_HRPWM_UnClampComparatorOutput(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { XMC_ASSERT("XMC_HRPWM_UnClampComparatorOutput:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + hrpwm->CSGCLRG = mask; } @@ -1398,7 +1374,7 @@ __STATIC_INLINE void XMC_HRPWM_UnClampComparatorOutput(XMC_HRPWM_t *const hrpwm, __STATIC_INLINE uint32_t XMC_HRPWM_IsComparatorClamped(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { XMC_ASSERT("XMC_HRPWM_IsComparatorClamped:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + return (hrpwm->CSGSTATG & mask); } @@ -1489,9 +1465,9 @@ __STATIC_INLINE void XMC_HRPWM_StopSlopeGeneration(XMC_HRPWM_t *const hrpwm, con __STATIC_INLINE bool XMC_HRPWM_IsSlopeGenerationRunning(XMC_HRPWM_t *const hrpwm, const uint32_t mask) { bool status; - + XMC_ASSERT("XMC_HRPWM_IsSlopeGenerationRunning:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + if (hrpwm->CSGFSG & mask) { status = true; @@ -1500,7 +1476,7 @@ __STATIC_INLINE bool XMC_HRPWM_IsSlopeGenerationRunning(XMC_HRPWM_t *const hrpwm { status = false; } - + return (status); } @@ -1564,7 +1540,7 @@ __STATIC_INLINE void XMC_HRPWM_DisableComparatorShadowTransfer(XMC_HRPWM_t *cons __STATIC_INLINE uint32_t XMC_HRPWM_GetComparatorShadowTransferStatus(XMC_HRPWM_t *const hrpwm) { XMC_ASSERT("XMC_HRPWM_GetComparatorShadowTransferStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - return(hrpwm->CSGTRSG & XMC_HRPWM_COMPARATOR_STATUS); + return (hrpwm->CSGTRSG & XMC_HRPWM_COMPARATOR_STATUS); } /** @@ -1642,12 +1618,12 @@ __STATIC_INLINE uint32_t XMC_HRPWM_GetCMPInput(XMC_HRPWM_t *const hrpwm, const u * \parRelated APIs:
      * */ -__STATIC_INLINE void XMC_HRPWM_SetCsgPowerMode(XMC_HRPWM_t *const hrpwm, - const XMC_HRPWM_CSG_SLICE_t slice, - const XMC_HRPWM_CSG_POWER_MODE_t power_mode) +__STATIC_INLINE void XMC_HRPWM_SetCsgPowerMode(XMC_HRPWM_t *const hrpwm, + const XMC_HRPWM_CSG_SLICE_t slice, + const XMC_HRPWM_CSG_POWER_MODE_t power_mode) { XMC_ASSERT("XMC_HRPWM_SetCsgPowerMode:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + hrpwm->CSGCFG &= ~(3U << (slice * 2U)); hrpwm->CSGCFG |= power_mode << (slice * 2U); } @@ -1844,7 +1820,7 @@ __STATIC_INLINE void XMC_HRPWM_HRC_Set_HR_Source(XMC_HRPWM_HRC_t *const hrc, XMC XMC_ASSERT("XMC_HRPWM_HRC_Set_HR_Source:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); hrc->SSC = (uint32_t) source; } - + /*********************************************************************************************************************** * API PROTOTYPES - HRPWM CSG SLICE **********************************************************************************************************************/ @@ -2132,7 +2108,7 @@ __STATIC_INLINE void XMC_HRPWM_CSG_UpdateFilterWindow(XMC_HRPWM_CSG_t *const csg * XMC_HRPWM_CSG_UpdateFilterWindow()
      */ -__STATIC_INLINE void XMC_HRPWM_CSG_UpdatePulseClk(XMC_HRPWM_CSG_t *const csg, uint32_t value) +__STATIC_INLINE void XMC_HRPWM_CSG_UpdatePulseClk(XMC_HRPWM_CSG_t *const csg, uint32_t value) { XMC_ASSERT("XMC_HRPWM_CSG_UpdatePulseClk:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); csg->SPC = value & HRPWM0_CSG_SPC_SPSWV_Msk; @@ -2159,7 +2135,7 @@ __STATIC_INLINE void XMC_HRPWM_CSG_UpdateDACRefDSV1(XMC_HRPWM_CSG_t *const csg, { XMC_ASSERT("XMC_HRPWM_CSG_UpdateDACRefDSV1:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); csg->SDSV1 = value & HRPWM0_CSG_SDSV1_SDSV1_Msk; -} +} /** * @param csg Constant pointer to XMC_HRPWM_CSG_t, pointing to the CSG channel base address @@ -2303,10 +2279,7 @@ __STATIC_INLINE void XMC_HRPWM_CSG_ClrEventSW(XMC_HRPWM_CSG_t *const csg, XMC_HR /** * @} */ - -/** - * @} - */ + #endif /* #if defined(HRPWM0) */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h b/cores/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h index 7b471566..90bc12d6 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_hrpwm_map.h @@ -1,66 +1,52 @@ /** * @file xmc_hrpwm_map.h - * @date 2015-06-20 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Updated copyright and change history section. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ - + /** * * @brief HRPWM mapping for XMC4 microcontroller family.
      * */ - -/********************************************************************************************************************* - * HEADER FILES - ********************************************************************************************************************/ -#include "xmc_hrpwm.h" #ifndef XMC_HRPWM_MAP_H #define XMC_HRPWM_MAP_H diff --git a/cores/xmc_lib/XMCLib/inc/xmc_i2c.h b/cores/xmc_lib/XMCLib/inc/xmc_i2c.h index 4902d75e..98a7e372 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_i2c.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_i2c.h @@ -1,76 +1,43 @@ /** * @file xmc_i2c.h - * @date 2016-05-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
      - * - * 2015-05-20: - * - Description updated
      - * - Added XMC_I2C_CH_TriggerServiceRequest() and XMC_I2C_CH_SelectInterruptNodePointer()
      - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
      - * - * 2015-08-27: - * - Added APIs for external input for BRG configuration:XMC_I2C_CH_ConfigExternalInputSignalToBRG()
      - * - * 2015-09-01: - * - Added APIs for enabling or disabling the ACK response to a 0x00 slave address: XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and - * XMC_I2C_CH_DisableSlaveAcknowledgeTo00().
      - * - Modified XMC_I2C_CH_SetInputSource() API for avoiding complete DXCR register overwriting.
      - * - Modified XMC_I2C_CH_EVENT_t enum for supporting XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() - * for supporting multiple events configuration
      - * - * 2015-10-02: - * - Fix 10bit addressing - * - * 2015-10-07: - * - Fix register access in XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and XMC_I2C_CH_DisableSlaveAcknowledgeTo00() APIs. - * - Naming of APIs modified: from XMC_I2C_CH_EnableSlaveAcknowledgeTo00() to XMC_I2C_CH_EnableAcknowledgeAddress0() - * and from XMC_I2C_CH_DisableSlaveAcknowledgeTo00() to XMC_I2C_CH_DisableAcknowledgeAddress0(). - * - * 2016-05-20: - * - Added XMC_I2C_CH_EnableDataTransmission() and XMC_I2C_CH_DisableDataTransmission() - * - * 2016-08-17: - * - Improved documentation of slave address passing - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -83,14 +50,10 @@ #include "xmc_usic.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup I2C - * @brief Inter Integrated Circuit(IIC) driver for the XMC microcontroller family. + * @brief Inter Integrated Circuit(IIC) driver for the XMC microcontroller family. * * USIC IIC Features:
      * * Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA)
      @@ -172,14 +135,14 @@ typedef enum XMC_I2C_CH_STATUS_FLAG typedef enum XMC_I2C_CH_RECEIVER_STATUS_FLAG { XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK = 0x1U, /**< Bit 8: Value of Received Acknowledgement bit */ - XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN = 0x2U, /**< Bit 9: A 1 at this bit position indicates that after a (repeated) start condition - followed by the address reception the first data byte of a new frame has + XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN = 0x2U, /**< Bit 9: A 1 at this bit position indicates that after a (repeated) start condition + followed by the address reception the first data byte of a new frame has been received. A 0 at this bit position indicates further data bytes */ - XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE = 0x4U, /**< Bit 10: A 0 at this bit position indicates that the data byte has been received + XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE = 0x4U, /**< Bit 10: A 0 at this bit position indicates that the data byte has been received when the device has been in slave mode, whereas a 1 indicates a reception in master mode */ - XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR = 0x8U, /**< Bit 11: A 1 at this bit position indicates an incomplete/erroneous + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR = 0x8U, /**< Bit 11: A 1 at this bit position indicates an incomplete/erroneous data byte in the receive buffer */ - XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR = 0x10 /**< Bit 12: A 0 at this bit position indicates that the programmed address + XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR = 0x10 /**< Bit 12: A 0 at this bit position indicates that the programmed address has been received. A 1 indicates a general call address. */ } XMC_I2C_CH_RECEIVER_STATUS_FLAG_t; @@ -224,11 +187,11 @@ typedef enum XMC_I2C_CH_INPUT #if UC_FAMILY == XMC1 XMC_I2C_CH_INPUT_SDA1 = 3U, XMC_I2C_CH_INPUT_SDA2 = 5U, -#endif +#endif XMC_I2C_CH_INPUT_SCL = 1U, /**< selection of scl input stage */ #if UC_FAMILY == XMC1 XMC_I2C_CH_INPUT_SCL1 = 4U -#endif +#endif } XMC_I2C_CH_INPUT_t; /** @@ -252,7 +215,8 @@ typedef enum XMC_I2C_CH_INTERRUPT_NODE_POINTER typedef struct XMC_I2C_CH_CONFIG { uint32_t baudrate; /**< baud rate configuration upto max of 400KHz */ - uint16_t address; /**< slave address + bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */ + uint16_t address; /**< slave address A 7-bit address needs to be left shifted it by 1. A 10-bit address needs to be ORed with XMC_I2C_10BIT_ADDR_GROUP. */ } XMC_I2C_CH_CONFIG_t; @@ -268,6 +232,7 @@ extern "C" { /** * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t * @param config Constant pointer to I2C channel config structure of type @ref XMC_I2C_CH_CONFIG_t + * @param init_brg Selects if the baudrate generator should be configured automatically. * * @return None
      * @@ -281,8 +246,28 @@ extern "C" { * \parRelated APIs:
      * XMC_USIC_CH_Enable()\n\n */ +void XMC_I2C_CH_InitEx(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config, bool init_brg); -void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config); +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param config Constant pointer to I2C channel config structure of type @ref XMC_I2C_CH_CONFIG_t + * + * @return None
      + * + * \parDescription:
      + * Initializes the I2C \a channel.
      + * + * \par + * Configures the data format in SCTR register. Sets the slave address, baud rate. Enables transmit data valid, clears status flags + * and disables parity generation.
      + * + * \parRelated APIs:
      + * XMC_USIC_CH_Enable()\n\n + */ +__STATIC_INLINE void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config) +{ + XMC_I2C_CH_InitEx(channel, config, true); +} /** * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t @@ -301,6 +286,24 @@ void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *co */ XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); +/** + * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t + * @param rate baud rate of I2C channel + * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter of signal at the cost of frequency selection + * + * @return None
      + * + * \parDescription:
      + * Sets the rate of I2C \a channel. + * + * \parNote:
      + * Standard over sampling is considered if rate <= 100KHz and fast over sampling is considered if rate > 100KHz.
      + * + * \parRelated APIs:
      + * XMC_USIC_CH_SetBaudrate()\n\n + */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, bool normal_divider_mode); + /** * @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t * @@ -355,7 +358,7 @@ XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel); * XMC_I2C_CH_EnableEvent(), NVIC_SetPriority(), NVIC_EnableIRQ(), XMC_I2C_CH_SetInputSource()
      */ __STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const uint8_t service_request) + const uint8_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, service_request); } @@ -381,11 +384,11 @@ __STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const cha * XMC_I2C_CH_EnableEvent() \n\n\n */ __STATIC_INLINE void XMC_I2C_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_I2C_CH_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_I2C_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, - (uint32_t)service_request); + (uint32_t)service_request); } /** @@ -614,7 +617,7 @@ uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel); */ __STATIC_INLINE uint8_t XMC_I2C_CH_GetReceiverStatusFlag(XMC_USIC_CH_t *const channel) { - return((uint8_t)((channel->RBUF) >> 8U)); + return ((uint8_t)((channel->RBUF) >> 8U)); } /** @@ -693,11 +696,11 @@ __STATIC_INLINE void XMC_I2C_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, ui * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n */ __STATIC_INLINE void XMC_I2C_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, - const uint16_t pdiv, - const uint32_t oversampling, - const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) { - XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,oversampling,combination_mode); + XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel, pdiv, oversampling, combination_mode); } /** @@ -764,16 +767,72 @@ __STATIC_INLINE void XMC_I2C_CH_EnableDataTransmission(XMC_USIC_CH_t *const chan */ __STATIC_INLINE void XMC_I2C_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) { - XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); } -#ifdef __cplusplus +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
      + * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n + * This clock can be used as a clock reference for external devices. This is not enabled during initialization in + * XMC_I2C_CH_Init(). Invoke XMC_I2C_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by + * XMC_I2C_CH_DisableMasterClock(). + * + * \parRelated APIs:
      + * XMC_I2C_CH_DisableMasterClock() + */ +__STATIC_INLINE void XMC_I2C_CH_EnableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_MCLK_Msk; } -#endif /** - * @} + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
      + * Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n + * This clock can be enabled by invoking XMC_I2C_CH_EnableMasterClock() as needed in the program. + * + * \parRelated APIs:
      + * XMC_I2C_CH_EnableMasterClock() */ +__STATIC_INLINE void XMC_I2C_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_MCLK_Msk; +} + + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * + * @return None + * + * \parDescription:
      + * To respect the specified SDA hold time of 300 ns for standard mode and fast mode after + * a falling edge of signal SCL, a hold delay tHDEL has been introduced. It also prevents an + * erroneous detection of a start or a stop condition. The length of this delay can be + * programmed by bit field PCR.HDEL. Taking into account the input sampling and output + * update, bit field HDEL can be programmed according to: + * - HDEL >= 300ns x fPPP - (3 x fPPP/fPERIH) + 1 (with digital filter and HDELmin = 2) + * - HDEL >= 300ns x fPPP - (3 x fPPP/fPERIH) + 2 (without digital filter and HDELmin = 1) + * If the digital input filter is used, HDEL compensates the filter delay of 2 filter periods (fPPP + * should be used) in case of a spike on the input signal. This ensures that a data bit on the + * SDA line changing just before the rising edge or behind the falling edge of SCL will not + * be treated as a start or stop condition. + */ +__STATIC_INLINE void XMC_I2C_CH_SetHoldDelay(XMC_USIC_CH_t *const channel, uint32_t hdel) +{ + channel->PCR_IICMode = (channel->PCR_IICMode & (uint32_t)~USIC_CH_PCR_IICMode_HDEL_Msk) | ((hdel << USIC_CH_PCR_IICMode_HDEL_Pos) & USIC_CH_PCR_IICMode_HDEL_Msk); +} + +#ifdef __cplusplus +} +#endif /** * @} diff --git a/cores/xmc_lib/XMCLib/inc/xmc_i2s.h b/cores/xmc_lib/XMCLib/inc/xmc_i2s.h index 8b8c2160..d6f7b454 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_i2s.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_i2s.h @@ -1,61 +1,41 @@ /** * @file xmc_i2s.h - * @date 2016-06-30 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2023, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-08-21: - * - Initial
      - * - * 2015-08-24: - * - Added APIs for enabling/disabling delay compensation XMC_I2S_CH_DisableDelayCompensation() and - * XMC_I2S_CH_EnableDelayCompensation()
      - * - * 2015-09-01: - * - Modified XMC_I2S_CH_SetInputSource() for avoiding complete DXCR register overwriting.
      - * - Modified XMC_I2S_CH_EVENT_t enum for supporting XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent()
      - * for supporting multiple events configuration
      - * - * 2015-09-14: - * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length
      - * - * 2016-05-20: - * - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission() - * - * 2016-06-30: - * - Documentation updates. + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -69,11 +49,6 @@ *********************************************************************************************************************/ #include "xmc_usic.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - /** * @addtogroup I2S * @brief (IIS) driver for the XMC microcontroller family. @@ -229,6 +204,7 @@ typedef enum XMC_I2S_CH_BUS_MODE typedef struct XMC_I2S_CH_CONFIG { uint32_t baudrate; /**< Module baud rate for communication */ + bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */ uint8_t data_bits; /**< Data word length. A data frame can consists of several data words. \n Value configured as USIC channel word length. \n \b Range: minimum= 1, maximum= 16*/ @@ -252,6 +228,7 @@ extern "C" { * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection * @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t. + * @param init_brg Selects if the baudrate generator should be configured automatically. * @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n * \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n * @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed. @@ -270,7 +247,34 @@ extern "C" { * \parRelated APIs:
      * XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n */ -void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config); +void XMC_I2S_CH_InitEx(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config, bool init_brg); + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection + * @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t. + * @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n + * \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n + * @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed. + * + * \parDescription
      + * Initializes the USIC channel for I2S protocol.\n\n + * During the initialization, USIC channel is enabled and baudrate is configured. + * After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length). + * The number of data bits transferred after a change of signal WA is defined by config->frame_length. + * A data frame can consist of several data words with a data word length defined by config->data_bits. + * The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA. + * The system word length is set by default to the frame length defined by config->frame_length. + * + * XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel. + * + * \parRelated APIs:
      + * XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n + */ +__STATIC_INLINE void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config) +{ + XMC_I2S_CH_InitEx(channel, config, true); +} /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. @@ -324,6 +328,23 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel); */ XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param rate Bus speed in bits per second + * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection + * + * @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n + * XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n + * XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range. + * + * \parDescription:
      + * Sets the bus speed in bits per second + * + * \parRelated APIs:
      + * XMC_I2S_CH_Init(), XMC_I2S_CH_Stop() + */ +XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode); + /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param sclk_cycles_system_word_length system word length in terms of sclk clock cycles. @@ -335,7 +356,7 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const u * This value has to be always higher than 1U and lower than the data with (SCTR.FLE) * */ -void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length); +void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel, uint32_t sclk_cycles_system_word_length); /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. @@ -374,7 +395,7 @@ void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, cons __STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number) { /* Transmit dummy data */ - XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number); + XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU, channel_number); } /** @@ -551,10 +572,10 @@ __STATIC_INLINE void XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n */ __STATIC_INLINE void XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, - const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) + const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) { XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)0U, - (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); + (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); } /** @@ -612,8 +633,8 @@ __STATIC_INLINE void XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t *const channel, con * the I2S communication. */ __STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel, - const XMC_I2S_CH_INPUT_t input, - const uint8_t source) + const XMC_I2S_CH_INPUT_t input, + const uint8_t source) { channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk; XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); @@ -633,7 +654,7 @@ __STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel, * needed later in the program. */ __STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const channel, - const XMC_I2S_CH_WA_POLARITY_t wa_inversion) + const XMC_I2S_CH_WA_POLARITY_t wa_inversion) { /* Configuration of Protocol Control Register */ channel->PCR_IISMode = (uint32_t)((channel->PCR_IISMode & (~USIC_CH_PCR_IISMode_SELINV_Msk)) | (uint32_t)wa_inversion); @@ -655,7 +676,7 @@ __STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const c * XMC_I2S_CH_DisableInputInversion() */ __STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, - const XMC_I2S_CH_INPUT_t input) + const XMC_I2S_CH_INPUT_t input) { XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); } @@ -675,7 +696,7 @@ __STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channe * XMC_I2S_CH_EnableInputInversion() */ __STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, - const XMC_I2S_CH_INPUT_t input) + const XMC_I2S_CH_INPUT_t input) { XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); } @@ -700,7 +721,7 @@ __STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const chann * XMC_USIC_CH_EnableEvent() */ __STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const uint8_t service_request) + const uint8_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request); } @@ -726,11 +747,11 @@ __STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const cha * XMC_I2S_CH_EnableEvent() \n\n\n */ __STATIC_INLINE void XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, - (uint32_t)service_request); + (uint32_t)service_request); } /** @@ -820,7 +841,7 @@ __STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const chan */ __STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) { - XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); } #ifdef __cplusplus @@ -831,7 +852,4 @@ __STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const cha * @} */ -/** - * @} - */ #endif /* XMC_I2S_H_ */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_ledts.h b/cores/xmc_lib/XMCLib/inc/xmc_ledts.h index 16ad4ea6..8cf6002b 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_ledts.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_ledts.h @@ -1,48 +1,41 @@ /** * @file xmc_ledts.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial draft
      - * - Documentation improved
      - * - New API added: XMC_LEDTS_SetActivePADNo()
      - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -54,20 +47,16 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_common.h" #if defined(LEDTS0) #include "xmc_scu.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup LEDTS * @brief LED and Touch-Sense control(LEDTS) driver for the XMC controller family. - * + * * The LED and Touch-Sense (LEDTS) drives LEDs and controls touch pads used as human-machine interface (HMI) in an * application. The LEDTS can measure the capacitance of up to 8 touch pads, can also drive up to 64 LEDs in an LED matrix. * Touch pads and LEDs can share pins to minimize the number of pins needed for such applications, this is realized by @@ -75,7 +64,7 @@ * * This device contains LEDTS kernel that has an LED driving function and a touch-sensing function. * - * It is recommended to set up all configurations for the LEDTS in all Special Function Registers(SFR) before + * It is recommended to set up all configurations for the LEDTS in all Special Function Registers(SFR) before * enabling and starting LED and/or touch-sense function(s). * * This Low Level Driver(LLD) provides APIs to configure and control LED functionality, Touch-Sense functionality and @@ -146,7 +135,8 @@ * Defines LEDTS module structure. This holds data and configuration registers of LEDTS modules. Use type * XMC_LEDTS_GLOBAL_t for this data structure.\n */ -typedef struct XMC_LEDTS_GLOBAL{ /*!< (@ 0x50020000) LEDTS Structure */ +typedef struct XMC_LEDTS_GLOBAL /*!< (@ 0x50020000) LEDTS Structure */ +{ __I uint32_t ID; /*!< (@ 0x50020000) Module Identification Register */ __IO uint32_t GLOBCTL; /*!< (@ 0x50020004) Global Control Register */ __IO uint32_t FNCTL; /*!< (@ 0x50020008) Function Control Register */ @@ -155,7 +145,7 @@ typedef struct XMC_LEDTS_GLOBAL{ /*!< (@ 0x50020000) LEDTS St __IO uint32_t LINE[2]; /*!< (@ 0x50020014) Line Pattern Register 0 */ __IO uint32_t LDCMP[2]; /*!< (@ 0x5002001C) LED Compare Register 0 */ __IO uint32_t TSCMP[2]; /*!< (@ 0x50020024) Touch-sense Compare Register 0 */ - } XMC_LEDTS_GLOBAL_t; +} XMC_LEDTS_GLOBAL_t; /********************************************************************************************************************* * ENUMS @@ -430,7 +420,7 @@ typedef enum XMC_LEDTS_TF_INTERRUPT_FLAG } XMC_LEDTS_TF_INTERRUPT_FLAG_t; /** - * Defines Autoscan time period interrupt flag status. Use type XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t for this enum. + * Defines Autoscan time period interrupt flag status. Use type XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t for this enum. */ typedef enum XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG { @@ -480,16 +470,16 @@ typedef enum XMC_LEDTS_TS_INPUT /********************************************************************************************************************* * DATA STRUCTURES ********************************************************************************************************************/ - /*Anonymous structure/union guard start*/ - #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +/*Anonymous structure/union guard start*/ +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** - * Data structure for initialization of global features common to LED and touch-sense function. Use + * Data structure for initialization of global features common to LED and touch-sense function. Use * type XMC_LEDTS_GLOBAL_CONFIG_t for this structure. */ typedef struct XMC_LEDTS_GLOBAL_CONFIG @@ -499,19 +489,19 @@ typedef struct XMC_LEDTS_GLOBAL_CONFIG struct { uint32_t : 2; - uint32_t clock_generation:1; /**< When this bit is set LEDTS counter takes its clock from another master + uint32_t clock_generation: 1; /**< When this bit is set LEDTS counter takes its clock from another master kernel. Kernel generates its own clock when this bit is not set (CMTR). Refer @ref XMC_LEDTS_CLOCK_TYPE_t enum for possible values. */ - - uint32_t autoscan_synchronization:1; /**< Set this bit to synchronize start of autoscan time period with master + + uint32_t autoscan_synchronization: 1; /**< Set this bit to synchronize start of autoscan time period with master kernel(ENSYNC). Refer @ref XMC_LEDTS_TP_SYNC_t enum for possible values. */ uint32_t : 4; - uint32_t suspend_response:1; /**< Suspend request configuration(SUSCFG). + uint32_t suspend_response: 1; /**< Suspend request configuration(SUSCFG). Refer @ref XMC_LEDTS_SUSPEND_t enum for possible values.*/ }; uint32_t globctl; }; -}XMC_LEDTS_GLOBAL_CONFIG_t; +} XMC_LEDTS_GLOBAL_CONFIG_t; /** * Data structure for LED function initialization. Use type XMC_LEDTS_LED_CONFIG_t for this structure. @@ -523,20 +513,20 @@ typedef struct XMC_LEDTS_LED_CONFIG struct { uint32_t : 28; - uint32_t column_active_level:1; /**< When this bit is set LED column level is active high, otherwise column + uint32_t column_active_level: 1; /**< When this bit is set LED column level is active high, otherwise column level is active low(COLLEV). Refer @ref XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t enum for possible values.*/ - - uint32_t no_of_led_columns:3; /**< Defines number of LED columns(NR_LEDCOL). Range 0 - 7. + + uint32_t no_of_led_columns: 3; /**< Defines number of LED columns(NR_LEDCOL). Range 0 - 7. Refer @ref XMC_LEDTS_NUMBER_LED_COLUMNS_t enum for possible values. */ }; uint32_t fnctl; }; -}XMC_LEDTS_LED_CONFIG_t; +} XMC_LEDTS_LED_CONFIG_t; /** * Data structure for basic Touch-Sense function initialization. Use type XMC_LEDTS_TS_CONFIG_BASIC_t for - * this structure. + * this structure. */ typedef struct XMC_LEDTS_TS_CONFIG_BASIC { @@ -545,28 +535,28 @@ typedef struct XMC_LEDTS_TS_CONFIG_BASIC struct { uint32_t : 16; - uint32_t no_of_accumulation:4; /**< Defines number of times touch-sense input pin is enabled in touch-sense + uint32_t no_of_accumulation: 4; /**< Defines number of times touch-sense input pin is enabled in touch-sense time slice of consecutive frames(ACCCNT). Range 0 - 15. Refer @ref XMC_LEDTS_ACCUMULATION_COUNT_t enum type for possible values. */ - - uint32_t common_compare:1; /**< When this bit is set it enables common compare for all touch sense inputs. + + uint32_t common_compare: 1; /**< When this bit is set it enables common compare for all touch sense inputs. Disables common compare when not set(TSCCMP). Refer @ref XMC_LEDTS_COMMON_COMPARE_t enum for possible values.*/ uint32_t : 2; - uint32_t counter_auto_reset:1; /**< When this bit is set TS-counter is automatically reset to 00H on first pad + uint32_t counter_auto_reset: 1; /**< When this bit is set TS-counter is automatically reset to 00H on first pad turn of a new touch-sense pin(TSCTRR). Refer @ref XMC_LEDTS_TS_COUNTER_AUTO_RESET_t enum for possible values.*/ - - uint32_t counter_saturation:1; /**< When this bit is set TS-counter stops counting in the touch-sense time slice - of the same frame when it reaches FFH (TSCTRSAT). + + uint32_t counter_saturation: 1; /**< When this bit is set TS-counter stops counting in the touch-sense time slice + of the same frame when it reaches FFH (TSCTRSAT). Refer @ref XMC_LEDTS_TS_COUNTER_SATURATION_t enum for possible values. */ - - uint32_t no_of_touch_inputs:3; /**< Defines number of touch-sense inputs (NR_TSIN). Range 0 - 7. + + uint32_t no_of_touch_inputs: 3; /**< Defines number of touch-sense inputs (NR_TSIN). Range 0 - 7. Refer @ref XMC_LEDTS_NUMBER_TS_INPUT_t enum for possible values. */ }; uint32_t fnctl; }; -}XMC_LEDTS_TS_CONFIG_BASIC_t; +} XMC_LEDTS_TS_CONFIG_BASIC_t; /** * Data structure for advanced Touch-Sense function initialization. Use type XMC_LEDTS_TS_CONFIG_ADVANCED_t @@ -579,11 +569,11 @@ typedef struct XMC_LEDTS_TS_CONFIG_ADVANCED struct { uint32_t : 9; - uint32_t validation_mask:3; /**< This bit-field defines number of LSB bits to mask for TS counter and shadow + uint32_t validation_mask: 3; /**< This bit-field defines number of LSB bits to mask for TS counter and shadow TS counter comparison when Time Frame validation is enabled(MASKVAL). Refer @ref XMC_LEDTS_TS_COUNTER_MASK_t enum for possible values.*/ - - uint32_t time_frame_validation:1; /**< Disable or enable (extended) time frame validation(FENVAL). + + uint32_t time_frame_validation: 1; /**< Disable or enable (extended) time frame validation(FENVAL). when validation fails time frame interrupt is not triggered. Refer @ref XMC_LEDTS_TF_VALIDATION_t enum for possible values.*/ uint32_t : 1; @@ -595,29 +585,29 @@ typedef struct XMC_LEDTS_TS_CONFIG_ADVANCED { struct { - uint32_t first_pad_turn:3; /**< This bit-field denotes TSIN[x] pin on which oscillations are measured + uint32_t first_pad_turn: 3; /**< This bit-field denotes TSIN[x] pin on which oscillations are measured currently/next(PADT). Refer @ref XMC_LEDTS_PAD_TURN_t enum for possible values.*/ - - uint32_t pad_turn_control:1; /**< Control pad turn via HW or SW(PADTSW). + + uint32_t pad_turn_control: 1; /**< Control pad turn via HW or SW(PADTSW). Refer @ref XMC_LEDTS_PAD_TURN_SW_CONTROL_t enum for possible values. */ - - uint32_t external_pullup:1; /**< Disable or enable external pull-up on touch pin(EPULL). + + uint32_t external_pullup: 1; /**< Disable or enable external pull-up on touch pin(EPULL). Refer @ref XMC_LEDTS_EXT_PULLUP_COLA_t enum for possible values. */ uint32_t : 16; - uint32_t pin_low_extend:2; /**< This bit extends touch-sense output for pin-low-level configuration for - adjustment of oscillation per user system. + uint32_t pin_low_extend: 2; /**< This bit extends touch-sense output for pin-low-level configuration for + adjustment of oscillation per user system. Refer @ref XMC_LEDTS_EXTEND_TS_OUTPUT_t enum for possible values. */ }; uint32_t fnctl; }; -}XMC_LEDTS_TS_CONFIG_ADVANCED_t; +} XMC_LEDTS_TS_CONFIG_ADVANCED_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif #ifdef __cplusplus @@ -638,9 +628,9 @@ extern "C" { * XMC_LEDTS_STATUS_RUNNING - LEDTS module currently active. Refer @ref XMC_LEDTS_STATUS_t enum type.
      * * \parDescription
      - * Initializes and configures GLOBCTL register of \a ledts with configuration data pointed by \a config. + * Initializes and configures GLOBCTL register of \a ledts with configuration data pointed by \a config. * \par - * This API selects clock source (GLOBCTL.CMTR), enables/disables auto scan sync(GLOBCTL.ENSYNC) & + * This API selects clock source (GLOBCTL.CMTR), enables/disables auto scan sync(GLOBCTL.ENSYNC) & * suspend config(GLOBCTL.SUSCFG).
      * Call this API to initialize global register fields common to both LED and touch-sense(TS).\n * @@ -649,7 +639,7 @@ extern "C" { * * \parRelated API's
      * XMC_LEDTS_StopCounter()\n - * + * */ XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config); @@ -677,7 +667,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDT * * \parRelated API's
      * XMC_LEDTS_StopCounter() XMC_LEDTS_InitGlobal()\n - * + * */ XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config); @@ -697,8 +687,8 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_L * \par * This API sets number of touch inputs(FNCTL.NR_TSIN), accumulate count on touch input(FNCTL.ACCCNT). * \par - * This API Enables/disables common compare(FNCTL.TSCCMP), TS counter auto reset(FNCTL.TSCTRR), counter - * saturation(FNCTL.TSCTRSAT) and enables TS functionality(GLOBCTL.TS_EN). + * This API Enables/disables common compare(FNCTL.TSCCMP), TS counter auto reset(FNCTL.TSCTRR), counter + * saturation(FNCTL.TSCTRSAT) and enables TS functionality(GLOBCTL.TS_EN). * \par * Call this API to configure \a FNCTL & \a GLOBCTL registers for basic touch sense function. Global initialization * of LEDTS module should be done by calling XMC_LEDTS_InitGlobal() prior to calling this API.\n @@ -708,7 +698,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_L * * \parRelated API's
      * XMC_LEDTS_StopCounter() XMC_LEDTS_InitGlobal()\n - * + * */ XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config); @@ -741,7 +731,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LED * * \parRelated API's
      * XMC_LEDTS_StopCounter(), XMC_LEDTS_InitTSBasic().\n - * + * */ XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config); @@ -765,7 +755,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC * * \parRelated API's
      * XMC_LEDTS_StopCounter(), XMC_LEDTS_InitLED(), XMC_LEDTS_InitTSBasic(), XMC_LEDTS_InitTSAdvanced().\n - * + * */ void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler); @@ -778,12 +768,12 @@ void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler); * * \parDescription
      * Stops the LEDTS module by programming the CLK_PS bit field(with value = 0) of GLOBCTL register.
      - * This could be done when it is required to change some module configuration which requires the LEDTS-counter + * This could be done when it is required to change some module configuration which requires the LEDTS-counter * to be stopped before the register bit/bit field can be programmed.
      Call this API to stop LEDTS counter.\n * * \parRelated API's
      * XMC_LEDTS_StartCounter(), XMC_LEDTS_InitLED(), XMC_LEDTS_InitTSBasic(), XMC_LEDTS_InitTSAdvanced().\n - * + * */ void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts); @@ -791,7 +781,7 @@ void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts); * * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
      * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
      - * + * * @return * None.
      * @@ -803,7 +793,7 @@ void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts); * * \parRelated API's
      * XMC_LEDTS_DisableInterrupt().\n - * + * */ __STATIC_INLINE void XMC_LEDTS_EnableInterrupt(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) { @@ -816,7 +806,7 @@ __STATIC_INLINE void XMC_LEDTS_EnableInterrupt(XMC_LEDTS_t *const ledts, uint32_ * * @param ledts Constant pointer to LEDTS module structure. Refer @ref XMC_LEDTS_GLOBAL_t data structure.
      * @param interrupt_mask mask value of @ref XMC_LEDTS_INTERRUPT_t enum type.
      - * + * * @return * None.
      * @@ -828,7 +818,7 @@ __STATIC_INLINE void XMC_LEDTS_EnableInterrupt(XMC_LEDTS_t *const ledts, uint32_ * * \parRelated API's
      * XMC_LEDTS_EnableInterrupt().\n - * + * */ __STATIC_INLINE void XMC_LEDTS_DisableInterrupt(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask) { @@ -855,7 +845,7 @@ __STATIC_INLINE void XMC_LEDTS_DisableInterrupt(XMC_LEDTS_t *const ledts, uint32 * * \parRelated API's
      * XMC_LEDTS_ClearInterruptFlag().\n - * + * */ uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts); @@ -875,12 +865,12 @@ uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts); * Typically used along with XMC_LEDTS_ReadInterruptFlag() to figure out which event triggered the interrupt.\n * * \parNote
      - * Calling this API moves interrupt from pending/active state to inactive state. If the interrupt is pulsed, + * Calling this API moves interrupt from pending/active state to inactive state. If the interrupt is pulsed, * failing to clear the event bit might cause CPU to immediately re-enter the interrupt service routine(ISR).\n * * \parRelated API's
      * XMC_LEDTS_ReadInterruptFlag().\n - * + * */ void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask); @@ -950,9 +940,9 @@ void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUM * None.
      * * \parDescription
      - * Programs the respective LDCMP1 register bit field CMP_LDA_TSCOM with \a common_size. + * Programs the respective LDCMP1 register bit field CMP_LDA_TSCOM with \a common_size. * \par - * Call this API to adjust the size of the common oscillation window to increase/decrease the number of recorded + * Call this API to adjust the size of the common oscillation window to increase/decrease the number of recorded * number of oscillation counts for all touch-sense inputs.\n * */ @@ -988,7 +978,7 @@ uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts); * \parNote
      * NR_LEDCOL bit field can only be modified when LEDTS counter is not running, use XMC_LEDTS_StopCounter() * to stop LEDTS module before calling this API.\n - * + * * \parRelated API's
      * XMC_LEDTS_StopCounter().\n */ @@ -1009,7 +999,7 @@ void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count); * * \parNote
      * This is the latched value of the TS-counter(on every extended time frame event).\n - * + * * \parRelated API's
      * XMC_LEDTS_ReadInterruptFlag().\n */ @@ -1039,10 +1029,6 @@ void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_T } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_math.h b/cores/xmc_lib/XMCLib/inc/xmc_math.h index 9cd16708..d64bcc2c 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_math.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_math.h @@ -1,62 +1,43 @@ /** * @file xmc_math.h - * @date 2015-10-08 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** - * - * Change History - * -------------- - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
      - * - Updated copyright and change history section. - * - * 2015-08-25: - * - XMC_MATH_ClearEvent() API is updated to set the event clear flag bit.
      - * - * 2015-09-23: - * - Added SQRT functions - * - * 2015-10-08: - * - Return values for sin(), cos(), sinh(), cosh(), arctan() are corrected. - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -70,22 +51,18 @@ extern "C" { /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_common.h" #if defined(MATH) -#include +#include "xmc_scu.h" -/** - * @addtogroup XMClib - * @{ - */ /** * @addtogroup MATH * @{ * @brief MATH Coprocessor (MATH) driver for the XMC1302 microcontroller family
      - * - * The MATH Coprocessor (MATH) module comprises of two independent sub-blocks to support the CPU in math-intensive + * + * The MATH Coprocessor (MATH) module comprises of two independent sub-blocks to support the CPU in math-intensive * computations: a Divider Unit (DIV) for signed and unsigned 32-bit division operations and a CORDIC * (COrdinate Rotation DIgital Computer) Coprocessor for computation of trigonometric, linear or hyperbolic functions.
      * @@ -101,7 +78,7 @@ extern "C" { * All non-blocking MATH APIs are not atomic and hence occurence of interrupts during the normal execution of * these APIs may lead to erroneous results. User has to exercise caution while using these APIs. * - * Example: + * Example: * Execution of divide instruction (/) in an ISR during the normal execution of non-blocking APIs may give erroneous results. * */ @@ -1075,12 +1052,8 @@ int32_t XMC_MATH_CORDIC_Q31_Sqrt(int32_t x); * @} */ -/** - * @} - */ - #endif /* end of #if defined(MATH) */ - + #ifdef __cplusplus } #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_pau.h b/cores/xmc_lib/XMCLib/inc/xmc_pau.h index c55f43d1..e9f833a7 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_pau.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_pau.h @@ -1,50 +1,43 @@ /** * @file xmc_pau.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version - * - * 2015-05-20: - * - Documentation updated + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -58,17 +51,12 @@ #include "xmc_common.h" #if defined(PAU) - -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup PAU * @brief Peripheral Access Unit (PAU) driver for the XMC1000 microcontroller family * - * The Peripheral Access Unit (PAU) supports access control of memories and peripherals. + * The Peripheral Access Unit (PAU) supports access control of memories and peripherals. * It allows user application to enable/disable the access to the registers of a peripheral. * It generates a HardFault exception when there is an access to a disabled or unassigned * address location. It also provides information on the availability of peripherals and @@ -77,8 +65,8 @@ * The PAU low level driver provides functions to check the availability of peripherals * and to enable/disable peripheral access. * @{ - */ - + */ + /********************************************************************************************************************* * MACROS *********************************************************************************************************************/ @@ -99,14 +87,14 @@ /** * Status return values for PAU low level driver - */ + */ typedef enum XMC_PAU_STATUS { XMC_PAU_STATUS_OK = 0U, /**< Operation successful */ XMC_PAU_STATUS_BUSY = 1U, /**< Busy with a previous request */ XMC_PAU_STATUS_ERROR = 2U /**< Operation unsuccessful */ } XMC_PAU_STATUS_t; - + /** * PAU peripheral select */ @@ -116,127 +104,127 @@ typedef enum XMC_PAU_PERIPHERAL XMC_PAU_PERIPHERAL_RAM_BLOCK1 = PAU_PRIVDIS0_PDIS5_Msk, /**< RAM Block 1 Privilege Disable Flag */ XMC_PAU_PERIPHERAL_RAM_BLOCK2 = PAU_PRIVDIS0_PDIS6_Msk, /**< RAM Block 2 Privilege Disable Flag */ XMC_PAU_PERIPHERAL_RAM_BLOCK3 = PAU_PRIVDIS0_PDIS7_Msk, /**< RAM Block 3 Privilege Disable Flag */ - #if defined(WDT) - XMC_PAU_PERIPHERAL_WDT = PAU_PRIVDIS0_PDIS19_Msk, /**< WDT Privilege Disable Flag */ - #endif - #if defined(MATH) - XMC_PAU_PERIPHERAL_MATH_GLOBAL_AND_DIV = PAU_PRIVDIS0_PDIS20_Msk, /**< MATH Global SFRs and Divider Privilege Disable Flag */ - #endif - #if defined(MATH) - XMC_PAU_PERIPHERAL_MATH_CORDIC = PAU_PRIVDIS0_PDIS21_Msk, /**< MATH CORDIC Privilege Disable Flag */ - #endif - #if defined(PORT0) - XMC_PAU_PERIPHERAL_PORT0 = PAU_PRIVDIS0_PDIS22_Msk, /**< Port 0 Privilege Disable Flag */ - #endif - #if defined(PORT1) - XMC_PAU_PERIPHERAL_PORT1 = PAU_PRIVDIS0_PDIS23_Msk, /**< Port 1 Privilege Disable Flag */ - #endif - #if defined(PORT2) - XMC_PAU_PERIPHERAL_PORT2 = PAU_PRIVDIS0_PDIS24_Msk, /**< Port 2 Privilege Disable Flag */ +#if defined(WDT) + XMC_PAU_PERIPHERAL_WDT = PAU_PRIVDIS0_PDIS19_Msk, /**< WDT Privilege Disable Flag */ +#endif +#if defined(MATH) + XMC_PAU_PERIPHERAL_MATH_GLOBAL_AND_DIV = PAU_PRIVDIS0_PDIS20_Msk, /**< MATH Global SFRs and Divider Privilege Disable Flag */ +#endif +#if defined(MATH) + XMC_PAU_PERIPHERAL_MATH_CORDIC = PAU_PRIVDIS0_PDIS21_Msk, /**< MATH CORDIC Privilege Disable Flag */ +#endif +#if defined(PORT0) + XMC_PAU_PERIPHERAL_PORT0 = PAU_PRIVDIS0_PDIS22_Msk, /**< Port 0 Privilege Disable Flag */ +#endif +#if defined(PORT1) + XMC_PAU_PERIPHERAL_PORT1 = PAU_PRIVDIS0_PDIS23_Msk, /**< Port 1 Privilege Disable Flag */ +#endif +#if defined(PORT2) + XMC_PAU_PERIPHERAL_PORT2 = PAU_PRIVDIS0_PDIS24_Msk, /**< Port 2 Privilege Disable Flag */ #endif #if defined(PORT3) - XMC_PAU_PERIPHERAL_PORT3 = PAU_PRIVDIS0_PDIS25_Msk, /**< Port 3 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_PORT3 = PAU_PRIVDIS0_PDIS25_Msk, /**< Port 3 Privilege Disable Flag */ #endif #if defined(PORT4) - XMC_PAU_PERIPHERAL_PORT4 = PAU_PRIVDIS0_PDIS26_Msk, /**< Port 4 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_PORT4 = PAU_PRIVDIS0_PDIS26_Msk, /**< Port 4 Privilege Disable Flag */ #endif #if defined(USIC0) - XMC_PAU_PERIPHERAL_USIC0_CH0 = PAU_PRIVDIS1_PDIS0_Msk | 0x10000000U, /**< USIC0 Channel 0 Privilege Disable Flag */ - XMC_PAU_PERIPHERAL_USIC0_CH1 = PAU_PRIVDIS1_PDIS1_Msk | 0x10000000U, /**< USIC0 Channel 1 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_USIC0_CH0 = PAU_PRIVDIS1_PDIS0_Msk | 0x10000000U, /**< USIC0 Channel 0 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_USIC0_CH1 = PAU_PRIVDIS1_PDIS1_Msk | 0x10000000U, /**< USIC0 Channel 1 Privilege Disable Flag */ #endif #if defined(USIC1) - XMC_PAU_PERIPHERAL_USIC1_CH0 = PAU_PRIVDIS1_PDIS16_Msk | 0x10000000U, /**< USIC1 Channel 0 Privilege Disable Flag */ - XMC_PAU_PERIPHERAL_USIC1_CH1 = PAU_PRIVDIS1_PDIS17_Msk | 0x10000000U, /**< USIC1 Channel 1 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_USIC1_CH0 = PAU_PRIVDIS1_PDIS16_Msk | 0x10000000U, /**< USIC1 Channel 0 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_USIC1_CH1 = PAU_PRIVDIS1_PDIS17_Msk | 0x10000000U, /**< USIC1 Channel 1 Privilege Disable Flag */ #endif #if defined(PRNG) - XMC_PAU_PERIPHERAL_PRNG = PAU_AVAIL1_AVAIL4_Msk | 0x10000000U, /**< PRNG Availability Flag*/ + XMC_PAU_PERIPHERAL_PRNG = PAU_AVAIL1_AVAIL4_Msk | 0x10000000U, /**< PRNG Availability Flag*/ #endif #if defined(VADC) - XMC_PAU_PERIPHERAL_VADC_GLOBAL = PAU_PRIVDIS1_PDIS5_Msk | 0x10000000U, /**< VADC0 Basic SFRs Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_VADC_GLOBAL = PAU_PRIVDIS1_PDIS5_Msk | 0x10000000U, /**< VADC0 Basic SFRs Privilege Disable Flag */ #if defined(VADC_G0) - XMC_PAU_PERIPHERAL_VADC_GROUP0 = PAU_PRIVDIS1_PDIS6_Msk | 0x10000000U, /**< VADC0 Group 0 SFRs Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_VADC_GROUP0 = PAU_PRIVDIS1_PDIS6_Msk | 0x10000000U, /**< VADC0 Group 0 SFRs Privilege Disable Flag */ #endif #if defined(VADC_G1) - XMC_PAU_PERIPHERAL_VADC_GROUP1 = PAU_PRIVDIS1_PDIS7_Msk | 0x10000000U, /**< VADC0 Group 1 SFRs Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_VADC_GROUP1 = PAU_PRIVDIS1_PDIS7_Msk | 0x10000000U, /**< VADC0 Group 1 SFRs Privilege Disable Flag */ #endif #endif #if defined(SHS0) - XMC_PAU_PERIPHERAL_VADC_SHS0 = PAU_PRIVDIS1_PDIS8_Msk | 0x10000000U, /**< SHS0 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_VADC_SHS0 = PAU_PRIVDIS1_PDIS8_Msk | 0x10000000U, /**< SHS0 Privilege Disable Flag */ #endif #if defined(CCU40) - XMC_PAU_PERIPHERAL_CCU40_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS9_Msk | 0x10000000U, /**< CCU40_CC40 and CCU40 Kernel SFRs Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU40_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS9_Msk | 0x10000000U, /**< CCU40_CC40 and CCU40 Kernel SFRs Privilege Disable Flag */ #if defined(CCU40_CC41) - XMC_PAU_PERIPHERAL_CCU40_CC41 = PAU_PRIVDIS1_PDIS10_Msk | 0x10000000U, /**< CCU40_CC41 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU40_CC41 = PAU_PRIVDIS1_PDIS10_Msk | 0x10000000U, /**< CCU40_CC41 Privilege Disable Flag */ #endif #if defined(CCU40_CC42) - XMC_PAU_PERIPHERAL_CCU40_CC42 = PAU_PRIVDIS1_PDIS11_Msk | 0x10000000U, /**< CCU40_CC42 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU40_CC42 = PAU_PRIVDIS1_PDIS11_Msk | 0x10000000U, /**< CCU40_CC42 Privilege Disable Flag */ #endif #if defined(CCU40_CC43) - XMC_PAU_PERIPHERAL_CCU40_CC43 = PAU_PRIVDIS1_PDIS12_Msk | 0x10000000U, /**< CCU40_CC43 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU40_CC43 = PAU_PRIVDIS1_PDIS12_Msk | 0x10000000U, /**< CCU40_CC43 Privilege Disable Flag */ #endif #endif #if defined(CCU41) - XMC_PAU_PERIPHERAL_CCU41_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS25_Msk | 0x10000000U, /**< CCU41_CC40 and CCU41 Kernel SFRs Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU41_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS25_Msk | 0x10000000U, /**< CCU41_CC40 and CCU41 Kernel SFRs Privilege Disable Flag */ #if defined(CCU41_CC41) - XMC_PAU_PERIPHERAL_CCU41_CC41 = PAU_PRIVDIS1_PDIS26_Msk | 0x10000000U, /**< CCU41_CC41 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU41_CC41 = PAU_PRIVDIS1_PDIS26_Msk | 0x10000000U, /**< CCU41_CC41 Privilege Disable Flag */ #endif #if defined(CCU41_CC42) - XMC_PAU_PERIPHERAL_CCU41_CC42 = PAU_PRIVDIS1_PDIS27_Msk | 0x10000000U, /**< CCU41_CC42 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU41_CC42 = PAU_PRIVDIS1_PDIS27_Msk | 0x10000000U, /**< CCU41_CC42 Privilege Disable Flag */ #endif #if defined(CCU41_CC43) - XMC_PAU_PERIPHERAL_CCU41_CC43 = PAU_PRIVDIS1_PDIS28_Msk | 0x10000000U, /**< CCU41_CC43 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU41_CC43 = PAU_PRIVDIS1_PDIS28_Msk | 0x10000000U, /**< CCU41_CC43 Privilege Disable Flag */ #endif #endif -#if defined(CCU80) - XMC_PAU_PERIPHERAL_CCU80_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS0_Msk | 0x20000000U, /**< CCU80_CC80 and CCU80 Kernel SFRs Privilege Disable Flag */ +#if defined(CCU80) + XMC_PAU_PERIPHERAL_CCU80_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS0_Msk | 0x20000000U, /**< CCU80_CC80 and CCU80 Kernel SFRs Privilege Disable Flag */ #if defined(CCU80_CC81) - XMC_PAU_PERIPHERAL_CCU80_CC81 = PAU_PRIVDIS2_PDIS1_Msk | 0x20000000U, /**< CCU80_CC81 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU80_CC81 = PAU_PRIVDIS2_PDIS1_Msk | 0x20000000U, /**< CCU80_CC81 Privilege Disable Flag */ #endif #if defined(CCU80_CC82) - XMC_PAU_PERIPHERAL_CCU80_CC82 = PAU_PRIVDIS2_PDIS2_Msk | 0x20000000U, /**< CCU80_CC82 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU80_CC82 = PAU_PRIVDIS2_PDIS2_Msk | 0x20000000U, /**< CCU80_CC82 Privilege Disable Flag */ #endif #if defined(CCU80_CC83) - XMC_PAU_PERIPHERAL_CCU80_CC83 = PAU_PRIVDIS2_PDIS3_Msk | 0x20000000U, /**< CCU80_CC83 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU80_CC83 = PAU_PRIVDIS2_PDIS3_Msk | 0x20000000U, /**< CCU80_CC83 Privilege Disable Flag */ #endif #endif -#if defined(CCU81) - XMC_PAU_PERIPHERAL_CCU81_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS16_Msk | 0x20000000U, /**< CCU81_CC80 and CCU81 Kernel SFRs Privilege Disable Flag */ +#if defined(CCU81) + XMC_PAU_PERIPHERAL_CCU81_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS16_Msk | 0x20000000U, /**< CCU81_CC80 and CCU81 Kernel SFRs Privilege Disable Flag */ #if defined(CCU81_CC81) - XMC_PAU_PERIPHERAL_CCU81_CC81 = PAU_PRIVDIS2_PDIS17_Msk | 0x20000000U, /**< CCU81_CC81 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU81_CC81 = PAU_PRIVDIS2_PDIS17_Msk | 0x20000000U, /**< CCU81_CC81 Privilege Disable Flag */ #endif #if defined(CCU81_CC82) - XMC_PAU_PERIPHERAL_CCU81_CC82 = PAU_PRIVDIS2_PDIS18_Msk | 0x20000000U, /**< CCU81_CC82 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU81_CC82 = PAU_PRIVDIS2_PDIS18_Msk | 0x20000000U, /**< CCU81_CC82 Privilege Disable Flag */ #endif #if defined(CCU81_CC83) - XMC_PAU_PERIPHERAL_CCU81_CC83 = PAU_PRIVDIS2_PDIS19_Msk | 0x20000000U, /**< CCU81_CC83 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_CCU81_CC83 = PAU_PRIVDIS2_PDIS19_Msk | 0x20000000U, /**< CCU81_CC83 Privilege Disable Flag */ #endif #endif #if defined(POSIF0) - XMC_PAU_PERIPHERAL_POSIF0 = PAU_PRIVDIS2_PDIS12_Msk | 0x20000000U, /**< POSIF0 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_POSIF0 = PAU_PRIVDIS2_PDIS12_Msk | 0x20000000U, /**< POSIF0 Privilege Disable Flag */ #endif #if defined(POSIF1) - XMC_PAU_PERIPHERAL_POSIF1 = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< POSIF1 Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_POSIF1 = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< POSIF1 Privilege Disable Flag */ +#endif +#if defined(LEDTS0) + XMC_PAU_PERIPHERAL_LEDTS0 = PAU_PRIVDIS2_PDIS13_Msk | 0x20000000U, /**< LEDTS0 Privilege Disable Flag */ #endif -#if defined(LEDTS0) - XMC_PAU_PERIPHERAL_LEDTS0 = PAU_PRIVDIS2_PDIS13_Msk | 0x20000000U, /**< LEDTS0 Privilege Disable Flag */ +#if defined(LEDTS1) + XMC_PAU_PERIPHERAL_LEDTS1 = PAU_PRIVDIS2_PDIS14_Msk | 0x20000000U, /**< LEDTS1 Privilege Disable Flag */ #endif -#if defined(LEDTS1) - XMC_PAU_PERIPHERAL_LEDTS1 = PAU_PRIVDIS2_PDIS14_Msk | 0x20000000U, /**< LEDTS1 Privilege Disable Flag */ +#if defined(LEDTS2) + XMC_PAU_PERIPHERAL_LEDTS2 = PAU_PRIVDIS2_PDIS29_Msk | 0x20000000U, /**< LEDTS2 Privilege Disable Flag */ #endif -#if defined(LEDTS2) - XMC_PAU_PERIPHERAL_LEDTS2 = PAU_PRIVDIS2_PDIS29_Msk | 0x20000000U, /**< LEDTS2 Privilege Disable Flag */ +#if defined(BCCU0) + XMC_PAU_PERIPHERAL_BCCU0 = PAU_PRIVDIS2_PDIS15_Msk | 0x20000000U, /**< BCCU0 Privilege Disable Flag */ #endif -#if defined(BCCU0) - XMC_PAU_PERIPHERAL_BCCU0 = PAU_PRIVDIS2_PDIS15_Msk | 0x20000000U, /**< BCCU0 Privilege Disable Flag */ +#if defined(CAN_xmc) +#if defined(CAN_NODE0) + XMC_PAU_PERIPHERAL_MCAN_NODE0_AND_GLOBAL = PAU_PRIVDIS2_PDIS21_Msk | 0x20000000U, /**< MCAN NODE0 and Global SFRs Privilege */ #endif -#if defined(CAN) -#if defined(CAN_NODE0) - XMC_PAU_PERIPHERAL_MCAN_NODE0_AND_GLOBAL = PAU_PRIVDIS2_PDIS21_Msk | 0x20000000U, /**< MCAN NODE0 and Global SFRs Privilege */ -#endif -#if defined(CAN_NODE1) - XMC_PAU_PERIPHERAL_MCAN_NODE1_AND_GLOBAL = PAU_PRIVDIS2_PDIS23_Msk | 0x20000000U, /**< MCAN NODE1 Privilege Disable Flag */ +#if defined(CAN_NODE1) + XMC_PAU_PERIPHERAL_MCAN_NODE1_AND_GLOBAL = PAU_PRIVDIS2_PDIS23_Msk | 0x20000000U, /**< MCAN NODE1 Privilege Disable Flag */ #endif - XMC_PAU_PERIPHERAL_MCAN_OBJECTS = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< MCAN Message Objects Privilege Disable Flag */ + XMC_PAU_PERIPHERAL_MCAN_OBJECTS = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< MCAN Message Objects Privilege Disable Flag */ #endif } XMC_PAU_PERIPHERAL_t; @@ -244,8 +232,8 @@ typedef enum XMC_PAU_PERIPHERAL /********************************************************************************************************************* * DATA STRUCTURES *********************************************************************************************************************/ - - + + /** * External Peripheral Access Unit (PAU) device structure
      * @@ -253,7 +241,7 @@ typedef enum XMC_PAU_PERIPHERAL * used to configure the PAU peripheral on the XMC microcontroller. * The registers can be accessed with ::XMC_PAU. */ -typedef struct +typedef struct { __I uint32_t RESERVED0[16]; __I uint32_t AVAIL[3]; @@ -261,7 +249,7 @@ typedef struct __IO uint32_t PRIVDIS[3]; __I uint32_t RESERVED2[221]; __I uint32_t ROMSIZE; - __I uint32_t FLSIZE; + __I uint32_t FLSIZE; __I uint32_t RESERVED3[2]; __I uint32_t RAM0SIZE; } XMC_PAU_t; @@ -282,11 +270,11 @@ extern "C" { * Enable the peripheral access
      * * \par - * The function resets the PRIVDISx.PDISy bit to enable the access to the registers of a peripheral + * The function resets the PRIVDISx.PDISy bit to enable the access to the registers of a peripheral * during run time. * * \parRelated APIs:
      - * XMC_PAU_DisablePeripheralAccess() + * XMC_PAU_DisablePeripheralAccess() */ void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral); @@ -298,12 +286,12 @@ void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral); * Disable the peripheral access
      * * \par - * The function sets the PRIVDISx.PDISy bit to disable the access to the registers of a peripheral - * during run time. An access to a disabled or unassigned address location generates a hardfault + * The function sets the PRIVDISx.PDISy bit to disable the access to the registers of a peripheral + * during run time. An access to a disabled or unassigned address location generates a hardfault * exception. * * \parRelated APIs:
      - * XMC_PAU_EnablePeripheralAccess() + * XMC_PAU_EnablePeripheralAccess() */ void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral); @@ -315,11 +303,11 @@ void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral); * Checks if the peripheral access is enabled or not
      * * \par - * The function checks the PRIVDISx.PDISy bit to know whether the access to the registers of a peripheral + * The function checks the PRIVDISx.PDISy bit to know whether the access to the registers of a peripheral * during run time is enabled or not. * * \parRelated APIs:
      - * XMC_PAU_DisablePeripheralAccess(), XMC_PAU_EnablePeripheralAccess() + * XMC_PAU_DisablePeripheralAccess(), XMC_PAU_EnablePeripheralAccess() */ bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral); @@ -331,7 +319,7 @@ bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral); * Checks if a peripheral is available or not
      * * \par - * The function checks the AVAILx.AVAILy bit to know whether the peripheral + * The function checks the AVAILx.AVAILy bit to know whether the peripheral * is available or not for the particular device variant. */ bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral); @@ -382,10 +370,6 @@ __STATIC_INLINE uint32_t XMC_PAU_GetRAMSize(void) } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_posif.h b/cores/xmc_lib/XMCLib/inc/xmc_posif.h index b3a04c3f..f663b730 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_posif.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_posif.h @@ -1,60 +1,43 @@ /** * @file xmc_posif.h - * @date 2017-06-24 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-18: - * - Initial version - * - * 2015-02-20: - * - Driver description added
      - * - * 2015-06-19: - * - Removed version macros and declaration of GetDriverVersion API
      - * - * 2015-07-02: - * - Updated XMC_POSIF_QD_GetDirection API - * - * 2016-03-09: - * - Optimization of write only registers - * - * 2017-06-24 - * - Added posif map connectivity file
      - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -65,16 +48,12 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_common.h" #if defined(POSIF0) -#include +#include "xmc_scu.h" #include "xmc_posif_map.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup POSIF @@ -106,9 +85,10 @@ * -# User need to call respective init functions to configure POSIF operating mode. e.g to configure POSIF in hall sensor control with multichannel mode * call both XMC_POSIF_HSC_Init() and XMC_POSIF_MCM_Init(). * -# Allows to enable and disable interrupt sources and assign to service request node using XMC_POSIF_EnableEvent(), XMC_POSIF_DisableEvent() and XMC_POSIF_SetInterruptNode() - * + * * @note POSIF is not available on XMC11 and XMC12 devices * + * Also, the POSIF block can be configured from the ModusToolbox™ Device Configurator: \ref section_personality_posif * @{ */ @@ -140,27 +120,27 @@ typedef enum XMC_POSIF_STATUS typedef enum XMC_POSIF_MODE { XMC_POSIF_MODE_HALL_SENSOR = 0U, /**< Hall sensor mode */ - XMC_POSIF_MODE_QD , /**< Quadrature Decoder mode */ - XMC_POSIF_MODE_MCM , /**< Standalone Multichannel mode */ + XMC_POSIF_MODE_QD, /**< Quadrature Decoder mode */ + XMC_POSIF_MODE_MCM, /**< Standalone Multichannel mode */ XMC_POSIF_MODE_MCM_QD /**< Quadrature Decoder + Standalone Multichannel mode */ } XMC_POSIF_MODE_t; /** * Defines POSIF configurable input ports.Use type @ref XMC_POSIF_INPUT_PORT_t for this enum. * The member defines the respective input selector(INSELX) bitfields of \a PCONF register. - * It selects, which input is used for the phase or Hall input function (depending on the module is set for + * It selects, which input is used for the phase or Hall input function (depending on the module is set for * Quadrature Decoder or Hall Sensor Mode). Same enum can be used to configure pattern update signal select by configuring * \a PCONF register's \a MSETS bit field. */ typedef enum XMC_POSIF_INPUT_PORT { XMC_POSIF_INPUT_PORT_A = 0U, /**< INPUT-A */ - XMC_POSIF_INPUT_PORT_B , /**< INPUT-B */ - XMC_POSIF_INPUT_PORT_C , /**< INPUT-C */ - XMC_POSIF_INPUT_PORT_D , /**< INPUT-D */ - XMC_POSIF_INPUT_PORT_E , /**< INPUT-E */ - XMC_POSIF_INPUT_PORT_F , /**< INPUT-F */ - XMC_POSIF_INPUT_PORT_G , /**< INPUT-G */ + XMC_POSIF_INPUT_PORT_B, /**< INPUT-B */ + XMC_POSIF_INPUT_PORT_C, /**< INPUT-C */ + XMC_POSIF_INPUT_PORT_D, /**< INPUT-D */ + XMC_POSIF_INPUT_PORT_E, /**< INPUT-E */ + XMC_POSIF_INPUT_PORT_F, /**< INPUT-F */ + XMC_POSIF_INPUT_PORT_G, /**< INPUT-G */ XMC_POSIF_INPUT_PORT_H /**< INPUT-H */ } XMC_POSIF_INPUT_PORT_t; @@ -182,12 +162,12 @@ typedef enum XMC_POSIF_INPUT_ACTIVE_LEVEL typedef enum XMC_POSIF_FILTER { XMC_POSIF_FILTER_DISABLED = 0U, /**< No filtering */ - XMC_POSIF_FILTER_1_CLOCK_CYCLE , /**< Filter of 1 Clock Cycle */ - XMC_POSIF_FILTER_2_CLOCK_CYCLE , /**< Filter of 2 Clock Cycles */ - XMC_POSIF_FILTER_4_CLOCK_CYCLE , /**< Filter of 4 Clock Cycles */ - XMC_POSIF_FILTER_8_CLOCK_CYCLE , /**< Filter of 8 Clock Cycles */ - XMC_POSIF_FILTER_16_CLOCK_CYCLE , /**< Filter of 16 Clock Cycles */ - XMC_POSIF_FILTER_32_CLOCK_CYCLE , /**< Filter of 32 Clock Cycles */ + XMC_POSIF_FILTER_1_CLOCK_CYCLE, /**< Filter of 1 Clock Cycle */ + XMC_POSIF_FILTER_2_CLOCK_CYCLE, /**< Filter of 2 Clock Cycles */ + XMC_POSIF_FILTER_4_CLOCK_CYCLE, /**< Filter of 4 Clock Cycles */ + XMC_POSIF_FILTER_8_CLOCK_CYCLE, /**< Filter of 8 Clock Cycles */ + XMC_POSIF_FILTER_16_CLOCK_CYCLE, /**< Filter of 16 Clock Cycles */ + XMC_POSIF_FILTER_32_CLOCK_CYCLE, /**< Filter of 32 Clock Cycles */ XMC_POSIF_FILTER_64_CLOCK_CYCLE /**< Filter of 64 Clock Cycles */ } XMC_POSIF_FILTER_t; @@ -248,7 +228,7 @@ typedef enum XMC_POSIF_QD_DIR typedef enum XMC_POSIF_QD_INDEX_GENERATION { XMC_POSIF_QD_INDEX_GENERATION_NEVER = 0U, /**< Never generate the index marker signal */ - XMC_POSIF_QD_INDEX_GENERATION_ONCE , /**< Generate only once after the first revolution */ + XMC_POSIF_QD_INDEX_GENERATION_ONCE, /**< Generate only once after the first revolution */ XMC_POSIF_QD_INDEX_GENERATION_ALWAYS /**< Index marker generated upon every revolution */ } XMC_POSIF_QD_INDEX_GENERATION_t; @@ -268,10 +248,10 @@ typedef enum XMC_POSIF_HSC_TRIGGER_EDGE /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -319,7 +299,7 @@ typedef struct XMC_POSIF_HSC_CONFIG uint32_t : 11; uint32_t sampling_trigger: 1; /**< Of HSDA and HSDB, which one is to be used to trigger POSIF to sample hall pattern? */ uint32_t sampling_trigger_edge: 1; /**< Which edge of the sampling trigger signal is to be considered? */ - uint32_t : 6; + uint32_t : 6; uint32_t external_error_port: 2; /**< Of the 4 external error ports, which one is to be considered? */ uint32_t external_error_enable: 1; /**< Should external errors lead to Wrong Hall event? */ uint32_t external_error_level: 1; /**< What should be the active level of external error signal? */ @@ -343,14 +323,14 @@ typedef struct XMC_POSIF_MCM_CONFIG uint32_t : 5; uint32_t pattern_sw_update: 1; /**< should multi channel pattern updated by SW ? */ uint32_t : 12; - uint32_t pattern_update_trigger: 3; /**< Of the 8 update triggers, which one is to be considered? */ + uint32_t pattern_update_trigger: 3; /**< Of the 8 update triggers, which one is to be considered? */ uint32_t pattern_trigger_edge: 1; /**< Which edge of the pattern update trigger is to be considered? */ uint32_t pwm_sync: 2; /**< Of the 4 pwm sync inputs, which one is to be considered? */ uint32_t : 8; }; uint32_t mcm_config; }; -}XMC_POSIF_MCM_CONFIG_t; +} XMC_POSIF_MCM_CONFIG_t; /** * Defines POSIF module initialization data structure. @@ -364,11 +344,11 @@ typedef struct XMC_POSIF_CONFIG struct { uint32_t mode: 2; /**< POSIF Operational mode. Use @ref XMC_POSIF_MODE_t to configure */ - uint32_t :6; + uint32_t : 6; uint32_t input0: 2; /**< Choice of input for Input-1 */ uint32_t input1: 2; /**< Choice of input for Input-2 */ uint32_t input2: 2; /**< Choice of input for Input-3 */ - uint32_t :14; + uint32_t : 14; uint32_t filter: 3; /**< Input filter configuration */ uint32_t: 1; }; @@ -378,9 +358,9 @@ typedef struct XMC_POSIF_CONFIG /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* @@ -436,7 +416,7 @@ void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral); * \parRelated APIs:
      * XMC_POSIF_HSC_Init(),XMC_POSIF_QD_Init(),XMC_POSIF_MCM_Init() \n\n\n */ -void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t * const config); +void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t *const config); /** * @param peripheral Pointer to an instance of POSIF module @@ -455,7 +435,7 @@ void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t * co * \parRelated APIs:
      * XMC_POSIF_Init() \n\n\n */ -XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config); +XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t *const config); /** * @param peripheral Pointer to an instance of POSIF module @@ -473,7 +453,7 @@ XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_P * \parRelated APIs:
      * XMC_POSIF_Init() \n\n\n */ -XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config); +XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t *const config); /** * @param peripheral Pointer to an instance of POSIF module @@ -492,7 +472,7 @@ XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_PO * \parRelated APIs:
      * XMC_POSIF_Init(),XMC_POSIF_HSC_Init(),XMC_POSIF_QD_Init() \n\n\n */ -XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config); +XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t *const config); /** * @param peripheral Pointer to an instance of POSIF module @@ -513,7 +493,7 @@ XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_P __STATIC_INLINE void XMC_POSIF_SetMode(XMC_POSIF_t *const peripheral, const XMC_POSIF_MODE_t mode) { peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)(POSIF_PCONF_FSEL_Msk)) | - (((uint32_t)mode << POSIF_PCONF_FSEL_Pos) & (uint32_t)POSIF_PCONF_FSEL_Msk)); + (((uint32_t)mode << POSIF_PCONF_FSEL_Pos) & (uint32_t)POSIF_PCONF_FSEL_Msk)); } /** @@ -536,7 +516,7 @@ __STATIC_INLINE void XMC_POSIF_SetMode(XMC_POSIF_t *const peripheral, const XMC_ * XMC_POSIF_Init() \n\n\n */ void XMC_POSIF_SelectInputSource(XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0, - const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2); + const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2); /** @@ -673,7 +653,7 @@ __STATIC_INLINE uint8_t XMC_POSIF_HSC_GetExpectedPattern(XMC_POSIF_t *const peri __STATIC_INLINE void XMC_POSIF_HSC_SetCurrentPattern(XMC_POSIF_t *const peripheral, const uint8_t pattern) { peripheral->HALPS = ((peripheral->HALPS & ~(uint32_t)(POSIF_HALPS_HCPS_Msk)) | - (((uint32_t)pattern << POSIF_HALPS_HCPS_Pos) & (uint32_t)POSIF_HALPS_HCPS_Msk)); + (((uint32_t)pattern << POSIF_HALPS_HCPS_Pos) & (uint32_t)POSIF_HALPS_HCPS_Msk)); } /** @@ -697,7 +677,7 @@ __STATIC_INLINE void XMC_POSIF_HSC_SetCurrentPattern(XMC_POSIF_t *const peripher __STATIC_INLINE void XMC_POSIF_HSC_SetExpectedPattern(XMC_POSIF_t *const peripheral, const uint8_t pattern) { peripheral->HALPS = ((peripheral->HALPS & ~(uint32_t)(POSIF_HALPS_HEPS_Msk)) | - (((uint32_t)pattern << POSIF_HALPS_HEPS_Pos) & (uint32_t)POSIF_HALPS_HEPS_Msk)); + (((uint32_t)pattern << POSIF_HALPS_HEPS_Pos) & (uint32_t)POSIF_HALPS_HEPS_Msk)); } /** @@ -1027,10 +1007,6 @@ void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_I } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_posif_map.h b/cores/xmc_lib/XMCLib/inc/xmc_posif_map.h index 748fdbbc..46ead92f 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_posif_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_posif_map.h @@ -1,43 +1,41 @@ /** * @file xmc_posif_map.h - * @date 2016-08-22 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial version + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -318,6 +316,20 @@ #define POSIF1_IN2_VADC_G1BFL2 2 #endif +#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN40) +#define POSIF0_IN0_ERU0_PDOUT0 3 +#define POSIF0_IN0_P0_13 1 +#define POSIF0_IN0_P1_2 0 +#define POSIF0_IN0_VADC_G1BFL0 2 +#define POSIF0_IN1_ERU0_PDOUT1 3 +#define POSIF0_IN1_P0_14 1 +#define POSIF0_IN1_P1_1 0 +#define POSIF0_IN1_VADC_G1BFL1 2 +#define POSIF0_IN2_ERU0_PDOUT2 3 +#define POSIF0_IN2_P0_15 1 +#define POSIF0_IN2_P1_0 0 +#define POSIF0_IN2_VADC_G1BFL2 2 +#endif #if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48) #define POSIF0_IN0_ERU0_PDOUT0 3 @@ -846,6 +858,7 @@ #define POSIF0_IN2_P14_5 1 #define POSIF0_IN2_P1_1 0 #define POSIF0_IN2_VADC_C0SR0 2 +#define POSIF0_HSD_CCU40_ST0 0 #define POSIF1_IN0_ERU1_PDOUT0 3 #define POSIF1_IN0_P2_5 0 #define POSIF1_IN0_P3_10 1 @@ -858,6 +871,7 @@ #define POSIF1_IN2_P2_3 0 #define POSIF1_IN2_P3_8 1 #define POSIF1_IN2_VADC_C0SR1 2 +#define POSIF0_HSD_CCU41_ST0 0 #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_prng.h b/cores/xmc_lib/XMCLib/inc/xmc_prng.h index 35d97f25..6cdd326a 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_prng.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_prng.h @@ -1,52 +1,46 @@ /** * @file xmc_prng.h - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
      - * - Documentation updates
      + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
      + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ - + #ifndef XMC_PRNG_H #define XMC_PRNG_H @@ -56,12 +50,7 @@ #include "xmc_common.h" -#if defined (PRNG) - -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ +#if defined (PRNG) /** * @addtogroup PRNG @@ -70,19 +59,19 @@ * The pseudo random bit generator (PRNG) provides random data with fast generation times. * PRNG has to be initialized by the user software before use. The initialization consists * of two basic phases: key-loading and warm-up. - * + * * The PRNG low level driver provides functions to configure and initialize the PRNG hardware * peripheral. * @{ - */ + */ /********************************************************************************************************************* * MACROS *********************************************************************************************************************/ - + /** * Byte mask value for random data block size - */ + */ #define XMC_PRNG_RDBS_BYTE_READ_MASK (0x00FFU) /********************************************************************************************************************* @@ -92,7 +81,8 @@ /** * PRNG key load operation modes */ -typedef enum XMC_PRNG_KEY_LOAD_OP_MODE { +typedef enum XMC_PRNG_KEY_LOAD_OP_MODE +{ XMC_PRNG_STRM_MODE = 0U, /**< Streaming mode (default) */ XMC_PRNG_KLD_MODE = 1U /**< Loading mode */ } XMC_PRNG_KEY_LOAD_OP_MODE_t; @@ -100,7 +90,8 @@ typedef enum XMC_PRNG_KEY_LOAD_OP_MODE { /** * PRNG data block size */ -typedef enum XMC_PRNG_DATA_BLOCK_SIZE { +typedef enum XMC_PRNG_DATA_BLOCK_SIZE +{ XMC_PRNG_RDBS_RESET = 0U, /**< Reset state (no random data block size defined) */ XMC_PRNG_RDBS_BYTE = 1U, /**< BYTE (8-bit) */ XMC_PRNG_RDBS_WORD = 2U /**< WORD (16-bit) */ @@ -109,7 +100,8 @@ typedef enum XMC_PRNG_DATA_BLOCK_SIZE { /** * PRNG driver initialization status */ -typedef enum XMC_PRNG_INIT_STATUS { +typedef enum XMC_PRNG_INIT_STATUS +{ XMC_PRNG_NOT_INITIALIZED = 0U, /**< Reset state or Non-initialized state (Same as XMC_PRNG_RDBS_RESET) */ XMC_PRNG_INITIALIZED = 1U /**< Initialized state */ } XMC_PRNG_INIT_STATUS_t; @@ -125,7 +117,7 @@ typedef enum XMC_PRNG_INIT_STATUS { * values of PRNG. * The XMC_PRNG_Init() can be used to populate the structure with the key word and data block * configuration values of the PRNG module. - */ + */ typedef struct XMC_PRNG_INIT { uint16_t key_words[5]; /**< Keywords */ @@ -152,7 +144,7 @@ extern "C" { * \par * The function configures block size for key loading mode, enables key loading mode, * loads key words (80 bits) and wait till RDV is set, enables the streaming mode and - * waits for warmup phase. This function programmes the CTRL and WORD registers. + * waits for warmup phase. This function programmes the CTRL and WORD registers. */ XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng); @@ -218,7 +210,7 @@ __STATIC_INLINE void XMC_PRNG_EnableKeyLoadingMode(void) * * \par * The function enables the streaming mode and disables the PRNG key loading mode by resetting the - * CTRL.KLD bit. + * CTRL.KLD bit. * * \parRelated APIs:
      * XMC_PRNG_EnableKeyLoadingMode() @@ -239,7 +231,7 @@ __STATIC_INLINE void XMC_PRNG_EnableStreamingMode(void) * The function loads partial key word to WORD registr. These partial * words are sequentially written and loading a key word will take 16 clock * cycles. The CHK.RDV bit is set to '0' while loading is in progress. '1' indicates - * that the next partial key word can be written to WORD register. + * that the next partial key word can be written to WORD register. */ __STATIC_INLINE void XMC_PRNG_LoadKeyWords(uint16_t key) { @@ -272,10 +264,6 @@ __STATIC_INLINE uint16_t XMC_PRNG_GetPseudoRandomNumber(void) } #endif -/** - * @} - */ - /** * @} */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_rtc.h b/cores/xmc_lib/XMCLib/inc/xmc_rtc.h index 87fba75c..69172595 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_rtc.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_rtc.h @@ -1,56 +1,43 @@ /** * @file xmc_rtc.h - * @date 2016-05-19 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial - * - * 2015-05-20: - * - Documentation updates
      - * - In xmc1_rtc file XMC_RTC_Init function - * is modified by adding the RTC running condition check - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * - * 2016-05-19: - * - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat() - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -61,14 +48,10 @@ * HEADER FILES *********************************************************************************************************************/ -#include #include -/** - * - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ +#include "xmc_common.h" + /** * @addtogroup RTC @@ -81,8 +64,9 @@ * hibernate. * * The RTC low level driver provides functions to configure and initialize the RTC - * hardware peripheral. - * + * hardware peripheral. + * + * Also, the RTC block can be configured from the ModusToolbox™ Device Configurator: \ref section_personality_rtc * @{ */ @@ -110,45 +94,45 @@ typedef enum XMC_RTC_STATUS typedef enum XMC_RTC_EVENT { XMC_RTC_EVENT_PERIODIC_SECONDS = RTC_MSKSR_MPSE_Msk, /**< Mask value to enable an event on periodic seconds */ - XMC_RTC_EVENT_PERIODIC_MINUTES = RTC_MSKSR_MPMI_Msk, /**< Mask value to enable an event on periodic seconds */ - XMC_RTC_EVENT_PERIODIC_HOURS = RTC_MSKSR_MPHO_Msk, /**< Mask value to enable an event on periodic seconds */ - XMC_RTC_EVENT_PERIODIC_DAYS = RTC_MSKSR_MPDA_Msk, /**< Mask value to enable an event on periodic seconds */ - XMC_RTC_EVENT_PERIODIC_MONTHS = RTC_MSKSR_MPMO_Msk, /**< Mask value to enable an event on periodic seconds */ - XMC_RTC_EVENT_PERIODIC_YEARS = RTC_MSKSR_MPYE_Msk, /**< Mask value to enable an event on periodic seconds */ - XMC_RTC_EVENT_ALARM = RTC_MSKSR_MAI_Msk /**< Mask value to enable an event on periodic seconds */ + XMC_RTC_EVENT_PERIODIC_MINUTES = RTC_MSKSR_MPMI_Msk, /**< Mask value to enable an event on periodic minutes */ + XMC_RTC_EVENT_PERIODIC_HOURS = RTC_MSKSR_MPHO_Msk, /**< Mask value to enable an event on periodic hours */ + XMC_RTC_EVENT_PERIODIC_DAYS = RTC_MSKSR_MPDA_Msk, /**< Mask value to enable an event on periodic days */ + XMC_RTC_EVENT_PERIODIC_MONTHS = RTC_MSKSR_MPMO_Msk, /**< Mask value to enable an event on periodic months */ + XMC_RTC_EVENT_PERIODIC_YEARS = RTC_MSKSR_MPYE_Msk, /**< Mask value to enable an event on periodic years */ + XMC_RTC_EVENT_ALARM = RTC_MSKSR_MAI_Msk /**< Mask value to enable an alarm event */ } XMC_RTC_EVENT_t; /** - * Months used to program the date + * Months used to program the date */ typedef enum XMC_RTC_MONTH { - XMC_RTC_MONTH_JANUARY = 0U, - XMC_RTC_MONTH_FEBRUARY = 1U, - XMC_RTC_MONTH_MARCH = 2U, - XMC_RTC_MONTH_APRIL = 3U, - XMC_RTC_MONTH_MAY = 4U, - XMC_RTC_MONTH_JUNE = 5U, - XMC_RTC_MONTH_JULY = 6U, - XMC_RTC_MONTH_AUGUST = 7U, - XMC_RTC_MONTH_SEPTEMBER = 8U, - XMC_RTC_MONTH_OCTOBER = 9U, - XMC_RTC_MONTH_NOVEMBER = 10U, - XMC_RTC_MONTH_DECEMBER = 11U + XMC_RTC_MONTH_JANUARY = 0U, + XMC_RTC_MONTH_FEBRUARY = 1U, + XMC_RTC_MONTH_MARCH = 2U, + XMC_RTC_MONTH_APRIL = 3U, + XMC_RTC_MONTH_MAY = 4U, + XMC_RTC_MONTH_JUNE = 5U, + XMC_RTC_MONTH_JULY = 6U, + XMC_RTC_MONTH_AUGUST = 7U, + XMC_RTC_MONTH_SEPTEMBER = 8U, + XMC_RTC_MONTH_OCTOBER = 9U, + XMC_RTC_MONTH_NOVEMBER = 10U, + XMC_RTC_MONTH_DECEMBER = 11U } XMC_RTC_MONTH_t; /** - * Week days used program the date + * Week days used program the date */ typedef enum XMC_RTC_WEEKDAY { - XMC_RTC_WEEKDAY_SUNDAY = 0U, - XMC_RTC_WEEKDAY_MONDAY = 1U, - XMC_RTC_WEEKDAY_TUESDAY = 2U, - XMC_RTC_WEEKDAY_WEDNESDAY = 3U, - XMC_RTC_WEEKDAY_THURSDAY = 4U, - XMC_RTC_WEEKDAY_FRIDAY = 5U, - XMC_RTC_WEEKDAY_SATURDAY = 6U + XMC_RTC_WEEKDAY_SUNDAY = 0U, + XMC_RTC_WEEKDAY_MONDAY = 1U, + XMC_RTC_WEEKDAY_TUESDAY = 2U, + XMC_RTC_WEEKDAY_WEDNESDAY = 3U, + XMC_RTC_WEEKDAY_THURSDAY = 4U, + XMC_RTC_WEEKDAY_FRIDAY = 5U, + XMC_RTC_WEEKDAY_SATURDAY = 6U } XMC_RTC_WEEKDAY_t; /********************************************************************************************************************* @@ -156,107 +140,107 @@ typedef enum XMC_RTC_WEEKDAY *********************************************************************************************************************/ /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** * Alarm time values of RTC
      * - * The structure presents a convenient way to set/obtain the - * alarm time values for seconds, minutes, hours, days, month and year of RTC. + * The structure presents a convenient way to set/obtain the + * alarm time values for seconds, minutes, hours, days, month and year of RTC. * The XMC_RTC_SetAlarm() and XMC_RTC_GetAlarm() can be * used to populate the structure with the alarm time value of - * RTC - */ + * RTC + */ typedef struct XMC_RTC_ALARM { union { - uint32_t raw0; - struct - { - uint32_t seconds : 6; /**< Alarm seconds compare value (0-59: Above this causes this bitfield to be set with 0)*/ - uint32_t : 2; - uint32_t minutes : 6; /**< Alarm minutes compare value (0-59: Above this causes this bitfield to be set with 0)*/ - uint32_t : 2; - uint32_t hours : 5; /**< Alarm hours compare value (0-23: Above this causes this bitfield to be set with 0)*/ - uint32_t : 3; - uint32_t days : 5; /**< Alarm days compare value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ - uint32_t : 3; - }; + uint32_t raw0; + struct + { + uint32_t seconds : 6; /**< Alarm seconds compare value (0-59: Above this causes this bitfield to be set with 0)*/ + uint32_t : 2; + uint32_t minutes : 6; /**< Alarm minutes compare value (0-59: Above this causes this bitfield to be set with 0)*/ + uint32_t : 2; + uint32_t hours : 5; /**< Alarm hours compare value (0-23: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + uint32_t days : 5; /**< Alarm days compare value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + }; }; union { uint32_t raw1; - struct - { - uint32_t : 8; - uint32_t month : 4; /**< Alarm month compare value (0-11: Above this causes this bitfield to be set with 0) */ - uint32_t : 4; - uint32_t year : 16; /**< Alarm year compare value */ - }; + struct + { + uint32_t : 8; + uint32_t month : 4; /**< Alarm month compare value (0-11: Above this causes this bitfield to be set with 0) */ + uint32_t : 4; + uint32_t year : 16; /**< Alarm year compare value */ + }; }; } XMC_RTC_ALARM_t; /** * Time values of RTC
      * - * The structure presents a convenient way to set/obtain the - * time values for seconds, minutes, hours, days, month and year of RTC. + * The structure presents a convenient way to set/obtain the + * time values for seconds, minutes, hours, days, month and year of RTC. * The XMC_RTC_SetTime() and XMC_RTC_GetTime() can be * used to populate the structure with the time value of - * RTC - */ + * RTC + */ typedef struct XMC_RTC_TIME { union { uint32_t raw0; - struct - { - uint32_t seconds : 6; /**< Seconds time value (0-59: Above this causes this bitfield to be set with 0) */ - uint32_t : 2; - uint32_t minutes : 6; /**< Minutes time value (0-59: Above this causes this bitfield to be set with 0) */ - uint32_t : 2; - uint32_t hours : 5; /**< Hours time value (0-23: Above this causes this bitfield to be set with 0) */ - uint32_t : 3; - uint32_t days : 5; /**< Days time value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ - uint32_t : 3; - }; + struct + { + uint32_t seconds : 6; /**< Seconds time value (0-59: Above this causes this bitfield to be set with 0) */ + uint32_t : 2; + uint32_t minutes : 6; /**< Minutes time value (0-59: Above this causes this bitfield to be set with 0) */ + uint32_t : 2; + uint32_t hours : 5; /**< Hours time value (0-23: Above this causes this bitfield to be set with 0) */ + uint32_t : 3; + uint32_t days : 5; /**< Days time value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/ + uint32_t : 3; + }; }; union { uint32_t raw1; - struct - { - uint32_t daysofweek : 3; /**< Days of week time value (0-6: Above this causes this bitfield to be set with 0) */ - uint32_t : 5; - uint32_t month : 4; /**< Month time value (0-11: Above this causes this bitfield to be set with 0) */ - uint32_t : 4; - uint32_t year : 16; /**< Year time value */ - }; + struct + { + uint32_t daysofweek : 3; /**< Days of week time value (0-6: Above this causes this bitfield to be set with 0) */ + uint32_t : 5; + uint32_t month : 4; /**< Month time value (0-11: Above this causes this bitfield to be set with 0) */ + uint32_t : 4; + uint32_t year : 16; /**< Year time value */ + }; }; } XMC_RTC_TIME_t; /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** * RTC initialization with time, alarm and clock divider(prescaler) configurations
      * - * The structure presents a convenient way to set/obtain the time and alarm configurations + * The structure presents a convenient way to set/obtain the time and alarm configurations * for RTC. The XMC_RTC_Init() can be used to populate the structure with the time and alarm * values of RTC. - */ + */ typedef struct XMC_RTC_CONFIG { XMC_RTC_TIME_t time; @@ -286,27 +270,27 @@ extern "C" { /** * @param config Constant pointer to a constant ::XMC_RTC_CONFIG_t structure containing the - * time, alarm time and clock divider(prescaler) configuration. + * time, alarm time and clock divider(prescaler) configuration. * @return XMC_RTC_STATUS_t Always returns XMC_RTC_STATUS_OK (It contains only register assignment statements) * * \parDescription:
      * Initialize the RTC peripheral
      * * \par \if XMC4 - * The function enables the hibernate domain for accessing RTC peripheral registers, configures + * The function enables the hibernate domain for accessing RTC peripheral registers, configures * internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and * ATIM1 registers. * \endif * * \if XMC1 - * The function ungates the peripheral clock for RTC, configures + * The function ungates the peripheral clock for RTC, configures * internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and * ATIM1 registers. * \endif */ XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config); -/** +/** * @return None * * \parDescription
      @@ -322,10 +306,10 @@ XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config); * * \parRelated APIs:
      * XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset() - */ + */ void XMC_RTC_Enable(void); -/** +/** * @return None * * \parDescription
      @@ -341,10 +325,10 @@ void XMC_RTC_Enable(void); * * \parRelated APIs:
      * XMC_RTC_Enable(), XMC_SCU_RESET_AssertPeripheralReset() - */ + */ void XMC_RTC_Disable(void); -/** +/** * @return None * * \parDescription
      @@ -361,9 +345,9 @@ void XMC_RTC_Disable(void); * \parRelated APIs:
      * XMC_RTC_Enable(), XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset(), * XMC_SCU_RESET_AssertPeripheralReset() - */ + */ bool XMC_RTC_IsEnabled(void); - + /** * @return None * @@ -371,13 +355,13 @@ bool XMC_RTC_IsEnabled(void); * Enables RTC peripheral to start counting time
      * * \par - * The function starts the RTC for counting time by setting + * The function starts the RTC for counting time by setting * CTR.ENB bit. Before starting the RTC, it should not be in * running mode and also hibernate domain should be enabled. * * \parRelated APIs:
      * XMC_RTC_Enable(), XMC_RTC_Stop(), XMC_SCU_RESET_DeassertPeripheralReset() - */ + */ void XMC_RTC_Start(void); /** @@ -387,30 +371,30 @@ void XMC_RTC_Start(void); * Disables RTC peripheral to start counting time
      * * \par - * The function stops the RTC for counting time by resetting + * The function stops the RTC for counting time by resetting * CTR.ENB. Before stopping the RTC, hibernate domain should be enabled. * * \parRelated APIs:
      * XMC_RTC_Enable(), XMC_RTC_Start(), XMC_SCU_RESET_AssertPeripheralReset() - */ + */ void XMC_RTC_Stop(void); - + /** - * @param prescaler Prescaler value to be set + * @param prescaler Prescaler value to be set * @return None * * \parDescription:
      * Sets the RTC module prescaler value
      * * \par - * The function sets the CTR.DIV bitfield to configure the prescalar value. - * The default value for the prescalar with the 32.768kHz crystal (or the internal clock) + * The function sets the CTR.DIV bitfield to configure the prescalar value. + * The default value for the prescalar with the 32.768kHz crystal (or the internal clock) * is 7FFFH for a time interval of 1 sec. Before setting the prescaler value RTC should be * in stop mode and hibernate domain should be enabled. * * \parRelated APIs:
      * XMC_RTC_Stop(), XMC_RTC_Enable(), XMC_RTC_GetPrescaler() - */ + */ void XMC_RTC_SetPrescaler(uint16_t prescaler); /** @@ -420,13 +404,13 @@ void XMC_RTC_SetPrescaler(uint16_t prescaler); * Gets the RTC module prescaler value
      * * \par - * The function reads the CTR.DIV bitfield to get the prescalar value. The default value - * for the prescalar with the 32.768kHz crystal (or the internal clock) is 7FFFH for a + * The function reads the CTR.DIV bitfield to get the prescalar value. The default value + * for the prescalar with the 32.768kHz crystal (or the internal clock) is 7FFFH for a * time interval of 1 sec. * * \parRelated APIs:
      * XMC_RTC_SetPrescaler() - */ + */ __STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void) { return (uint32_t)(((uint32_t)RTC->CTR & (uint32_t)RTC_CTR_DIV_Msk) >> (uint32_t)RTC_CTR_DIV_Pos); @@ -434,7 +418,7 @@ __STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void) /** * @param timeval Contstant pointer to a constant ::XMC_RTC_TIME_t structure containing the - * time parameters seconds, minutes, hours, days, daysofweek, month and year. + * time parameters seconds, minutes, hours, days, daysofweek, month and year. * @return None * * \parDescription:
      @@ -446,135 +430,135 @@ __STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void) * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
      * * \parRelated APIs:
      - * XMC_RTC_GetTime(), XMC_RTC_Stop() - */ + * XMC_RTC_GetTime(), XMC_RTC_Stop() + */ void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const timeval); /** * @param time Pointer to a constant ::XMC_RTC_TIME_t structure containing the time parameters - * seconds, minutes, hours, days, daysofweek, month and year. + * seconds, minutes, hours, days, daysofweek, month and year. * @return None * * \parDescription:
      * Gets the RTC module time value
      * * \par - * The function gets the time values from TIM0, TIM1 registers. + * The function gets the time values from TIM0, TIM1 registers. * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
      * * \parRelated APIs:
      * XMC_RTC_SetTime() - */ + */ void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time); /** * @param stdtime Pointer to a ::tm structure containing the time parameters seconds, - * minutes, hours, days, daysofweek, month, year(since 1900) and days in a - * year in standard format. + * minutes, hours, days, daysofweek, month, year(since 1900) and days in a + * year in standard format. * @return None * * \parDescription:
      * Sets the RTC module time value in standard format
      * * \par - * The function sets the time values from TIM0, TIM1 registers. + * The function sets the time values from TIM0, TIM1 registers. * * \parRelated APIs:
      * XMC_RTC_SetTime(), XMC_RTC_GetTime() - */ + */ void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime); /** * @param stdtime Pointer to a constant ::tm structure containing the time parameters seconds, - * minutes, hours, days, daysofweek, month, year(since 1900) and days in a - * year in standard format. + * minutes, hours, days, daysofweek, month, year(since 1900) and days in a + * year in standard format. * @return None * * \parDescription:
      * Gets the RTC module time value in standard format
      * * \par - * The function gets the time values from TIM0, TIM1 registers. + * The function gets the time values from TIM0, TIM1 registers. * See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters.
      - * For days the valid range is (1 - Actual days of month), year (since 1900) and + * For days the valid range is (1 - Actual days of month), year (since 1900) and * daysinyear (0 -365). * * \parRelated APIs:
      * XMC_RTC_SetTime(), XMC_RTC_GetTime() - */ + */ void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime); /** * @param alarm Constant pointer to a constant ::XMC_RTC_ALARM_t structure containing the - * alarm time parameters alarm seconds, alarm minutes, alarm hours, alarm days, - * alarm daysofweek, alarm month and alarm year. + * alarm time parameters alarm seconds, alarm minutes, alarm hours, alarm days, + * alarm daysofweek, alarm month and alarm year. * @return None * * \parDescription:
      * Sets the RTC module alarm time value
      * * \par - * The function sets the ATIM0, ATIM1 registers with alarm time values. + * The function sets the ATIM0, ATIM1 registers with alarm time values. * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
      * * \parRelated APIs:
      * XMC_RTC_GetAlarm() - */ + */ void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm); /** * @param alarm Pointer to a constant ::XMC_RTC_ALARM_t structure containing the - * time parameters alarm seconds, alarm minutes, alarm hours, alarm days, - * alarm daysofweek, alarm month and alarm year. + * time parameters alarm seconds, alarm minutes, alarm hours, alarm days, + * alarm daysofweek, alarm month and alarm year. * @return None * * \parDescription:
      * Gets the RTC module alarm time value
      * * \par - * The function gets the alarm time values from ATIM0, ATIM1 registers. + * The function gets the alarm time values from ATIM0, ATIM1 registers. * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
      * * \parRelated APIs:
      * XMC_RTC_SetAlarm() - */ + */ void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm); /** * @param stdtime Pointer to a ::tm structure containing the time parameters alarm seconds, - * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, - * alarm year(since 1900) and alarm days in a year in standard format. + * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, + * alarm year(since 1900) and alarm days in a year in standard format. * @return None * * \parDescription:
      * Sets the RTC module alarm time value in standard format
      * * \par - * The function sets the alarm time values from ATIM0, ATIM1 registers. + * The function sets the alarm time values from ATIM0, ATIM1 registers. * * \parRelated APIs:
      * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm() - */ + */ void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime); /** * @param stdtime Pointer to a constant ::tm structure containing the time parameters alarm seconds, - * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, - * alarm year(since 1900) and alarm days in a year in standard format. + * alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month, + * alarm year(since 1900) and alarm days in a year in standard format. * @return None * * \parDescription:
      * Gets the RTC module alarm time value in standard format
      * * \par - * The function gets the alarm time values from ATIM0, ATIM1 registers. + * The function gets the alarm time values from ATIM0, ATIM1 registers. * See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters.
      - * For days the valid range is (1 - Actual days of month), year (since 1900) and + * For days the valid range is (1 - Actual days of month), year (since 1900) and * daysinyear (0 -365). * * \parRelated APIs:
      * XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm() - */ + */ void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime); /** @@ -586,9 +570,9 @@ void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime); * Enable RTC periodic and alarm event(s)
      * * \par - * The function sets the bitfields of MSKSR register to enable interrupt generation - * for requested RTC event(s). - * Setting the masking value for the event(s) containing in the ::XMC_RTC_EVENT_t leads + * The function sets the bitfields of MSKSR register to enable interrupt generation + * for requested RTC event(s). + * Setting the masking value for the event(s) containing in the ::XMC_RTC_EVENT_t leads * to a generation of the interrupt. * * \parRelated APIs:
      @@ -605,11 +589,11 @@ void XMC_RTC_EnableEvent(const uint32_t event); * Disable RTC periodic and alarm event(s)
      * * \par - * The function resets the bitfields of MSKSR register to disable interrupt generation - * for requested RTC event(s). - * Resetting the masking value for the the event(s) containing in the ::XMC_RTC_EVENT_t blocks + * The function resets the bitfields of MSKSR register to disable interrupt generation + * for requested RTC event(s). + * Resetting the masking value for the the event(s) containing in the ::XMC_RTC_EVENT_t blocks * the generation of the interrupt. - * + * * \parRelated APIs:
      * XMC_RTC_EnableEvent() */ @@ -624,13 +608,13 @@ void XMC_RTC_DisableEvent(const uint32_t event); * Clears periodic and alarm event(s) status
      * * \par - * The function sets the bitfields of CLRSR register to clear status bits in RAWSTAT and STSSR registers. - * Setting the value for the the RTC event(s) containing in the ::XMC_RTC_EVENT_t clears the + * The function sets the bitfields of CLRSR register to clear status bits in RAWSTAT and STSSR registers. + * Setting the value for the the RTC event(s) containing in the ::XMC_RTC_EVENT_t clears the * corresponding status bits in RAWSTAT and STSSR registers. - * + * * \parRelated APIs:
      * XMC_RTC_GetEventStatus() - */ + */ void XMC_RTC_ClearEvent(const uint32_t event); /** @@ -640,10 +624,10 @@ void XMC_RTC_ClearEvent(const uint32_t event); * Gets the RTC periodic and alarm event(s) status
      * * \par - * The function reads the bitfields of STSSR register - * to get the status of RTC events. - * Reading the value of the register STSSR gives the status of the event(s) containing in the ::XMC_RTC_EVENT_t. - * + * The function reads the bitfields of STSSR register + * to get the status of RTC events. + * Reading the value of the register STSSR gives the status of the event(s) containing in the ::XMC_RTC_EVENT_t. + * * \parRelated APIs:
      * XMC_RTC_ClearEvent() */ @@ -657,12 +641,12 @@ uint32_t XMC_RTC_GetEventStatus(void); * Checks the running status of the RTC
      * * \par - * The function reads the bitfield ENB of CTR register - * to get the running status of RTC. + * The function reads the bitfield ENB of CTR register + * to get the running status of RTC. * * \parRelated APIs:
      * XMC_RTC_Start(), XMC_RTC_Stop() - */ + */ __STATIC_INLINE bool XMC_RTC_IsRunning(void) { return (bool)(RTC->CTR & RTC_CTR_ENB_Msk); @@ -676,8 +660,5 @@ __STATIC_INLINE bool XMC_RTC_IsRunning(void) * @} */ -/** - * @} - */ #endif /* XMC_RTC_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_scu.h b/cores/xmc_lib/XMCLib/inc/xmc_scu.h index f1ce86a6..62139583 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_scu.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_scu.h @@ -1,77 +1,54 @@ /** * @file xmc_scu.h - * @date 2016-03-09 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
      - * - * 2015-05-20: - * - Documentation improved
      - * - XMC_ASSERT() hanging issues have fixed for XMC4 devices.
      - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * - Removed STATIC_INLINE property for the below APIs and declared as void - * XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent, - * XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus, - * XMC_SCU_INTERUPT_ClearEventStatus - * - * 2015-11-30: - * - Documentation improved
      - * - * 2016-03-09: - * - Optimization of write only registers - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ #ifndef XMC_SCU_H #define XMC_SCU_H - + /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_common.h" + -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - /** * @addtogroup SCU * @brief System Control Unit(SCU) driver for XMC microcontroller family. @@ -80,8 +57,8 @@ * providing system stability protection and other auxiliary functions.
      * SCU provides the following features, * -# Power control - \if XMC4 - * -# Hibernate control + \if XMC4 + * -# Hibernate control \endif * -# Reset control * -# Clock control @@ -89,7 +66,7 @@ * * The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic \if XMC4 - * , hibernate control logic, trap control logic, parity control logic + * , hibernate control logic, trap control logic, parity control logic \endif * and miscellaneous control logic.
      * @@ -101,7 +78,7 @@ * -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider() * -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource() * -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator() - * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), + * -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()
      \endif \if XMC1 @@ -120,7 +97,7 @@ \endif
      * * Interrupt driver features: - * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), + * -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), XMC_SCU_INTERRUPT_DisableEvent() * -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()
      * @@ -156,7 +133,7 @@ \endif * @{ */ - + /********************************************************************************************************************* * MACROS ********************************************************************************************************************/ @@ -167,7 +144,7 @@ /** * Defines the status of SCU API execution, used to verify the SCU related API calls. */ -typedef enum XMC_SCU_STATUS +typedef enum XMC_SCU_STATUS { XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/ XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */ @@ -191,9 +168,9 @@ typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void); ********************************************************************************************************************/ #if (UC_FAMILY == XMC1) -#include +#include "xmc1_scu.h" #elif (UC_FAMILY == XMC4) -#include +#include "xmc4_scu.h" #else #error "Unspecified chipset" #endif @@ -211,7 +188,7 @@ extern "C" { * * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits * in the register CCUCON.
      - * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be + * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be * combined using \a OR operation. * * @return None @@ -221,8 +198,8 @@ extern "C" { * Before executing this API, all the required CCU timers should configure external start. * The edge of the start signal should be selected as active edge. * The input signal for the CCU slice should be selected as SCU input. - * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). - * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering + * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). + * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering * the timer using this API.
      * \parRelated APIs:
      * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n @@ -236,7 +213,7 @@ __STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger) * * @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits * in the register CCUCON.
      - * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be + * \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be * combined using \a OR operation. * * @return None @@ -246,8 +223,8 @@ __STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger) * Before executing this API, all the required CCU timers should configure external start. * The edge of the start signal should be selected as passive edge. * The input signal for the CCU slice should be selected as SCU input. - * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). - * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering + * The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). + * CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering * the timer using this API.
      * \parRelated APIs:
      * XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n @@ -259,7 +236,7 @@ __STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger) /** * - * @param config Pointer to structure holding the clock prescaler values and divider values for + * @param config Pointer to structure holding the clock prescaler values and divider values for * configuring clock generators and clock tree.\n * \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various * parameters of clock setup. @@ -272,8 +249,8 @@ __STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger) * Peripheral clock and system clock are configured based on the input configuration \a config. * The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register. * The values of FDIV and IDIV can be provided as part of input configuration. - * The PCLK divider determines the ratio of peripheral clock to the system clock. - * The source of RTC clock is set based on the input configuration. + * The PCLK divider determines the ratio of peripheral clock to the system clock. + * The source of RTC clock is set based on the input configuration. * \a SystemCoreClock variable will be updated with the value of * system clock frequency. Access to protected bit fields are handled internally. * \endif @@ -343,10 +320,10 @@ void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event); * * \parDescription
      * Provides the status of all SCU events.\n\n - * The status is read from the SRRAW register. To check the status of a particular + * The status is read from the SRRAW register. To check the status of a particular * event, the returned value should be masked with the bit mask of the event. The bitmask * of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events' - * status can be checked by combining the bit masks using \a OR operation. + * status can be checked by combining the bit masks using \a OR operation. * After detecting the event, the event status should be cleared using software to detect the event again. * \parRelated APIs:
      * XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n @@ -379,8 +356,8 @@ void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event); * Provides the value representing the reason for device reset.\n\n * The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the * returned word is representative of a last reset cause. The returned value should be appropriately masked to check - * the cause of reset. - * The cause of the last reset gets automatically stored in + * the cause of reset. + * The cause of the last reset gets automatically stored in * the \a SCU_RSTSTAT register. The reset status shall be reset after each * startup in order to ensure consistent source indication after the next reset. * \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause. @@ -393,7 +370,7 @@ __STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void) return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk); } /** - * @return None + * @return None * * \parDescription
      * Clears the reset reason bits in the reset status register. \n\n @@ -408,7 +385,7 @@ __STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void) /* Clear RSTSTAT.RSTSTAT bitfield */ SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk; } - + /** * @return uint32_t Value of CPU clock frequency. * @@ -436,10 +413,10 @@ __STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void) * \parRelated APIs:
      * XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n */ -uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); +uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); #if(UC_SERIES != XMC45) - + /** * * @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t @@ -462,7 +439,7 @@ uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); * the clock supply for the selected peripheral. * Software can request for individual gating of such peripheral clocks by enabling one of the \a * SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields. - * + * * \endif * Note: Clock gating shall not be activated unless the module is in reset state. So use \a * XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral. @@ -470,7 +447,7 @@ uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void); * XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n */ void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral); - + /** * * @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t @@ -480,7 +457,7 @@ void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripher * * \parDescription
      * Enables the supply of clock to the selected peripheral.\n\n - * By default when the device powers on, the peripheral clock will be gated for the + * By default when the device powers on, the peripheral clock will be gated for the * peripherals that support clock gating. * The peripheral clock should be enabled before using it for any functionality. * \if XMC1 @@ -501,7 +478,7 @@ void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t periph /** * - * @param peripheral The peripheral for which the check for clock gating has to be done. + * @param peripheral The peripheral for which the check for clock gating has to be done. * \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral. * * @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated. @@ -527,14 +504,14 @@ bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t perip /** * @return uint32_t Status of the register mirror update.\n - * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of - * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined + * \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of + * interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined * using \a OR operation. * * \parDescription
      * Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\n - * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register - * representing the communication of changed value of a mirror register to its corresponding register in the + * The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register + * representing the communication of changed value of a mirror register to its corresponding register in the * hibernate domain. The bit fields of the register indicate * that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface * is busy with executing the previous operation.\n @@ -542,7 +519,7 @@ bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t perip */ __STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void) { - return(SCU_GENERAL->MIRRSTS); + return (SCU_GENERAL->MIRRSTS); } /** @@ -559,7 +536,7 @@ __STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void) * when the interrupt is generated and the event status is set in the event status register. By using this API, * polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events * can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed. - * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the + * It checks for status flags of events which can generate the interrupt. The handler function will be executed if the * event flag is set. * * \parRelated APIs:
      @@ -590,9 +567,6 @@ void XMC_SCU_IRQHandler(uint32_t sr_num); /** * @} */ - -/** - * @} - */ - + + #endif /* SCU_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_sdmmc.h b/cores/xmc_lib/XMCLib/inc/xmc_sdmmc.h index 3de17f2c..0ee03d7c 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_sdmmc.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_sdmmc.h @@ -1,70 +1,43 @@ + /** * @file xmc_sdmmc.h - * @date 2017-02-14 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial version - * - Documentation updates - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
      - * - * 2016-01-16: - * - Added the following APIs to the XMC_SDMMC low level driver
      - * 1) XMC_SDMMC_EnableDelayCmdDatLines
      - * 2) XMC_SDMMC_DisableDelayCmdDatLines
      - * 3) XMC_SDMMC_SetDelay
      - * 4) XMC_SDMMC_EnableHighSpeed
      - * 5) XMC_SDMMC_DisableHighSpeed
      - * - * 2016-04-07: - * - Added XMC_SDMMC_COMMAND_RESPONSE_t
      - * - * 2016-07-11: - * - Adjust masks for the following functions:
      - * 1) XMC_SDMMC_SetBusVoltage
      - * 2) XMC_SDMMC_SetDataLineTimeout
      - * 3) XMC_SDMMC_SDClockFreqSelect
      - * - * 2017-02-14: - * - Added:
      - * 1) XMC_SDMMC_SetCardDetectionStatus()
      - * 2) XMC_SDMMC_SetCardDetectionSource()
      - + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * * @endcond */ @@ -74,15 +47,22 @@ /******************************************************************************* * HEADER FILES *******************************************************************************/ - + #include "xmc_common.h" #if defined (SDMMC) -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ +#if (UC_SERIES != XMC45) +#define SDMMC_CON_WPSEL_Pos 0 +#define SDMMC_CON_WPSEL_Msk 0x00000001UL +#define SDMMC_CON_WPSVAL_Pos 4 +#define SDMMC_CON_WPSVAL_Msk 0x00000010UL +#define SDMMC_CON_CDSEL_Pos 16 +#define SDMMC_CON_CDSEL_Msk 0x00010000UL +#define SDMMC_CON_CDSVAL_Pos 20 +#define SDMMC_CON_CDSVAL_Msk 0x00100000UL +#endif + /** * @addtogroup SDMMC @@ -214,7 +194,7 @@ /** * Number of data lines for SDMMC data transfer */ -typedef enum +typedef enum XMC_SDMMC_DATA_LINES { XMC_SDMMC_DATA_LINES_1 = 0x00U, /**< Single data line mode */ XMC_SDMMC_DATA_LINES_4 = 0x02U, /**< 4-bit mode */ @@ -224,7 +204,7 @@ typedef enum /** * Valid SD clock frequency divider selection */ -typedef enum +typedef enum XMC_SDMMC_SDCLK_FREQ_SEL { XMC_SDMMC_CLK_DIV_1 = 0x00U, /**< Base clock (10 Mhz -> 63 Mhz) */ XMC_SDMMC_CLK_DIV_2 = 0x01U, /**< Base clock divided by 2 */ @@ -240,7 +220,7 @@ typedef enum /** * Status return values for the SDMMC low level driver */ -typedef enum +typedef enum XMC_SDMMC_STATUS { XMC_SDMMC_STATUS_SUCCESS = 0U, /**< Operation successful */ XMC_SDMMC_STATUS_CMD_LINE_BUSY, /**< Command line busy */ @@ -250,7 +230,7 @@ typedef enum /** * SDMMC events (Normal and error events) */ -typedef enum +typedef enum XMC_SDMMC_EVENT { XMC_SDMMC_CMD_COMPLETE = 0x01U, /**< Command complete event */ XMC_SDMMC_TX_COMPLETE = 0x02U, /**< Transmit complete event */ @@ -276,7 +256,7 @@ typedef enum /** * SDMMC wakeup events */ -typedef enum +typedef enum XMC_SDMMC_WAKEUP_EVENT { XMC_SDMMC_WAKEUP_EN_CARD_INT = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk, /**< Wakeup on card interrupt */ XMC_SDMMC_WAKEUP_EN_CARD_INS = SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk, /**< Wakeup on SD card insertion */ @@ -286,7 +266,7 @@ typedef enum /** * SDMMC software reset modes */ -typedef enum +typedef enum XMC_SDMMC_SW_RESET { XMC_SDMMC_SW_RESET_ALL = SDMMC_SW_RESET_SW_RST_ALL_Msk, /**< Software reset all */ XMC_SDMMC_SW_RST_CMD_LINE = SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk, /**< Software reset command line */ @@ -296,7 +276,7 @@ typedef enum /** * CMD12 response errors of Auto CMD12 */ -typedef enum +typedef enum XMC_SDMMC_ACMD_ERR { XMC_SDMMC_ACMD12_NOT_EXEC_ERR = SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk, /**< ACMD12 not executed error */ XMC_SDMMC_ACMD_TIMEOUT_ERR = SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk, /**< ACMD timeout error */ @@ -309,7 +289,7 @@ typedef enum /** * SDMMC response types */ -typedef enum +typedef enum XMC_SDMMC_RESPONSE_TYPE { XMC_SDMMC_RESPONSE_TYPE_NO_RESPONSE = 0U, /**< No response */ XMC_SDMMC_RESPONSE_TYPE_R1, /**< Response type: R1 */ @@ -334,7 +314,7 @@ typedef enum XMC_SDMMC_COMMAND_RESPONSE /** * Types of SDMMC commands */ -typedef enum +typedef enum XMC_SDMMC_COMMAND_TYPE { XMC_SDMMC_COMMAND_TYPE_NORMAL = 0U, /**< Command normal */ XMC_SDMMC_COMMAND_TYPE_SUSPEND, /**< Command suspend */ @@ -345,7 +325,7 @@ typedef enum /** * SDMMC transfer modes */ -typedef enum +typedef enum XMC_SDMMC_TRANSFER_MODE_TYPE { XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE = 0x00U, /**< Transfer mode type: single */ XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE = 0x20U, /**< Transfer mode type: infinite */ @@ -356,7 +336,7 @@ typedef enum /** * Auto command transfer modes */ -typedef enum +typedef enum XMC_SDMMC_TRANSFER_MODE_AUTO_CMD { XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_DISABLED = 0x00U, /**< ACMD mode disabled */ XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_12 /**< ACMD12 mode */ @@ -365,40 +345,40 @@ typedef enum /** * SDMMC bus voltage level */ -typedef enum +typedef enum XMC_SDMMC_BUS_VOLTAGE { - XMC_SDMMC_BUS_VOLTAGE_3_3_VOLTS = 0x07U + XMC_SDMMC_BUS_VOLTAGE_3_3_VOLTS = 0x07U /**< 3.3V */ } XMC_SDMMC_BUS_VOLTAGE_t; /** * Data line timeout counter values */ -typedef enum -{ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_13 = 0U, /** SDCLK * (2 ^ 13) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14 = 1U, /** SDCLK * (2 ^ 14) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15 = 2U, /** SDCLK * (2 ^ 15) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16 = 3U, /** SDCLK * (2 ^ 16) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17 = 4U, /** SDCLK * (2 ^ 17) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18 = 5U, /** SDCLK * (2 ^ 18) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19 = 6U, /** SDCLK * (2 ^ 19) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20 = 7U, /** SDCLK * (2 ^ 20) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21 = 8U, /** SDCLK * (2 ^ 21) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22 = 9U, /** SDCLK * (2 ^ 22) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23 = 10U, /** SDCLK * (2 ^ 23) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24 = 11U, /** SDCLK * (2 ^ 24) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25 = 12U, /** SDCLK * (2 ^ 25) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26 = 13U, /** SDCLK * (2 ^ 26) */ - XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27 = 14U, /** SDCLK * (2 ^ 27) */ +typedef enum XMC_SDMMC_DAT_TIMEOUT_COUNTER +{ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_13 = 0U, /**< SDCLK * (2 ^ 13) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14 = 1U, /**< SDCLK * (2 ^ 14) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15 = 2U, /**< SDCLK * (2 ^ 15) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16 = 3U, /**< SDCLK * (2 ^ 16) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17 = 4U, /**< SDCLK * (2 ^ 17) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18 = 5U, /**< SDCLK * (2 ^ 18) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19 = 6U, /**< SDCLK * (2 ^ 19) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20 = 7U, /**< SDCLK * (2 ^ 20) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21 = 8U, /**< SDCLK * (2 ^ 21) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22 = 9U, /**< SDCLK * (2 ^ 22) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23 = 10U, /**< SDCLK * (2 ^ 23) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24 = 11U, /**< SDCLK * (2 ^ 24) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25 = 12U, /**< SDCLK * (2 ^ 25) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26 = 13U, /**< SDCLK * (2 ^ 26) */ + XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27 = 14U, /**< SDCLK * (2 ^ 27) */ } XMC_SDMMC_DAT_TIMEOUT_COUNTER_t; /** * SDMMC data transfer direction */ -typedef enum +typedef enum XMC_SDMMC_DATA_TRANSFER_DIR { - XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD = 0U, /** Host to card */ - XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST /** Card to host */ + XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD = 0U, /**< Host to card */ + XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST /**< Card to host */ } XMC_SDMMC_DATA_TRANSFER_DIR_t; /** @@ -406,19 +386,51 @@ typedef enum */ typedef enum XMC_SDMMC_CD_SOURCE { - XMC_SDMMC_CD_SOURCE_PIN = 0, - XMC_SDMMC_CD_SOURCE_SW = 1 << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos +#if UC_SERIES == XMC45 || defined(DOXYGEN) + XMC_SDMMC_CD_SOURCE_PIN = 0 << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos, /**< P1.10 input pin selected */ + XMC_SDMMC_CD_SOURCE_SW = 1 << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos /**< Software is selected */ +#else + XMC_SDMMC_CD_SOURCE_PIN = 0 << SDMMC_CON_CDSEL_Pos, /**< P1.10 input pin selected */ + XMC_SDMMC_CD_SOURCE_SW = 1 << SDMMC_CON_CDSEL_Pos /**< Software is selected */ +#endif } XMC_SDMMC_CD_SOURCE_t; /** - * SDMMC card detection status + * Used to set the SDMMC card detection status when the card detection status source input is set to software */ typedef enum XMC_SDMMC_CD_STATUS { - XMC_SDMMC_CD_STATUS_NO_CARD = 0, - XMC_SDMMC_CD_STATUS_INSERTED = 1 << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos +#if UC_SERIES == XMC45 || defined(DOXYGEN) + XMC_SDMMC_CD_STATUS_NO_CARD = 0 << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos, /**< No card detected */ + XMC_SDMMC_CD_STATUS_INSERTED = 1 << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos /**< Card detected */ +#else + XMC_SDMMC_CD_STATUS_NO_CARD = 0 << SDMMC_CON_CDSVAL_Pos, /**< No card detected */ + XMC_SDMMC_CD_STATUS_INSERTED = 1 << SDMMC_CON_CDSVAL_Pos /**< Card detected */ +#endif } XMC_SDMMC_CD_STATUS_t; +#if UC_SERIES != XMC45 || defined(DOXYGEN) +/** + * SDMMC card write protection signal source + * @note Only available for XMC4300, XMC4800 and XMC4700 series + */ +typedef enum XMC_SDMMC_WP_SOURCE +{ + XMC_SDMMC_WP_SOURCE_PIN = 0 << SDMMC_CON_WPSEL_Pos, /**< P1.1 input pin selected */ + XMC_SDMMC_WP_SOURCE_SW = 1 << SDMMC_CON_WPSEL_Pos /**< Software is selected */ +} XMC_SDMMC_WP_SOURCE_t; + +/** + * Used to set the SDMMC card protection status when the card protection status source input is set to software + * @note Only available for XMC4300, XMC4800 and XMC4700 series + */ +typedef enum XMC_SDMMC_WP_STATUS +{ + XMC_SDMMC_WP_STATUS_NO_WRITE_PROTECTION = 0 << SDMMC_CON_WPSVAL_Pos, /**< No write protection */ + XMC_SDMMC_WP_STATUS_WRITE_PROTECTION = 1 << SDMMC_CON_WPSVAL_Pos /**< Write protection active */ +} XMC_SDMMC_WP_STATUS_t; +#endif + /******************************************************************************* * DATA STRUCTURES *******************************************************************************/ @@ -468,10 +480,10 @@ typedef struct /* Anonymous structure/union guard start */ #if defined (__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined (__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -482,27 +494,27 @@ typedef struct * XMC_SDMMC_GetPresentState() API can be used to populate the structure * with the state of the SD host controller. */ -typedef union +typedef union XMC_SDMMC_PRESENT_STATE { struct { - uint32_t command_inihibit_cmd : 1; /**< Command: Inhibit command */ - uint32_t command_inihibit_dat : 1; /**< Command: Inhibit data */ - uint32_t dat_line_active : 1; /**< Data line active */ - uint32_t : 5; - uint32_t write_transfer_active : 1; /**< Write transfer active */ - uint32_t read_transfer_active : 1; /**< Read transfer active */ - uint32_t buffer_write_enable : 1; /**< Buffer write enable */ - uint32_t buffer_read_enable : 1; /**< Buffer read enable */ - uint32_t : 4; - uint32_t card_inserted : 1; /**< Card inserted */ - uint32_t card_state_stable : 1; /**< Card state stable */ - uint32_t card_detect_pin_level : 1; /**< Card detect pin level */ - uint32_t write_protect_pin_level : 1; /**< Write protect pin level */ - uint32_t dat_3_0_pin_level : 4; /**< Data 3_0 pin level */ - uint32_t cmd_line_level : 1; /**< Command line level */ - uint32_t dat7_4_pin_level : 4; /**< Data 7_4 pin level */ - uint32_t : 3; + uint32_t command_inihibit_cmd : 1; /**< Command: Inhibit command */ + uint32_t command_inihibit_dat : 1; /**< Command: Inhibit data */ + uint32_t dat_line_active : 1; /**< Data line active */ + uint32_t : 5; + uint32_t write_transfer_active : 1; /**< Write transfer active */ + uint32_t read_transfer_active : 1; /**< Read transfer active */ + uint32_t buffer_write_enable : 1; /**< Buffer write enable */ + uint32_t buffer_read_enable : 1; /**< Buffer read enable */ + uint32_t : 4; + uint32_t card_inserted : 1; /**< Card inserted */ + uint32_t card_state_stable : 1; /**< Card state stable */ + uint32_t card_detect_pin_level : 1; /**< Card detect pin level */ + uint32_t write_protect_pin_level : 1; /**< Write protect pin level */ + uint32_t dat_3_0_pin_level : 4; /**< Data 3_0 pin level */ + uint32_t cmd_line_level : 1; /**< Command line level */ + uint32_t dat7_4_pin_level : 4; /**< Data 7_4 pin level */ + uint32_t : 3; }; uint32_t b32; } XMC_SDMMC_PRESENT_STATE_t; @@ -510,7 +522,7 @@ typedef union /** * SDMMC transfer mode configuration */ -typedef struct +typedef struct XMC_SDMMC_TRANSFER_MODE { uint32_t block_size; uint32_t num_blocks; @@ -528,7 +540,7 @@ typedef struct * enable (and a few more). Once SDMMC.COMMAND is configured, the * XMC_SDMMC_SendCommand() function can be used to send the command. */ -typedef union +typedef union XMC_SDMMC_COMMAND { struct { @@ -546,15 +558,15 @@ typedef union /* Anonymous structure/union guard end */ #if defined (__CC_ARM) - #pragma pop +#pragma pop #elif defined (__TASKING__) - #pragma warning restore +#pragma warning restore #endif /** * Card response structure */ -typedef struct +typedef struct XMC_SDMMC_RESPONSE { uint32_t response_0; uint32_t response_2; @@ -567,7 +579,7 @@ typedef struct * * The structure is used to configure the bus width and the clock divider. */ -typedef struct +typedef struct XMC_SDMMC_CONFIG { uint8_t bus_width; /**< SDMMC bus width */ XMC_SDMMC_SDCLK_FREQ_SEL_t clock_divider; /**< SDMMC clock divider */ @@ -604,7 +616,7 @@ bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc); * \par * The function de-asserts the peripheral reset. The peripheral needs to be initialized. */ -void XMC_SDMMC_Enable( ); +void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc); /** * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address @@ -616,7 +628,7 @@ void XMC_SDMMC_Enable( ); * \par * The function asserts the peripheral reset. */ -void XMC_SDMMC_Disable( ); +void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc); /** * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address @@ -752,7 +764,7 @@ void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event); __STATIC_INLINE void XMC_SDMMC_TriggerEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) { XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + sdmmc->FORCE_EVENT_ERR_STATUS |= (uint16_t)(event >> 16U); } @@ -766,11 +778,18 @@ __STATIC_INLINE void XMC_SDMMC_TriggerEvent(XMC_SDMMC_t *const sdmmc, uint32_t e */ __STATIC_INLINE void XMC_SDMMC_SetCardDetectionSource(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_CD_SOURCE_t source) { - XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetCardDetectionSource: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + +#if UC_SERIES == XMC45 + sdmmc->HOST_CTRL = (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk) | source; +#else + XMC_UNUSED_ARG(sdmmc); + *(uint32_t *)SDMMC_CON = (*(uint32_t *)SDMMC_CON & (uint32_t)~SDMMC_CON_CDSEL_Msk) | source; +#endif - sdmmc->HOST_CTRL |= (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk) | source; } + /** * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address * @param status A valid SDMMC card detection status (::XMC_SDMMC_CD_STATUS_t) @@ -784,11 +803,55 @@ __STATIC_INLINE void XMC_SDMMC_SetCardDetectionSource(XMC_SDMMC_t *const sdmmc, */ __STATIC_INLINE void XMC_SDMMC_SetCardDetectionStatus(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_CD_STATUS_t status) { - XMC_ASSERT("XMC_SDMMC_TriggerEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_SetCardDetectionStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + +#if UC_SERIES == XMC45 + sdmmc->HOST_CTRL = (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk) | status; +#else + XMC_UNUSED_ARG(sdmmc); + *(uint32_t *)SDMMC_CON = (*(uint32_t *)SDMMC_CON & (uint32_t)~SDMMC_CON_CDSVAL_Msk) | status; +#endif +} - sdmmc->HOST_CTRL |= (sdmmc->HOST_CTRL & (uint32_t)~SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk) | status; +#if (UC_SERIES != XMC45) || defined(DOXYGEN) +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param source A valid SDMMC card detection signal source (::XMC_SDMMC_WP_SOURCE_t) + * @return None + * + * \parDescription:
      + * Selects input for card write protection status + */ +__STATIC_INLINE void XMC_SDMMC_SetWriteProtectionSource(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_WP_SOURCE_t source) +{ + XMC_ASSERT("XMC_SDMMC_SetWriteProtectionSource: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_UNUSED_ARG(sdmmc); + +#if UC_SERIES != XMC45 + *(uint32_t *)SDMMC_CON = (*(uint32_t *)SDMMC_CON & (uint32_t)~SDMMC_CON_WPSEL_Msk) | source; +#endif } +/** + * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address + * @param status A valid SDMMC card detection status (::XMC_SDMMC_WP_STATUS_t) + * @return None + * + * \parDescription:
      + * Sets the card write protection status indicating whether card is write protected or not. + * @note Only valid if SDMMC card detection signal source is set to XMC_SDMMC_WP_SOURCE_SW
      + * + */ +__STATIC_INLINE void XMC_SDMMC_SetWriteProtectionStatus(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_WP_STATUS_t status) +{ + XMC_ASSERT("XMC_SDMMC_SetWriteProtectionStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_UNUSED_ARG(sdmmc); + +#if UC_SERIES != XMC45 + *(uint32_t *)SDMMC_CON = (*(uint32_t *)SDMMC_CON & (uint32_t)~SDMMC_CON_WPSVAL_Msk) | status; +#endif +} +#endif /** * @param sdmmc A constant pointer to XMC_SDMMC_t, pointing to the SDMMC base address @@ -831,7 +894,7 @@ __STATIC_INLINE bool XMC_SDMMC_IsAnyErrorEvent(XMC_SDMMC_t *const sdmmc) __STATIC_INLINE void XMC_SDMMC_EnableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) { XMC_ASSERT("XMC_SDMMC_EnableWakeupEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + sdmmc->WAKEUP_CTRL |= (uint8_t)event; } @@ -856,7 +919,7 @@ __STATIC_INLINE void XMC_SDMMC_EnableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint3 __STATIC_INLINE void XMC_SDMMC_DisableWakeupEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) { XMC_ASSERT("XMC_SDMMC_DisableWakeupEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + sdmmc->WAKEUP_CTRL &= (uint8_t)~event; } @@ -876,7 +939,7 @@ __STATIC_INLINE bool XMC_SDMMC_GetACMDErrStatus(XMC_SDMMC_t *const sdmmc, XMC_SD { XMC_ASSERT("XMC_SDMMC_GetACMDErrStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); XMC_ASSERT("XMC_SDMMC_GetACMDErrStatus: Invalid ACMD response error", XMC_SDMMC_CHECK_ACMD_ERR(error)); - + return (bool)(sdmmc->ACMD_ERR_STATUS & (uint16_t)error); } @@ -899,7 +962,7 @@ __STATIC_INLINE bool XMC_SDMMC_GetACMDErrStatus(XMC_SDMMC_t *const sdmmc, XMC_SD __STATIC_INLINE void XMC_SDMMC_TriggerACMDErr(XMC_SDMMC_t *const sdmmc, uint32_t error) { XMC_ASSERT("XMC_SDMMC_TriggerACMDErr: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + sdmmc->FORCE_EVENT_ACMD_ERR_STATUS |= (uint16_t)error; } @@ -985,7 +1048,7 @@ __STATIC_INLINE void XMC_SDMMC_BusPowerOff(XMC_SDMMC_t *const sdmmc) __STATIC_INLINE void XMC_SDMMC_Start(XMC_SDMMC_t *const sdmmc) { XMC_ASSERT("XMC_SDMMC_Start: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + /* Enable internal clock */ sdmmc->CLOCK_CTRL |= (uint16_t)SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk; } @@ -1004,7 +1067,7 @@ __STATIC_INLINE void XMC_SDMMC_Start(XMC_SDMMC_t *const sdmmc) __STATIC_INLINE bool XMC_SDMMC_GetClockStability(XMC_SDMMC_t *const sdmmc) { XMC_ASSERT("XMC_SDMMC_GetClockStability: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + /* Return clock stability */ return (bool)(sdmmc->CLOCK_CTRL & SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk); } @@ -1103,7 +1166,7 @@ __STATIC_INLINE void XMC_SDMMC_SetSWReset(XMC_SDMMC_t *const sdmmc, uint32_t res __STATIC_INLINE uint32_t XMC_SDMMC_GetSWResetStatus(XMC_SDMMC_t *const sdmmc) { XMC_ASSERT("XMC_SDMMC_GetSWResetStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + return (uint32_t)(sdmmc->SW_RESET); } @@ -1186,7 +1249,7 @@ __STATIC_INLINE bool XMC_SDMMC_IsAllDataLinesHigh(XMC_SDMMC_t *const sdmmc) XMC_ASSERT("XMC_SDMMC_IsAllDataLinesHigh: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); return ((((sdmmc->PRESENT_STATE & SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk) >> - SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos) == 0x0FU) ? true : false); + SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos) == 0x0FU) ? true : false); } /** @@ -1221,7 +1284,7 @@ XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDM __STATIC_INLINE uint32_t XMC_SDMMC_GetCommandResponse(XMC_SDMMC_t *const sdmmc) { XMC_ASSERT("XMC_SDMMC_GetCommandResponse: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + return (sdmmc->RESPONSE[0]); } @@ -1393,10 +1456,13 @@ __STATIC_INLINE bool XMC_SDMMC_GetContinueRequest(XMC_SDMMC_t *const sdmmc) * at block gap for a multi-block transfer. This bit is only valid in a 4-bit mode of * the SDIO card. */ -__STATIC_INLINE void XMC_SDMMC_EnableInterruptAtBlockGap( XMC_SDMMC_t *const sdmmc ) +__STATIC_INLINE void XMC_SDMMC_EnableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config) { XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: This operation is only valid in 4-bit mode", + (config->bus_width == XMC_SDMMC_DATA_LINES_1)); + XMC_UNUSED_ARG(config); sdmmc->BLOCK_GAP_CTRL |= (uint8_t)SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk; } @@ -1412,11 +1478,15 @@ __STATIC_INLINE void XMC_SDMMC_EnableInterruptAtBlockGap( XMC_SDMMC_t *const sdm * The function resets the BLOCK_GAP_CTRL.INT_AT_BLOCK_GAP bit-field to disable interrupt * at block gap. This bit is only valid in a 4-bit mode of the SDIO card. */ -__STATIC_INLINE void XMC_SDMMC_DisableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc ) +__STATIC_INLINE void XMC_SDMMC_DisableInterruptAtBlockGap(XMC_SDMMC_t *const sdmmc, + const XMC_SDMMC_CONFIG_t *config) { XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_ASSERT("XMC_SDMMC_EnableInterruptAtBlockGap: This operation is only valid in 4-bit mode", + (config->bus_width == XMC_SDMMC_DATA_LINES_1)); + XMC_UNUSED_ARG(config); sdmmc->BLOCK_GAP_CTRL &= (uint8_t)~SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk; } @@ -1536,13 +1606,13 @@ __STATIC_INLINE void XMC_SDMMC_SetDataTransferWidth(XMC_SDMMC_t *const sdmmc, XM * example, XMC_SDMMC_DATA_TRANSFER_HOST_TO_CARD must be used for a write block operation. */ __STATIC_INLINE void XMC_SDMMC_SetDataTransferDirection(XMC_SDMMC_t *const sdmmc, - XMC_SDMMC_DATA_TRANSFER_DIR_t dir) + XMC_SDMMC_DATA_TRANSFER_DIR_t dir) { XMC_ASSERT("XMC_SDMMC_SetDataTransferDirection: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); XMC_ASSERT("XMC_SDMMC_SetDataTransferDirection: Invalid direction", XMC_SDMMC_CHECK_DATA_TRANSFER_DIR(dir)); sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk) | - (uint16_t)((uint16_t)dir << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)); + (uint16_t)((uint16_t)dir << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)); } /** @@ -1592,7 +1662,7 @@ __STATIC_INLINE void XMC_SDMMC_DisableDelayCmdDatLines(void) __STATIC_INLINE void XMC_SDMMC_SetDelay(uint8_t tapdel) { SCU_GENERAL->SDMMCDEL = (uint32_t)((SCU_GENERAL->SDMMCDEL & (uint32_t)~SCU_GENERAL_SDMMCDEL_TAPDEL_Msk) | - (uint32_t)(tapdel << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)); + (uint32_t)(tapdel << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)); } /** @@ -1641,9 +1711,6 @@ __STATIC_INLINE void XMC_SDMMC_DisableHighSpeed(XMC_SDMMC_t *const sdmmc) * @} */ -/** - * @} - */ #endif /* #if defined (SDMMC) */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_spi.h b/cores/xmc_lib/XMCLib/inc/xmc_spi.h index c7613543..0c318c16 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_spi.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_spi.h @@ -1,75 +1,43 @@ /** * @file xmc_spi.h - * @date 2016-05-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial - * - * 2015-05-20: - * - Documentation improved
      - * - Added XMC_SPI_CH_SetSlaveSelectDelay(), XMC_SPI_CH_TriggerServiceRequest() and - * XMC_SPI_CH_SelectInterruptNodePointer()
      - * - Added XMC_SPI_CH_SetInterwordDelaySCLK()
      - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
      - * - * 2015-08-24: - * - Added APIs for enabling/disabling delay compensation XMC_SPI_CH_DisableDelayCompensation() and - * XMC_SPI_CH_EnableDelayCompensation()
      - * - * 2015-08-27: - * - Added APIs for external input for BRG configuration:XMC_SPI_CH_ConfigExternalInputSignalToBRG()
      - * - * 2015-09-01: - * - Modified XMC_SPI_CH_SetInputSource() for avoiding complete DXCR register overwriting.
      - * - Modified XMC_SPI_CH_EVENT_t enum for supporting XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() - * for supporting multiple events configuration
      - * - * 2015-09-08: - * - Adding API for configuring the receiving clock phase in the slave:XMC_SPI_CH_DataLatchedInTrailingEdge() and XMC_SPI_CH_DataLatchedInLeadingEdge()
      - * - * 2016-04-10: - * - Added an API for configuring the transmit mode:XMC_SPI_CH_SetTransmitMode()
      - * - * 2016-05-20: - * - Added XMC_SPI_CH_EnableDataTransmission() and XMC_SPI_CH_DisableDataTransmission() - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -81,28 +49,24 @@ *********************************************************************************************************************/ #include "xmc_usic.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup SPI * @brief Synchronous serial channel driver for SPI-like communication. - * - * The SPI driver uses Universal Serial Interface Channel(USIC) module. + * + * The SPI driver uses Universal Serial Interface Channel(USIC) module. * The USIC module supports multiple data lines for SPI communication. \n * -# Full duplex communication with 2 separate lines for transmission and reception. * -# Half duplex communication with 1 common line shared for transmission and reception. * -# Dual mode communication with 2 common lines shared for transmission and reception. * -# Quad mode communication with 4 common lines shared for transmission and reception.

      - * + * * SPI driver provides structures, enumerations and APIs for configuring the USIC channel for SPI communication * and also for data transaction.
      * SPI driver features: * -# Configuration structure XMC_SPI_CH_CONFIG_t and SPI initialization function XMC_SPI_CH_Init() * -# Allows configuration of protocol word and frame length using XMC_SPI_CH_SetWordLength(), XMC_SPI_CH_SetFrameLength() - * -# Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(), XMC_SPI_CH_EnableEOF(), + * -# Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(), XMC_SPI_CH_EnableEOF(), XMC_SPI_CH_EnableSlaveSelect(), XMC_SPI_CH_DisableSlaveSelect() * -# Provides APIs for transmitting data and receiving data using XMC_SPI_CH_Transmit(), XMC_SPI_CH_Receive(), XMC_SPI_CH_GetReceivedData() * -# Allows configuration of shift clock using XMC_SPI_CH_ConfigureShiftClockOutput() @@ -156,9 +120,9 @@ typedef enum XMC_SPI_CH_BUS_MODE */ typedef enum XMC_SPI_CH_SLAVE_SEL_MSLS_INV { - XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS = 0x0UL, /**< The SELO outputs have the same polarity as the MSLS signal + XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS = 0x0UL, /**< The SELO outputs have the same polarity as the MSLS signal (active high) */ - XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS = 0x1UL << USIC_CH_PCR_SSCMode_SELINV_Pos /**< The SELO outputs have the inverted + XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS = 0x1UL << USIC_CH_PCR_SSCMode_SELINV_Pos /**< The SELO outputs have the inverted polarity to the MSLS signal (active low)*/ } XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t; @@ -210,27 +174,27 @@ typedef enum XMC_SPI_CH_EVENT */ typedef enum XMC_SPI_CH_STATUS_FLAG { - XMC_SPI_CH_STATUS_FLAG_MSLS = USIC_CH_PSR_SSCMode_MSLS_Msk, /**< Status of Master slave + XMC_SPI_CH_STATUS_FLAG_MSLS = USIC_CH_PSR_SSCMode_MSLS_Msk, /**< Status of Master slave select(MSLS) signal */ XMC_SPI_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_SSCMode_DX2S_Msk, /**< Status of slave select - input(DX2) signal*/ + input(DX2) signal*/ XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED = USIC_CH_PSR_SSCMode_MSLSEV_Msk, /**< Status for master slave select output signal transition*/ - XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_SSCMode_DX2TEV_Msk, /**< Status for slave select + XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_SSCMode_DX2TEV_Msk, /**< Status for slave select input signal transition */ - XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED = USIC_CH_PSR_SSCMode_PARERR_Msk, /**< Indicates status of the + XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED = USIC_CH_PSR_SSCMode_PARERR_Msk, /**< Indicates status of the parity error */ XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_SSCMode_RSIF_Msk, /**< Status for receive start event */ XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_SSCMode_DLIF_Msk, /**< Status for data lost event*/ XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_SSCMode_TSIF_Msk, /**< Status for transmit shift event */ - XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_SSCMode_TBIF_Msk, /**< Status for transmit buffer + XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_SSCMode_TBIF_Msk, /**< Status for transmit buffer event */ XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_RIF_Msk, /**< Status for receive event */ - XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_AIF_Msk, /**< Status for alternative + XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_SSCMode_AIF_Msk, /**< Status for alternative receive event */ - XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_SSCMode_BRGIF_Msk/**< Status for baud rate + XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_SSCMode_BRGIF_Msk/**< Status for baud rate generation error event */ } XMC_SPI_CH_STATUS_FLAG_t; @@ -250,7 +214,7 @@ typedef enum XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY */ typedef enum XMC_SPI_CH_INPUT { - XMC_SPI_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */ + XMC_SPI_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */ XMC_SPI_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */ XMC_SPI_CH_INPUT_SLAVE_SELIN = 2UL, /**< Slave select input stage */ XMC_SPI_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */ @@ -263,10 +227,10 @@ typedef enum XMC_SPI_CH_INPUT */ typedef enum XMC_SPI_CH_MODE { - XMC_SPI_CH_MODE_STANDARD = 0UL, /**< SPI standard full duplex mode */ - XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX = 4UL, /**< SPI standard half duplex mode */ - XMC_SPI_CH_MODE_DUAL= 6UL, /**< SPI half duplex mode with dual data lines */ - XMC_SPI_CH_MODE_QUAD= 7UL /**< SPI half duplex mode with quad data lines */ + XMC_SPI_CH_MODE_STANDARD = 0UL, /**< SPI standard full duplex mode */ + XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX = 5UL, /**< SPI standard half duplex mode */ + XMC_SPI_CH_MODE_DUAL = 6UL, /**< SPI half duplex mode with dual data lines */ + XMC_SPI_CH_MODE_QUAD = 7UL /**< SPI half duplex mode with quad data lines */ } XMC_SPI_CH_MODE_t; @@ -285,6 +249,24 @@ typedef enum XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED } XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t; +/** + * SPI clock modes + */ + +/* CPOL=0 is a clock which idles at 0, and each cycle consists of a pulse of 1. That is, the leading edge is a rising edge, and the trailing edge is a falling edge */ +/* CPOL=1 is a clock which idles at 1, and each cycle consists of a pulse of 0. That is, the leading edge is a falling edge, and the trailing edge is a rising edge */ +/* CPHA=0, the "out" side changes the data on the trailing edge of the preceding clock cycle, while the "in" side captures the data on (or shortly after) the leading edge of the clock cycle. + The out side holds the data valid until the trailing edge of the current clock cycle. For the first cycle, the first bit must be on the MOSI line before the leading clock edge.*/ +/* For CPHA=1, the "out" side changes the data on the leading edge of the current clock cycle, while the "in" side captures the data on (or shortly after) the trailing edge of the clock cycle. + The out side holds the data valid until the leading edge of the following clock cycle. For the last cycle, the slave holds the MISO line valid until slave select is deasserted. */ +typedef enum XMC_SPI_CLOCK_MODE +{ + XMC_SPI_CPOL_0_CPHA_0 = XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED, + XMC_SPI_CPOL_0_CPHA_1 = XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED, + XMC_SPI_CPOL_1_CPHA_0 = XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED, + XMC_SPI_CPOL_1_CPHA_1 = XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED +} XMC_SPI_CLOCK_MODE_t; + /** * SPI Baudrate Generator shift clock output */ @@ -315,9 +297,10 @@ typedef enum XMC_SPI_CH_INTERRUPT_NODE_POINTER */ typedef struct XMC_SPI_CH_CONFIG { - uint32_t baudrate; /**< Module baud rate for communication */ + uint32_t baudrate; /**< Module baud rate for communication */ + bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */ XMC_SPI_CH_BUS_MODE_t bus_mode; /**< Bus mode: Master/Slave */ - XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion; /**< Enable inversion of Slave select signal relative to the internal + XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion; /**< Enable inversion of Slave select signal relative to the internal MSLS signal */ XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Enable parity check for transmit and received data */ } XMC_SPI_CH_CONFIG_t; @@ -334,6 +317,7 @@ extern "C" { * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param config pointer to constant SPI channel configuration data structure.\n * Refer data structure @ref XMC_SPI_CH_CONFIG_t for detail. + * @param init_brg Selects if the baudrate generator should be configured automatically. * * @return None * @@ -359,7 +343,41 @@ extern "C" { *
    • Enable Frame end mode(MSLS signal is kept active after transmission of a frame)
      • *
    */ -void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config); +void XMC_SPI_CH_InitEx(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config, bool init_brg); + +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param config pointer to constant SPI channel configuration data structure.\n + * Refer data structure @ref XMC_SPI_CH_CONFIG_t for detail. + * + * @return None + * + * \parDescription:
    + * Initializes the selected SPI \a channel with the \a config structure.\n\n + * Enable SPI channel by calling XMC_USIC_CH_Enable() and then configures + *
      + *
    • Baudrate,
      • + *
    • Passive data level as active high,
      • + *
    • Shift control signal as active high,
      • + *
    • Frame length as 64U,
      • + *
    • Word length as 8U,
      • + *
    • Enable Hardware port control mode,
      • + *
    • Enable transmission of data TDV(Transmit data valid) bit is set to 1,
      • + *
    • Enable invalidation of data in TBUF once loaded into shift register,
      • + *
    • Parity mode settings
      • + *
    + * And if master mode is selected, + *
      + *
    • Enables MSLS signal generation,
      • + *
    • configures slave selection as normal mode,
      • + *
    • Set polarity for the Slave signal,
      • + *
    • Enable Frame end mode(MSLS signal is kept active after transmission of a frame)
      • + *
    + */ +__STATIC_INLINE void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config) +{ + XMC_SPI_CH_InitEx(channel, config, true); +} /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. @@ -389,7 +407,7 @@ __STATIC_INLINE void XMC_SPI_CH_Start(XMC_USIC_CH_t *const channel) * * \parDescription:
    * Set the selected SPI channel to IDLE mode, by clearing CCR.MODE bits.\n\n - * After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_SPI_CH_Start() has to be + * After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_SPI_CH_Start() has to be * invoked to start the communication again. * * \parRelated APIs:
    @@ -409,10 +427,27 @@ XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel); * Sets the bus speed in bits per second * * \parRelated APIs:
    - * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop() + * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop(), XMC_USIC_CH_GetSCLKFrequency() */ XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate); +/** + * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. + * @param rate Bus speed in bits per second + * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter of signal at the cost of frequency selection + * + * @return XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting baudrate is processed. \n + * XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed. \n + * XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range. + * + * \parDescription:
    + * Sets the bus speed in bits per second + * + * \parRelated APIs:
    + * XMC_SPI_CH_Init(), XMC_SPI_CH_Stop(), XMC_USIC_CH_GetSCLKFrequency() + */ +XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode); + /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param slave Slave select signal.\n @@ -454,16 +489,16 @@ void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel); * * \parDescription:
    * In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. \n\n - * By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the + * By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the * mode to ensure the proper communication. - * + * * \parRelated APIs:
    * XMC_SPI_CH_Transmit() */ __STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode) { channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) | - (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk); + (((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk); } /** @@ -480,8 +515,8 @@ __STATIC_INLINE void XMC_SPI_CH_SetTransmitMode(XMC_USIC_CH_t *const channel, co * pin is updated by hardware itself. TCI(Transmit Control Information) allows dynamic control of both the data shift mode * and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR bit fields. To support this auto * update, TCSR.HPCMD(Hardware Port control) will be enabled during the initialization using XMC_SPI_CH_Init() for all modes. - * - * + * + * * \parRelated APIs:
    * XMC_SPI_CH_Receive() */ @@ -490,15 +525,15 @@ void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, cons /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param mode Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated.\n - * Refer @ref XMC_SPI_CH_MODE_t for valid values. + * Refer @ref XMC_SPI_CH_MODE_t for valid values. * * @return None * * \parDescription:
    * Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n - * XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data + * XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data * XMC_SPI_CH_GetReceivedData() can be invoked to read the data from the buffers. - * + * * \parRelated APIs:
    * XMC_SPI_CH_GetReceivedDaa() */ @@ -517,7 +552,7 @@ __STATIC_INLINE void XMC_SPI_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_ * Reads data from the receive buffer based on the FIFO selection.\n\n * Invocation of XMC_SPI_CH_Receive() receives the data and place it into receive buffer. After receiving the data * XMC_SPI_CH_GetReceivedData() can be used to read the data from the buffer. - * + * * \parRelated APIs:
    * XMC_SPI_CH_Receive() */ @@ -548,7 +583,7 @@ __STATIC_INLINE void XMC_SPI_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel * * \parDescription:
    * Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n - * This is typically based on the slave settings. This is not set during XMC_SPI_CH_Init(). + * This is typically based on the slave settings. This is not set during XMC_SPI_CH_Init(). * Invoke XMC_SPI_CH_SetBitOrderMsbFirst() to set direction as needed in the program. * * \parRelated APIs:
    @@ -562,14 +597,14 @@ __STATIC_INLINE void XMC_SPI_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param event Protocol events which have to be enabled. - * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum items can be used + * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum items can be used * as input. * * @return None * * \parDescription:
    * Enables the SPI protocol specific events, by configuring PCR register.\n\n - * Events can be enabled as needed using XMC_SPI_CH_EnableEvent(). + * Events can be enabled as needed using XMC_SPI_CH_EnableEvent(). * XMC_SPI_CH_DisableEvent() can be used to disable the events. * * \parRelated APIs:
    @@ -580,7 +615,7 @@ void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event); /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param event Protocol events which have to be disabled. - * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum item can be used + * Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum item can be used * as input. * * @return None @@ -601,7 +636,7 @@ void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) * * \parDescription:
    * Returns the status of the events, by reading PSR register.\n\n - * This indicates the status of the all the events, for SPI communication. + * This indicates the status of the all the events, for SPI communication. * * \parRelated APIs:
    * XMC_SPI_CH_ClearStatusFlag() @@ -614,7 +649,7 @@ __STATIC_INLINE uint32_t XMC_SPI_CH_GetStatusFlag(XMC_USIC_CH_t *const channel) /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param flag Protocol event status to be cleared for detection of next occurence. - * Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used + * Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used * as input. * @return None * @@ -639,7 +674,7 @@ __STATIC_INLINE void XMC_SPI_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, co * * \parDescription:
    * Enables the generation of Master clock by setting PCR.MCLK bit.\n\n - * This clock can be used as a clock reference for external devices. This is not enabled during initialization in + * This clock can be used as a clock reference for external devices. This is not enabled during initialization in * XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by * XMC_SPI_CH_DisableMasterClock(). * @@ -709,12 +744,12 @@ __STATIC_INLINE void XMC_SPI_CH_DataLatchedInLeadingEdge(XMC_USIC_CH_t *const ch * * \parDescription:
    * Enables the delay after each word, by setting PCR.TIWEN bit.\n\n - * The inter word delay starts at the end of last SCLK cycle of data word. During this time no clock pulses are - * generated and MSLS signal stays active. If inter word delay is not enabled, last data bit of a data word is directly - * followed by the first data bit of the next data word. This is not enabled in XMC_SPI_CH_Init(). To enable + * The inter word delay starts at the end of last SCLK cycle of data word. During this time no clock pulses are + * generated and MSLS signal stays active. If inter word delay is not enabled, last data bit of a data word is directly + * followed by the first data bit of the next data word. This is not enabled in XMC_SPI_CH_Init(). To enable * XMC_SPI_CH_EnableInterwordDelay() has to be invoked as needed in the program. And can be disabled by invoking * XMC_SPI_CH_DisableInterwordDelay(). - * + * * \parRelated APIs:
    * XMC_SPI_CH_DisableInterwordDelay() */ @@ -730,7 +765,7 @@ __STATIC_INLINE void XMC_SPI_CH_EnableInterwordDelay(XMC_USIC_CH_t *const channe * * \parDescription:
    * Disables the delay after after each word, by clearing PCR.TIWEN bit.\n\n - * So the last data bit of a data word is directly followed by the first data bit of the next data word. If needed can + * So the last data bit of a data word is directly followed by the first data bit of the next data word. If needed can * be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). * * \parRelated APIs:
    @@ -749,16 +784,16 @@ __STATIC_INLINE void XMC_SPI_CH_DisableInterwordDelay(XMC_USIC_CH_t *const chann * * \parDescription:
    * Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields.\n\n - * The inter word delay is dependent on the peripheral clock. The maximum possible value is calculated by using the + * The inter word delay is dependent on the peripheral clock. The maximum possible value is calculated by using the * below formula\n * Maximum inter word delay = ((1 + PCTQ1_max)(1 + DCTQ1_max)) / peripheral clock\n * where PCTQ1_max = 3 and DCTQ1_max = 31\n * After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay(). - * + * * \parRelated APIs:
    * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_SetInterwordDelaySCLK() */ -void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_ns); +void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel, uint32_t tinterword_delay_ns); /** * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. @@ -775,13 +810,13 @@ void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterwo * \parRelated APIs:
    * XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_EnableInterwordDelay() */ -__STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const channel,uint32_t sclk_period) +__STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const channel, uint32_t sclk_period) { channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk | - USIC_CH_PCR_SSCMode_PCTQ1_Msk | - USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | + USIC_CH_PCR_SSCMode_PCTQ1_Msk | + USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | (((sclk_period - 1U) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) | - (0x02U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)); + (0x02U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)); } /** @@ -796,11 +831,11 @@ __STATIC_INLINE void XMC_SPI_CH_SetInterwordDelaySCLK(XMC_USIC_CH_t *const chann * is 30 clock cycles. * */ -__STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel,uint32_t sclk_period) +__STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel, uint32_t sclk_period) { channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | - USIC_CH_BRG_PCTQ_Msk)) | + USIC_CH_BRG_PCTQ_Msk)) | (((sclk_period - 1U) << USIC_CH_BRG_DCTQ_Pos) | (0x01U << USIC_CH_BRG_PCTQ_Pos)); } @@ -813,10 +848,10 @@ __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectDelay(XMC_USIC_CH_t *const channel * * Configure to keep MSLS(Slave select signal) active even after finishing the current data frame, * by setting PCR.FEM bit.\n\n - * This is typically used during the transmission of multi-data word frames, where there is possibility of delay in + * This is typically used during the transmission of multi-data word frames, where there is possibility of delay in * delivering the data. Frame end mode is enabled in XMC_SPI_CH_Init() during initialization. To disable * XMC_SPI_CH_DisableFEM() can be invoked as needed in the program. - * + * * \parRelated APIs:
    * XMC_SPI_CH_DisableFEM() */ @@ -834,9 +869,9 @@ __STATIC_INLINE void XMC_SPI_CH_EnableFEM(XMC_USIC_CH_t *const channel) * Configure to disable the MSLS(Slave select signal) if the current data frame is considered as finished, * by setting PCR.FEM bit.\n\n * - * When the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data, is + * When the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data, is * considered as frame is ended and MSLS(Slave select signal) is disabled. - * + * * \parRelated APIs:
    * XMC_SPI_CH_EnableFEM() */ @@ -859,15 +894,15 @@ __STATIC_INLINE void XMC_SPI_CH_DisableFEM(XMC_USIC_CH_t *const channel) * In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available * for external slave devices by SCLKOUT signal.\n * In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n - * The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock + * The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock * period. These settings are applicable only in master mode. */ __STATIC_INLINE void XMC_SPI_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, - const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, - const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) + const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, + const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) { XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)passive_level, - (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); + (XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output); } /** @@ -919,10 +954,10 @@ __STATIC_INLINE void XMC_SPI_CH_SetFrameLength(XMC_USIC_CH_t *const channel, con * * \parDescription
    * Configure the handling of start of frame through software, by setting TCSR.SOF bit.\n\n - * This can be used if the software handles the TBUF data without FIFO. If SOF is set, a valid content of the TBUF is + * This can be used if the software handles the TBUF data without FIFO. If SOF is set, a valid content of the TBUF is * considered as first word of a new frame by finishing the currently running frame. For software handling of SOF bit, * it is recommended to configure TCSR.WLEMD as 0. This is not configured during initialization. XMC_SPI_CH_EnableSOF() - * can be called as needed in the program and can be disabled by XMC_SPI_CH_DisableSOF(). + * can be called as needed in the program and can be disabled by XMC_SPI_CH_DisableSOF(). * * \parRelated APIs:
    * XMC_SPI_CH_DisableSOF() @@ -956,8 +991,8 @@ __STATIC_INLINE void XMC_SPI_CH_DisableSOF(XMC_USIC_CH_t *const channel) * * \parDescription
    * Configure the handling of end of frame through software, by setting TCSR.EOF bit.\n\n - * This can be used if the software handles the TBUF data without FIFO. If EOF is set, a valid content of the TBUF is - * considered as last word of a frame. After transfer of the last word, MSLS signal becomes inactive. For software + * This can be used if the software handles the TBUF data without FIFO. If EOF is set, a valid content of the TBUF is + * considered as last word of a frame. After transfer of the last word, MSLS signal becomes inactive. For software * handling of EOF bit, it is recommended to configure TCSR.WLEMD as 0. \n * \b Note: The API should be called before putting the last data word of the frame to TBUF. * @@ -997,13 +1032,13 @@ __STATIC_INLINE void XMC_SPI_CH_DisableEOF(XMC_USIC_CH_t *const channel) * * \parDescription
    * Selects the data source for SPI input stage, by configuring DXCR.DSEL bits.\n\n - * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the * input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting * the SPI communication. */ __STATIC_INLINE void XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t *const channel, - const XMC_SPI_CH_INPUT_t input, - const uint8_t source) + const XMC_SPI_CH_INPUT_t input, + const uint8_t source) { channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk; XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); @@ -1018,12 +1053,12 @@ __STATIC_INLINE void XMC_SPI_CH_SetInputSource(XMC_USIC_CH_t *const channel, * * \parDescription
    * Set the polarity of the slave select signal, by configuring PCR.SELINV bit.\n\n - * Normally MSLS signal is active low level signal. SO based on the slave inversion has to be applied. This is configured - * in XMC_SPI_CH_Init() during initialization. Invoke XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as + * Normally MSLS signal is active low level signal. SO based on the slave inversion has to be applied. This is configured + * in XMC_SPI_CH_Init() during initialization. Invoke XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as * needed later in the program. */ __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t *const channel, - const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion) + const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion) { /* Configuration of Protocol Control Register */ channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode & (~USIC_CH_PCR_SSCMode_SELINV_Msk)) | (uint32_t)selo_inversion); @@ -1038,14 +1073,14 @@ __STATIC_INLINE void XMC_SPI_CH_SetSlaveSelectPolarity(XMC_USIC_CH_t *const chan * * \parDescription
    * Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n - * This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as needed later in the program. To + * This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as needed later in the program. To * disable the inversion XMC_SPI_CH_DisableInputInversion() can be invoked. * * \parRelated APIs:
    * XMC_SPI_CH_DisableInputInversion() */ __STATIC_INLINE void XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, - const XMC_SPI_CH_INPUT_t input) + const XMC_SPI_CH_INPUT_t input) { XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); } @@ -1065,7 +1100,7 @@ __STATIC_INLINE void XMC_SPI_CH_EnableInputInversion(XMC_USIC_CH_t *const channe * XMC_SPI_CH_EnableInputInversion() */ __STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, - const XMC_SPI_CH_INPUT_t input) + const XMC_SPI_CH_INPUT_t input) { XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input); } @@ -1074,12 +1109,12 @@ __STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const chann * @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address. * @param service_request Service request number. Range: [0 to 5] - * + * * @return None * * \parDescription
    * Sets the interrupt node for SPI channel events.\n\n - * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). * The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_SPI_CH_Init() during * initialization. * @@ -1090,7 +1125,7 @@ __STATIC_INLINE void XMC_SPI_CH_DisableInputInversion(XMC_USIC_CH_t *const chann * XMC_USIC_CH_EnableEvent() */ __STATIC_INLINE void XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const uint8_t service_request) + const uint8_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request); } @@ -1116,11 +1151,11 @@ __STATIC_INLINE void XMC_SPI_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const cha * XMC_SPI_CH_EnableEvent() \n\n\n */ __STATIC_INLINE void XMC_SPI_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, - (uint32_t)service_request); + (uint32_t)service_request); } /** @@ -1192,10 +1227,10 @@ __STATIC_INLINE void XMC_SPI_CH_DisableDelayCompensation(XMC_USIC_CH_t *const ch * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n */ __STATIC_INLINE void XMC_SPI_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, - const uint16_t pdiv, - const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) + const uint16_t pdiv, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) { - XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,2U,combination_mode); + XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel, pdiv, 2U, combination_mode); } /** @@ -1261,7 +1296,7 @@ __STATIC_INLINE void XMC_SPI_CH_EnableDataTransmission(XMC_USIC_CH_t *const chan */ __STATIC_INLINE void XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) { - XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); } #ifdef __cplusplus @@ -1276,4 +1311,4 @@ __STATIC_INLINE void XMC_SPI_CH_DisableDataTransmission(XMC_USIC_CH_t *const cha * @} */ -#endif +#endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_uart.h b/cores/xmc_lib/XMCLib/inc/xmc_uart.h index 774d65b8..dbd21c82 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_uart.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_uart.h @@ -1,62 +1,45 @@ - /** - * @file xmc_uart.h - * @date 2016-05-20 - * - * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial - * - * 2015-05-20: - * - Description updated
    - * - Added XMC_UART_CH_TriggerServiceRequest() and XMC_UART_CH_SelectInterruptNodePointer
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
    - * - * 2015-09-01: - * - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting.
    - * - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() - * for supporting multiple events configuration
    - * - * 2016-05-20: - * - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission() - * - * @endcond - * - */ +/** +* @file xmc_uart.h +* +* @cond +***************************************************************************** +* XMClib - XMC Peripheral Driver Library +* +* Copyright (c) 2015-2023, Infineon Technologies AG +* All rights reserved. +* +* Boost Software License - Version 1.0 - August 17th, 2003 +* +* Permission is hereby granted, free of charge, to any person or organization +* obtaining a copy of the software and accompanying documentation covered by +* this license (the "Software") to use, reproduce, display, distribute, +* execute, and transmit the Software, and to prepare derivative works of the +* Software, and to permit third-parties to whom the Software is furnished to +* do so, all subject to the following: +* +* The copyright notices in the Software and this entire statement, including +* the above license grant, this restriction and the following disclaimer, +* must be included in all copies of the Software, in whole or in part, and +* all derivative works of the Software, unless such copies or derivative +* works are solely in the form of machine-executable object code generated by +* a source language processor. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT +* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE +* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* To improve the quality of the software, users are encouraged to share +* modifications, enhancements or bug fixes with Infineon Technologies AG +* at XMCSupport@infineon.com. +***************************************************************************** +* +* @endcond +* +*/ #ifndef XMC_UART_H #define XMC_UART_H @@ -67,10 +50,6 @@ #include "xmc_usic.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup UART @@ -80,16 +59,16 @@ * It provides APIs to configure USIC channel for UART communication. The driver enables the user * in getting the status of UART protocol events, configuring interrupt service requests, protocol * related parameter configuration etc. - * + * * UART driver features: * -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function XMC_UART_CH_Init() * -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref XMC_UART_CH_STATUS_FLAG_t * -# Allows the selection of input source for the DX0 input stage using the API XMC_UART_CH_SetInputSource() - * -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using + * -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength() * -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag() * -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data using XMC_UART_CH_GetReceivedData() - * + * * @{ */ @@ -163,7 +142,7 @@ typedef enum XMC_CH_UART_EVENT XMC_UART_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */ XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */ XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */ - + XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event synchronization break */ XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event collision */ XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event receiver noise */ @@ -216,13 +195,14 @@ typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER typedef struct XMC_UART_CH_CONFIG { uint32_t baudrate; /**< Desired baudrate. \b Range: minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */ + bool normal_divider_mode; /**< Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter at cost of frequency selection */ uint8_t data_bits; /**< Number of bits for the data field. Value configured as USIC channel word length. \n \b Range: minimum= 1, maximum= 16*/ - uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n + uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n \b Range: minimum= 1, maximum= 63*/ uint8_t stop_bits; /**< Number of stop bits. \b Range: minimum= 1, maximum= 2 */ uint8_t oversampling; /**< Number of samples for a symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/ - XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n + XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n @ref XMC_USIC_CH_PARITY_MODE_ODD*/ } XMC_UART_CH_CONFIG_t; @@ -234,6 +214,31 @@ typedef struct XMC_UART_CH_CONFIG extern "C" { #endif +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param config Constant pointer to UART configuration structure of type @ref XMC_UART_CH_CONFIG_t. + * @param init_brg Selects if the baudrate generator should be configured automatically. + * @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART protocol.\n + * \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n + * @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate failed. + * + * \parDescription
    + * Initializes the USIC channel for UART protocol.\n\n + * During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value + * in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16 + * is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the + * majority decision among 3 samples. + * Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length + * is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length. + * Parity mode is set to the value configured for \a parity_mode. + * The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API after the initialization. + * + * \parRelated APIs:
    + * XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n + */ +void XMC_UART_CH_InitEx(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config, bool init_brg); + /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection @@ -247,7 +252,7 @@ extern "C" { * During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value * in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16 * is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the - * majority decision among 3 samples. + * majority decision among 3 samples. * Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length * is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length. * Parity mode is set to the value configured for \a parity_mode. @@ -256,7 +261,10 @@ extern "C" { * \parRelated APIs:
    * XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n */ -void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config); +__STATIC_INLINE void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config) +{ + XMC_UART_CH_InitEx(channel, config, true); +} /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n @@ -266,7 +274,7 @@ void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t * * \parDescription
    * Sets the USIC channel operation mode to UART mode.\n\n * CCR register bitfield \a Mode is set to 2(UART mode). This API should be called after configuring - * the USIC channel. Transmission and reception can happen only when the UART mode is set. + * the USIC channel. Transmission and reception can happen only when the UART mode is set. * This is an inline function. * * \parRelated APIs:
    @@ -315,14 +323,40 @@ XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel); * a minimum oversampling of 4 for UART. * * \parRelated APIs:
    - * XMC_UART_CH_Init(), XMC_UART_CH_Stop() + * XMC_UART_CH_Init(), XMC_UART_CH_Stop(), XMC_USIC_CH_GetBaudrate() */ XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling); +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @param rate Desired baudrate. \n + * \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n + * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling) + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n + * This can be related to the number of samples for each logic state of the data signal.\n + * \b Range: 4 to 32. Value should be chosen based on the protocol used. + * @param normal_divider_mode Selects normal divider mode for baudrate generator instead of default fractional divider decreasing jitter of signal at the cost of frequency selection + * @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n + * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, + * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid. + * + * \parDescription:
    + * Sets the bus speed in bits per second.\n\n + * Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible. + * \a oversampling is the number of samples to be taken for each symbol of UART protocol. + * Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep + * a minimum oversampling of 4 for UART. + * + * \parRelated APIs:
    + * XMC_UART_CH_Init(), XMC_UART_CH_Stop(), XMC_USIC_CH_GetBaudrate() + */ +XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling, bool normal_divider_mode); + /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param data Data to be transmitted. \n + * @param data Data to be transmitted. \n * \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of * data transmitted depends on the configured number of bits for the UART protocol in the register SCTR. * @return None @@ -330,11 +364,12 @@ XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint3 * \parDescription
    * Transmits data over serial communication channel using UART protocol.\n\n * Based on the channel configuration, data is either put to the transmit FIFO or to TBUF register. - * Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register. - * So user can continuously execute the API without checking for TBUF busy status. Based on the number of + * Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register. + * So user can continuously execute the API without checking for TBUF busy status. Based on the number of * data bits configured, the lower significant bits will be extracted for transmission. * - * Note: When FIFO is not configured, the API waits for the TBUF to be available. + * \parNote:
    + * When FIFO is not configured, the API waits for the TBUF to be available. * This makes the execution a blocking call. * * \parRelated APIs:
    @@ -372,7 +407,7 @@ uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel); * If the UART data bits is more than 16, then the frame length should be set to the actual number of bits and * word length should be configured with the number of bits expected in each transaction. For example, if number of data bits * for UART communication is 20 bits, then the frame length should be set as 20. Word length can be set based on the - * transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case, + * transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case, * a full message of UART data should be transmitted/ received as 3 data words. * * \parRelated APIs:
    @@ -452,18 +487,20 @@ void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event * \parDescription
    * Sets the interrupt node for UART channel protocol events.\n\n * For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one common - * interrupt gets generated. The service request connects the interrupt node to the UART + * interrupt gets generated. The service request connects the interrupt node to the UART * protocol events. - * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parNote:
    + * NVIC node should be separately enabled to generate the interrupt. * * \parRelated APIs:
    * XMC_UART_CH_EnableEvent() \n\n\n */ __STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const uint8_t service_request) + const uint8_t service_request) { - XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, - (uint32_t)service_request); + XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, + (uint32_t)service_request); } /** @@ -480,17 +517,19 @@ __STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const ch * Sets the interrupt node for USIC channel events. \n\n * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). * The NVIC node gets linked to the interrupt event by doing so.
    - * Note: NVIC node should be separately enabled to generate the interrupt. + * + * \parNote:
    + * NVIC node should be separately enabled to generate the interrupt. * * \parRelated APIs:
    * XMC_UART_CH_EnableEvent() \n\n\n */ __STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node, - (uint32_t)service_request); + (uint32_t)service_request); } /** @@ -516,7 +555,7 @@ __STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const chan /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @return Status of UART channel events. \n + * @return Status of UART channel events. \n * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE, * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc. @@ -561,7 +600,7 @@ __STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, c /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @param source Input source select for the input stage. The table provided below maps the decimal value with the input source. @@ -573,22 +612,22 @@ __STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, c * \parDescription
    * Sets input soource for the UART communication.\n\n * It is used for configuring the input stage for data reception. - * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. - * The API can be used for the input stages DX0, DX3 and DX5. + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. + * The API can be used for the input stages DX0, DX3 and DX5. * * \parRelated APIs:
    * XMC_UART_CH_EnableInputInversion() \n\n\n */ __STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input, const uint8_t source) { - channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk|USIC_CH_DX0CR_DSEN_Msk))); + channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk | USIC_CH_DX0CR_DSEN_Msk))); XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source); } /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param pulse_length Length of the zero pulse in number of time quanta. \n + * @param pulse_length Length of the zero pulse in number of time quanta. \n * \b Range: 0 to 7. * @return None * @@ -606,6 +645,39 @@ __STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, co ((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos); } + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
    + * Enables the generation of the master clock MCLK.\n\n + * \parRelated APIs:
    + * XMC_USIC_CH_SetMclkOutputPassiveLevel()\n\n\n + * +*/ +__STATIC_INLINE void XMC_UART_CH_EnableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_ASCMode |= USIC_CH_PCR_ASCMode_MCLK_Msk; +} + +/** + * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection + * @return None + * + * \parDescription
    + * Disables the generation of the master clock MCLK.\n\n + * \parRelated APIs:
    + * XMC_USIC_CH_SetMclkOutputPassiveLevel()\n\n\n + * +*/ +__STATIC_INLINE void XMC_UART_CH_DisableMasterClock(XMC_USIC_CH_t *const channel) +{ + channel->PCR_ASCMode &= (uint32_t)~USIC_CH_PCR_ASCMode_MCLK_Msk; +} + /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection @@ -616,7 +688,7 @@ __STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, co * \parDescription
    * Sets the sample point among the multiple samples for each UART symbol.\n\n * The sample point is the one sample among number of samples set as oversampling. The value should be less than - * the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For + * the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For * example if the oversampling is 16, then the sample point is set to 9. * \parRelated APIs:
    * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n @@ -624,13 +696,13 @@ __STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, co __STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const uint32_t sample_point) { channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~USIC_CH_PCR_ASCMode_SP_Msk)) | - (sample_point << USIC_CH_PCR_ASCMode_SP_Pos)); + (sample_point << USIC_CH_PCR_ASCMode_SP_Pos)); } /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @return None @@ -649,7 +721,7 @@ __STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const chann /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @return None @@ -667,7 +739,7 @@ __STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const chan /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @return None @@ -685,7 +757,7 @@ __STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const c /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @return None @@ -703,7 +775,7 @@ __STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @return None @@ -720,7 +792,7 @@ __STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, c /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @return None @@ -738,7 +810,7 @@ __STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, /** * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection - * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n + * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0), * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5). * @param sampling_freq Input sampling frequency. \n @@ -752,8 +824,8 @@ __STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n */ __STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel, - const XMC_UART_CH_INPUT_t input, - const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq) + const XMC_UART_CH_INPUT_t input, + const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq) { XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq); } @@ -767,7 +839,9 @@ __STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const chann * Enable data transmission.\n\n * Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. * FIFO is filled using XMC_USIC_CH_TXFIFO_PutData(). - * @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() + * + * \parNote:
    + * If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode() * * \parRelated APIs:
    * XMC_UART_CH_DisableDataTransmission()\n\n\n @@ -792,7 +866,7 @@ __STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const cha */ __STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel) { - XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); + XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED); } #ifdef __cplusplus @@ -803,8 +877,5 @@ __STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const ch * @} */ -/** - * @} - */ #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usbd.h b/cores/xmc_lib/XMCLib/inc/xmc_usbd.h index a47df601..c87e4564 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_usbd.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_usbd.h @@ -1,52 +1,42 @@ /** * @file xmc_usbd.h - * @date 2015-06-20 - * - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-16: - * - Initial Version.
    - * 2015-03-18: - * - Updated the doxygen comments for documentation.
    - * - Updated the XMC_USBD_PATCH_VERSION to 4.
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API.
    - * - Updated the doxygen comments for API XMC_USBD_IsEnumDone().
    - * - Updated the copy right in the file header.
    - * - * @endcond + * + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -65,10 +55,6 @@ #include "xmc_usbd_regs.h" #include "xmc_scu.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup USBD @@ -86,10 +72,10 @@ * -# Supports USB soft disconnect. * -# Supports DMA mode. * -# Supports FIFO mode. - * + * * The below figure shows the overview of USB0 module in XMC4 microntroller. * @image html USB_module_overview.png - * @image latex ../images/USB_module_overview.png + * @image latex ../images/USB_module_overview.png * * The below figure shows the USB device connection of USB0 module. * @image html USB_device_connection.png @@ -104,7 +90,7 @@ * -# Stall/Abort the USB endpoints. * -# USB IN transfers on EP0 and non EP0 endpoints. * -# USB OUT transfers on EP0 and non EP0 endpoints. - * + * * The USBD device driver provides the configuration structure ::XMC_USBD_t which user need to configure before initializing the USB.\n * The following elements of configuration structure need to be initialized before calling the ::XMC_USBD_Init API: * -# cb_xmc_device_event of type ::XMC_USBD_SignalDeviceEvent_t. @@ -118,14 +104,14 @@ /********************************************************************************************************************** * MACROS *********************************************************************************************************************/ - + #define XMC_USBD_NUM_TX_FIFOS (7U) /**< Number of hardware transmission endpoint fifos */ #define XMC_USBD_MAX_FIFO_SIZE (2048U) /**< Maximum USBD endpoint fifo size */ #define XMC_USBD_NUM_EPS (7U) /**< Number of hardware endpoints */ -#define XMC_USBD_MAX_PACKET_SIZE (64U) /**< Maximum packet size for all endpoints +#define XMC_USBD_MAX_PACKET_SIZE (64U) /**< Maximum packet size for all endpoints (including ep0) */ /**< Maximum transfer size for endpoints. @@ -189,7 +175,8 @@ * Defines the options for the global receive fifo packet status. * Use type ::XMC_USBD_GRXSTS_PKTSTS_t for this enum. * */ -typedef enum XMC_USBD_GRXSTS_PKTSTS { +typedef enum XMC_USBD_GRXSTS_PKTSTS +{ XMC_USBD_GRXSTS_PKTSTS_GOUTNAK = 0x1U, /**< Global out nack send ( triggers an interrupt ) */ XMC_USBD_GRXSTS_PKTSTS_OUTDATA = 0x2U, /**< OUT data packet received */ XMC_USBD_GRXSTS_PKTSTS_OUTCMPL = 0x3U, /**< OUT transfer completed (triggers an interrupt) */ @@ -201,7 +188,8 @@ typedef enum XMC_USBD_GRXSTS_PKTSTS { * Defines the options for the USB endpoint type. The values are from the USB 2.0 specification. * Use type ::XMC_USBD_ENDPOINT_TYPE_t for this enum. */ -typedef enum XMC_USBD_ENDPOINT_TYPE { +typedef enum XMC_USBD_ENDPOINT_TYPE +{ XMC_USBD_ENDPOINT_TYPE_CONTROL = 0x0U, /**< Control endpoint */ XMC_USBD_ENDPOINT_TYPE_ISOCHRONOUS = 0x01U, /**< Isochronous endpoint */ XMC_USBD_ENDPOINT_TYPE_BULK = 0x02U, /**< Bulk endpoint */ @@ -213,7 +201,8 @@ typedef enum XMC_USBD_ENDPOINT_TYPE { * Defines the options for USB device state while setting the address. * Use type ::XMC_USBD_SET_ADDRESS_STAGE_t for this enum. */ -typedef enum XMC_USBD_SET_ADDRESS_STAGE { +typedef enum XMC_USBD_SET_ADDRESS_STAGE +{ XMC_USBD_SET_ADDRESS_STAGE_SETUP, /**< Setup address */ XMC_USBD_SET_ADDRESS_STAGE_STATUS /**< Status address */ } XMC_USBD_SET_ADDRESS_STAGE_t; @@ -223,7 +212,8 @@ typedef enum XMC_USBD_SET_ADDRESS_STAGE { * Defines the USB Device Status of executed operation. * Use type ::XMC_USBD_STATUS_t for this enum. */ -typedef enum XMC_USBD_STATUS { +typedef enum XMC_USBD_STATUS +{ XMC_USBD_STATUS_OK = 0U, /**< USBD Status: Operation succeeded*/ XMC_USBD_STATUS_BUSY = 2U, /**< Driver is busy and cannot handle request */ XMC_USBD_STATUS_ERROR = 1U /**< USBD Status: Unspecified error*/ @@ -234,7 +224,8 @@ typedef enum XMC_USBD_STATUS { * Defines the USB Device events. * Use type ::XMC_USBD_EVENT_t for this enum. */ -typedef enum XMC_USBD_EVENT { +typedef enum XMC_USBD_EVENT +{ XMC_USBD_EVENT_POWER_ON, /**< USB Device Power On */ XMC_USBD_EVENT_POWER_OFF, /**< USB Device Power Off */ XMC_USBD_EVENT_CONNECT, /**< USB Device connected */ @@ -256,7 +247,8 @@ typedef enum XMC_USBD_EVENT { * Defines the USB IN endpoint events. * Use type ::XMC_USBD_EVENT_IN_EP_t for this enum. */ -typedef enum XMC_USBD_EVENT_IN_EP { +typedef enum XMC_USBD_EVENT_IN_EP +{ XMC_USBD_EVENT_IN_EP_TX_COMPLET = 1U, /**< USB IN ep transmission complete */ XMC_USBD_EVENT_IN_EP_DISABLED = 2U, /**< USB IN ep disabled */ XMC_USBD_EVENT_IN_EP_AHB_ERROR = 4U, /**< USB IN ep AHB error */ @@ -267,7 +259,8 @@ typedef enum XMC_USBD_EVENT_IN_EP { * Defines the USB OUT endpoint events. * Use type ::XMC_USBD_EVENT_OUT_EP_t for this enum. */ -typedef enum XMC_USBD_EVENT_OUT_EP { +typedef enum XMC_USBD_EVENT_OUT_EP +{ XMC_USBD_EVENT_OUT_EP_TX_COMPLET = 1U, /**< USB OUT ep transmission complete */ XMC_USBD_EVENT_OUT_EP_DISABLED = 2U, /**< USB OUT ep disabled */ XMC_USBD_EVENT_OUT_EP_AHB_ERROR = 4U, /**< USB OUT ep AHB error */ @@ -279,7 +272,8 @@ typedef enum XMC_USBD_EVENT_OUT_EP { * Defines the generic USB endpoint events. * Use type ::XMC_USBD_EP_EVENT_t for this enum. */ -typedef enum XMC_USBD_EP_EVENT { +typedef enum XMC_USBD_EP_EVENT +{ XMC_USBD_EP_EVENT_SETUP, /**< SETUP packet*/ XMC_USBD_EP_EVENT_OUT, /**< OUT packet*/ XMC_USBD_EP_EVENT_IN /**< IN packet*/ @@ -289,7 +283,8 @@ typedef enum XMC_USBD_EP_EVENT { * Defines the options for the USB data transfer modes. * Use type ::XMC_USBD_TRANSFER_MODE_t for this enum. */ -typedef enum XMC_USBD_TRANSFER_MODE { +typedef enum XMC_USBD_TRANSFER_MODE +{ XMC_USBD_USE_DMA, /**< Transfer by DMA*/ XMC_USBD_USE_FIFO /**< Transfer by FIFO*/ } XMC_USBD_TRANSFER_MODE_t; @@ -298,7 +293,8 @@ typedef enum XMC_USBD_TRANSFER_MODE { * Defines the options for the maximum number of endpoints used. * Use type ::XMC_USBD_MAX_NUM_EPS_t for this enum. */ -typedef enum XMC_USBD_MAX_NUM_EPS { +typedef enum XMC_USBD_MAX_NUM_EPS +{ XMC_USBD_MAX_NUM_EPS_1 = 1U, /**< Maximum 1 endpoint used*/ XMC_USBD_MAX_NUM_EPS_2 = 2U, /**< Maximum 2 endpoints used*/ XMC_USBD_MAX_NUM_EPS_3 = 3U, /**< Maximum 3 endpoints used*/ @@ -323,7 +319,8 @@ typedef void (*XMC_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, XMC_USBD_EP_EVE /** * Describes the USB Device Driver Capabilities. */ -typedef struct XMC_USBD_CAPABILITIES { +typedef struct XMC_USBD_CAPABILITIES +{ uint32_t event_power_on : 1; /**< Signal Power On event*/ uint32_t event_power_off : 1; /**< Signal Power Off event*/ uint32_t event_connect : 1; /**< Signal Connect event*/ @@ -339,7 +336,8 @@ typedef struct XMC_USBD_CAPABILITIES { /** * Describes the current USB Device State. */ -typedef struct XMC_USBD_STATE { +typedef struct XMC_USBD_STATE +{ uint32_t powered : 1; /**< USB Device powered flag*/ uint32_t connected : 1; /**< USB Device connected flag*/ uint32_t active : 1; /**< USB Device active lag*/ @@ -352,15 +350,18 @@ typedef struct XMC_USBD_STATE { * All information to control an endpoint is stored in this structure. * It contains information about the endpoints and the status of the device. */ -typedef struct { - union { +typedef struct +{ + union + { uint32_t address : 8; /**< The endpoint address including the direction */ - struct { - uint32_t number : 4; /**< The endpoint number.It can be from 0 to 6 */ - uint32_t pading : 3; /**< Padding between number and direction */ - uint32_t direction : 1; /**< The endpoint direction */ - } address_st; - } address_u; + struct + { + uint32_t number : 4; /**< The endpoint number.It can be from 0 to 6 */ + uint32_t pading : 3; /**< Padding between number and direction */ + uint32_t direction : 1; /**< The endpoint direction */ + } address_st; + } address_u; uint32_t type : 2; /**< The endpoint type */ uint32_t isConfigured : 1; /**< The flag showing, if the endpoint is configured */ volatile uint32_t inInUse : 1; /**< Sets if the selected USB IN endpoint is currently in use */ @@ -389,7 +390,8 @@ typedef struct { * this structure. It contains register, callbacks, information * about the endpoints and the status of the device. */ -typedef struct XMC_USBD_DEVICE { +typedef struct XMC_USBD_DEVICE +{ XMC_USBD_EP_t ep[8]; /**< Endpoints of the USB device. It is of type ::XMC_USBD_EP_t */ dwc_otg_core_global_regs_t *global_register; /**< Global register interface */ dwc_otg_device_global_regs_t *device_register; /**< Device register interface */ @@ -420,7 +422,8 @@ typedef struct XMC_USBD_OBJ /** * Defines the access structure of the USB Device Driver. */ -typedef struct XMC_USBD_DRIVER { +typedef struct XMC_USBD_DRIVER +{ XMC_USBD_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to @ref XMC_USBD_GetCapabilities : Get driver capabilities.*/ @@ -444,7 +447,7 @@ typedef struct XMC_USBD_DRIVER { XMC_USBD_STATUS_t (*DeviceSetAddress) (uint8_t dev_addr, XMC_USBD_SET_ADDRESS_STAGE_t stage);/**< Pointer to @ref XMC_USBD_DeviceSetAddress : Set USB Device Address.*/ - XMC_USBD_STATUS_t (*EndpointConfigure) (uint8_t ep_addr,XMC_USBD_ENDPOINT_TYPE_t ep_type, uint16_t ep_max_packet_size);/**< Pointer to @ref XMC_USBD_EndpointConfigure : Configure USB Endpoint.*/ + XMC_USBD_STATUS_t (*EndpointConfigure) (uint8_t ep_addr, XMC_USBD_ENDPOINT_TYPE_t ep_type, uint16_t ep_max_packet_size); /**< Pointer to @ref XMC_USBD_EndpointConfigure : Configure USB Endpoint.*/ XMC_USBD_STATUS_t (*EndpointUnconfigure)(uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.*/ @@ -487,7 +490,7 @@ extern XMC_USBD_DEVICE_t xmc_device; /********************************************************************************************************************** * API PROTOTYPES *********************************************************************************************************************/ - + #ifdef __cplusplus extern "C" { #endif @@ -561,7 +564,7 @@ void XMC_USBD_ClearEvent(XMC_USBD_EVENT_t event); * \parRelated APIs:
    * ::XMC_USBD_ClearEventOUTEP()\n **/ -void XMC_USBD_ClearEventINEP(uint32_t event,uint8_t ep_num); +void XMC_USBD_ClearEventINEP(uint32_t event, uint8_t ep_num); /** @@ -583,7 +586,7 @@ void XMC_USBD_ClearEventINEP(uint32_t event,uint8_t ep_num); * \parRelated APIs:
    * ::XMC_USBD_ClearEventINEP()\n **/ -void XMC_USBD_ClearEventOUTEP(uint32_t event,uint8_t ep_num); +void XMC_USBD_ClearEventOUTEP(uint32_t event, uint8_t ep_num); /** * @param event The single event or multiple events that need to be enabled. @@ -757,7 +760,7 @@ XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj); * \parRelated APIs:
    * ::XMC_USBD_Init(), ::XMC_USBD_DeviceConnect()\n **/ -XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(uint8_t address,XMC_USBD_SET_ADDRESS_STAGE_t stage); +XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(uint8_t address, XMC_USBD_SET_ADDRESS_STAGE_t stage); /** * @param ep_addr The address of the USB endpoint, which needs to be configured. @@ -785,8 +788,8 @@ XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(uint8_t address,XMC_USBD_SET_ADDRESS * ::XMC_USBD_Init(),::XMC_USBD_DeviceConnect(),::XMC_USBD_EndpointUnconfigure()\n **/ XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(uint8_t ep_addr, - XMC_USBD_ENDPOINT_TYPE_t ep_type, - uint16_t ep_max_packet_size); + XMC_USBD_ENDPOINT_TYPE_t ep_type, + uint16_t ep_max_packet_size); /** * @param ep_addr The address of the USB endpoint, which needs to be unconfigured. @@ -872,7 +875,7 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t siz * \parRelated APIs:
    * ::XMC_USBD_EndpointReadStart()\n **/ -int32_t XMC_USBD_EndpointRead(const uint8_t ep_addr,uint8_t * buffer, uint32_t length); +int32_t XMC_USBD_EndpointRead(const uint8_t ep_addr, uint8_t *buffer, uint32_t length); /** @@ -895,7 +898,7 @@ int32_t XMC_USBD_EndpointRead(const uint8_t ep_addr,uint8_t * buffer, uint32_t l * \parRelated APIs:
    * ::XMC_USBD_EndpointRead()\n **/ -int32_t XMC_USBD_EndpointWrite(const uint8_t ep_addr,const uint8_t * buffer,uint32_t length); +int32_t XMC_USBD_EndpointWrite(const uint8_t ep_addr, const uint8_t *buffer, uint32_t length); /** @@ -980,10 +983,6 @@ void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj); * @} */ -/** - * @} - */ - #endif /* defined(USB0) */ #endif /* XMC_USBD_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usbd_regs.h b/cores/xmc_lib/XMCLib/inc/xmc_usbd_regs.h index 591bef82..85e0ad92 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_usbd_regs.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_usbd_regs.h @@ -1,7 +1,6 @@ /* ========================================================================== * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ * $Revision: #91 $ - * $Date: 2010/11/29 $ * $Change: 1636033 $ * * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, @@ -33,46 +32,44 @@ /* * @file xmc_usbd_regs.h - * @date 2015-02-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -115,20 +112,21 @@ /** Maximum tx fifos */ #define MAX_TX_FIFOS ( 14U ) /* dwc_dma_t type definition and register header file inclusion */ -typedef void* dwc_dma_t; +typedef void *dwc_dma_t; /****************************************************************************/ -/** DWC_otg Core registers . +/** DWC_otg Core registers . * The dwc_otg_core_global_regs structure defines the size * and relative field offsets for the Core Global registers. */ -typedef struct dwc_otg_core_global_regs { - /** OTG Control and Status Register. Offset: 000h */ - volatile uint32_t gotgctl; - /** OTG Interrupt Register. Offset: 004h */ - volatile uint32_t gotgint; - /**Core AHB Configuration Register. Offset: 008h */ - volatile uint32_t gahbcfg; +typedef struct dwc_otg_core_global_regs +{ + /** OTG Control and Status Register. Offset: 000h */ + volatile uint32_t gotgctl; + /** OTG Interrupt Register. Offset: 004h */ + volatile uint32_t gotgint; + /**Core AHB Configuration Register. Offset: 008h */ + volatile uint32_t gahbcfg; #define DWC_GLBINTRMASK 0x0001 #define DWC_DMAENABLE 0x0020 @@ -137,39 +135,39 @@ typedef struct dwc_otg_core_global_regs { #define DWC_PTXEMPTYLVL_EMPTY 0x0100 #define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 - /**Core USB Configuration Register. Offset: 00Ch */ - volatile uint32_t gusbcfg; - /**Core Reset Register. Offset: 010h */ - volatile uint32_t grstctl; - /**Core Interrupt Register. Offset: 014h */ - volatile uint32_t gintsts; - /**Core Interrupt Mask Register. Offset: 018h */ - volatile uint32_t gintmsk; - /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ - volatile uint32_t grxstsr; - /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ - volatile uint32_t grxstsp; - /**Receive FIFO Size Register. Offset: 024h */ - volatile uint32_t grxfsiz; - /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ - volatile uint32_t gnptxfsiz; - /**Non Periodic Transmit FIFO/Queue Status Register (Read - * Only). Offset: 02Ch */ - volatile uint32_t gnptxsts; - /**I2C Access Register. Offset: 030h */ - volatile uint32_t gi2cctl; - /**PHY Vendor Control Register. Offset: 034h */ - volatile uint32_t gpvndctl; - /**General Purpose Input/Output Register. Offset: 038h */ - volatile uint32_t ggpio; - /**User ID Register. Offset: 03Ch */ - volatile uint32_t guid; - /**Synopsys ID Register (Read Only). Offset: 040h */ - volatile uint32_t gsnpsid; - /**User HW Config1 Register (Read Only). Offset: 044h */ - volatile uint32_t ghwcfg1; - /**User HW Config2 Register (Read Only). Offset: 048h */ - volatile uint32_t ghwcfg2; + /**Core USB Configuration Register. Offset: 00Ch */ + volatile uint32_t gusbcfg; + /**Core Reset Register. Offset: 010h */ + volatile uint32_t grstctl; + /**Core Interrupt Register. Offset: 014h */ + volatile uint32_t gintsts; + /**Core Interrupt Mask Register. Offset: 018h */ + volatile uint32_t gintmsk; + /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ + volatile uint32_t grxstsr; + /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ + volatile uint32_t grxstsp; + /**Receive FIFO Size Register. Offset: 024h */ + volatile uint32_t grxfsiz; + /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ + volatile uint32_t gnptxfsiz; + /**Non Periodic Transmit FIFO/Queue Status Register (Read + * Only). Offset: 02Ch */ + volatile uint32_t gnptxsts; + /**I2C Access Register. Offset: 030h */ + volatile uint32_t gi2cctl; + /**PHY Vendor Control Register. Offset: 034h */ + volatile uint32_t gpvndctl; + /**General Purpose Input/Output Register. Offset: 038h */ + volatile uint32_t ggpio; + /**User ID Register. Offset: 03Ch */ + volatile uint32_t guid; + /**Synopsys ID Register (Read Only). Offset: 040h */ + volatile uint32_t gsnpsid; + /**User HW Config1 Register (Read Only). Offset: 044h */ + volatile uint32_t ghwcfg1; + /**User HW Config2 Register (Read Only). Offset: 048h */ + volatile uint32_t ghwcfg2; #define DWC_SLAVE_ONLY_ARCH 0 #define DWC_EXT_DMA_ARCH 1 #define DWC_INT_DMA_ARCH 2 @@ -182,26 +180,26 @@ typedef struct dwc_otg_core_global_regs { #define DWC_MODE_SRP_CAPABLE_HOST 5 #define DWC_MODE_NO_SRP_CAPABLE_HOST 6 - /**User HW Config3 Register (Read Only). Offset: 04Ch */ - volatile uint32_t ghwcfg3; - /**User HW Config4 Register (Read Only). Offset: 050h*/ - volatile uint32_t ghwcfg4; - /** Core LPM Configuration register Offset: 054h*/ - volatile uint32_t glpmcfg; - /** Global PowerDn Register Offset: 058h */ - volatile uint32_t gpwrdn; - /** Global DFIFO SW Config Register Offset: 05Ch */ - volatile uint32_t gdfifocfg; - /** ADP Control Register Offset: 060h */ - volatile uint32_t adpctl; - /** Reserved Offset: 064h-0FFh */ - volatile uint32_t reserved39[39]; - /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ - volatile uint32_t hptxfsiz; - /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, - otherwise Device Transmit FIFO#n Register. - * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ - volatile uint32_t dtxfsiz[15]; + /**User HW Config3 Register (Read Only). Offset: 04Ch */ + volatile uint32_t ghwcfg3; + /**User HW Config4 Register (Read Only). Offset: 050h*/ + volatile uint32_t ghwcfg4; + /** Core LPM Configuration register Offset: 054h*/ + volatile uint32_t glpmcfg; + /** Global PowerDn Register Offset: 058h */ + volatile uint32_t gpwrdn; + /** Global DFIFO SW Config Register Offset: 05Ch */ + volatile uint32_t gdfifocfg; + /** ADP Control Register Offset: 060h */ + volatile uint32_t adpctl; + /** Reserved Offset: 064h-0FFh */ + volatile uint32_t reserved39[39]; + /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ + volatile uint32_t hptxfsiz; + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, + otherwise Device Transmit FIFO#n Register. + * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ + volatile uint32_t dtxfsiz[15]; } dwc_otg_core_global_regs_t; /** @@ -209,34 +207,36 @@ typedef struct dwc_otg_core_global_regs { * and Status Register (GOTGCTL). Set the bits using the bit * fields then write the d32 value to the register. */ -typedef union gotgctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned sesreqscs:1; - unsigned sesreq:1; - unsigned vbvalidoven:1; - unsigned vbvalidovval:1; - unsigned avalidoven:1; - unsigned avalidovval:1; - unsigned bvalidoven:1; - unsigned bvalidovval:1; - unsigned hstnegscs:1; - unsigned hnpreq:1; - unsigned hstsethnpen:1; - unsigned devhnpen:1; - unsigned reserved12_15:4; - unsigned conidsts:1; - unsigned dbnctime:1; - unsigned asesvld:1; - unsigned bsesvld:1; - unsigned otgver:1; - unsigned reserved1:1; - unsigned multvalidbc:5; - unsigned chirpen:1; - unsigned reserved28_31:4; - } b; +typedef union gotgctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned sesreqscs: 1; + unsigned sesreq: 1; + unsigned vbvalidoven: 1; + unsigned vbvalidovval: 1; + unsigned avalidoven: 1; + unsigned avalidovval: 1; + unsigned bvalidoven: 1; + unsigned bvalidovval: 1; + unsigned hstnegscs: 1; + unsigned hnpreq: 1; + unsigned hstsethnpen: 1; + unsigned devhnpen: 1; + unsigned reserved12_15: 4; + unsigned conidsts: 1; + unsigned dbnctime: 1; + unsigned asesvld: 1; + unsigned bsesvld: 1; + unsigned otgver: 1; + unsigned reserved1: 1; + unsigned multvalidbc: 5; + unsigned chirpen: 1; + unsigned reserved28_31: 4; + } b; } gotgctl_data_t; /** @@ -244,39 +244,41 @@ typedef union gotgctl_data { * (GOTGINT). Set/clear the bits using the bit fields then write the d32 * value to the register. */ -typedef union gotgint_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Current Mode */ - unsigned reserved0_1:2; +typedef union gotgint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Current Mode */ + unsigned reserved0_1: 2; - /** Session End Detected */ - unsigned sesenddet:1; + /** Session End Detected */ + unsigned sesenddet: 1; - unsigned reserved3_7:5; + unsigned reserved3_7: 5; - /** Session Request Success Status Change */ - unsigned sesreqsucstschng:1; - /** Host Negotiation Success Status Change */ - unsigned hstnegsucstschng:1; + /** Session Request Success Status Change */ + unsigned sesreqsucstschng: 1; + /** Host Negotiation Success Status Change */ + unsigned hstnegsucstschng: 1; - unsigned reserved10_16:7; + unsigned reserved10_16: 7; - /** Host Negotiation Detected */ - unsigned hstnegdet:1; - /** A-Device Timeout Change */ - unsigned adevtoutchng:1; - /** Debounce Done */ - unsigned debdone:1; - /** Multi-Valued input changed */ - unsigned mvic:1; + /** Host Negotiation Detected */ + unsigned hstnegdet: 1; + /** A-Device Timeout Change */ + unsigned adevtoutchng: 1; + /** Debounce Done */ + unsigned debdone: 1; + /** Multi-Valued input changed */ + unsigned mvic: 1; - unsigned reserved31_21:11; + unsigned reserved31_21: 11; - } b; + } b; } gotgint_data_t; /** @@ -284,33 +286,35 @@ typedef union gotgint_data { * Register (GAHBCFG). Set/clear the bits using the bit fields then * write the d32 value to the register. */ -typedef union gahbcfg_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned glblintrmsk:1; +typedef union gahbcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned glblintrmsk: 1; #define DWC_GAHBCFG_GLBINT_ENABLE 1 - unsigned hburstlen:4; + unsigned hburstlen: 4; #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 - unsigned dmaenable:1; + unsigned dmaenable: 1; #define DWC_GAHBCFG_DMAENABLE 1 - unsigned reserved:1; - unsigned nptxfemplvl_txfemplvl:1; - unsigned ptxfemplvl:1; + unsigned reserved: 1; + unsigned nptxfemplvl_txfemplvl: 1; + unsigned ptxfemplvl: 1; #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 - unsigned reserved9_20:12; - unsigned remmemsupp:1; - unsigned notialldmawrit:1; - unsigned reserved23_31:9; - } b; + unsigned reserved9_20: 12; + unsigned remmemsupp: 1; + unsigned notialldmawrit: 1; + unsigned reserved23_31: 9; + } b; } gahbcfg_data_t; /** @@ -318,39 +322,41 @@ typedef union gahbcfg_data { * Register (GUSBCFG). Set the bits using the bit fields then write * the d32 value to the register. */ -typedef union gusbcfg_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned toutcal:3; - unsigned phyif:1; - unsigned ulpi_utmi_sel:1; - unsigned fsintf:1; - unsigned physel:1; - unsigned ddrsel:1; - unsigned srpcap:1; - unsigned hnpcap:1; - unsigned usbtrdtim:4; - unsigned reserved1:1; - unsigned phylpwrclksel:1; - unsigned otgutmifssel:1; - unsigned ulpi_fsls:1; - unsigned ulpi_auto_res:1; - unsigned ulpi_clk_sus_m:1; - unsigned ulpi_ext_vbus_drv:1; - unsigned ulpi_int_vbus_indicator:1; - unsigned term_sel_dl_pulse:1; - unsigned indicator_complement:1; - unsigned indicator_pass_through:1; - unsigned ulpi_int_prot_dis:1; - unsigned ic_usb_cap:1; - unsigned ic_traffic_pull_remove:1; - unsigned tx_end_delay:1; - unsigned force_host_mode:1; - unsigned force_dev_mode:1; - unsigned reserved31:1; - } b; +typedef union gusbcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned toutcal: 3; + unsigned phyif: 1; + unsigned ulpi_utmi_sel: 1; + unsigned fsintf: 1; + unsigned physel: 1; + unsigned ddrsel: 1; + unsigned srpcap: 1; + unsigned hnpcap: 1; + unsigned usbtrdtim: 4; + unsigned reserved1: 1; + unsigned phylpwrclksel: 1; + unsigned otgutmifssel: 1; + unsigned ulpi_fsls: 1; + unsigned ulpi_auto_res: 1; + unsigned ulpi_clk_sus_m: 1; + unsigned ulpi_ext_vbus_drv: 1; + unsigned ulpi_int_vbus_indicator: 1; + unsigned term_sel_dl_pulse: 1; + unsigned indicator_complement: 1; + unsigned indicator_pass_through: 1; + unsigned ulpi_int_prot_dis: 1; + unsigned ic_usb_cap: 1; + unsigned ic_traffic_pull_remove: 1; + unsigned tx_end_delay: 1; + unsigned force_host_mode: 1; + unsigned force_dev_mode: 1; + unsigned reserved31: 1; + } b; } gusbcfg_data_t; /** @@ -358,123 +364,125 @@ typedef union gusbcfg_data { * (GRSTCTL). Set/clear the bits using the bit fields then write the * d32 value to the register. */ -typedef union grstctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Core Soft Reset (CSftRst) (Device and Host) - * - * The application can flush the control logic in the - * entire core using this bit. This bit resets the - * pipelines in the AHB Clock domain as well as the - * PHY Clock domain. - * - * The state machines are reset to an IDLE state, the - * control bits in the CSRs are cleared, all the - * transmit FIFOs and the receive FIFO are flushed. - * - * The status mask bits that control the generation of - * the interrupt, are cleared, to clear the - * interrupt. The interrupt status bits are not - * cleared, so the application can get the status of - * any events that occurred in the core after it has - * set this bit. - * - * Any transactions on the AHB are terminated as soon - * as possible following the protocol. Any - * transactions on the USB are terminated immediately. - * - * The configuration settings in the CSRs are - * unchanged, so the software doesn't have to - * reprogram these registers (Device - * Configuration/Host Configuration/Core System - * Configuration/Core PHY Configuration). - * - * The application can write to this bit, any time it - * wants to reset the core. This is a self clearing - * bit and the core clears this bit after all the - * necessary logic is reset in the core, which may - * take several clocks, depending on the current state - * of the core. - */ - unsigned csftrst:1; - /** Hclk Soft Reset - * - * The application uses this bit to reset the control logic in - * the AHB clock domain. Only AHB clock domain pipelines are - * reset. - */ - unsigned hsftrst:1; - /** Host Frame Counter Reset (Host Only)
    - * - * The application can reset the (micro)frame number - * counter inside the core, using this bit. When the - * (micro)frame counter is reset, the subsequent SOF - * sent out by the core, will have a (micro)frame - * number of 0. - */ - unsigned hstfrm:1; - /** In Token Sequence Learning Queue Flush - * (INTknQFlsh) (Device Only) - */ - unsigned intknqflsh:1; - /** RxFIFO Flush (RxFFlsh) (Device and Host) - * - * The application can flush the entire Receive FIFO - * using this bit. The application must first - * ensure that the core is not in the middle of a - * transaction. The application should write into - * this bit, only after making sure that neither the - * DMA engine is reading from the RxFIFO nor the MAC - * is writing the data in to the FIFO. The - * application should wait until the bit is cleared - * before performing any other operations. This bit - * will takes 8 clocks (slowest of PHY or AHB clock) - * to clear. - */ - unsigned rxfflsh:1; - /** TxFIFO Flush (TxFFlsh) (Device and Host). - * - * This bit is used to selectively flush a single or - * all transmit FIFOs. The application must first - * ensure that the core is not in the middle of a - * transaction. The application should write into - * this bit, only after making sure that neither the - * DMA engine is writing into the TxFIFO nor the MAC - * is reading the data out of the FIFO. The - * application should wait until the core clears this - * bit, before performing any operations. This bit - * will takes 8 clocks (slowest of PHY or AHB clock) - * to clear. - */ - unsigned txfflsh:1; - - /** TxFIFO Number (TxFNum) (Device and Host). - * - * This is the FIFO number which needs to be flushed, - * using the TxFIFO Flush bit. This field should not - * be changed until the TxFIFO Flush bit is cleared by - * the core. - * - 0x0 : Non Periodic TxFIFO Flush - * - 0x1 : Periodic TxFIFO #1 Flush in device mode - * or Periodic TxFIFO in host mode - * - 0x2 : Periodic TxFIFO #2 Flush in device mode. - * - ... - * - 0xF : Periodic TxFIFO #15 Flush in device mode - * - 0x10: Flush all the Transmit NonPeriodic and - * Transmit Periodic FIFOs in the core - */ - unsigned txfnum:5; - /** Reserved */ - unsigned reserved11_29:19; - /** DMA Request Signal. Indicated DMA request is in - * probress. Used for debug purpose. */ - unsigned dmareq:1; - /** AHB Master Idle. Indicates the AHB Master State - * Machine is in IDLE condition. */ - unsigned ahbidle:1; - } b; +typedef union grstctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Core Soft Reset (CSftRst) (Device and Host) + * + * The application can flush the control logic in the + * entire core using this bit. This bit resets the + * pipelines in the AHB Clock domain as well as the + * PHY Clock domain. + * + * The state machines are reset to an IDLE state, the + * control bits in the CSRs are cleared, all the + * transmit FIFOs and the receive FIFO are flushed. + * + * The status mask bits that control the generation of + * the interrupt, are cleared, to clear the + * interrupt. The interrupt status bits are not + * cleared, so the application can get the status of + * any events that occurred in the core after it has + * set this bit. + * + * Any transactions on the AHB are terminated as soon + * as possible following the protocol. Any + * transactions on the USB are terminated immediately. + * + * The configuration settings in the CSRs are + * unchanged, so the software doesn't have to + * reprogram these registers (Device + * Configuration/Host Configuration/Core System + * Configuration/Core PHY Configuration). + * + * The application can write to this bit, any time it + * wants to reset the core. This is a self clearing + * bit and the core clears this bit after all the + * necessary logic is reset in the core, which may + * take several clocks, depending on the current state + * of the core. + */ + unsigned csftrst: 1; + /** Hclk Soft Reset + * + * The application uses this bit to reset the control logic in + * the AHB clock domain. Only AHB clock domain pipelines are + * reset. + */ + unsigned hsftrst: 1; + /** Host Frame Counter Reset (Host Only)
    + * + * The application can reset the (micro)frame number + * counter inside the core, using this bit. When the + * (micro)frame counter is reset, the subsequent SOF + * sent out by the core, will have a (micro)frame + * number of 0. + */ + unsigned hstfrm: 1; + /** In Token Sequence Learning Queue Flush + * (INTknQFlsh) (Device Only) + */ + unsigned intknqflsh: 1; + /** RxFIFO Flush (RxFFlsh) (Device and Host) + * + * The application can flush the entire Receive FIFO + * using this bit. The application must first + * ensure that the core is not in the middle of a + * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is reading from the RxFIFO nor the MAC + * is writing the data in to the FIFO. The + * application should wait until the bit is cleared + * before performing any other operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned rxfflsh: 1; + /** TxFIFO Flush (TxFFlsh) (Device and Host). + * + * This bit is used to selectively flush a single or + * all transmit FIFOs. The application must first + * ensure that the core is not in the middle of a + * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is writing into the TxFIFO nor the MAC + * is reading the data out of the FIFO. The + * application should wait until the core clears this + * bit, before performing any operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned txfflsh: 1; + + /** TxFIFO Number (TxFNum) (Device and Host). + * + * This is the FIFO number which needs to be flushed, + * using the TxFIFO Flush bit. This field should not + * be changed until the TxFIFO Flush bit is cleared by + * the core. + * - 0x0 : Non Periodic TxFIFO Flush + * - 0x1 : Periodic TxFIFO #1 Flush in device mode + * or Periodic TxFIFO in host mode + * - 0x2 : Periodic TxFIFO #2 Flush in device mode. + * - ... + * - 0xF : Periodic TxFIFO #15 Flush in device mode + * - 0x10: Flush all the Transmit NonPeriodic and + * Transmit Periodic FIFOs in the core + */ + unsigned txfnum: 5; + /** Reserved */ + unsigned reserved11_29: 19; + /** DMA Request Signal. Indicated DMA request is in + * probress. Used for debug purpose. */ + unsigned dmareq: 1; + /** AHB Master Idle. Indicates the AHB Master State + * Machine is in IDLE condition. */ + unsigned ahbidle: 1; + } b; } grstctl_t; /** @@ -482,90 +490,94 @@ typedef union grstctl_data { * Register (GINTMSK). Set/clear the bits using the bit fields then * write the d32 value to the register. */ -typedef union gintmsk_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved0:1; - unsigned modemismatch:1; - unsigned otgintr:1; - unsigned sofintr:1; - unsigned rxstsqlvl:1; - unsigned nptxfempty:1; - unsigned ginnakeff:1; - unsigned goutnakeff:1; - unsigned ulpickint:1; - unsigned i2cintr:1; - unsigned erlysuspend:1; - unsigned usbsuspend:1; - unsigned usbreset:1; - unsigned enumdone:1; - unsigned isooutdrop:1; - unsigned eopframe:1; - unsigned restoredone:1; - unsigned epmismatch:1; - unsigned inepintr:1; - unsigned outepintr:1; - unsigned incomplisoin:1; - unsigned incomplisoout:1; - unsigned fetsusp:1; - unsigned resetdet:1; - unsigned portintr:1; - unsigned hcintr:1; - unsigned ptxfempty:1; - unsigned lpmtranrcvd:1; - unsigned conidstschng:1; - unsigned disconnect:1; - unsigned sessreqintr:1; - unsigned wkupintr:1; - } b; +typedef union gintmsk_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned reserved0: 1; + unsigned modemismatch: 1; + unsigned otgintr: 1; + unsigned sofintr: 1; + unsigned rxstsqlvl: 1; + unsigned nptxfempty: 1; + unsigned ginnakeff: 1; + unsigned goutnakeff: 1; + unsigned ulpickint: 1; + unsigned i2cintr: 1; + unsigned erlysuspend: 1; + unsigned usbsuspend: 1; + unsigned usbreset: 1; + unsigned enumdone: 1; + unsigned isooutdrop: 1; + unsigned eopframe: 1; + unsigned restoredone: 1; + unsigned epmismatch: 1; + unsigned inepintr: 1; + unsigned outepintr: 1; + unsigned incomplisoin: 1; + unsigned incomplisoout: 1; + unsigned fetsusp: 1; + unsigned resetdet: 1; + unsigned portintr: 1; + unsigned hcintr: 1; + unsigned ptxfempty: 1; + unsigned lpmtranrcvd: 1; + unsigned conidstschng: 1; + unsigned disconnect: 1; + unsigned sessreqintr: 1; + unsigned wkupintr: 1; + } b; } gintmsk_data_t; /** * This union represents the bit fields of the Core Interrupt Register * (GINTSTS). Set/clear the bits using the bit fields then write the * d32 value to the register. */ -typedef union gintsts_data { - /** raw register data */ - uint32_t d32; +typedef union gintsts_data +{ + /** raw register data */ + uint32_t d32; #define DWC_SOF_INTR_MASK 0x0008 - /** register bits */ - struct { + /** register bits */ + struct + { #define DWC_HOST_MODE 1 - unsigned curmode:1; - unsigned modemismatch:1; - unsigned otgintr:1; - unsigned sofintr:1; - unsigned rxstsqlvl:1; - unsigned nptxfempty:1; - unsigned ginnakeff:1; - unsigned goutnakeff:1; - unsigned ulpickint:1; - unsigned i2cintr:1; - unsigned erlysuspend:1; - unsigned usbsuspend:1; - unsigned usbreset:1; - unsigned enumdone:1; - unsigned isooutdrop:1; - unsigned eopframe:1; - unsigned restoredone:1; - unsigned epmismatch:1; - unsigned inepint:1; - unsigned outepintr:1; - unsigned incomplisoin:1; - unsigned incomplisoout:1; - unsigned fetsusp:1; - unsigned resetdet:1; - unsigned portintr:1; - unsigned hcintr:1; - unsigned ptxfempty:1; - unsigned lpmtranrcvd:1; - unsigned conidstschng:1; - unsigned disconnect:1; - unsigned sessreqintr:1; - unsigned wkupintr:1; - } b; + unsigned curmode: 1; + unsigned modemismatch: 1; + unsigned otgintr: 1; + unsigned sofintr: 1; + unsigned rxstsqlvl: 1; + unsigned nptxfempty: 1; + unsigned ginnakeff: 1; + unsigned goutnakeff: 1; + unsigned ulpickint: 1; + unsigned i2cintr: 1; + unsigned erlysuspend: 1; + unsigned usbsuspend: 1; + unsigned usbreset: 1; + unsigned enumdone: 1; + unsigned isooutdrop: 1; + unsigned eopframe: 1; + unsigned restoredone: 1; + unsigned epmismatch: 1; + unsigned inepint: 1; + unsigned outepintr: 1; + unsigned incomplisoin: 1; + unsigned incomplisoout: 1; + unsigned fetsusp: 1; + unsigned resetdet: 1; + unsigned portintr: 1; + unsigned hcintr: 1; + unsigned ptxfempty: 1; + unsigned lpmtranrcvd: 1; + unsigned conidstschng: 1; + unsigned disconnect: 1; + unsigned sessreqintr: 1; + unsigned wkupintr: 1; + } b; } gintsts_data_t; /** @@ -573,14 +585,16 @@ typedef union gintsts_data { * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 * element then read out the bits using the bit elements. */ -typedef union device_grxsts_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned epnum:4; - unsigned bcnt:11; - unsigned dpid:2; +typedef union device_grxsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned epnum: 4; + unsigned bcnt: 11; + unsigned dpid: 2; #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete @@ -588,10 +602,10 @@ typedef union device_grxsts_data { #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet - unsigned pktsts:4; - unsigned fn:4; - unsigned reserved25_31:7; - } b; + unsigned pktsts: 4; + unsigned fn: 4; + unsigned reserved25_31: 7; + } b; } device_grxsts_data_t; /** @@ -599,23 +613,25 @@ typedef union device_grxsts_data { * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 * element then read out the bits using the bit elements. */ -typedef union host_grxsts_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned chnum:4; - unsigned bcnt:11; - unsigned dpid:2; - - unsigned pktsts:4; +typedef union host_grxsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned chnum: 4; + unsigned bcnt: 11; + unsigned dpid: 2; + + unsigned pktsts: 4; #define DWC_GRXSTS_PKTSTS_IN 0x2 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 - unsigned reserved21_31:11; - } b; + unsigned reserved21_31: 11; + } b; } host_grxsts_data_t; /** @@ -623,14 +639,16 @@ typedef union host_grxsts_data { * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then * read out the bits using the bit elements. */ -typedef union fifosize_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned startaddr:16; - unsigned depth:16; - } b; +typedef union fifosize_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned startaddr: 16; + unsigned depth: 16; + } b; } fifosize_data_t; /** @@ -639,28 +657,30 @@ typedef union fifosize_data { * d32 element then read out the bits using the bit * elements. */ -typedef union gnptxsts_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned nptxfspcavail:16; - unsigned nptxqspcavail:8; - /** Top of the Non-Periodic Transmit Request Queue - * - bit 24 - Terminate (Last entry for the selected - * channel/EP) - * - bits 26:25 - Token Type - * - 2'b00 - IN/OUT - * - 2'b01 - Zero Length OUT - * - 2'b10 - PING/Complete Split - * - 2'b11 - Channel Halt - * - bits 30:27 - Channel/EP Number - */ - unsigned nptxqtop_terminate:1; - unsigned nptxqtop_token:2; - unsigned nptxqtop_chnep:4; - unsigned reserved:1; - } b; +typedef union gnptxsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned nptxfspcavail: 16; + unsigned nptxqspcavail: 8; + /** Top of the Non-Periodic Transmit Request Queue + * - bit 24 - Terminate (Last entry for the selected + * channel/EP) + * - bits 26:25 - Token Type + * - 2'b00 - IN/OUT + * - 2'b01 - Zero Length OUT + * - 2'b10 - PING/Complete Split + * - 2'b11 - Channel Halt + * - bits 30:27 - Channel/EP Number + */ + unsigned nptxqtop_terminate: 1; + unsigned nptxqtop_token: 2; + unsigned nptxqtop_chnep: 4; + unsigned reserved: 1; + } b; } gnptxsts_data_t; /** @@ -669,14 +689,16 @@ typedef union gnptxsts_data { * d32 element then read out the bits using the bit * elements. */ -typedef union dtxfsts_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned txfspcavail:16; - unsigned reserved:16; - } b; +typedef union dtxfsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned txfspcavail: 16; + unsigned reserved: 16; + } b; } dtxfsts_data_t; /** @@ -684,23 +706,25 @@ typedef union dtxfsts_data { * (I2CCTL). Read the register into the d32 element then read out the * bits using the bit elements. */ -typedef union gi2cctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned rwdata:8; - unsigned regaddr:8; - unsigned addr:7; - unsigned i2cen:1; - unsigned ack:1; - unsigned i2csuspctl:1; - unsigned i2cdevaddr:2; - unsigned i2cdatse0:1; - unsigned reserved:1; - unsigned rw:1; - unsigned bsydne:1; - } b; +typedef union gi2cctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned rwdata: 8; + unsigned regaddr: 8; + unsigned addr: 7; + unsigned i2cen: 1; + unsigned ack: 1; + unsigned i2csuspctl: 1; + unsigned i2cdevaddr: 2; + unsigned i2cdatse0: 1; + unsigned reserved: 1; + unsigned rw: 1; + unsigned bsydne: 1; + } b; } gi2cctl_data_t; /** @@ -708,22 +732,24 @@ typedef union gi2cctl_data { * (GPVNDCTL). Read the register into the d32 element then read out the * bits using the bit elements. */ -typedef union gpvndctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned regdata:8; - unsigned vctrl:8; - unsigned regaddr16_21:6; - unsigned regwr:1; - unsigned reserved23_24:2; - unsigned newregreq:1; - unsigned vstsbsy:1; - unsigned vstsdone:1; - unsigned reserved28_30:3; - unsigned disulpidrvr:1; - } b; +typedef union gpvndctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned regdata: 8; + unsigned vctrl: 8; + unsigned regaddr16_21: 6; + unsigned regwr: 1; + unsigned reserved23_24: 2; + unsigned newregreq: 1; + unsigned vstsbsy: 1; + unsigned vstsdone: 1; + unsigned reserved28_30: 3; + unsigned disulpidrvr: 1; + } b; } gpvndctl_data_t; /** @@ -732,14 +758,16 @@ typedef union gpvndctl_data { * Read the register into the d32 element then read out the * bits using the bit elements. */ -typedef union ggpio_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned gpi:16; - unsigned gpo:16; - } b; +typedef union ggpio_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned gpi: 16; + unsigned gpo: 16; + } b; } ggpio_data_t; /** @@ -747,13 +775,15 @@ typedef union ggpio_data { * (GUID). Read the register into the d32 element then read out the * bits using the bit elements. */ -typedef union guid_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned rwdata:32; - } b; +typedef union guid_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned rwdata: 32; + } b; } guid_data_t; /** @@ -761,13 +791,15 @@ typedef union guid_data { * (GSNPSID). Read the register into the d32 element then read out the * bits using the bit elements. */ -typedef union gsnpsid_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned rwdata:32; - } b; +typedef union gsnpsid_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned rwdata: 32; + } b; } gsnpsid_data_t; /** @@ -775,28 +807,30 @@ typedef union gsnpsid_data { * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ -typedef union hwcfg1_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned ep_dir0:2; - unsigned ep_dir1:2; - unsigned ep_dir2:2; - unsigned ep_dir3:2; - unsigned ep_dir4:2; - unsigned ep_dir5:2; - unsigned ep_dir6:2; - unsigned ep_dir7:2; - unsigned ep_dir8:2; - unsigned ep_dir9:2; - unsigned ep_dir10:2; - unsigned ep_dir11:2; - unsigned ep_dir12:2; - unsigned ep_dir13:2; - unsigned ep_dir14:2; - unsigned ep_dir15:2; - } b; +typedef union hwcfg1_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned ep_dir0: 2; + unsigned ep_dir1: 2; + unsigned ep_dir2: 2; + unsigned ep_dir3: 2; + unsigned ep_dir4: 2; + unsigned ep_dir5: 2; + unsigned ep_dir6: 2; + unsigned ep_dir7: 2; + unsigned ep_dir8: 2; + unsigned ep_dir9: 2; + unsigned ep_dir10: 2; + unsigned ep_dir11: 2; + unsigned ep_dir12: 2; + unsigned ep_dir13: 2; + unsigned ep_dir14: 2; + unsigned ep_dir15: 2; + } b; } hwcfg1_data_t; /** @@ -804,13 +838,15 @@ typedef union hwcfg1_data { * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ -typedef union hwcfg2_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /* GHWCFG2 */ - unsigned op_mode:3; +typedef union hwcfg2_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /* GHWCFG2 */ + unsigned op_mode: 3; #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 @@ -819,26 +855,26 @@ typedef union hwcfg2_data { #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 - unsigned architecture:2; - unsigned point2point:1; - unsigned hs_phy_type:2; + unsigned architecture: 2; + unsigned point2point: 1; + unsigned hs_phy_type: 2; #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 - unsigned fs_phy_type:2; - unsigned num_dev_ep:4; - unsigned num_host_chan:4; - unsigned perio_ep_supported:1; - unsigned dynamic_fifo:1; - unsigned multi_proc_int:1; - unsigned reserved21:1; - unsigned nonperio_tx_q_depth:2; - unsigned host_perio_tx_q_depth:2; - unsigned dev_token_q_depth:5; - unsigned otg_enable_ic_usb:1; - } b; + unsigned fs_phy_type: 2; + unsigned num_dev_ep: 4; + unsigned num_host_chan: 4; + unsigned perio_ep_supported: 1; + unsigned dynamic_fifo: 1; + unsigned multi_proc_int: 1; + unsigned reserved21: 1; + unsigned nonperio_tx_q_depth: 2; + unsigned host_perio_tx_q_depth: 2; + unsigned dev_token_q_depth: 5; + unsigned otg_enable_ic_usb: 1; + } b; } hwcfg2_data_t; /** @@ -846,25 +882,27 @@ typedef union hwcfg2_data { * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ -typedef union hwcfg3_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /* GHWCFG3 */ - unsigned xfer_size_cntr_width:4; - unsigned packet_size_cntr_width:3; - unsigned otg_func:1; - unsigned i2c:1; - unsigned vendor_ctrl_if:1; - unsigned optional_features:1; - unsigned synch_reset_type:1; - unsigned adp_supp:1; - unsigned otg_enable_hsic:1; - unsigned otg_ver_support:1; - unsigned otg_lpm_en:1; - unsigned dfifo_depth:16; - } b; +typedef union hwcfg3_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /* GHWCFG3 */ + unsigned xfer_size_cntr_width: 4; + unsigned packet_size_cntr_width: 3; + unsigned otg_func: 1; + unsigned i2c: 1; + unsigned vendor_ctrl_if: 1; + unsigned optional_features: 1; + unsigned synch_reset_type: 1; + unsigned adp_supp: 1; + unsigned otg_enable_hsic: 1; + unsigned otg_ver_support: 1; + unsigned otg_lpm_en: 1; + unsigned dfifo_depth: 16; + } b; } hwcfg3_data_t; /** @@ -872,28 +910,30 @@ typedef union hwcfg3_data { * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ -typedef union hwcfg4_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned num_dev_perio_in_ep:4; - unsigned power_optimiz:1; - unsigned min_ahb_freq:1; - unsigned part_power_down:1; - unsigned reserved:7; - unsigned utmi_phy_data_width:2; - unsigned num_dev_mode_ctrl_ep:4; - unsigned iddig_filt_en:1; - unsigned vbus_valid_filt_en:1; - unsigned a_valid_filt_en:1; - unsigned b_valid_filt_en:1; - unsigned session_end_filt_en:1; - unsigned ded_fifo_en:1; - unsigned num_in_eps:4; - unsigned desc_dma:1; - unsigned desc_dma_dyn:1; - } b; +typedef union hwcfg4_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned num_dev_perio_in_ep: 4; + unsigned power_optimiz: 1; + unsigned min_ahb_freq: 1; + unsigned part_power_down: 1; + unsigned reserved: 7; + unsigned utmi_phy_data_width: 2; + unsigned num_dev_mode_ctrl_ep: 4; + unsigned iddig_filt_en: 1; + unsigned vbus_valid_filt_en: 1; + unsigned a_valid_filt_en: 1; + unsigned b_valid_filt_en: 1; + unsigned session_end_filt_en: 1; + unsigned ded_fifo_en: 1; + unsigned num_in_eps: 4; + unsigned desc_dma: 1; + unsigned desc_dma_dyn: 1; + } b; } hwcfg4_data_t; /** @@ -901,104 +941,106 @@ typedef union hwcfg4_data { * Register (GLPMCFG). Set the bits using bit fields then write * the d32 value to the register. */ -typedef union glpmctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** LPM-Capable (LPMCap) (Device and Host) - * The application uses this bit to control - * the DWC_otg core LPM capabilities. - */ - unsigned lpm_cap_en:1; - /** LPM response programmed by application (AppL1Res) (Device) - * Handshake response to LPM token pre-programmed - * by device application software. - */ - unsigned appl_resp:1; - /** Host Initiated Resume Duration (HIRD) (Device and Host) - * In Host mode this field indicates the value of HIRD - * to be sent in an LPM transaction. - * In Device mode this field is updated with the - * Received LPM Token HIRD bmAttribute - * when an ACK/NYET/STALL response is sent - * to an LPM transaction. - */ - unsigned hird:4; - /** RemoteWakeEnable (bRemoteWake) (Device and Host) - * In Host mode this bit indicates the value of remote - * wake up to be sent in wIndex field of LPM transaction. - * In Device mode this field is updated with the - * Received LPM Token bRemoteWake bmAttribute - * when an ACK/NYET/STALL response is sent - * to an LPM transaction. - */ - unsigned rem_wkup_en:1; - /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) - * The application uses this bit to control - * the utmi_sleep_n assertion to the PHY when in L1 state. - */ - unsigned en_utmi_sleep:1; - /** HIRD Threshold (HIRD_Thres) (Device and Host) - */ - unsigned hird_thres:5; - /** LPM Response (CoreL1Res) (Device and Host) - * In Host mode this bit contains handsake response to - * LPM transaction. - * In Device mode the response of the core to - * LPM transaction received is reflected in these two bits. - - 0x0 : ERROR (No handshake response) - - 0x1 : STALL - - 0x2 : NYET - - 0x3 : ACK - */ - unsigned lpm_resp:2; - /** Port Sleep Status (SlpSts) (Device and Host) - * This bit is set as long as a Sleep condition - * is present on the USB bus. - */ - unsigned prt_sleep_sts:1; - /** Sleep State Resume OK (L1ResumeOK) (Device and Host) - * Indicates that the application or host - * can start resume from Sleep state. - */ - unsigned sleep_state_resumeok:1; - /** LPM channel Index (LPM_Chnl_Indx) (Host) - * The channel number on which the LPM transaction - * has to be applied while sending - * an LPM transaction to the local device. - */ - unsigned lpm_chan_index:4; - /** LPM Retry Count (LPM_Retry_Cnt) (Host) - * Number host retries that would be performed - * if the device response was not valid response. - */ - unsigned retry_count:3; - /** Send LPM Transaction (SndLPM) (Host) - * When set by application software, - * an LPM transaction containing two tokens - * is sent. - */ - unsigned send_lpm:1; - /** LPM Retry status (LPM_RetryCnt_Sts) (Host) - * Number of LPM Host Retries still remaining - * to be transmitted for the current LPM sequence - */ - unsigned retry_count_sts:3; - unsigned reserved28_29:2; - /** In host mode once this bit is set, the host - * configures to drive the HSIC Idle state on the bus. - * It then waits for the device to initiate the Connect sequence. - * In device mode once this bit is set, the device waits for - * the HSIC Idle line state on the bus. Upon receving the Idle - * line state, it initiates the HSIC Connect sequence. - */ - unsigned hsic_connect:1; - /** This bit overrides and functionally inverts - * the if_select_hsic input port signal. - */ - unsigned inv_sel_hsic:1; - } b; +typedef union glpmctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** LPM-Capable (LPMCap) (Device and Host) + * The application uses this bit to control + * the DWC_otg core LPM capabilities. + */ + unsigned lpm_cap_en: 1; + /** LPM response programmed by application (AppL1Res) (Device) + * Handshake response to LPM token pre-programmed + * by device application software. + */ + unsigned appl_resp: 1; + /** Host Initiated Resume Duration (HIRD) (Device and Host) + * In Host mode this field indicates the value of HIRD + * to be sent in an LPM transaction. + * In Device mode this field is updated with the + * Received LPM Token HIRD bmAttribute + * when an ACK/NYET/STALL response is sent + * to an LPM transaction. + */ + unsigned hird: 4; + /** RemoteWakeEnable (bRemoteWake) (Device and Host) + * In Host mode this bit indicates the value of remote + * wake up to be sent in wIndex field of LPM transaction. + * In Device mode this field is updated with the + * Received LPM Token bRemoteWake bmAttribute + * when an ACK/NYET/STALL response is sent + * to an LPM transaction. + */ + unsigned rem_wkup_en: 1; + /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) + * The application uses this bit to control + * the utmi_sleep_n assertion to the PHY when in L1 state. + */ + unsigned en_utmi_sleep: 1; + /** HIRD Threshold (HIRD_Thres) (Device and Host) + */ + unsigned hird_thres: 5; + /** LPM Response (CoreL1Res) (Device and Host) + * In Host mode this bit contains handsake response to + * LPM transaction. + * In Device mode the response of the core to + * LPM transaction received is reflected in these two bits. + - 0x0 : ERROR (No handshake response) + - 0x1 : STALL + - 0x2 : NYET + - 0x3 : ACK + */ + unsigned lpm_resp: 2; + /** Port Sleep Status (SlpSts) (Device and Host) + * This bit is set as long as a Sleep condition + * is present on the USB bus. + */ + unsigned prt_sleep_sts: 1; + /** Sleep State Resume OK (L1ResumeOK) (Device and Host) + * Indicates that the application or host + * can start resume from Sleep state. + */ + unsigned sleep_state_resumeok: 1; + /** LPM channel Index (LPM_Chnl_Indx) (Host) + * The channel number on which the LPM transaction + * has to be applied while sending + * an LPM transaction to the local device. + */ + unsigned lpm_chan_index: 4; + /** LPM Retry Count (LPM_Retry_Cnt) (Host) + * Number host retries that would be performed + * if the device response was not valid response. + */ + unsigned retry_count: 3; + /** Send LPM Transaction (SndLPM) (Host) + * When set by application software, + * an LPM transaction containing two tokens + * is sent. + */ + unsigned send_lpm: 1; + /** LPM Retry status (LPM_RetryCnt_Sts) (Host) + * Number of LPM Host Retries still remaining + * to be transmitted for the current LPM sequence + */ + unsigned retry_count_sts: 3; + unsigned reserved28_29: 2; + /** In host mode once this bit is set, the host + * configures to drive the HSIC Idle state on the bus. + * It then waits for the device to initiate the Connect sequence. + * In device mode once this bit is set, the device waits for + * the HSIC Idle line state on the bus. Upon receving the Idle + * line state, it initiates the HSIC Connect sequence. + */ + unsigned hsic_connect: 1; + /** This bit overrides and functionally inverts + * the if_select_hsic input port signal. + */ + unsigned inv_sel_hsic: 1; + } b; } glpmcfg_data_t; /** @@ -1006,117 +1048,119 @@ typedef union glpmctl_data { * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write * the d32 value to the register. */ -typedef union adpctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Probe Discharge (PRB_DSCHG) - * These bits set the times for TADP_DSCHG. - * These bits are defined as follows: - * 2'b00 - 4 msec - * 2'b01 - 8 msec - * 2'b10 - 16 msec - * 2'b11 - 32 msec - */ - unsigned prb_dschg:2; - /** Probe Delta (PRB_DELTA) - * These bits set the resolution for RTIM value. - * The bits are defined in units of 32 kHz clock cycles as follows: - * 2'b00 - 1 cycles - * 2'b01 - 2 cycles - * 2'b10 - 3 cycles - * 2'b11 - 4 cycles - * For example if this value is chosen to 2'b01, it means that RTIM - * increments for every 3(three) 32Khz clock cycles. - */ - unsigned prb_delta:2; - /** Probe Period (PRB_PER) - * These bits sets the TADP_PRD as shown in Figure 4 as follows: - * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) - * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) - * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) - * 2'b11 - Reserved - */ - unsigned prb_per:2; - /** These bits capture the latest time it took for VBUS to ramp from VADP_SINK - * to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: - * 0x000 - 1 cycles - * 0x001 - 2 cycles - * 0x002 - 3 cycles - * etc - * 0x7FF - 2048 cycles - * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. - */ - unsigned rtim:11; - /** Enable Probe (EnaPrb) - * When programmed to 1'b1, the core performs a probe operation. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned enaprb:1; - /** Enable Sense (EnaSns) - * When programmed to 1'b1, the core performs a Sense operation. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned enasns:1; - /** ADP Reset (ADPRes) - * When set, ADP controller is reset. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adpres:1; - /** ADP Enable (ADPEn) - * When set, the core performs either ADP probing or sensing - * based on EnaPrb or EnaSns. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adpen:1; - /** ADP Probe Interrupt (ADP_PRB_INT) - * When this bit is set, it means that the VBUS - * voltage is greater than VADP_PRB or VADP_PRB is reached. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adp_prb_int:1; - /** - * ADP Sense Interrupt (ADP_SNS_INT) - * When this bit is set, it means that the VBUS voltage is greater than - * VADP_SNS value or VADP_SNS is reached. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adp_sns_int:1; - /** ADP Tomeout Interrupt (ADP_TMOUT_INT) - * This bit is relevant only for an ADP probe. - * When this bit is set, it means that the ramp time has - * completed ie ADPCTL.RTIM has reached its terminal value - * of 0x7FF. This is a debug feature that allows software - * to read the ramp time after each cycle. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adp_tmout_int:1; - /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) - * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adp_prb_int_msk:1; - /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) - * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adp_sns_int_msk:1; - /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) - * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. - * This bit is valid only if OTG_Ver = 1'b1. - */ - unsigned adp_tmout_int_msk:1; - /** Access Request - * 2'b00 - Read/Write Valid (updated by the core) - * 2'b01 - Read - * 2'b00 - Write - * 2'b00 - Reserved - */ - unsigned ar:2; - /** Reserved */ - unsigned reserved29_31:3; - } b; +typedef union adpctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Probe Discharge (PRB_DSCHG) + * These bits set the times for TADP_DSCHG. + * These bits are defined as follows: + * 2'b00 - 4 msec + * 2'b01 - 8 msec + * 2'b10 - 16 msec + * 2'b11 - 32 msec + */ + unsigned prb_dschg: 2; + /** Probe Delta (PRB_DELTA) + * These bits set the resolution for RTIM value. + * The bits are defined in units of 32 kHz clock cycles as follows: + * 2'b00 - 1 cycles + * 2'b01 - 2 cycles + * 2'b10 - 3 cycles + * 2'b11 - 4 cycles + * For example if this value is chosen to 2'b01, it means that RTIM + * increments for every 3(three) 32Khz clock cycles. + */ + unsigned prb_delta: 2; + /** Probe Period (PRB_PER) + * These bits sets the TADP_PRD as shown in Figure 4 as follows: + * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) + * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) + * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) + * 2'b11 - Reserved + */ + unsigned prb_per: 2; + /** These bits capture the latest time it took for VBUS to ramp from VADP_SINK + * to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: + * 0x000 - 1 cycles + * 0x001 - 2 cycles + * 0x002 - 3 cycles + * etc + * 0x7FF - 2048 cycles + * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. + */ + unsigned rtim: 11; + /** Enable Probe (EnaPrb) + * When programmed to 1'b1, the core performs a probe operation. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned enaprb: 1; + /** Enable Sense (EnaSns) + * When programmed to 1'b1, the core performs a Sense operation. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned enasns: 1; + /** ADP Reset (ADPRes) + * When set, ADP controller is reset. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adpres: 1; + /** ADP Enable (ADPEn) + * When set, the core performs either ADP probing or sensing + * based on EnaPrb or EnaSns. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adpen: 1; + /** ADP Probe Interrupt (ADP_PRB_INT) + * When this bit is set, it means that the VBUS + * voltage is greater than VADP_PRB or VADP_PRB is reached. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_prb_int: 1; + /** + * ADP Sense Interrupt (ADP_SNS_INT) + * When this bit is set, it means that the VBUS voltage is greater than + * VADP_SNS value or VADP_SNS is reached. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_sns_int: 1; + /** ADP Tomeout Interrupt (ADP_TMOUT_INT) + * This bit is relevant only for an ADP probe. + * When this bit is set, it means that the ramp time has + * completed ie ADPCTL.RTIM has reached its terminal value + * of 0x7FF. This is a debug feature that allows software + * to read the ramp time after each cycle. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_tmout_int: 1; + /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_prb_int_msk: 1; + /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_sns_int_msk: 1; + /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) + * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. + * This bit is valid only if OTG_Ver = 1'b1. + */ + unsigned adp_tmout_int_msk: 1; + /** Access Request + * 2'b00 - Read/Write Valid (updated by the core) + * 2'b01 - Read + * 2'b00 - Write + * 2'b00 - Reserved + */ + unsigned ar: 2; + /** Reserved */ + unsigned reserved29_31: 3; + } b; } adpctl_data_t; //////////////////////////////////////////// @@ -1130,56 +1174,57 @@ typedef union adpctl_data { * These registers are visible only in Device mode and must not be * accessed in Host mode, as the results are unknown. */ -typedef struct dwc_otg_dev_global_regs { - /** Device Configuration Register. Offset 800h */ - volatile uint32_t dcfg; - /** Device Control Register. Offset: 804h */ - volatile uint32_t dctl; - /** Device Status Register (Read Only). Offset: 808h */ - volatile uint32_t dsts; - /** Reserved. Offset: 80Ch */ - uint32_t unused; - /** Device IN Endpoint Common Interrupt Mask - * Register. Offset: 810h */ - volatile uint32_t diepmsk; - /** Device OUT Endpoint Common Interrupt Mask - * Register. Offset: 814h */ - volatile uint32_t doepmsk; - /** Device All Endpoints Interrupt Register. Offset: 818h */ - volatile uint32_t daint; - /** Device All Endpoints Interrupt Mask Register. Offset: - * 81Ch */ - volatile uint32_t daintmsk; - /** Device IN Token Queue Read Register-1 (Read Only). - * Offset: 820h */ - volatile uint32_t dtknqr1; - /** Device IN Token Queue Read Register-2 (Read Only). - * Offset: 824h */ - volatile uint32_t dtknqr2; - /** Device VBUS discharge Register. Offset: 828h */ - volatile uint32_t dvbusdis; - /** Device VBUS Pulse Register. Offset: 82Ch */ - volatile uint32_t dvbuspulse; - /** Device IN Token Queue Read Register-3 (Read Only). / - * Device Thresholding control register (Read/Write) - * Offset: 830h */ - volatile uint32_t dtknqr3_dthrctl; - /** Device IN Token Queue Read Register-4 (Read Only). / - * Device IN EPs empty Inr. Mask Register (Read/Write) - * Offset: 834h */ - volatile uint32_t dtknqr4_fifoemptymsk; - /** Device Each Endpoint Interrupt Register (Read Only). / - * Offset: 838h */ - volatile uint32_t deachint; - /** Device Each Endpoint Interrupt mask Register (Read/Write). / - * Offset: 83Ch */ - volatile uint32_t deachintmsk; - /** Device Each In Endpoint Interrupt mask Register (Read/Write). / - * Offset: 840h */ - volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; - /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / - * Offset: 880h */ - volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; +typedef struct dwc_otg_dev_global_regs +{ + /** Device Configuration Register. Offset 800h */ + volatile uint32_t dcfg; + /** Device Control Register. Offset: 804h */ + volatile uint32_t dctl; + /** Device Status Register (Read Only). Offset: 808h */ + volatile uint32_t dsts; + /** Reserved. Offset: 80Ch */ + uint32_t unused; + /** Device IN Endpoint Common Interrupt Mask + * Register. Offset: 810h */ + volatile uint32_t diepmsk; + /** Device OUT Endpoint Common Interrupt Mask + * Register. Offset: 814h */ + volatile uint32_t doepmsk; + /** Device All Endpoints Interrupt Register. Offset: 818h */ + volatile uint32_t daint; + /** Device All Endpoints Interrupt Mask Register. Offset: + * 81Ch */ + volatile uint32_t daintmsk; + /** Device IN Token Queue Read Register-1 (Read Only). + * Offset: 820h */ + volatile uint32_t dtknqr1; + /** Device IN Token Queue Read Register-2 (Read Only). + * Offset: 824h */ + volatile uint32_t dtknqr2; + /** Device VBUS discharge Register. Offset: 828h */ + volatile uint32_t dvbusdis; + /** Device VBUS Pulse Register. Offset: 82Ch */ + volatile uint32_t dvbuspulse; + /** Device IN Token Queue Read Register-3 (Read Only). / + * Device Thresholding control register (Read/Write) + * Offset: 830h */ + volatile uint32_t dtknqr3_dthrctl; + /** Device IN Token Queue Read Register-4 (Read Only). / + * Device IN EPs empty Inr. Mask Register (Read/Write) + * Offset: 834h */ + volatile uint32_t dtknqr4_fifoemptymsk; + /** Device Each Endpoint Interrupt Register (Read Only). / + * Offset: 838h */ + volatile uint32_t deachint; + /** Device Each Endpoint Interrupt mask Register (Read/Write). / + * Offset: 83Ch */ + volatile uint32_t deachintmsk; + /** Device Each In Endpoint Interrupt mask Register (Read/Write). / + * Offset: 840h */ + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / + * Offset: 880h */ + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; } dwc_otg_device_global_regs_t; /** @@ -1188,35 +1233,37 @@ typedef struct dwc_otg_dev_global_regs { * set/clear the bits using the bit elements. Write the * d32 member to the dcfg register. */ -typedef union dcfg_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Device Speed */ - unsigned devspd:2; - /** Non Zero Length Status OUT Handshake */ - unsigned nzstsouthshk:1; +typedef union dcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Device Speed */ + unsigned devspd: 2; + /** Non Zero Length Status OUT Handshake */ + unsigned nzstsouthshk: 1; #define DWC_DCFG_SEND_STALL 1 - unsigned ena32khzs:1; - /** Device Addresses */ - unsigned devaddr:7; - /** Periodic Frame Interval */ - unsigned perfrint:2; + unsigned ena32khzs: 1; + /** Device Addresses */ + unsigned devaddr: 7; + /** Periodic Frame Interval */ + unsigned perfrint: 2; #define DWC_DCFG_FRAME_INTERVAL_80 0 #define DWC_DCFG_FRAME_INTERVAL_85 1 #define DWC_DCFG_FRAME_INTERVAL_90 2 #define DWC_DCFG_FRAME_INTERVAL_95 3 - unsigned reserved13_17:5; - /** In Endpoint Mis-match count */ - unsigned epmscnt:5; - /** Enable Descriptor DMA in Device mode */ - unsigned descdma:1; - unsigned perschintvl:2; - unsigned resvalid:6; - } b; + unsigned reserved13_17: 5; + /** In Endpoint Mis-match count */ + unsigned epmscnt: 5; + /** Enable Descriptor DMA in Device mode */ + unsigned descdma: 1; + unsigned perschintvl: 2; + unsigned resvalid: 6; + } b; } dcfg_data_t; /** @@ -1224,43 +1271,45 @@ typedef union dcfg_data { * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ -typedef union dctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Remote Wakeup */ - unsigned rmtwkupsig:1; - /** Soft Disconnect */ - unsigned sftdiscon:1; - /** Global Non-Periodic IN NAK Status */ - unsigned gnpinnaksts:1; - /** Global OUT NAK Status */ - unsigned goutnaksts:1; - /** Test Control */ - unsigned tstctl:3; - /** Set Global Non-Periodic IN NAK */ - unsigned sgnpinnak:1; - /** Clear Global Non-Periodic IN NAK */ - unsigned cgnpinnak:1; - /** Set Global OUT NAK */ - unsigned sgoutnak:1; - /** Clear Global OUT NAK */ - unsigned cgoutnak:1; - - /** Power-On Programming Done */ - unsigned pwronprgdone:1; - /** Reserved */ - unsigned reserved:1; - /** Global Multi Count */ - unsigned gmc:2; - /** Ignore Frame Number for ISOC EPs */ - unsigned ifrmnum:1; - /** NAK on Babble */ - unsigned nakonbble:1; - - unsigned reserved17_31:15; - } b; +typedef union dctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Remote Wakeup */ + unsigned rmtwkupsig: 1; + /** Soft Disconnect */ + unsigned sftdiscon: 1; + /** Global Non-Periodic IN NAK Status */ + unsigned gnpinnaksts: 1; + /** Global OUT NAK Status */ + unsigned goutnaksts: 1; + /** Test Control */ + unsigned tstctl: 3; + /** Set Global Non-Periodic IN NAK */ + unsigned sgnpinnak: 1; + /** Clear Global Non-Periodic IN NAK */ + unsigned cgnpinnak: 1; + /** Set Global OUT NAK */ + unsigned sgoutnak: 1; + /** Clear Global OUT NAK */ + unsigned cgoutnak: 1; + + /** Power-On Programming Done */ + unsigned pwronprgdone: 1; + /** Reserved */ + unsigned reserved: 1; + /** Global Multi Count */ + unsigned gmc: 2; + /** Ignore Frame Number for ISOC EPs */ + unsigned ifrmnum: 1; + /** NAK on Babble */ + unsigned nakonbble: 1; + + unsigned reserved17_31: 15; + } b; } dctl_data_t; /** @@ -1268,26 +1317,28 @@ typedef union dctl_data { * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ -typedef union dsts_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Suspend Status */ - unsigned suspsts:1; - /** Enumerated Speed */ - unsigned enumspd:2; +typedef union dsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Suspend Status */ + unsigned suspsts: 1; + /** Enumerated Speed */ + unsigned enumspd: 2; #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 - /** Erratic Error */ - unsigned errticerr:1; - unsigned reserved4_7:4; - /** Frame or Microframe Number of the received SOF */ - unsigned soffn:14; - unsigned reserved22_31:10; - } b; + /** Erratic Error */ + unsigned errticerr: 1; + unsigned reserved4_7: 4; + /** Frame or Microframe Number of the received SOF */ + unsigned soffn: 14; + unsigned reserved22_31: 10; + } b; } dsts_data_t; /** @@ -1297,39 +1348,41 @@ typedef union dsts_data { * - Read the register into the d32 member then set/clear the * bits using the bit elements. */ -typedef union diepint_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer complete mask */ - unsigned xfercompl:1; - /** Endpoint disable mask */ - unsigned epdisabled:1; - /** AHB Error mask */ - unsigned ahberr:1; - /** TimeOUT Handshake mask (non-ISOC EPs) */ - unsigned timeout:1; - /** IN Token received with TxF Empty mask */ - unsigned intktxfemp:1; - /** IN Token Received with EP mismatch mask */ - unsigned intknepmis:1; - /** IN Endpoint NAK Effective mask */ - unsigned inepnakeff:1; - /** Reserved */ - unsigned emptyintr:1; - - unsigned txfifoundrn:1; - - /** BNA Interrupt mask */ - unsigned bna:1; - - unsigned reserved10_12:3; - /** BNA Interrupt mask */ - unsigned nak:1; - - unsigned reserved14_31:18; - } b; +typedef union diepint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer complete mask */ + unsigned xfercompl: 1; + /** Endpoint disable mask */ + unsigned epdisabled: 1; + /** AHB Error mask */ + unsigned ahberr: 1; + /** TimeOUT Handshake mask (non-ISOC EPs) */ + unsigned timeout: 1; + /** IN Token received with TxF Empty mask */ + unsigned intktxfemp: 1; + /** IN Token Received with EP mismatch mask */ + unsigned intknepmis: 1; + /** IN Endpoint NAK Effective mask */ + unsigned inepnakeff: 1; + /** Reserved */ + unsigned emptyintr: 1; + + unsigned txfifoundrn: 1; + + /** BNA Interrupt mask */ + unsigned bna: 1; + + unsigned reserved10_12: 3; + /** BNA Interrupt mask */ + unsigned nak: 1; + + unsigned reserved14_31: 18; + } b; } diepint_data_t; /** @@ -1345,44 +1398,46 @@ typedef union diepint_data diepmsk_data_t; * - Read the register into the d32 member then set/clear the * bits using the bit elements. */ -typedef union doepint_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer complete */ - unsigned xfercompl:1; - /** Endpoint disable */ - unsigned epdisabled:1; - /** AHB Error */ - unsigned ahberr:1; - /** Setup Phase Done (contorl EPs) */ - unsigned setup:1; - /** OUT Token Received when Endpoint Disabled */ - unsigned outtknepdis:1; - - unsigned stsphsercvd:1; - /** Back-to-Back SETUP Packets Received */ - unsigned back2backsetup:1; - - unsigned reserved7:1; - /** OUT packet Error */ - unsigned outpkterr:1; - /** BNA Interrupt */ - unsigned bna:1; - - unsigned reserved10:1; - /** Packet Drop Status */ - unsigned pktdrpsts:1; - /** Babble Interrupt */ - unsigned babble:1; - /** NAK Interrupt */ - unsigned nak:1; - /** NYET Interrupt */ - unsigned nyet:1; - - unsigned reserved15_31:17; - } b; +typedef union doepint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer complete */ + unsigned xfercompl: 1; + /** Endpoint disable */ + unsigned epdisabled: 1; + /** AHB Error */ + unsigned ahberr: 1; + /** Setup Phase Done (contorl EPs) */ + unsigned setup: 1; + /** OUT Token Received when Endpoint Disabled */ + unsigned outtknepdis: 1; + + unsigned stsphsercvd: 1; + /** Back-to-Back SETUP Packets Received */ + unsigned back2backsetup: 1; + + unsigned reserved7: 1; + /** OUT packet Error */ + unsigned outpkterr: 1; + /** BNA Interrupt */ + unsigned bna: 1; + + unsigned reserved10: 1; + /** Packet Drop Status */ + unsigned pktdrpsts: 1; + /** Babble Interrupt */ + unsigned babble: 1; + /** NAK Interrupt */ + unsigned nak: 1; + /** NYET Interrupt */ + unsigned nyet: 1; + + unsigned reserved15_31: 17; + } b; } doepint_data_t; /** @@ -1397,52 +1452,55 @@ typedef union doepint_data doepmsk_data_t; * - Read the register into the d32 member then set/clear the * bits using the bit elements. */ -typedef union daint_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** IN Endpoint bits */ - unsigned in:16; - /** OUT Endpoint bits */ - unsigned out:16; - } ep; - struct { - /** IN Endpoint bits */ - unsigned inep0:1; - unsigned inep1:1; - unsigned inep2:1; - unsigned inep3:1; - unsigned inep4:1; - unsigned inep5:1; - unsigned inep6:1; - unsigned inep7:1; - unsigned inep8:1; - unsigned inep9:1; - unsigned inep10:1; - unsigned inep11:1; - unsigned inep12:1; - unsigned inep13:1; - unsigned inep14:1; - unsigned inep15:1; - /** OUT Endpoint bits */ - unsigned outep0:1; - unsigned outep1:1; - unsigned outep2:1; - unsigned outep3:1; - unsigned outep4:1; - unsigned outep5:1; - unsigned outep6:1; - unsigned outep7:1; - unsigned outep8:1; - unsigned outep9:1; - unsigned outep10:1; - unsigned outep11:1; - unsigned outep12:1; - unsigned outep13:1; - unsigned outep14:1; - unsigned outep15:1; - } b; +typedef union daint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** IN Endpoint bits */ + unsigned in: 16; + /** OUT Endpoint bits */ + unsigned out: 16; + } ep; + struct + { + /** IN Endpoint bits */ + unsigned inep0: 1; + unsigned inep1: 1; + unsigned inep2: 1; + unsigned inep3: 1; + unsigned inep4: 1; + unsigned inep5: 1; + unsigned inep6: 1; + unsigned inep7: 1; + unsigned inep8: 1; + unsigned inep9: 1; + unsigned inep10: 1; + unsigned inep11: 1; + unsigned inep12: 1; + unsigned inep13: 1; + unsigned inep14: 1; + unsigned inep15: 1; + /** OUT Endpoint bits */ + unsigned outep0: 1; + unsigned outep1: 1; + unsigned outep2: 1; + unsigned outep3: 1; + unsigned outep4: 1; + unsigned outep5: 1; + unsigned outep6: 1; + unsigned outep7: 1; + unsigned outep8: 1; + unsigned outep9: 1; + unsigned outep10: 1; + unsigned outep11: 1; + unsigned outep12: 1; + unsigned outep13: 1; + unsigned outep14: 1; + unsigned outep15: 1; + } b; } daint_data_t; /** @@ -1451,20 +1509,22 @@ typedef union daint_data { * - Read the register into the d32 member. * - READ-ONLY Register */ -typedef union dtknq1_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** In Token Queue Write Pointer */ - unsigned intknwptr:5; - /** Reserved */ - unsigned reserved05_06:2; - /** write pointer has wrapped. */ - unsigned wrap_bit:1; - /** EP Numbers of IN Tokens 0 ... 4 */ - unsigned epnums0_5:24; - } b; +typedef union dtknq1_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** In Token Queue Write Pointer */ + unsigned intknwptr: 5; + /** Reserved */ + unsigned reserved05_06: 2; + /** write pointer has wrapped. */ + unsigned wrap_bit: 1; + /** EP Numbers of IN Tokens 0 ... 4 */ + unsigned epnums0_5: 24; + } b; } dtknq1_data_t; /** @@ -1472,31 +1532,33 @@ typedef union dtknq1_data { * - Read and write the register into the d32 member. * - READ-WRITABLE Register */ -typedef union dthrctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** non ISO Tx Thr. Enable */ - unsigned non_iso_thr_en:1; - /** ISO Tx Thr. Enable */ - unsigned iso_thr_en:1; - /** Tx Thr. Length */ - unsigned tx_thr_len:9; - /** AHB Threshold ratio */ - unsigned ahb_thr_ratio:2; - /** Reserved */ - unsigned reserved13_15:3; - /** Rx Thr. Enable */ - unsigned rx_thr_en:1; - /** Rx Thr. Length */ - unsigned rx_thr_len:9; - unsigned reserved26:1; - /** Arbiter Parking Enable*/ - unsigned arbprken:1; - /** Reserved */ - unsigned reserved28_31:4; - } b; +typedef union dthrctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** non ISO Tx Thr. Enable */ + unsigned non_iso_thr_en: 1; + /** ISO Tx Thr. Enable */ + unsigned iso_thr_en: 1; + /** Tx Thr. Length */ + unsigned tx_thr_len: 9; + /** AHB Threshold ratio */ + unsigned ahb_thr_ratio: 2; + /** Reserved */ + unsigned reserved13_15: 3; + /** Rx Thr. Enable */ + unsigned rx_thr_en: 1; + /** Rx Thr. Length */ + unsigned rx_thr_len: 9; + unsigned reserved26: 1; + /** Arbiter Parking Enable*/ + unsigned arbprken: 1; + /** Reserved */ + unsigned reserved28_31: 4; + } b; } dthrctl_data_t; /** @@ -1509,29 +1571,30 @@ typedef union dthrctl_data { * These registers are visible only in Device mode and must not be * accessed in Host mode, as the results are unknown. */ -typedef struct dwc_otg_dev_in_ep_regs { - /** Device IN Endpoint Control Register. Offset:900h + - * (ep_num * 20h) + 00h */ - volatile uint32_t diepctl; - /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ - uint32_t reserved04; - /** Device IN Endpoint Interrupt Register. Offset:900h + - * (ep_num * 20h) + 08h */ - volatile uint32_t diepint; - /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ - uint32_t reserved0C; - /** Device IN Endpoint Transfer Size - * Register. Offset:900h + (ep_num * 20h) + 10h */ - volatile uint32_t dieptsiz; - /** Device IN Endpoint DMA Address Register. Offset:900h + - * (ep_num * 20h) + 14h */ - volatile uint32_t diepdma; - /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + - * (ep_num * 20h) + 18h */ - volatile uint32_t dtxfsts; - /** Device IN Endpoint DMA Buffer Register. Offset:900h + - * (ep_num * 20h) + 1Ch */ - volatile uint32_t diepdmab; +typedef struct dwc_otg_dev_in_ep_regs +{ + /** Device IN Endpoint Control Register. Offset:900h + + * (ep_num * 20h) + 00h */ + volatile uint32_t diepctl; + /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ + uint32_t reserved04; + /** Device IN Endpoint Interrupt Register. Offset:900h + + * (ep_num * 20h) + 08h */ + volatile uint32_t diepint; + /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device IN Endpoint Transfer Size + * Register. Offset:900h + (ep_num * 20h) + 10h */ + volatile uint32_t dieptsiz; + /** Device IN Endpoint DMA Address Register. Offset:900h + + * (ep_num * 20h) + 14h */ + volatile uint32_t diepdma; + /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + + * (ep_num * 20h) + 18h */ + volatile uint32_t dtxfsts; + /** Device IN Endpoint DMA Buffer Register. Offset:900h + + * (ep_num * 20h) + 1Ch */ + volatile uint32_t diepdmab; } dwc_otg_dev_in_ep_regs_t; /** @@ -1544,29 +1607,30 @@ typedef struct dwc_otg_dev_in_ep_regs { * These registers are visible only in Device mode and must not be * accessed in Host mode, as the results are unknown. */ -typedef struct dwc_otg_dev_out_ep_regs { - /** Device OUT Endpoint Control Register. Offset:B00h + - * (ep_num * 20h) + 00h */ - volatile uint32_t doepctl; - /** Device OUT Endpoint Frame number Register. Offset: - * B00h + (ep_num * 20h) + 04h */ - volatile uint32_t doepfn; - /** Device OUT Endpoint Interrupt Register. Offset:B00h + - * (ep_num * 20h) + 08h */ - volatile uint32_t doepint; - /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ - uint32_t reserved0C; - /** Device OUT Endpoint Transfer Size Register. Offset: - * B00h + (ep_num * 20h) + 10h */ - volatile uint32_t doeptsiz; - /** Device OUT Endpoint DMA Address Register. Offset:B00h - * + (ep_num * 20h) + 14h */ - volatile uint32_t doepdma; - /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ - uint32_t unused; - /** Device OUT Endpoint DMA Buffer Register. Offset:B00h - * + (ep_num * 20h) + 1Ch */ - uint32_t doepdmab; +typedef struct dwc_otg_dev_out_ep_regs +{ + /** Device OUT Endpoint Control Register. Offset:B00h + + * (ep_num * 20h) + 00h */ + volatile uint32_t doepctl; + /** Device OUT Endpoint Frame number Register. Offset: + * B00h + (ep_num * 20h) + 04h */ + volatile uint32_t doepfn; + /** Device OUT Endpoint Interrupt Register. Offset:B00h + + * (ep_num * 20h) + 08h */ + volatile uint32_t doepint; + /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device OUT Endpoint Transfer Size Register. Offset: + * B00h + (ep_num * 20h) + 10h */ + volatile uint32_t doeptsiz; + /** Device OUT Endpoint DMA Address Register. Offset:B00h + * + (ep_num * 20h) + 14h */ + volatile uint32_t doepdma; + /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ + uint32_t unused; + /** Device OUT Endpoint DMA Buffer Register. Offset:B00h + * + (ep_num * 20h) + 1Ch */ + uint32_t doepdmab; } dwc_otg_dev_out_ep_regs_t; /** @@ -1574,98 +1638,100 @@ typedef struct dwc_otg_dev_out_ep_regs { * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ -typedef union depctl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Maximum Packet Size - * IN/OUT EPn - * IN/OUT EP0 - 2 bits - * 2'b00: 64 Bytes - * 2'b01: 32 - * 2'b10: 16 - * 2'b11: 8 */ - unsigned mps:11; +typedef union depctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ + unsigned mps: 11; #define DWC_DEP0CTL_MPS_64 0 #define DWC_DEP0CTL_MPS_32 1 #define DWC_DEP0CTL_MPS_16 2 #define DWC_DEP0CTL_MPS_8 3 - /** Next Endpoint - * IN EPn/IN EP0 - * OUT EPn/OUT EP0 - reserved */ - unsigned nextep:4; - - /** USB Active Endpoint */ - unsigned usbactep:1; - - /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) - * This field contains the PID of the packet going to - * be received or transmitted on this endpoint. The - * application should program the PID of the first - * packet going to be received or transmitted on this - * endpoint , after the endpoint is - * activated. Application use the SetD1PID and - * SetD0PID fields of this register to program either - * D0 or D1 PID. - * - * The encoding for this field is - * - 0: D0 - * - 1: D1 - */ - unsigned dpid:1; - - /** NAK Status */ - unsigned naksts:1; - - /** Endpoint Type - * 2'b00: Control - * 2'b01: Isochronous - * 2'b10: Bulk - * 2'b11: Interrupt */ - unsigned eptype:2; - - /** Snoop Mode - * OUT EPn/OUT EP0 - * IN EPn/IN EP0 - reserved */ - unsigned snp:1; - - /** Stall Handshake */ - unsigned stall:1; - - /** Tx Fifo Number - * IN EPn/IN EP0 - * OUT EPn/OUT EP0 - reserved */ - unsigned txfnum:4; - - /** Clear NAK */ - unsigned cnak:1; - /** Set NAK */ - unsigned snak:1; - /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) - * Writing to this field sets the Endpoint DPID (DPID) - * field in this register to DATA0. Set Even - * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) - * Writing to this field sets the Even/Odd - * (micro)frame (EO_FrNum) field to even (micro) - * frame. - */ - unsigned setd0pid:1; - /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) - * Writing to this field sets the Endpoint DPID (DPID) - * field in this register to DATA1 Set Odd - * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) - * Writing to this field sets the Even/Odd - * (micro)frame (EO_FrNum) field to odd (micro) frame. - */ - unsigned setd1pid:1; - - /** Endpoint Disable */ - unsigned epdis:1; - /** Endpoint Enable */ - unsigned epena:1; - } b; + /** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned nextep: 4; + + /** USB Active Endpoint */ + unsigned usbactep: 1; + + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ + unsigned dpid: 1; + + /** NAK Status */ + unsigned naksts: 1; + + /** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ + unsigned eptype: 2; + + /** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ + unsigned snp: 1; + + /** Stall Handshake */ + unsigned stall: 1; + + /** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned txfnum: 4; + + /** Clear NAK */ + unsigned cnak: 1; + /** Set NAK */ + unsigned snak: 1; + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ + unsigned setd0pid: 1; + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ + unsigned setd1pid: 1; + + /** Endpoint Disable */ + unsigned epdis: 1; + /** Endpoint Enable */ + unsigned epena: 1; + } b; } depctl_data_t; /** @@ -1673,19 +1739,21 @@ typedef union depctl_data { * Size Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ -typedef union deptsiz_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer size */ - unsigned xfersize:19; - /** Packet Count */ - unsigned pktcnt:10; - /** Multi Count - Periodic IN endpoints */ - unsigned mc:2; - unsigned reserved:1; - } b; +typedef union deptsiz_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer size */ + unsigned xfersize: 19; + /** Packet Count */ + unsigned pktcnt: 10; + /** Multi Count - Periodic IN endpoints */ + unsigned mc: 2; + unsigned reserved: 1; + } b; } deptsiz_data_t; /** @@ -1693,28 +1761,30 @@ typedef union deptsiz_data { * Size Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ -typedef union deptsiz0_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer size */ - unsigned xfersize:7; - /** Reserved */ - unsigned reserved7_18:12; - /** Packet Count */ - unsigned pktcnt:2; - /** Reserved */ - unsigned reserved21_28:8; - /**Setup Packet Count (DOEPTSIZ0 Only) */ - unsigned supcnt:2; - unsigned reserved31; - } b; +typedef union deptsiz0_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer size */ + unsigned xfersize: 7; + /** Reserved */ + unsigned reserved7_18: 12; + /** Packet Count */ + unsigned pktcnt: 2; + /** Reserved */ + unsigned reserved21_28: 8; + /**Setup Packet Count (DOEPTSIZ0 Only) */ + unsigned supcnt: 2; + unsigned reserved31: 1; + } b; } #if __GNUC__ /*GCC*/ __attribute__((__may_alias__)) deptsiz0_data_t; #else - deptsiz0_data_t; +deptsiz0_data_t; #endif ///////////////////////////////////////////////// // DMA Descriptor Specific Structures @@ -1740,73 +1810,77 @@ __attribute__((__may_alias__)) deptsiz0_data_t; * set/clear the bits using the bit, b_iso_out and * b_iso_in elements. */ -typedef union dev_dma_desc_sts { - /** raw register data */ - uint32_t d32; - /** quadlet bits */ - struct { - /** Received number of bytes */ - unsigned bytes:16; - - unsigned reserved16_22:7; - /** Multiple Transfer - only for OUT EPs */ - unsigned mtrf:1; - /** Setup Packet received - only for OUT EPs */ - unsigned sr:1; - /** Interrupt On Complete */ - unsigned ioc:1; - /** Short Packet */ - unsigned sp:1; - /** Last */ - unsigned l:1; - /** Receive Status */ - unsigned sts:2; - /** Buffer Status */ - unsigned bs:2; - } b; +typedef union dev_dma_desc_sts +{ + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + struct + { + /** Received number of bytes */ + unsigned bytes: 16; + + unsigned reserved16_22: 7; + /** Multiple Transfer - only for OUT EPs */ + unsigned mtrf: 1; + /** Setup Packet received - only for OUT EPs */ + unsigned sr: 1; + /** Interrupt On Complete */ + unsigned ioc: 1; + /** Short Packet */ + unsigned sp: 1; + /** Last */ + unsigned l: 1; + /** Receive Status */ + unsigned sts: 2; + /** Buffer Status */ + unsigned bs: 2; + } b; //#ifdef DWC_EN_ISOC - /** iso out quadlet bits */ - struct { - /** Received number of bytes */ - unsigned rxbytes:11; - - unsigned reserved11:1; - /** Frame Number */ - unsigned framenum:11; - /** Received ISO Data PID */ - unsigned pid:2; - /** Interrupt On Complete */ - unsigned ioc:1; - /** Short Packet */ - unsigned sp:1; - /** Last */ - unsigned l:1; - /** Receive Status */ - unsigned rxsts:2; - /** Buffer Status */ - unsigned bs:2; - } b_iso_out; - - /** iso in quadlet bits */ - struct { - /** Transmited number of bytes */ - unsigned txbytes:12; - /** Frame Number */ - unsigned framenum:11; - /** Transmited ISO Data PID */ - unsigned pid:2; - /** Interrupt On Complete */ - unsigned ioc:1; - /** Short Packet */ - unsigned sp:1; - /** Last */ - unsigned l:1; - /** Transmit Status */ - unsigned txsts:2; - /** Buffer Status */ - unsigned bs:2; - } b_iso_in; + /** iso out quadlet bits */ + struct + { + /** Received number of bytes */ + unsigned rxbytes: 11; + + unsigned reserved11: 1; + /** Frame Number */ + unsigned framenum: 11; + /** Received ISO Data PID */ + unsigned pid: 2; + /** Interrupt On Complete */ + unsigned ioc: 1; + /** Short Packet */ + unsigned sp: 1; + /** Last */ + unsigned l: 1; + /** Receive Status */ + unsigned rxsts: 2; + /** Buffer Status */ + unsigned bs: 2; + } b_iso_out; + + /** iso in quadlet bits */ + struct + { + /** Transmited number of bytes */ + unsigned txbytes: 12; + /** Frame Number */ + unsigned framenum: 11; + /** Transmited ISO Data PID */ + unsigned pid: 2; + /** Interrupt On Complete */ + unsigned ioc: 1; + /** Short Packet */ + unsigned sp: 1; + /** Last */ + unsigned l: 1; + /** Transmit Status */ + unsigned txsts: 2; + /** Buffer Status */ + unsigned bs: 2; + } b_iso_in; //#endif /* DWC_EN_ISOC */ } dev_dma_desc_sts_t; @@ -1816,11 +1890,12 @@ typedef union dev_dma_desc_sts { * DMA Descriptor structure contains two quadlets: * Status quadlet and Data buffer pointer. */ -typedef struct dwc_otg_dev_dma_desc { - /** DMA Descriptor status quadlet */ - dev_dma_desc_sts_t status; - /** DMA Descriptor data buffer pointer */ - uint32_t buf; +typedef struct dwc_otg_dev_dma_desc +{ + /** DMA Descriptor status quadlet */ + dev_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ + uint32_t buf; } dwc_otg_dev_dma_desc_t; /** @@ -1828,68 +1903,69 @@ typedef struct dwc_otg_dev_dma_desc { * the DWC_otg controller acting in device mode. It represents the * programming view of the device-specific aspects of the controller. */ -typedef struct dwc_otg_dev_if { - /** Pointer to device Global registers. - * Device Global Registers starting at offset 800h - */ - dwc_otg_device_global_regs_t *dev_global_regs; +typedef struct dwc_otg_dev_if +{ + /** Pointer to device Global registers. + * Device Global Registers starting at offset 800h + */ + dwc_otg_device_global_regs_t *dev_global_regs; #define DWC_DEV_GLOBAL_REG_OFFSET 0x800 - /** - * Device Logical IN Endpoint-Specific Registers 900h-AFCh - */ - dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; + /** + * Device Logical IN Endpoint-Specific Registers 900h-AFCh + */ + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; #define DWC_DEV_IN_EP_REG_OFFSET 0x900 #define DWC_EP_REG_OFFSET 0x20 - /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ - dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 - /* Device configuration information */ - uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ - uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ - uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ + /* Device configuration information */ + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ - /** Size of periodic FIFOs (Bytes) */ - uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; + /** Size of periodic FIFOs (Bytes) */ + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; - /** Size of Tx FIFOs (Bytes) */ - uint16_t tx_fifo_size[MAX_TX_FIFOS]; + /** Size of Tx FIFOs (Bytes) */ + uint16_t tx_fifo_size[MAX_TX_FIFOS]; - /** Thresholding enable flags and length varaiables **/ - uint16_t rx_thr_en; - uint16_t iso_tx_thr_en; - uint16_t non_iso_tx_thr_en; + /** Thresholding enable flags and length varaiables **/ + uint16_t rx_thr_en; + uint16_t iso_tx_thr_en; + uint16_t non_iso_tx_thr_en; - uint16_t rx_thr_length; - uint16_t tx_thr_length; + uint16_t rx_thr_length; + uint16_t tx_thr_length; - /** - * Pointers to the DMA Descriptors for EP0 Control - * transfers (virtual and physical) - */ + /** + * Pointers to the DMA Descriptors for EP0 Control + * transfers (virtual and physical) + */ - /** 2 descriptors for SETUP packets */ - dwc_dma_t dma_setup_desc_addr[2]; - dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; + /** 2 descriptors for SETUP packets */ + dwc_dma_t dma_setup_desc_addr[2]; + dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; - /** Pointer to Descriptor with latest SETUP packet */ - dwc_otg_dev_dma_desc_t *psetup; + /** Pointer to Descriptor with latest SETUP packet */ + dwc_otg_dev_dma_desc_t *psetup; - /** Index of current SETUP handler descriptor */ - uint32_t setup_desc_index; + /** Index of current SETUP handler descriptor */ + uint32_t setup_desc_index; - /** Descriptor for Data In or Status In phases */ - dwc_dma_t dma_in_desc_addr; - dwc_otg_dev_dma_desc_t *in_desc_addr; + /** Descriptor for Data In or Status In phases */ + dwc_dma_t dma_in_desc_addr; + dwc_otg_dev_dma_desc_t *in_desc_addr; - /** Descriptor for Data Out or Status Out phases */ - dwc_dma_t dma_out_desc_addr; - dwc_otg_dev_dma_desc_t *out_desc_addr; + /** Descriptor for Data Out or Status Out phases */ + dwc_dma_t dma_out_desc_addr; + dwc_otg_dev_dma_desc_t *out_desc_addr; - /** Setup Packet Detected - if set clear NAK when queueing */ - uint32_t spd; + /** Setup Packet Detected - if set clear NAK when queueing */ + uint32_t spd; } dwc_otg_dev_if_t; @@ -1901,23 +1977,24 @@ typedef struct dwc_otg_dev_if { * field offsets for the Host Mode Global Registers. Host Global * Registers offsets 400h-7FFh. */ -typedef struct dwc_otg_host_global_regs { - /** Host Configuration Register. Offset: 400h */ - volatile uint32_t hcfg; - /** Host Frame Interval Register. Offset: 404h */ - volatile uint32_t hfir; - /** Host Frame Number / Frame Remaining Register. Offset: 408h */ - volatile uint32_t hfnum; - /** Reserved. Offset: 40Ch */ - uint32_t reserved40C; - /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ - volatile uint32_t hptxsts; - /** Host All Channels Interrupt Register. Offset: 414h */ - volatile uint32_t haint; - /** Host All Channels Interrupt Mask Register. Offset: 418h */ - volatile uint32_t haintmsk; - /** Host Frame List Base Address Register . Offset: 41Ch */ - volatile uint32_t hflbaddr; +typedef struct dwc_otg_host_global_regs +{ + /** Host Configuration Register. Offset: 400h */ + volatile uint32_t hcfg; + /** Host Frame Interval Register. Offset: 404h */ + volatile uint32_t hfir; + /** Host Frame Number / Frame Remaining Register. Offset: 408h */ + volatile uint32_t hfnum; + /** Reserved. Offset: 40Ch */ + uint32_t reserved40C; + /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ + volatile uint32_t hptxsts; + /** Host All Channels Interrupt Register. Offset: 414h */ + volatile uint32_t haint; + /** Host All Channels Interrupt Mask Register. Offset: 418h */ + volatile uint32_t haintmsk; + /** Host Frame List Base Address Register . Offset: 41Ch */ + volatile uint32_t hflbaddr; } dwc_otg_host_global_regs_t; /** @@ -1925,91 +2002,99 @@ typedef struct dwc_otg_host_global_regs { * Read the register into the d32 member then set/clear the bits using * the bit elements. Write the d32 member to the hcfg register. */ -typedef union hcfg_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - /** FS/LS Phy Clock Select */ - unsigned fslspclksel:2; +typedef union hcfg_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** FS/LS Phy Clock Select */ + unsigned fslspclksel: 2; #define DWC_HCFG_30_60_MHZ 0 #define DWC_HCFG_48_MHZ 1 #define DWC_HCFG_6_MHZ 2 - /** FS/LS Only Support */ - unsigned fslssupp:1; - unsigned reserved3_6:4; - /** Enable 32-KHz Suspend Mode */ - unsigned ena32khzs:1; - /** Resume Validation Periiod */ - unsigned resvalid:8; - unsigned reserved16_22:7; - /** Enable Scatter/gather DMA in Host mode */ - unsigned descdma:1; - /** Frame List Entries */ - unsigned frlisten:2; - /** Enable Periodic Scheduling */ - unsigned perschedena:1; - unsigned reserved27_30:4; - unsigned modechtimen:1; - } b; + /** FS/LS Only Support */ + unsigned fslssupp: 1; + unsigned reserved3_6: 4; + /** Enable 32-KHz Suspend Mode */ + unsigned ena32khzs: 1; + /** Resume Validation Periiod */ + unsigned resvalid: 8; + unsigned reserved16_22: 7; + /** Enable Scatter/gather DMA in Host mode */ + unsigned descdma: 1; + /** Frame List Entries */ + unsigned frlisten: 2; + /** Enable Periodic Scheduling */ + unsigned perschedena: 1; + unsigned reserved27_30: 4; + unsigned modechtimen: 1; + } b; } hcfg_data_t; /** * This union represents the bit fields in the Host Frame Remaing/Number - * Register. + * Register. */ -typedef union hfir_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - unsigned frint:16; - unsigned hfirrldctrl:1; - unsigned reserved:15; - } b; +typedef union hfir_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned frint: 16; + unsigned hfirrldctrl: 1; + unsigned reserved: 15; + } b; } hfir_data_t; /** * This union represents the bit fields in the Host Frame Remaing/Number - * Register. + * Register. */ -typedef union hfnum_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - unsigned frnum:16; +typedef union hfnum_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned frnum: 16; #define DWC_HFNUM_MAX_FRNUM 0x3FFF - unsigned frrem:16; - } b; + unsigned frrem: 16; + } b; } hfnum_data_t; -typedef union hptxsts_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - unsigned ptxfspcavail:16; - unsigned ptxqspcavail:8; - /** Top of the Periodic Transmit Request Queue - * - bit 24 - Terminate (last entry for the selected channel) - * - bits 26:25 - Token Type - * - 2'b00 - Zero length - * - 2'b01 - Ping - * - 2'b10 - Disable - * - bits 30:27 - Channel Number - * - bit 31 - Odd/even microframe - */ - unsigned ptxqtop_terminate:1; - unsigned ptxqtop_token:2; - unsigned ptxqtop_chnum:4; - unsigned ptxqtop_odd:1; - } b; +typedef union hptxsts_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned ptxfspcavail: 16; + unsigned ptxqspcavail: 8; + /** Top of the Periodic Transmit Request Queue + * - bit 24 - Terminate (last entry for the selected channel) + * - bits 26:25 - Token Type + * - 2'b00 - Zero length + * - 2'b01 - Ping + * - 2'b10 - Disable + * - bits 30:27 - Channel Number + * - bit 31 - Odd/even microframe + */ + unsigned ptxqtop_terminate: 1; + unsigned ptxqtop_token: 2; + unsigned ptxqtop_chnum: 4; + unsigned ptxqtop_odd: 1; + } b; } hptxsts_data_t; /** @@ -2018,119 +2103,128 @@ typedef union hptxsts_data { * bits using the bit elements. Write the d32 member to the * hprt0 register. */ -typedef union hprt0_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned prtconnsts:1; - unsigned prtconndet:1; - unsigned prtena:1; - unsigned prtenchng:1; - unsigned prtovrcurract:1; - unsigned prtovrcurrchng:1; - unsigned prtres:1; - unsigned prtsusp:1; - unsigned prtrst:1; - unsigned reserved9:1; - unsigned prtlnsts:2; - unsigned prtpwr:1; - unsigned prttstctl:4; - unsigned prtspd:2; +typedef union hprt0_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned prtconnsts: 1; + unsigned prtconndet: 1; + unsigned prtena: 1; + unsigned prtenchng: 1; + unsigned prtovrcurract: 1; + unsigned prtovrcurrchng: 1; + unsigned prtres: 1; + unsigned prtsusp: 1; + unsigned prtrst: 1; + unsigned reserved9: 1; + unsigned prtlnsts: 2; + unsigned prtpwr: 1; + unsigned prttstctl: 4; + unsigned prtspd: 2; #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2 - unsigned reserved19_31:13; - } b; + unsigned reserved19_31: 13; + } b; } hprt0_data_t; /** * This union represents the bit fields in the Host All Interrupt - * Register. + * Register. */ -typedef union haint_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned ch0:1; - unsigned ch1:1; - unsigned ch2:1; - unsigned ch3:1; - unsigned ch4:1; - unsigned ch5:1; - unsigned ch6:1; - unsigned ch7:1; - unsigned ch8:1; - unsigned ch9:1; - unsigned ch10:1; - unsigned ch11:1; - unsigned ch12:1; - unsigned ch13:1; - unsigned ch14:1; - unsigned ch15:1; - unsigned reserved:16; - } b; - - struct { - unsigned chint:16; - unsigned reserved:16; - } b2; +typedef union haint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned ch0: 1; + unsigned ch1: 1; + unsigned ch2: 1; + unsigned ch3: 1; + unsigned ch4: 1; + unsigned ch5: 1; + unsigned ch6: 1; + unsigned ch7: 1; + unsigned ch8: 1; + unsigned ch9: 1; + unsigned ch10: 1; + unsigned ch11: 1; + unsigned ch12: 1; + unsigned ch13: 1; + unsigned ch14: 1; + unsigned ch15: 1; + unsigned reserved: 16; + } b; + + struct + { + unsigned chint: 16; + unsigned reserved: 16; + } b2; } haint_data_t; /** * This union represents the bit fields in the Host All Interrupt - * Register. + * Register. */ -typedef union haintmsk_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned ch0:1; - unsigned ch1:1; - unsigned ch2:1; - unsigned ch3:1; - unsigned ch4:1; - unsigned ch5:1; - unsigned ch6:1; - unsigned ch7:1; - unsigned ch8:1; - unsigned ch9:1; - unsigned ch10:1; - unsigned ch11:1; - unsigned ch12:1; - unsigned ch13:1; - unsigned ch14:1; - unsigned ch15:1; - unsigned reserved:16; - } b; - - struct { - unsigned chint:16; - unsigned reserved:16; - } b2; +typedef union haintmsk_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned ch0: 1; + unsigned ch1: 1; + unsigned ch2: 1; + unsigned ch3: 1; + unsigned ch4: 1; + unsigned ch5: 1; + unsigned ch6: 1; + unsigned ch7: 1; + unsigned ch8: 1; + unsigned ch9: 1; + unsigned ch10: 1; + unsigned ch11: 1; + unsigned ch12: 1; + unsigned ch13: 1; + unsigned ch14: 1; + unsigned ch15: 1; + unsigned reserved: 16; + } b; + + struct + { + unsigned chint: 16; + unsigned reserved: 16; + } b2; } haintmsk_data_t; /** * Host Channel Specific Registers. 500h-5FCh */ -typedef struct dwc_otg_hc_regs { - /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ - volatile uint32_t hcchar; - /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ - volatile uint32_t hcsplt; - /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ - volatile uint32_t hcint; - /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ - volatile uint32_t hcintmsk; - /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ - volatile uint32_t hctsiz; - /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ - volatile uint32_t hcdma; - volatile uint32_t reserved; - /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ - volatile uint32_t hcdmab; +typedef struct dwc_otg_hc_regs +{ + /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ + volatile uint32_t hcchar; + /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ + volatile uint32_t hcsplt; + /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ + volatile uint32_t hcint; + /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ + volatile uint32_t hcintmsk; + /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ + volatile uint32_t hctsiz; + /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ + volatile uint32_t hcdma; + volatile uint32_t reserved; + /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ + volatile uint32_t hcdmab; } dwc_otg_hc_regs_t; /** @@ -2139,119 +2233,125 @@ typedef struct dwc_otg_hc_regs { * bits using the bit elements. Write the d32 member to the * hcchar register. */ -typedef union hcchar_data { - /** raw register data */ - uint32_t d32; +typedef union hcchar_data +{ + /** raw register data */ + uint32_t d32; - /** register bits */ - struct { - /** Maximum packet size in bytes */ - unsigned mps:11; + /** register bits */ + struct + { + /** Maximum packet size in bytes */ + unsigned mps: 11; - /** Endpoint number */ - unsigned epnum:4; + /** Endpoint number */ + unsigned epnum: 4; - /** 0: OUT, 1: IN */ - unsigned epdir:1; + /** 0: OUT, 1: IN */ + unsigned epdir: 1; - unsigned reserved:1; + unsigned reserved: 1; - /** 0: Full/high speed device, 1: Low speed device */ - unsigned lspddev:1; + /** 0: Full/high speed device, 1: Low speed device */ + unsigned lspddev: 1; - /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ - unsigned eptype:2; + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ + unsigned eptype: 2; - /** Packets per frame for periodic transfers. 0 is reserved. */ - unsigned multicnt:2; + /** Packets per frame for periodic transfers. 0 is reserved. */ + unsigned multicnt: 2; - /** Device address */ - unsigned devaddr:7; + /** Device address */ + unsigned devaddr: 7; - /** - * Frame to transmit periodic transaction. - * 0: even, 1: odd - */ - unsigned oddfrm:1; + /** + * Frame to transmit periodic transaction. + * 0: even, 1: odd + */ + unsigned oddfrm: 1; - /** Channel disable */ - unsigned chdis:1; + /** Channel disable */ + unsigned chdis: 1; - /** Channel enable */ - unsigned chen:1; - } b; + /** Channel enable */ + unsigned chen: 1; + } b; } hcchar_data_t; -typedef union hcsplt_data { - /** raw register data */ - uint32_t d32; +typedef union hcsplt_data +{ + /** raw register data */ + uint32_t d32; - /** register bits */ - struct { - /** Port Address */ - unsigned prtaddr:7; + /** register bits */ + struct + { + /** Port Address */ + unsigned prtaddr: 7; - /** Hub Address */ - unsigned hubaddr:7; + /** Hub Address */ + unsigned hubaddr: 7; - /** Transaction Position */ - unsigned xactpos:2; + /** Transaction Position */ + unsigned xactpos: 2; #define DWC_HCSPLIT_XACTPOS_MID 0 #define DWC_HCSPLIT_XACTPOS_END 1 #define DWC_HCSPLIT_XACTPOS_BEGIN 2 #define DWC_HCSPLIT_XACTPOS_ALL 3 - /** Do Complete Split */ - unsigned compsplt:1; + /** Do Complete Split */ + unsigned compsplt: 1; - /** Reserved */ - unsigned reserved:14; + /** Reserved */ + unsigned reserved: 14; - /** Split Enble */ - unsigned spltena:1; - } b; + /** Split Enble */ + unsigned spltena: 1; + } b; } hcsplt_data_t; /** * This union represents the bit fields in the Host All Interrupt - * Register. + * Register. */ -typedef union hcint_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** Transfer Complete */ - unsigned xfercomp:1; - /** Channel Halted */ - unsigned chhltd:1; - /** AHB Error */ - unsigned ahberr:1; - /** STALL Response Received */ - unsigned stall:1; - /** NAK Response Received */ - unsigned nak:1; - /** ACK Response Received */ - unsigned ack:1; - /** NYET Response Received */ - unsigned nyet:1; - /** Transaction Err */ - unsigned xacterr:1; - /** Babble Error */ - unsigned bblerr:1; - /** Frame Overrun */ - unsigned frmovrun:1; - /** Data Toggle Error */ - unsigned datatglerr:1; - /** Buffer Not Available (only for DDMA mode) */ - unsigned bna:1; - /** Exessive transaction error (only for DDMA mode) */ - unsigned xcs_xact:1; - /** Frame List Rollover interrupt */ - unsigned frm_list_roll:1; - /** Reserved */ - unsigned reserved14_31:18; - } b; +typedef union hcint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Transfer Complete */ + unsigned xfercomp: 1; + /** Channel Halted */ + unsigned chhltd: 1; + /** AHB Error */ + unsigned ahberr: 1; + /** STALL Response Received */ + unsigned stall: 1; + /** NAK Response Received */ + unsigned nak: 1; + /** ACK Response Received */ + unsigned ack: 1; + /** NYET Response Received */ + unsigned nyet: 1; + /** Transaction Err */ + unsigned xacterr: 1; + /** Babble Error */ + unsigned bblerr: 1; + /** Frame Overrun */ + unsigned frmovrun: 1; + /** Data Toggle Error */ + unsigned datatglerr: 1; + /** Buffer Not Available (only for DDMA mode) */ + unsigned bna: 1; + /** Exessive transaction error (only for DDMA mode) */ + unsigned xcs_xact: 1; + /** Frame List Rollover interrupt */ + unsigned frm_list_roll: 1; + /** Reserved */ + unsigned reserved14_31: 18; + } b; } hcint_data_t; /** @@ -2260,28 +2360,30 @@ typedef union hcint_data { * bits using the bit elements. Write the d32 member to the * hcintmsk register. */ -typedef union hcintmsk_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - unsigned xfercompl:1; - unsigned chhltd:1; - unsigned ahberr:1; - unsigned stall:1; - unsigned nak:1; - unsigned ack:1; - unsigned nyet:1; - unsigned xacterr:1; - unsigned bblerr:1; - unsigned frmovrun:1; - unsigned datatglerr:1; - unsigned bna:1; - unsigned xcs_xact:1; - unsigned frm_list_roll:1; - unsigned reserved14_31:18; - } b; +typedef union hcintmsk_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + unsigned xfercompl: 1; + unsigned chhltd: 1; + unsigned ahberr: 1; + unsigned stall: 1; + unsigned nak: 1; + unsigned ack: 1; + unsigned nyet: 1; + unsigned xacterr: 1; + unsigned bblerr: 1; + unsigned frmovrun: 1; + unsigned datatglerr: 1; + unsigned bna: 1; + unsigned xcs_xact: 1; + unsigned frm_list_roll: 1; + unsigned reserved14_31: 18; + } b; } hcintmsk_data_t; /** @@ -2291,80 +2393,85 @@ typedef union hcintmsk_data { * hcchar register. */ -typedef union hctsiz_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - /** Total transfer size in bytes */ - unsigned xfersize:19; - - /** Data packets to transfer */ - unsigned pktcnt:10; - - /** - * Packet ID for next data packet - * 0: DATA0 - * 1: DATA2 - * 2: DATA1 - * 3: MDATA (non-Control), SETUP (Control) - */ - unsigned pid:2; +typedef union hctsiz_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** Total transfer size in bytes */ + unsigned xfersize: 19; + + /** Data packets to transfer */ + unsigned pktcnt: 10; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control), SETUP (Control) + */ + unsigned pid: 2; #define DWC_HCTSIZ_DATA0 0 #define DWC_HCTSIZ_DATA1 2 #define DWC_HCTSIZ_DATA2 1 #define DWC_HCTSIZ_MDATA 3 #define DWC_HCTSIZ_SETUP 3 - /** Do PING protocol when 1 */ - unsigned dopng:1; - } b; - - /** register bits */ - struct { - /** Scheduling information */ - unsigned schinfo:8; - - /** Number of transfer descriptors. - * Max value: - * 64 in general, - * 256 only for HS isochronous endpoint. - */ - unsigned ntd:8; - - /** Data packets to transfer */ - unsigned reserved16_28:13; - - /** - * Packet ID for next data packet - * 0: DATA0 - * 1: DATA2 - * 2: DATA1 - * 3: MDATA (non-Control) - */ - unsigned pid:2; - - /** Do PING protocol when 1 */ - unsigned dopng:1; - } b_ddma; + /** Do PING protocol when 1 */ + unsigned dopng: 1; + } b; + + /** register bits */ + struct + { + /** Scheduling information */ + unsigned schinfo: 8; + + /** Number of transfer descriptors. + * Max value: + * 64 in general, + * 256 only for HS isochronous endpoint. + */ + unsigned ntd: 8; + + /** Data packets to transfer */ + unsigned reserved16_28: 13; + + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control) + */ + unsigned pid: 2; + + /** Do PING protocol when 1 */ + unsigned dopng: 1; + } b_ddma; } hctsiz_data_t; /** * This union represents the bit fields in the Host DMA Address * Register used in Descriptor DMA mode. */ -typedef union hcdma_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved0_2:3; - /** Current Transfer Descriptor. Not used for ISOC */ - unsigned ctd:8; - /** Start Address of Descriptor List */ - unsigned dma_addr:21; - } b; +typedef union hcdma_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned reserved0_2: 3; + /** Current Transfer Descriptor. Not used for ISOC */ + unsigned ctd: 8; + /** Start Address of Descriptor List */ + unsigned dma_addr: 21; + } b; } hcdma_data_t; /** @@ -2372,53 +2479,56 @@ typedef union hcdma_data { * status quadlet for host mode. Read the quadlet into the d32 member then * set/clear the bits using the bit elements. */ -typedef union host_dma_desc_sts { - /** raw register data */ - uint32_t d32; - /** quadlet bits */ - - /* for non-isochronous */ - struct { - /** Number of bytes */ - unsigned n_bytes:17; - /** QTD offset to jump when Short Packet received - only for IN EPs */ - unsigned qtd_offset:6; - /** - * Set to request the core to jump to alternate QTD if - * Short Packet received - only for IN EPs - */ - unsigned a_qtd:1; - /** - * Setup Packet bit. When set indicates that buffer contains - * setup packet. - */ - unsigned sup:1; - /** Interrupt On Complete */ - unsigned ioc:1; - /** End of List */ - unsigned eol:1; - unsigned reserved27:1; - /** Rx/Tx Status */ - unsigned sts:2; +typedef union host_dma_desc_sts +{ + /** raw register data */ + uint32_t d32; + /** quadlet bits */ + + /* for non-isochronous */ + struct + { + /** Number of bytes */ + unsigned n_bytes: 17; + /** QTD offset to jump when Short Packet received - only for IN EPs */ + unsigned qtd_offset: 6; + /** + * Set to request the core to jump to alternate QTD if + * Short Packet received - only for IN EPs + */ + unsigned a_qtd: 1; + /** + * Setup Packet bit. When set indicates that buffer contains + * setup packet. + */ + unsigned sup: 1; + /** Interrupt On Complete */ + unsigned ioc: 1; + /** End of List */ + unsigned eol: 1; + unsigned reserved27: 1; + /** Rx/Tx Status */ + unsigned sts: 2; #define DMA_DESC_STS_PKTERR 1 - unsigned reserved30:1; - /** Active Bit */ - unsigned a:1; - } b; - /* for isochronous */ - struct { - /** Number of bytes */ - unsigned n_bytes:12; - unsigned reserved12_24:13; - /** Interrupt On Complete */ - unsigned ioc:1; - unsigned reserved26_27:2; - /** Rx/Tx Status */ - unsigned sts:2; - unsigned reserved30:1; - /** Active Bit */ - unsigned a:1; - } b_isoc; + unsigned reserved30: 1; + /** Active Bit */ + unsigned a: 1; + } b; + /* for isochronous */ + struct + { + /** Number of bytes */ + unsigned n_bytes: 12; + unsigned reserved12_24: 13; + /** Interrupt On Complete */ + unsigned ioc: 1; + unsigned reserved26_27: 2; + /** Rx/Tx Status */ + unsigned sts: 2; + unsigned reserved30: 1; + /** Active Bit */ + unsigned a: 1; + } b_isoc; } host_dma_desc_sts_t; #define MAX_DMA_DESC_SIZE 131071 @@ -2431,11 +2541,12 @@ typedef union host_dma_desc_sts { * DMA Descriptor structure contains two quadlets: * Status quadlet and Data buffer pointer. */ -typedef struct dwc_otg_host_dma_desc { - /** DMA Descriptor status quadlet */ - host_dma_desc_sts_t status; - /** DMA Descriptor data buffer pointer */ - uint32_t buf; +typedef struct dwc_otg_host_dma_desc +{ + /** DMA Descriptor status quadlet */ + host_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ + uint32_t buf; } dwc_otg_host_dma_desc_t; /** OTG Host Interface Structure. @@ -2445,27 +2556,28 @@ typedef struct dwc_otg_host_dma_desc { * represents the programming view of the host-specific aspects of the * controller. */ -typedef struct dwc_otg_host_if { - /** Host Global Registers starting at offset 400h.*/ - dwc_otg_host_global_regs_t *host_global_regs; +typedef struct dwc_otg_host_if +{ + /** Host Global Registers starting at offset 400h.*/ + dwc_otg_host_global_regs_t *host_global_regs; #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 - /** Host Port 0 Control and Status Register */ - volatile uint32_t *hprt0; + /** Host Port 0 Control and Status Register */ + volatile uint32_t *hprt0; #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 - /** Host Channel Specific Registers at offsets 500h-5FCh. */ - dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; + /** Host Channel Specific Registers at offsets 500h-5FCh. */ + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 #define DWC_OTG_CHAN_REGS_OFFSET 0x20 - /* Host configuration information */ - /** Number of Host Channels (range: 1-16) */ - uint8_t num_host_channels; - /** Periodic EPs supported (0: no, 1: yes) */ - uint8_t perio_eps_supported; - /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ - uint16_t perio_tx_fifo_size; + /* Host configuration information */ + /** Number of Host Channels (range: 1-16) */ + uint8_t num_host_channels; + /** Periodic EPs supported (0: no, 1: yes) */ + uint8_t perio_eps_supported; + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ + uint16_t perio_tx_fifo_size; } dwc_otg_host_if_t; @@ -2474,41 +2586,43 @@ typedef struct dwc_otg_host_if { * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. */ -typedef union pcgcctl_data { - /** raw register data */ - uint32_t d32; - - /** register bits */ - struct { - /** Stop Pclk */ - unsigned stoppclk:1; - /** Gate Hclk */ - unsigned gatehclk:1; - /** Power Clamp */ - unsigned pwrclmp:1; - /** Reset Power Down Modules */ - unsigned rstpdwnmodule:1; - /** Reserved */ - unsigned reserved:1; - /** Enable Sleep Clock Gating (Enbl_L1Gating) */ - unsigned enbl_sleep_gating:1; - /** PHY In Sleep (PhySleep) */ - unsigned phy_in_sleep:1; - /** Deep Sleep*/ - unsigned deep_sleep:1; - unsigned resetaftsusp:1; - unsigned restoremode:1; - unsigned reserved10_12:3; - unsigned ess_reg_restored:1; - unsigned prt_clk_sel:2; - unsigned port_power:1; - unsigned max_xcvrselect:2; - unsigned max_termsel:1; - unsigned mac_dev_addr:7; - unsigned p2hd_dev_enum_spd:2; - unsigned p2hd_prt_spd:2; - unsigned if_dev_mode:1; - } b; +typedef union pcgcctl_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** Stop Pclk */ + unsigned stoppclk: 1; + /** Gate Hclk */ + unsigned gatehclk: 1; + /** Power Clamp */ + unsigned pwrclmp: 1; + /** Reset Power Down Modules */ + unsigned rstpdwnmodule: 1; + /** Reserved */ + unsigned reserved: 1; + /** Enable Sleep Clock Gating (Enbl_L1Gating) */ + unsigned enbl_sleep_gating: 1; + /** PHY In Sleep (PhySleep) */ + unsigned phy_in_sleep: 1; + /** Deep Sleep*/ + unsigned deep_sleep: 1; + unsigned resetaftsusp: 1; + unsigned restoremode: 1; + unsigned reserved10_12: 3; + unsigned ess_reg_restored: 1; + unsigned prt_clk_sel: 2; + unsigned port_power: 1; + unsigned max_xcvrselect: 2; + unsigned max_termsel: 1; + unsigned mac_dev_addr: 7; + unsigned p2hd_dev_enum_spd: 2; + unsigned p2hd_prt_spd: 2; + unsigned if_dev_mode: 1; + } b; } pcgcctl_data_t; /** @@ -2516,16 +2630,18 @@ typedef union pcgcctl_data { * Read the register into the d32 member then set/clear the * bits using the bit elements. */ -typedef union gdfifocfg_data { - /* raw register data */ - uint32_t d32; - /** register bits */ - struct { - /** OTG Data FIFO depth */ - unsigned gdfifocfg:16; - /** Start address of EP info controller */ - unsigned epinfobase:16; - } b; +typedef union gdfifocfg_data +{ + /* raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** OTG Data FIFO depth */ + unsigned gdfifocfg: 16; + /** Start address of EP info controller */ + unsigned epinfobase: 16; + } b; } gdfifocfg_data_t; /** @@ -2533,63 +2649,65 @@ typedef union gdfifocfg_data { * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. */ -typedef union gpwrdn_data { - /* raw register data */ - uint32_t d32; - - /** register bits */ - struct { - /** PMU Interrupt Select */ - unsigned pmuintsel:1; - /** PMU Active */ - unsigned pmuactv:1; - /** Restore */ - unsigned restore:1; - /** Power Down Clamp */ - unsigned pwrdnclmp:1; - /** Power Down Reset */ - unsigned pwrdnrstn:1; - /** Power Down Switch */ - unsigned pwrdnswtch:1; - /** Disable VBUS */ - unsigned dis_vbus:1; - /** Line State Change */ - unsigned lnstschng:1; - /** Line state change mask */ - unsigned lnstchng_msk:1; - /** Reset Detected */ - unsigned rst_det:1; - /** Reset Detect mask */ - unsigned rst_det_msk:1; - /** Disconnect Detected */ - unsigned disconn_det:1; - /** Disconnect Detect mask */ - unsigned disconn_det_msk:1; - /** Connect Detected*/ - unsigned connect_det:1; - /** Connect Detected Mask*/ - unsigned connect_det_msk:1; - /** SRP Detected */ - unsigned srp_det:1; - /** SRP Detect mask */ - unsigned srp_det_msk:1; - /** Status Change Interrupt */ - unsigned sts_chngint:1; - /** Status Change Interrupt Mask */ - unsigned sts_chngint_msk:1; - /** Line State */ - unsigned linestate:2; - /** Indicates current mode(status of IDDIG signal) */ - unsigned idsts:1; - /** B Session Valid signal status*/ - unsigned bsessvld:1; - /** ADP Event Detected */ - unsigned adp_int:1; - /** Multi Valued ID pin */ - unsigned mult_val_id_bc:5; - /** Reserved 24_31 */ - unsigned reserved29_31:3; - } b; +typedef union gpwrdn_data +{ + /* raw register data */ + uint32_t d32; + + /** register bits */ + struct + { + /** PMU Interrupt Select */ + unsigned pmuintsel: 1; + /** PMU Active */ + unsigned pmuactv: 1; + /** Restore */ + unsigned restore: 1; + /** Power Down Clamp */ + unsigned pwrdnclmp: 1; + /** Power Down Reset */ + unsigned pwrdnrstn: 1; + /** Power Down Switch */ + unsigned pwrdnswtch: 1; + /** Disable VBUS */ + unsigned dis_vbus: 1; + /** Line State Change */ + unsigned lnstschng: 1; + /** Line state change mask */ + unsigned lnstchng_msk: 1; + /** Reset Detected */ + unsigned rst_det: 1; + /** Reset Detect mask */ + unsigned rst_det_msk: 1; + /** Disconnect Detected */ + unsigned disconn_det: 1; + /** Disconnect Detect mask */ + unsigned disconn_det_msk: 1; + /** Connect Detected*/ + unsigned connect_det: 1; + /** Connect Detected Mask*/ + unsigned connect_det_msk: 1; + /** SRP Detected */ + unsigned srp_det: 1; + /** SRP Detect mask */ + unsigned srp_det_msk: 1; + /** Status Change Interrupt */ + unsigned sts_chngint: 1; + /** Status Change Interrupt Mask */ + unsigned sts_chngint_msk: 1; + /** Line State */ + unsigned linestate: 2; + /** Indicates current mode(status of IDDIG signal) */ + unsigned idsts: 1; + /** B Session Valid signal status*/ + unsigned bsessvld: 1; + /** ADP Event Detected */ + unsigned adp_int: 1; + /** Multi Valued ID pin */ + unsigned mult_val_id_bc: 5; + /** Reserved 24_31 */ + unsigned reserved29_31: 3; + } b; } gpwrdn_data_t; #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usbh.h b/cores/xmc_lib/XMCLib/inc/xmc_usbh.h index 93d5bb9f..ec1d6261 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_usbh.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_usbh.h @@ -1,44 +1,40 @@ /** * @file xmc_usbh.h - * @date 2016-06-30 * - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2016-06-30: - * - Initial Version.
    - * 2016-09-01: - * - Removed Keil specific inclusions and macros
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -47,16 +43,13 @@ #ifndef XMC_USBH_H #define XMC_USBH_H -#include #include "xmc_common.h" + +#if (defined(USB0) && ((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48))) || defined(DOXYGEN) + #include "xmc_scu.h" #include "xmc_gpio.h" -#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || defined(DOXYGEN)) -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ /** * @addtogroup USBH @@ -220,7 +213,8 @@ /** * @brief General power states of USB peripheral driver */ -typedef enum XMC_USBH_POWER_STATE { +typedef enum XMC_USBH_POWER_STATE +{ XMC_USBH_POWER_OFF, /**< Power off: no operation possible */ XMC_USBH_POWER_LOW, /**< Low Power mode: retain state, detect and signal wake-up events */ XMC_USBH_POWER_FULL /**< Power on: full operation at maximum performance */ @@ -231,7 +225,8 @@ typedef enum XMC_USBH_POWER_STATE { /** * @brief USB host Driver Version */ -typedef struct XMC_USBH_DRIVER_VERSION { +typedef struct XMC_USBH_DRIVER_VERSION +{ uint16_t api; /**< API version */ uint16_t drv; /**< Driver version */ } XMC_USBH_DRIVER_VERSION_t; @@ -240,7 +235,8 @@ typedef struct XMC_USBH_DRIVER_VERSION { /** * @brief USB Host Port State */ -typedef struct XMC_USBH_PORT_STATE { +typedef struct XMC_USBH_PORT_STATE +{ uint32_t connected : 1; /**< USB Host Port connected flag */ uint32_t overcurrent : 1; /**< USB Host Port overcurrent flag */ uint32_t speed : 2; /**< USB Host Port speed setting (ARM_USB_SPEED_xxx) */ @@ -255,7 +251,8 @@ typedef uint32_t XMC_USBH_PIPE_HANDLE; /** * @brief USB Host Driver Capabilities. */ -typedef struct XMC_USBH_CAPABILITIES { +typedef struct XMC_USBH_CAPABILITIES +{ uint32_t port_mask : 15; /**< Root HUB available Ports Mask */ uint32_t auto_split : 1; /**< Automatic SPLIT packet handling */ uint32_t event_connect : 1; /**< Signal Connect event */ @@ -270,11 +267,12 @@ typedef void (*XMC_USBH_SignalPipeEvent_t) (XMC_USBH_PIPE_HANDLE pipe_hndl, uint /** * @brief Access structure of USB Host Driver. */ -typedef struct XMC_USBH_DRIVER { +typedef struct XMC_USBH_DRIVER +{ XMC_USBH_DRIVER_VERSION_t (*GetVersion) (void); /**< Pointer to \ref ARM_USBH_GetVersion : Get driver version. */ XMC_USBH_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. */ int32_t (*Initialize) (XMC_USBH_SignalPortEvent_t cb_port_event, - XMC_USBH_SignalPipeEvent_t cb_pipe_event); /**< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. */ + XMC_USBH_SignalPipeEvent_t cb_pipe_event); /**< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. */ int32_t (*Uninitialize) (void); /**< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. */ int32_t (*PowerControl) (XMC_USBH_POWER_STATE_t state); /**< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. */ int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); /**< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. */ @@ -283,19 +281,25 @@ typedef struct XMC_USBH_DRIVER { int32_t (*PortResume) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). */ XMC_USBH_PORT_STATE_t (*PortGetState) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. */ XMC_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_max_packet_size, - uint8_t ep_interval); /**< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. */ + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_max_packet_size, + uint8_t ep_interval); /**< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. */ int32_t (*PipeModify) (XMC_USBH_PIPE_HANDLE pipe_hndl, - uint8_t dev_addr, - uint16_t ep_max_packet_size); /**< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. */ + uint8_t dev_addr, + uint8_t dev_speed, + uint8_t hub_addr, + uint8_t hub_port, + uint16_t ep_max_packet_size); /**< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. */ int32_t (*PipeDelete) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. */ int32_t (*PipeReset) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. */ int32_t (*PipeTransfer) (XMC_USBH_PIPE_HANDLE pipe_hndl, - uint32_t packet, - uint8_t *data, - uint32_t num); /**< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. */ + uint32_t packet, + uint8_t *data, + uint32_t num); /**< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. */ uint32_t (*PipeTransferGetResult) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. */ int32_t (*PipeTransferAbort) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. */ uint16_t (*GetFrameNumber) (void); /**< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. */ @@ -305,7 +309,8 @@ typedef struct XMC_USBH_DRIVER { /** * @brief Structure to handle various states of USB host driver. An instance exists for each USB channel */ -typedef struct XMC_USBH0_pipe { +typedef struct XMC_USBH0_pipe +{ uint32_t packet; /**< Holds packet token and PID information of ongoing data packet transaction*/ uint8_t *data; /**< Holds address of data buffer. It represents source buffer for OUT or SETUP transfer and destination address for IN transfer*/ @@ -318,19 +323,20 @@ typedef struct XMC_USBH0_pipe { uint8_t ep_type; /**< Endpoint type for selected pipe*/ uint8_t in_use; /**< Set to true when transfer is in progress and reset only after the /ref num of bytes is transferred*/ uint8_t transfer_active; /**< Set to true when a transfer has been initiated and reset when event for transfer complete occurs*/ - uint8_t interrupt_triggered; /**< For INTERRUPT or ISOCHRONOUS pipe, indicates if retransmit timeout has occurred*/ + uint8_t interrupt_triggered; /**< For INTERRUPT or ISOCHRONOUS pipe, indicates if retransmit timeout has occurred*/ uint8_t event; /**< Holds pipe specific event flags*/ } XMC_USBH0_pipe_t; -typedef struct xmc_usb_host_device { - USB0_GLOBAL_TypeDef *global_register; /**< Global register interface */ - USB0_CH_TypeDef *host_channel_registers; /**< Host channel interface */ - XMC_USBH_SignalPortEvent_t SignalPortEvent_cb; /**< Port event callback; set during init */ +typedef struct xmc_usb_host_device +{ + USB0_GLOBAL_TypeDef *global_register; /**< Global register interface */ + USB0_CH_TypeDef *host_channel_registers; /**< Host channel interface */ + XMC_USBH_SignalPortEvent_t SignalPortEvent_cb; /**< Port event callback; set during init */ XMC_USBH_SignalPipeEvent_t SignalPipeEvent_cb; /**< Pipe event callback; set during init */ - bool init_done; /**< init status */ - XMC_USBH_POWER_STATE_t power_state; /**< USB Power status */ - bool port_reset_active; /**< Port reset state */ + bool init_done; /**< init status */ + XMC_USBH_POWER_STATE_t power_state; /**< USB Power status */ + bool port_reset_active; /**< Port reset state */ } XMC_USBH0_DEVICE_t; /******************************************************************************* @@ -351,8 +357,8 @@ extern "C" { * calls the relevant callback functions to indicate it to the application. */ void XMC_USBH_HandleIrq (uint32_t gintsts); - /** + * @param ms Delay in milliseconds. * @return uint8_t Value has no significance for the low level driver. * * \parDescription:
    @@ -360,8 +366,8 @@ void XMC_USBH_HandleIrq (uint32_t gintsts); * for delay which has to re-implemented with time delay logic. The low level driver expects blocking * implementation of the delay. */ - uint8_t XMC_USBH_osDelay( ); - +uint8_t XMC_USBH_osDelay(uint32_t ms); + /** * @param port Address of the port which has the pin used to enable VBUS charge pump. * @param pin Pin number in the port selected in previous argument using which the VBUS charge pump has to be enabled. @@ -373,7 +379,7 @@ void XMC_USBH_HandleIrq (uint32_t gintsts); * Typical ports that support VBUS enable are: P3_2 and P0_1. * */ -void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin); +void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t *port, uint32_t pin); /** * @return USB host mode interrupt status. Bit field USB0_BASE->GINTSTS_HOSTMODE @@ -397,14 +403,11 @@ void XMC_USBH_TurnOffResumeBit(void); #ifdef __cplusplus } #endif -/** - * @} - */ /** * @} */ -#endif +#endif /* ((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || DOXYGEN) */ #endif /* XMC_USBH_H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_usic.h b/cores/xmc_lib/XMCLib/inc/xmc_usic.h index a1496df6..dc14e599 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_usic.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_usic.h @@ -1,81 +1,41 @@ /** * @file xmc_usic.h - * @date 2017-02-10 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial draft
    - * - Documentation improved
    - * - * 2015-05-08: - * - Added XMC_USIC_CH_SetInputTriggerCombinationMode() and XMC_USIC_CH_SetTransmitBufferStatus()
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * - * 2015-08-17: - * - Bug fixed in XMC_USIC_CH_SetTransmitBufferStatus API. OR operator removed. - * - * 2015-08-24: - * - Added APIs for enabling/disabling delay compensation XMC_USIC_CH_DisableDelayCompensation() and - * XMC_USIC_CH_DisableDelayCompensation() - * - * 2015-08-25: - * - Added APIs for defining if the data shift unit input is derived - * from the input data path DXn or from the selected protocol pre-processors: XMC_USIC_CH_ConnectInputDataShiftToPPP() - * and XMC_USIC_CH_ConnectInputDataShiftToDataInput() - * - * 2015-08-27: - * - Fixed bug in XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T value. - * - Added APIs for direct TBUF access: XMC_USIC_CH_WriteToTBUF() and XMC_USIC_CH_WriteToTBUFTCI() - * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() and XMC_USIC_CH_SetBRGInputClockSource() - * - * 2015-08-28: - * - Added API for enabling the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active. Feature used for RS-232 - * Clear to Send (CTS) signal: XMC_USIC_CH_EnableTBUFDataValidTrigger() and XMC_USIC_CH_DisableTBUFDataValidTrigger(). - * - * 2016-03-09: - * - Optimization of write only registers - * - * 2016-04-10: - * - Added an API to put the data into FIFO when hardware port control is enabled: XMC_USIC_CH_TXFIFO_PutDataHPCMode()
    - * - * 2017-02-10: - * - Added XMC_USIC_CH_SetShiftDirection() to allow selection of shift direction of the data words for transmision and reception - * - Added XMC_USIC_CH_GetCaptureTimerValue() and XMC_USIC_CH_SetFractionalDivider() + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -89,11 +49,6 @@ #include "xmc_common.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - /** * @addtogroup USIC * @brief Universal Serial Interface Channel(USIC) driver for serial communication. @@ -105,7 +60,7 @@ * by each communication channel and which pins are used. * The driver provides APIs, configuration structures and enumerations to configure common features of multiple serial * communication protocols. - * + * * USIC driver features: * -# Allows configuration of FIFO for transmit and receive functions. * -# Provides a structure type XMC_USIC_CH_t to represent the USIC channel registers in a programmer @@ -151,11 +106,11 @@ #define USIC_CH_DXCR_INSW_pos USIC_CH_DX0CR_INSW_Pos /**< Common mask for INSW bitfield position in DXnCR register */ #if UC_FAMILY == XMC1 - #include "xmc1_usic_map.h" +#include "xmc1_usic_map.h" #endif #if UC_FAMILY == XMC4 - #include "xmc4_usic_map.h" +#include "xmc4_usic_map.h" #endif /******************************************************************************* @@ -401,9 +356,22 @@ typedef enum XMC_USIC_CH_RXFIFO_EVENT typedef enum XMC_USIC_CH_BRG_CLOCK_SOURCE { XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER = 0x0UL, /**< Baudrate generator clock source : Source divider. (Internal clock source)*/ - XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T = 0x2UL << USIC_CH_BRG_CLKSEL_Pos /**< Baudrate generator clock source : DX1T. (External clock source) */ + XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T = 0x2UL << USIC_CH_BRG_CLKSEL_Pos, /**< Baudrate generator clock source : DX1T. (External clock source) */ + XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1S = 0x3UL << USIC_CH_BRG_CLKSEL_Pos /**< Baudrate generator clock source : DX1S. (External clock source) */ } XMC_USIC_CH_BRG_CLOCK_SOURCE_t; +/** +* USIC channel input selection for CTQ +*/ +typedef enum XMC_USIC_CH_BRG_CTQSEL +{ + XMC_USIC_CH_BRG_CTQSEL_PDIV = 0x0UL, /**< fCTQIN = fPDIV */ + XMC_USIC_CH_BRG_CTQSEL_PPP = 0x1UL << USIC_CH_BRG_CTQSEL_Pos, /**< fCTQIN = fPPP */ + XMC_USIC_CH_BRG_CTQSEL_SCLK = 0x2UL << USIC_CH_BRG_CTQSEL_Pos, /**< fCTQIN = fSCLK */ + XMC_USIC_CH_BRG_CTQSEL_MCLK = 0x3UL << USIC_CH_BRG_CTQSEL_Pos /**< fCTQIN = fMCLK */ +} XMC_USIC_CH_BRG_CTQSEL_t; + + /** * USIC channel baudrate generator divider mode */ @@ -450,7 +418,7 @@ typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT typedef enum XMC_USIC_CH_SHIFT_DIRECTION { XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST = 0x0UL, /**< Shift LSB first. The first data bit of a data word is located at bit position 0. */ - XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST = 0x1UL << USIC_CH_SCTR_SDIR_Msk /**< Shift MSB first. The first data bit of a data word is located at the bit position given by the configured word length. */ + XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST = 0x1UL << USIC_CH_SCTR_SDIR_Pos /**< Shift MSB first. The first data bit of a data word is located at the bit position given by the configured word length. */ } XMC_USIC_CH_SHIFT_DIRECTION_t; @@ -460,10 +428,10 @@ typedef enum XMC_USIC_CH_SHIFT_DIRECTION /*Anonymous structure/union guard start*/ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif /** @@ -472,7 +440,7 @@ typedef enum XMC_USIC_CH_SHIFT_DIRECTION typedef USIC_GLOBAL_TypeDef XMC_USIC_t; /** - * USIC channel structure.
    The members of the structure are same as in the device header file, + * USIC channel structure.
    The members of the structure are same as in the device header file, * except for some registers. * DX0CR, DX1CR, DX2CR, DX3CR, DX4CR and DX5CR are replaced with the array DXCR[6]. * TBUF0 to TBUF31 are replaced with TBUF[32]. @@ -491,7 +459,8 @@ typedef struct XMC_USIC_CH __IO uint32_t SCTR; /**< Shift control register*/ __IO uint32_t TCSR; - union { + union + { __IO uint32_t PCR_IICMode; /**< I2C protocol configuration register*/ __IO uint32_t PCR_IISMode; /**< I2S protocol configuration register*/ __IO uint32_t PCR_SSCMode; /**< SPI protocol configuration register*/ @@ -501,7 +470,8 @@ typedef struct XMC_USIC_CH __IO uint32_t CCR; /**< Channel control register*/ __IO uint32_t CMTR; /**< Capture mode timer register*/ - union { + union + { __IO uint32_t PSR_IICMode; /**< I2C protocol status register*/ __IO uint32_t PSR_IISMode; /**< I2S protocol status register*/ __IO uint32_t PSR_SSCMode; /**< SPI protocol status register*/ @@ -534,9 +504,9 @@ typedef struct XMC_USIC_CH /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /******************************************************************************* @@ -552,10 +522,10 @@ __STATIC_INLINE bool XMC_USIC_IsModuleValid(const XMC_USIC_t *const module) bool tmp; tmp = (module == XMC_USIC0); -#if defined(XMC_USIC1) +#if defined(XMC_USIC1) tmp = tmp || (module == XMC_USIC1); #endif -#if defined(XMC_USIC2) +#if defined(XMC_USIC2) tmp = tmp || (module == XMC_USIC2); #endif @@ -567,10 +537,10 @@ __STATIC_INLINE bool XMC_USIC_IsChannelValid(const XMC_USIC_CH_t *const channel) bool tmp; tmp = ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1)); -#if defined(XMC_USIC1) +#if defined(XMC_USIC1) tmp = tmp || ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)); #endif -#if defined(XMC_USIC2) +#if defined(XMC_USIC2) tmp = tmp || ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)); #endif @@ -583,7 +553,7 @@ __STATIC_INLINE bool XMC_USIC_IsChannelValid(const XMC_USIC_CH_t *const channel) * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support. * @return None - * + * * \parDescription
    * Enables the USIC module.\n\n * Enables the clock for the USIC module by following the @@ -658,6 +628,98 @@ void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel); */ XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling); +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param rate Desired baudrate. Only integer dividers of peripheral clock are achievable + * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n + * This can be related to the number of samples for each logic state of the data signal. \n + * \b Range: 1 to 32. Value should be chosen based on the protocol used. + * @return Status indicating the baudrate configuration.\n + * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured, + * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid. + * + * \parDescription
    + * Configures the baudrate of the USIC channel using the integer divider which restrics the achievable baudrate but decreses jitter. \n\n + * Baudrate is configured by considering the peripheral frequency and the desired baudrate. + * Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired + * baudrate. + * + * \parRelated APIs:
    + * XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource() \n\n\n + */ +XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, int32_t rate, int32_t oversampling); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param clksel Baudrate generator clock source. + * @param pppen Enable 2:1 Divider for fPPP. + * @param pdiv Divider Factor to generate fPDIV = fPPP / (pDIV + 1) + * @param ctqsel Input selection for CTQ. + * @param pctq Pre-Divider for Time Quanta Counter. fCTQIN / (PCQT + 1) + * @param dctq Denominator for Time Quanta Counter. fTQ / (DCTQ + 1) + * @return None + * + * \parDescription
    + * Configures the baudrate generator of the USIC channel. + * + * \parRelated APIs:
    + * XMC_USIC_CH_SetFractionalDivider() \n\n\n + */ +void XMC_USIC_CH_SetBaudrateDivider(XMC_USIC_CH_t *const channel, + XMC_USIC_CH_BRG_CLOCK_SOURCE_t clksel, + bool pppen, + uint32_t pdiv, + XMC_USIC_CH_BRG_CTQSEL_t ctqsel, + uint32_t pctq, + uint32_t dctq); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return baudrate currently used by USIC channel for .\n + * + * \parDescription
    + * Calculates the current used baudrate (fCTQIN) of a USIC channel. \n\n + * @image html ../images/usic_brg.png + * @image latex ../images/usic_brg.png + * + * \parRelated APIs:
    + * XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx() \n\n\n + */ +uint32_t XMC_USIC_CH_GetBaudrate(XMC_USIC_CH_t *const channel); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return baudrate currently used by USIC channel.\n + * + * \parDescription
    + * Calculates the current used SCLK frequency of a USIC channel. \n\n + * @image html ../images/usic_brg.png + * @image latex ../images/usic_brg.png + * + * \parRelated APIs:
    + * XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx() \n\n\n + */ +uint32_t XMC_USIC_CH_GetSCLKFrequency(XMC_USIC_CH_t *const channel); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return baudrate currently used by USIC channel.\n + * + * \parDescription
    + * Calculates the current used MCLK frequency of a USIC channel. \n\n + * @image html ../images/usic_brg.png + * @image latex ../images/usic_brg.png + * + * \parRelated APIs:
    + * XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx() \n\n\n + */ +uint32_t XMC_USIC_CH_GetMCLKFrequency(XMC_USIC_CH_t *const channel); + /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. @@ -678,9 +740,9 @@ XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint3 * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n */ void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, - const uint16_t pdiv, - const uint32_t oversampling, - const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode); + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode); /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -695,9 +757,9 @@ void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, * * \parDescription
    * Selects the data source for USIC input stage.\n\n - * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages - * like DX0CR, DX1CR etc. - * + * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages + * like DX0CR, DX1CR etc. + * * \parRelated APIs:
    * XMC_USIC_CH_EnableInputInversion(), XMC_USIC_CH_EnableInputDigitalFilter(), XMC_USIC_CH_EnableInputSync(), * XMC_USIC_CH_SetInputSamplingFreq()\n\n\n @@ -705,7 +767,7 @@ void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, __STATIC_INLINE void XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const uint8_t source) { channel->DXCR[input] = (uint32_t)((channel->DXCR[input] & (uint32_t)(~USIC_CH_DXCR_DSEL_Msk)) | - ((uint32_t)source << USIC_CH_DXCR_DSEL_Pos)); + ((uint32_t)source << USIC_CH_DXCR_DSEL_Pos)); } /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -723,7 +785,7 @@ __STATIC_INLINE void XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t *const channel, co */ __STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToPPP(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) { - channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_INSW_Msk; + channel->DXCR[input] &= (uint32_t)~USIC_CH_DXCR_INSW_Msk; } /** @@ -783,7 +845,7 @@ __STATIC_INLINE void XMC_USIC_CH_EnableInputInversion(XMC_USIC_CH_t *const chann */ __STATIC_INLINE void XMC_USIC_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) { - channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DPOL_Msk; + channel->DXCR[input] &= (uint32_t)~USIC_CH_DXCR_DPOL_Msk; } /** @@ -816,7 +878,7 @@ __STATIC_INLINE void XMC_USIC_CH_EnableDelayCompensation(XMC_USIC_CH_t *const ch */ __STATIC_INLINE void XMC_USIC_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel) { - channel->DXCR[1U] &=(uint32_t)~USIC_CH_DX1CR_DCEN_Msk; + channel->DXCR[1U] &= (uint32_t)~USIC_CH_DX1CR_DCEN_Msk; } /** @@ -853,7 +915,7 @@ __STATIC_INLINE void XMC_USIC_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const c */ __STATIC_INLINE void XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) { - channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DFEN_Msk; + channel->DXCR[input] &= (uint32_t)~USIC_CH_DXCR_DFEN_Msk; } /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -872,7 +934,7 @@ __STATIC_INLINE void XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const */ __STATIC_INLINE void XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) { - channel->DXCR[input] |=(uint32_t)USIC_CH_DXCR_DSEN_Msk; + channel->DXCR[input] |= (uint32_t)USIC_CH_DXCR_DSEN_Msk; } /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -890,7 +952,7 @@ __STATIC_INLINE void XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t *const channel, c */ __STATIC_INLINE void XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input) { - channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DSEN_Msk; + channel->DXCR[input] &= (uint32_t)~USIC_CH_DXCR_DSEN_Msk; } /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -907,8 +969,8 @@ __STATIC_INLINE void XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t *const channel, * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_INPUT_t input, - const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq) + const XMC_USIC_CH_INPUT_t input, + const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq) { channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_SFSEL_Msk)) | ((uint32_t)sampling_freq); @@ -929,8 +991,8 @@ __STATIC_INLINE void XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const chann * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_SetInputTriggerCombinationMode(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_INPUT_t input, - const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) + const XMC_USIC_CH_INPUT_t input, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) { channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_CM_Msk)) | ((uint32_t)combination_mode << USIC_CH_DXCR_CM_Pos); @@ -990,8 +1052,8 @@ __STATIC_INLINE void XMC_USIC_CH_WriteToTBUF(XMC_USIC_CH_t *const channel, const * XMC_USIC_CH_WriteToTBUF() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_WriteToTBUFTCI(XMC_USIC_CH_t *const channel, - const uint16_t data, - const uint32_t transmit_control_information) + const uint16_t data, + const uint32_t transmit_control_information) { channel->TBUF[transmit_control_information] = data; } @@ -1041,7 +1103,7 @@ __STATIC_INLINE void XMC_USIC_CH_SetShiftDirection(XMC_USIC_CH_t *const channel, /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. - * @return Captured counter value + * @return Captured counter value * * * \parDescription
    @@ -1059,9 +1121,9 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_GetCaptureTimerValue(const XMC_USIC_CH_t *c * @param step divider \n * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL resulting divider = 1023 - step \n * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL resulting divider = 1023 / step \n - * + * * @return None - * + * * \parDescription
    * The fractional divider generates its output frequency fFD by either dividing the input frequency fPERIPH by an integer factor n or by multiplication of n/1024. * @@ -1083,7 +1145,7 @@ __STATIC_INLINE void XMC_USIC_CH_SetFractionalDivider(XMC_USIC_CH_t *const chann * Define the data frame length.\n\n * Set the number of bits to be serially transmitted in a frame. * The frame length should be multiples of word length. If the value is set to 0x40, the frame length - * has to be controlled explicitly. + * has to be controlled explicitly. * * \parRelated APIs:
    * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl() \n\n\n @@ -1149,7 +1211,7 @@ __STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, cons * * \parDescription
    * Sets the interrupt node for USIC channel events. \n\n - * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). + * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). * The NVIC node gets linked to the interrupt event by doing so.
    * Note: NVIC node should be separately enabled to generate the interrupt. * @@ -1157,8 +1219,8 @@ __STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, cons * XMC_USIC_CH_EnableEvent() \n\n\n */ void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request); + const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -1193,7 +1255,7 @@ __STATIC_INLINE XMC_USIC_CH_TBUF_STATUS_t XMC_USIC_CH_GetTransmitBufferStatus(XM * Checks if RBUF0 and RBUF1 have valid unread data. \n\n * It checks the bits RDV0 and RDV1 of the RBUFSR register. * Returns the value of RBUFSR masked with bitmasks of RDV0 and RDV1. - * It can be used to decide whether 2bytes has to be read from RBUF or 1 byte. + * It can be used to decide whether 2bytes has to be read from RBUF or 1 byte. * If both bitmasks XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 and XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 * are set, then 2 bytes can be read from RBUF. If only either of them is set, then only one byte * can be read from RBUF. @@ -1213,18 +1275,18 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_GetReceiveBufferStatus(XMC_USIC_CH_t *const * \b Range: @ref XMC_USIC_CH_START_TRANSMISION_DISABLED, * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV, @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0, * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 - * + * * @return None * * \parDescription
    * Configures data transmission. \n\n * The configuration affects the data shifted on the DOUT0 pin. - * + * * \parRelated APIs:
    * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetDataOutputMode() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode) + const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode) { channel->TCSR = (uint32_t)(channel->TCSR & (~USIC_CH_TCSR_TDEN_Msk)) | (uint32_t)start_transmision_mode; } @@ -1240,12 +1302,12 @@ __STATIC_INLINE void XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t *const ch * \parDescription
    * Configures the mode for data output. \n\n * USIC channel can be configured to shift inverted data or direct data based on the input to the API. - * + * * \parRelated APIs:
    * XMC_USIC_CH_SetStartTransmisionMode() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode) + const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode) { channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_DOCFG_Msk)) | (uint32_t)data_output_mode; } @@ -1257,7 +1319,7 @@ __STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel, * * \parDescription
    * Enables automatic update of frame length. \n\n - * When the automatic update of frame length is enabled, frame length is configured based on the + * When the automatic update of frame length is enabled, frame length is configured based on the * index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], frame length is configured * with the mask value of \a x at the last 5 bit positions. Same logic is applicable if data is written to * IN[x] register. @@ -1268,10 +1330,34 @@ __STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel, __STATIC_INLINE void XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t *const channel) { channel->TCSR = (uint32_t)(channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | - USIC_CH_TCSR_SELMD_Msk | - USIC_CH_TCSR_WAMD_Msk | - USIC_CH_TCSR_HPCMD_Msk))) | - (uint32_t)USIC_CH_TCSR_FLEMD_Msk; + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_WAMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + (uint32_t)USIC_CH_TCSR_FLEMD_Msk; +} + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
    + * Enables automatic update of word length. \n\n + * When the automatic update of word length is enabled, word length is configured based on the + * index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], word length is configured + * with the mask value of \a x at the last 5 bit positions. Same logic is applicable if data is written to + * IN[x] register. + * + * \parRelated APIs:
    + * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_EnableWordLengthControl(XMC_USIC_CH_t *const channel) +{ + channel->TCSR = (uint32_t)(channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_WAMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + (uint32_t)USIC_CH_TCSR_WLEMD_Msk; } /** @@ -1285,13 +1371,31 @@ __STATIC_INLINE void XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t *const c * Frame length remains fixed until it is changed again. * * \parRelated APIs:
    - * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_SetFrameLength() \n\n\n + * XMC_USIC_CH_EnableFrameLengthControl(), XMC_USIC_CH_SetFrameLength() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_DisableFrameLengthControl(XMC_USIC_CH_t *const channel) { channel->TCSR &= (uint32_t)~USIC_CH_TCSR_FLEMD_Msk; } +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @return None + * + * \parDescription
    + * Disables automatic update of word length. \n\n + * When automatic update of word length is disabled, word length has to configured explicitly. + * Word length remains fixed until it is changed again. + * + * \parRelated APIs:
    + * XMC_USIC_CH_EnableFrameLengthControl(), XMC_USIC_CH_SetWordLength() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_DisableWordLengthControl(XMC_USIC_CH_t *const channel) +{ + channel->TCSR &= (uint32_t)~USIC_CH_TCSR_WLEMD_Msk; +} + /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. @@ -1336,8 +1440,8 @@ __STATIC_INLINE void XMC_USIC_CH_DisableTBUFDataValidTrigger(XMC_USIC_CH_t *cons * * \parDescription
    * Trigger a USIC interrupt service request.\n\n - * When the USIC service request is triggered, the NVIC interrupt associated with it will be - * generated if enabled. + * When the USIC service request is triggered, the NVIC interrupt associated with it will be + * generated if enabled. * * \parRelated APIs:
    * XMC_USIC_CH_SetInterruptNodePointer() \n\n\n @@ -1361,11 +1465,29 @@ __STATIC_INLINE void XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t *const chan * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status) + const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status) { channel->FMR = (uint32_t)transmit_buffer_status; } +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * + * @return None + * + * \parDescription
    + * Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by software. + * + * \parRelated APIs:
    + * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_InvalidateReadData(XMC_USIC_CH_t *const channel) +{ + channel->FMR = USIC_CH_FMR_CRDV0_Msk | USIC_CH_FMR_CRDV1_Msk; +} + + /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. @@ -1375,14 +1497,14 @@ __STATIC_INLINE void XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t *const ch * * \parDescription
    * Set the passive data level of the output signal. \n\n - * When the USIC channel transmit stage is idle, the output signal level stays at the + * When the USIC channel transmit stage is idle, the output signal level stays at the * configured passive level. - * + * * \parRelated APIs:
    * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetStartTransmisionMode() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level) + const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level) { channel->SCTR &= (~USIC_CH_SCTR_PDL_Msk); channel->SCTR |= (uint32_t)passive_level; @@ -1402,8 +1524,8 @@ __STATIC_INLINE void XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t *const channe * * \parDescription
    * Initializes the transmit FIFO. \n\n - * Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. - * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, + * Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. + * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, * from where transmit data can be put, for the selected USIC channel. \a size represents the size of transmit FIFO as a multiple of * 2. Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard transmit buffer * event is generated when the FIFO filling level falls below the \a limit value. @@ -1425,17 +1547,40 @@ void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, * \b Range: 0 to \a size -1. * @return None * + * \deprecated { Use XMC_USIC_CH_TXFIFO_SetTriggerLimit() } + * * \parDescription
    * Sets the size and trigger limit for the transmit FIFO. \n\n - * The API is not to be called for initializing the transmit FIFO. The API shall be used for the + * The API is not to be called for initializing the transmit FIFO. The API shall be used for the * runtime change of transmit FIFO trigger limit. FIFO start position will not be affected on execution. * * \parRelated APIs:
    * XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit() \n\n\n */ void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_FIFO_SIZE_t size, - const uint32_t limit); + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param limit Threshold for transmit FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a fifo size -1. + * @return None + * + * \parDescription
    + * Sets the trigger limit for the TX FIFO. \n\n + * + * \parRelated APIs:
    + * XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_SetTriggerLimit(XMC_USIC_CH_t *const channel, + const uint32_t limit) +{ + channel->TBCTR = (channel->TBCTR & (uint32_t)~USIC_CH_TBCTR_LIMIT_Msk) | ((limit << USIC_CH_TBCTR_LIMIT_Pos) & USIC_CH_TBCTR_LIMIT_Msk); +} + /** @@ -1447,9 +1592,9 @@ void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, * \parDescription
    * Enables the interrupt events related to transmit FIFO. \n\n * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. - * Multiple events can be enabled by providing multiple events in a single call. For providing + * Multiple events can be enabled by providing multiple events in a single call. For providing * multiple events, combine the events using bitwise OR operation. Events are configured in the TBCTR register.
    - * + * * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node * must be enabled. * @@ -1470,8 +1615,8 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t *const channel * * \parDescription
    * Disables the interrupt events related to transmit FIFO. \n\n - * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event - * flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent(). + * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event + * flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent(). * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. For providing * multiple events, combine the events using bitwise OR operation. * @@ -1508,8 +1653,8 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t *const channe * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n */ void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request); + const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -1531,6 +1676,31 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t *const channel, co channel->IN[0] = data; } +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param data Data to be transmitted. \n + * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535 + * @param loc Input location. \n + * @return None + * + * \parDescription
    + * Transmit data can be loaded to TBUF by software by writing to the transmit buffer input + * locations TBUFx (x = 00-31), consisting of 32 consecutive addresses. The data written + * to one of these input locations is stored in the transmit buffer TBUF. Additionally, the + * address of the written location is evaluated and can be used for additional control + * purposes. This 5-bit wide information (named Transmit Control Information TCI) can be + * used for different purposes in different protocols. + * + * \parRelated APIs:
    + * XMC_USIC_CH_EnableWordLengthControl() \n + * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataEx(XMC_USIC_CH_t *const channel, const uint16_t data, uint8_t loc) +{ + channel->IN[loc] = data; +} + /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. @@ -1542,15 +1712,16 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t *const channel, co * \parDescription
    * Writes data to the transmit FIFO in frame length control mode. \n\n * When frame length control is enabled for dynamic update of frame length, this API can be used. - * \a frame_length represents the frame length to be updated by the peripheral. + * \a frame_length represents the frame length to be updated by the peripheral. * \a frame_length is used as index for the IN[] register array. - * + * * \parRelated APIs:
    + * XMC_USIC_CH_TXFIFO_PutDataEx() \n * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const channel, - const uint16_t data, - const uint32_t frame_length) + const uint16_t data, + const uint32_t frame_length) { channel->IN[frame_length] = data; } @@ -1566,15 +1737,15 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const chan * \parDescription
    * Writes data to the transmit FIFO in hardware port control mode. \n\n * When hardware port control is enabled for dynamic update of frame length, this API can be used. - * \a frame_length represents the frame length to be updated by the peripheral. + * \a frame_length represents the frame length to be updated by the peripheral. * \a frame_length is used as index for the IN[] register array. - * + * * \parRelated APIs:
    * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t *const channel, - const uint16_t data, - const uint32_t frame_length) + const uint16_t data, + const uint32_t frame_length) { channel->IN[frame_length] = data; } @@ -1587,7 +1758,7 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t *const chan * \parDescription
    * Clears the contents of transmit FIFO. \n\n * Transmit FIFO contents will be cleared and the filling level will be reset to 0. - * + * * \parRelated APIs:
    * XMC_USIC_CH_TXFIFO_GetLevel() \n\n\n */ @@ -1606,7 +1777,7 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t *const channel) * Checks if transmit FIFO is full. \n\n * When the transmit FIFO filling level reaches the configured size, FIFO full flag is set. * User should not write to the FIFO when the transmit FIFO is full. - * + * * \parRelated APIs:
    * XMC_USIC_CH_TXFIFO_IsEmpty(), XMC_USIC_CH_TXFIFO_Flush() \n\n\n */ @@ -1624,9 +1795,9 @@ __STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsFull(XMC_USIC_CH_t *const channel) * \parDescription
    * Checks if transmit FIFO is empty. \n\n * When the transmit FIFO is empty, data can be written to FIFO. - * When the last written word to the transmit FIFO is transmitted out of the FIFO, + * When the last written word to the transmit FIFO is transmitted out of the FIFO, * FIFO empty flag is set. - * + * * \parRelated APIs:
    * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n */ @@ -1638,14 +1809,14 @@ __STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsEmpty(XMC_USIC_CH_t *const channel) /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. - * @return Transmit FIFO filling level. \n + * @return Transmit FIFO filling level. \n * \b Range: minimum= 0(FIFO empty), maximum= transmit FIFO size. * * \parDescription
    * Gets the transmit FIFO filling level. \n\n * For every word written to the FIFO, filling level is updated. The API gives the value * of this filling level. - * + * * \parRelated APIs:
    * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n */ @@ -1658,14 +1829,14 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t *const channe * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. * @return Status of standard transmit and transmit buffer error events. @ref XMC_USIC_CH_TXFIFO_EVENT_t \n - * + * * \parDescription
    * Gets the transmit FIFO event status. \n\n * Gives the status of transmit FIFO standard transmit buffer event and transmit buffer error event. * The status bits are located at their bit positions in the TRBSR register in the returned value. * User can make use of the @ref XMC_USIC_CH_TXFIFO_EVENT_t enumeration for checking the status of return value. * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.
    - * + * * Note: Event status flags should be cleared by the user explicitly. * * \parRelated APIs:
    @@ -1674,7 +1845,7 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t *const channe __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channel) { return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_STBI_Msk | - USIC_CH_TRBSR_TBERI_Msk)); + USIC_CH_TRBSR_TBERI_Msk)); } /** @@ -1687,16 +1858,16 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channe * \parDescription
    * Clears the transmit FIFO event flags in the status register. \n\n * USIC channel peripheral does not clear the event flags after they are read. - * This API clears the events provided in the \a mask value. + * This API clears the events provided in the \a mask value. * XMC_USIC_CH_TXFIFO_EVENT enumeration can be used as input. Multiple events - * can be cleared by providing a mask value obtained by bitwise OR operation of + * can be cleared by providing a mask value obtained by bitwise OR operation of * multiple event enumerations. * * \parRelated APIs:
    * XMC_USIC_CH_TXFIFO_GetEvent() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, - const uint32_t event) + const uint32_t event) { channel->TRBSCR = event; } @@ -1714,9 +1885,9 @@ __STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, * * \parDescription
    * Configures the receive FIFO. \n\n - * Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. - * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, - * from where received data can be put. \a size represents the size of receive FIFO as a multiple of 2. + * Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module. + * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO, + * from where received data can be put. \a size represents the size of receive FIFO as a multiple of 2. * Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard receive buffer * event or alternative receive buffer event is generated when the FIFO filling level exceeds the \a limit value. * @@ -1737,17 +1908,38 @@ void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel, * \b Range: 0 to \a size -1. * @return None * + * \deprecated { Use XMC_USIC_CH_RXFIFO_SetTriggerLimit() } + * * \parDescription
    * Sets the size and trigger limit for the receive FIFO. \n\n - * The API is not to be called for initializing the receive FIFO. The API shall be used for the + * The API is not to be called for initializing the receive FIFO. The API shall be used for the * runtime change of receive FIFO trigger limit. FIFO start position will not be affected on execution. * * \parRelated APIs:
    * XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()\ n\n\n */ void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_FIFO_SIZE_t size, - const uint32_t limit); + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit); + +/** + * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n + * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support. + * @param limit Threshold for transmit FIFO filling level to be considered for generating events. \n + * \b Range: 0 to \a fifo size -1. + * @return None + * + * \parDescription
    + * Sets the trigger limit for the TX FIFO. \n\n + * + * \parRelated APIs:
    + * XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit() \n\n\n + */ +__STATIC_INLINE void XMC_USIC_CH_RXFIFO_SetTriggerLimit(XMC_USIC_CH_t *const channel, + const uint32_t limit) +{ + channel->RBCTR = (channel->RBCTR & (uint32_t)~USIC_CH_RBCTR_LIMIT_Msk) | ((limit << USIC_CH_RBCTR_LIMIT_Pos) & USIC_CH_RBCTR_LIMIT_Msk); +} /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -1758,9 +1950,9 @@ void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, * \parDescription
    * Enables the interrupt events related to transmit FIFO. \n\n * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t. - * Multiple events can be enabled by providing multiple events in a single call. For providing + * Multiple events can be enabled by providing multiple events in a single call. For providing * multiple events, combine the events using bitwise OR operation.
    - * + * * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node * must be enabled. * @@ -1783,9 +1975,9 @@ __STATIC_INLINE void XMC_USIC_CH_RXFIFO_EnableEvent(XMC_USIC_CH_t *const channel * * \parDescription
    * Disables the selected interrupt events related to receive FIFO. \n\n - * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event - * flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent(). - * Event bitmasks can be constructed using the enumeration \a XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing + * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event + * flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent(). + * Event bitmasks can be constructed using the enumeration \a XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing * multiple events, combine the events using bitwise OR operation. * * \parRelated APIs:
    @@ -1821,8 +2013,8 @@ __STATIC_INLINE void XMC_USIC_CH_RXFIFO_DisableEvent(XMC_USIC_CH_t *const channe * XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n */ void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request); + const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request); /** * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n @@ -1834,7 +2026,7 @@ void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, * Gets data from the receive FIFO. \n\n * Receive FIFO should be read only if data is availble in the FIFO. This can be checked using * the API XMC_USIC_CH_RXFIFO_IsEmpty(). Receive FIFO error flag will be set if an attempt is made - * to read from an empty receive FIFO. To read all the received data, user should keep reading data + * to read from an empty receive FIFO. To read all the received data, user should keep reading data * until receive FIFO is empty. * * \parRelated APIs:
    @@ -1853,7 +2045,7 @@ __STATIC_INLINE uint16_t XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t *const channel * \parDescription
    * Clears the contents of receive FIFO. \n\n * Receive FIFO contents will be cleared and the filling level will be reset to 0. - * + * * \parRelated APIs:
    * XMC_USIC_CH_RXFIFO_GetLevel() \n\n\n */ @@ -1872,7 +2064,7 @@ __STATIC_INLINE void XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t *const channel) * Checks if receive FIFO is full. \n\n * When the receive FIFO filling level reaches the configured size, FIFO full flag is set. * Any data received when the receive FIFO is full, is lost. - * + * * \parRelated APIs:
    * XMC_USIC_CH_RXFIFO_IsEmpty(), XMC_USIC_CH_RXFIFO_Flush() \n\n\n */ @@ -1892,7 +2084,7 @@ __STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsFull(XMC_USIC_CH_t *const channel) * When the receive FIFO is empty, received data will be put in receive FIFO. * When the last received word in the FIFO is read, FIFO empty flag is set. Any attempt * to read from an empty receive FIFO will set the receive FIFO error flag. - * + * * \parRelated APIs:
    * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n */ @@ -1910,9 +2102,9 @@ __STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsEmpty(XMC_USIC_CH_t *const channel) * \parDescription
    * Gets the receive FIFO filling level. \n\n * For every word received, the filling level is incremented. The API gives the value - * of this filling level. The filling level is decremented when the data is read out of the + * of this filling level. The filling level is decremented when the data is read out of the * receive FIFO. - * + * * \parRelated APIs:
    * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n */ @@ -1927,14 +2119,14 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t *const channe * @return Status of standard receive buffer, alternative receive buffer and receive buffer error events. \n * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR, * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE. - * + * * \parDescription
    * Gets the receive FIFO events' status. \n\n * Gives the status of receive FIFO standard receive buffer event, alternative receive buffer event and receive buffer error event. * The status bits are located at their bitpositions in the TRBSR register in the returned value. * User can make use of the XMC_USIC_CH_RXFIFO_EVENT enumeration for checking the status of return value. * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.
    - * + * * Note: Event status flags should be cleared by the user explicitly. * * \parRelated APIs:
    @@ -1943,8 +2135,8 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t *const channe __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channel) { return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_SRBI_Msk | - USIC_CH_TRBSR_RBERI_Msk | - USIC_CH_TRBSR_ARBI_Msk)); + USIC_CH_TRBSR_RBERI_Msk | + USIC_CH_TRBSR_ARBI_Msk)); } /** @@ -1958,16 +2150,16 @@ __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channe * \parDescription
    * Clears the receive FIFO event flags in the status register. \n\n * USIC channel peripheral does not clear the event flags after they are read. - * This API clears the events provided in the \a mask value. + * This API clears the events provided in the \a mask value. * XMC_USIC_CH_RXFIFO_EVENT enumeration can be used as input. Multiple events - * can be cleared by providing a mask value obtained by bitwise OR operation of + * can be cleared by providing a mask value obtained by bitwise OR operation of * multiple event enumerations. * * \parRelated APIs:
    * XMC_USIC_CH_RXFIFO_GetEvent() \n\n\n */ __STATIC_INLINE void XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t *const channel, - const uint32_t event) + const uint32_t event) { channel->TRBSCR = event; } @@ -2017,7 +2209,7 @@ __STATIC_INLINE void XMC_USIC_CH_DisableTimeMeasurement(XMC_USIC_CH_t *const cha * Sets the idle mode pin level for the master clock output. \n */ __STATIC_INLINE void XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level) + const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level) { channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_MCLKCFG_Msk)) | (uint32_t)passive_level; } @@ -2036,19 +2228,19 @@ __STATIC_INLINE void XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t *const * * \parDescription
    * Sets the idle mode shift clock output level and selects the shift clock source. \n\n - * Shift clock idle mode output level can be set to logic high or low. Shift clock output can be configured to have a + * Shift clock idle mode output level can be set to logic high or low. Shift clock output can be configured to have a * delay of half shift clock period. Both the configurations are available as enumeration values defined with type * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t. * This value should be configured based on the slave device requirement. * Shift clock source can be selected between internal clock(master) and external input(slave). - * + * */ __STATIC_INLINE void XMC_USIC_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, - const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) + const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, + const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output) { channel->BRG = (uint32_t)(channel->BRG & (~(USIC_CH_BRG_SCLKCFG_Msk | - USIC_CH_BRG_SCLKOSEL_Msk))) | + USIC_CH_BRG_SCLKOSEL_Msk))) | (uint32_t)passive_level | (uint32_t)clock_output; } @@ -2082,8 +2274,5 @@ __STATIC_INLINE void XMC_USIC_CH_SetMode(XMC_USIC_CH_t *const channel, const XMC * @} */ -/** - * @} - */ #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_vadc.h b/cores/xmc_lib/XMCLib/inc/xmc_vadc.h index a0191680..1b76d85e 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_vadc.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_vadc.h @@ -1,133 +1,57 @@ /** * @file xmc_vadc.h - * @date 2017-06-24 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-15: - * - Initial
    - * - * 2015-02-20: - * - Revised for XMC1201 device.
    - * - * 2015-04-27: - * - Added new APIs for SHS.
    - * - Added New APIs for trigger edge selection.
    - * - Added new APIs for Queue flush entries, boundary selection, Boundary node pointer.
    - * - Revised GatingMode APIs and EMUX Control Init API.
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API - * 2015-06-25: - * - BFL configuration in channel initialization fixed. - * - * 2015-07-28: - * - CLOCK_GATING_SUPPORTED and PERIPHERAL_RESET_SUPPORTED macros used - * - Clubbed the macro definitions for XMC13 XMC12 and XMC14 - * - Clubbed the macro definitions for XMC44 XMC47 and XMC48 - * - New APIs Created. - * - XMC_VADC_GLOBAL_SetIndividualBoundary - * - XMC_VADC_GROUP_SetIndividualBoundary - * - XMC_VADC_GROUP_GetAlias - * - XMC_VADC_GROUP_GetInputClass - * - XMC_VADC_GROUP_ChannelSetIclass - * - XMC_VADC_GROUP_ChannelGetResultAlignment - * - XMC_VADC_GROUP_ChannelGetInputClass - * - XMC_VADC_GROUP_SetResultSubtractionValue - * - * 2015-12-01: - * - Added: - * - XMC4300 device supported - * - * - Fixed: - * - XMC_VADC_GLOBAL_TriggerEvent API updated. OR operation removed. - * - XMC_VADC_GLOBAL_ClearEvent API updated. Multiple events triggering on clearing the event is fixed. - * - Wrong MACRO name defined in xmc_vadc_map.h file corrected for XMC4200/4100 devices. - * XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE - * - * 2015-12-01: - * - New APIs Created. - * - XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled - * - XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled - * - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range. - * - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100. - * - * 2016-03-09: - * - Optimization of write only registers - * - * 2016-03-18: - * - Fixed XMC_VADC_GLOBAL_SHS_IsConverterReady(): API checks the STEPCFG register for the ready bit instead of - * SHSCFG SFR. - * - * 2016-06-17: - * - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE - * - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t - * - New APIs added are: - * - XMC_VADC_GROUP_SetSyncSlaveReadySignal - * - XMC_VADC_GROUP_ChannelGetAssertedEvents - * - XMC_VADC_GROUP_GetAssertedResultEvents - * - XMC_VADC_GROUP_SetResultRegPriority - * - XMC_VADC_GROUP_SetSyncReadySignal - * - XMC_VADC_GROUP_GetSyncReadySignal - * - XMC_VADC_GROUP_GetResultRegPriority - * - * 2017-02-06: - * - Added new functions to remove channels from background request source, XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence() and XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels() - * - * 2017-06-24: - * - Added new function XMC_VADC_GLOBAL_SHS_SetAnalogReference() for XMC1 family - * - * @endcond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ #ifndef XMC_VADC_H #define XMC_VADC_H - + /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include -#include -#include +#include "xmc_common.h" +#include "xmc_scu.h" +#include "xmc_vadc_map.h" + -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ - /** * @addtogroup VADC * @brief Versatile Analog to Digital Converter (VADC) driver for XMC microcontroller family. @@ -183,7 +107,7 @@ *
    * @{ */ - + /********************************************************************************************************************* * MACROS ********************************************************************************************************************/ @@ -273,7 +197,7 @@ #define XMC_VADC_SHS_START_UP_CAL_ACTIVE (3U) /* Defines the need for SHS startup calibration activation for XMC1100 devices */ #define XMC_VADC_CONV_ENABLE_FOR_XMC11 (*(uint32_t*) 0x40010500UL) /* Defines the additional errata setting for - XMC1100 device for effective working*/ + XMC1100 device for effective working*/ #define XMC_VADC_EMUX_CH_SEL_STYLE (0U) /* Defines the external multiplexer channel selection mode of operation for a particular device*/ #define XMC_VADC_SHS_AVAILABLE (1U) /* Defines the availability of sample and hold module*/ @@ -377,7 +301,7 @@ typedef enum XMC_VADC_TRIGGER_INPUT_SELECT XMC_VADC_REQ_TR_N, /**< Trigger select signal N */ XMC_VADC_REQ_TR_O, /**< Trigger select signal O */ XMC_VADC_REQ_TR_P /**< Trigger select signal P */ - + } XMC_VADC_TRIGGER_INPUT_SELECT_t; /** @@ -404,7 +328,7 @@ typedef enum XMC_VADC_GATE_INPUT_SELECT XMC_VADC_REQ_GT_N, /**< Gating select signal N */ XMC_VADC_REQ_GT_O, /**< Gating select signal O */ XMC_VADC_REQ_GT_P /**< Gating select signal P */ - + } XMC_VADC_GATE_INPUT_SELECT_t; /** @@ -449,10 +373,10 @@ typedef enum XMC_VADC_CONVMODE typedef enum XMC_VADC_FAST_COMPARE { XMC_VADC_FAST_COMPARE_LOW = 0, /**< Input lower than than programmed reference */ - XMC_VADC_FAST_COMPARE_HIGH , /**< Input higher than than programmed reference */ + XMC_VADC_FAST_COMPARE_HIGH, /**< Input higher than than programmed reference */ XMC_VADC_FAST_COMPARE_UNKNOWN /**< Unknown, Conversion probably still ongoing */ } XMC_VADC_FAST_COMPARE_t; - + /** * Defines the type of scan request source to be used. It can choose between auto scan and background scan request * source methods. Use @ref XMC_VADC_SCAN_TYPE_t for this enumeration. @@ -532,7 +456,7 @@ typedef enum XMC_VADC_CHANNEL_REF XMC_VADC_CHANNEL_REF_INTREF = 0, /**< Internal VARef */ XMC_VADC_CHANNEL_REF_ALT_CH0 /**< External voltage available on Channel-0 of the perticular group */ } XMC_VADC_CHANNEL_REF_t; - + /** * Defines the criteria for boundary flag assertion. Use @ref XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t for this * enumeration. @@ -542,7 +466,7 @@ typedef enum XMC_VADC_CHANNEL_BOUNDARY_CONDITION XMC_VADC_CHANNEL_BOUNDARY_CONDITION_ABOVE_BAND = 0, /**< Set Boundary condition criteria to assert above the band */ XMC_VADC_CHANNEL_BOUNDARY_CONDITION_BELOW_BAND /**< Set Boundary condition criteria to assert below the band */ } XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t; - + /** * Defines the event which can lead to a global service request assertion. Use @ref XMC_VADC_GLOBAL_EVENT_t for this * enumeration. @@ -552,7 +476,7 @@ typedef enum XMC_VADC_GLOBAL_EVENT XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE = VADC_GLOBEFLAG_SEVGLB_Msk, /**< Background scan request source event */ XMC_VADC_GLOBAL_EVENT_RESULT = VADC_GLOBEFLAG_REVGLB_Msk /**< Global result event */ } XMC_VADC_GLOBAL_EVENT_t; - + /** * Defines the power modes of a VADC Group. Use @ref XMC_VADC_GROUP_POWERMODE_t for this enumeration. */ @@ -631,7 +555,7 @@ typedef enum XMC_VADC_RESULT_ALIGN XMC_VADC_RESULT_ALIGN_RIGHT /**< Always align result to right */ } XMC_VADC_RESULT_ALIGN_t; -typedef enum XMC_VADC_RESULT_SUBTRATION +typedef enum XMC_VADC_RESULT_SUBTRATION { XMC_VADC_RESULT_SUBTRATION_12BIT_LEFT_ALIGN = 0U, /**< Always align result to left */ XMC_VADC_RESULT_SUBTRATION_12BIT_RIGHT_ALIGN = 0U, /**< Always align result to right */ @@ -646,22 +570,22 @@ typedef enum XMC_VADC_RESULT_SUBTRATION */ typedef enum XMC_VADC_GROUP_RS_PRIORITY { - XMC_VADC_GROUP_RS_PRIORITY_0 = 0, /**< Lowest priority for the request source*/ - XMC_VADC_GROUP_RS_PRIORITY_1, /**< Second lowest priority for the request source*/ - XMC_VADC_GROUP_RS_PRIORITY_2, /**< Second highest priority for the request source*/ - XMC_VADC_GROUP_RS_PRIORITY_3, /**< Highest priority for the request source*/ -}XMC_VADC_GROUP_RS_PRIORITY_t; + XMC_VADC_GROUP_RS_PRIORITY_0 = 0, /**< Lowest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_1, /**< Second lowest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_2, /**< Second highest priority for the request source*/ + XMC_VADC_GROUP_RS_PRIORITY_3, /**< Highest priority for the request source*/ +} XMC_VADC_GROUP_RS_PRIORITY_t; /** * Defines the various modes for the boundary flag. Use @ref XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t for this enumeration. */ typedef enum XMC_VADC_GROUP_BOUNDARY_FLAG_MODE { - XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_DISABLED = 0, /**< Disable boundary flag*/ - XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED, /**< Always enable boundary*/ - XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_LOW, /**< Enable boundary flag when gate level is 0*/ - XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_HIGH /**< Enable boundary flag when gate level is 1*/ -}XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t; + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_DISABLED = 0, /**< Disable boundary flag*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED, /**< Always enable boundary*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_LOW, /**< Enable boundary flag when gate level is 0*/ + XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_HIGH /**< Enable boundary flag when gate level is 1*/ +} XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t; /** @@ -671,7 +595,7 @@ typedef enum XMC_VADC_BOUNDARY_SELECT { XMC_VADC_BOUNDARY_SELECT_LOWER_BOUND = 0U, /**< Select the lower boundary*/ XMC_VADC_BOUNDARY_SELECT_UPPER_BOUND = 2U /**< Selects the upper boundary*/ -}XMC_VADC_BOUNDARY_SELECT_t; +} XMC_VADC_BOUNDARY_SELECT_t; /** @@ -679,13 +603,13 @@ typedef enum XMC_VADC_BOUNDARY_SELECT */ typedef enum XMC_VADC_GROUP_INDEX { - XMC_VADC_GROUP_INDEX_0 = 0, - XMC_VADC_GROUP_INDEX_1, + XMC_VADC_GROUP_INDEX_0 = 0, + XMC_VADC_GROUP_INDEX_1, #if (XMC_VADC_MAXIMUM_NUM_GROUPS > 2U) - XMC_VADC_GROUP_INDEX_2, - XMC_VADC_GROUP_INDEX_3 + XMC_VADC_GROUP_INDEX_2, + XMC_VADC_GROUP_INDEX_3 #endif -}XMC_VADC_GROUP_INDEX_t; +} XMC_VADC_GROUP_INDEX_t; /** * Defines channel alias. @@ -711,9 +635,9 @@ typedef enum XMC_VADC_CHANNEL_ALIAS */ typedef enum XMC_VADC_GLOBAL_SHS_AREF { - XMC_VADC_GLOBAL_SHS_AREF_EXTERNAL_VDD_UPPER_RANGE = 0, /**< External reference, upper supply range, e.g. VDD >= 3.0V */ - XMC_VADC_GLOBAL_SHS_AREF_INTERNAL_VDD_UPPER_RANGE = 2, /**< Internal reference, upper supply range, e.g. VDD >= 3.0V */ - XMC_VADC_GLOBAL_SHS_AREF_INTERNAL_VDD_LOWER_RANGE = 3, /**< Internal reference, lower supply range, e.g. VDD < 3.0V */ + XMC_VADC_GLOBAL_SHS_AREF_EXTERNAL_VDD_UPPER_RANGE = 0 << SHS_SHSCFG_AREF_Pos, /**< External reference, upper supply range, e.g. VDD >= 3.0V */ + XMC_VADC_GLOBAL_SHS_AREF_INTERNAL_VDD_UPPER_RANGE = 2 << SHS_SHSCFG_AREF_Pos, /**< Internal reference, upper supply range, e.g. VDD >= 3.0V */ + XMC_VADC_GLOBAL_SHS_AREF_INTERNAL_VDD_LOWER_RANGE = 3 << SHS_SHSCFG_AREF_Pos, /**< Internal reference, lower supply range, e.g. VDD < 3.0V */ } XMC_VADC_GLOBAL_SHS_AREF_t; #if(XMC_VADC_SHS_FULL_SET_REG == 1U) @@ -726,7 +650,7 @@ typedef enum XMC_VADC_SHS_GAIN_LEVEL XMC_VADC_SHS_GAIN_LEVEL_1 = SHS_CALOC0_CALOFFVAL1_Pos, /**< Select the calibration value for gain level 1 */ XMC_VADC_SHS_GAIN_LEVEL_2 = SHS_CALOC0_CALOFFVAL2_Pos, /**< Select the calibration value for gain level 2 */ XMC_VADC_SHS_GAIN_LEVEL_3 = SHS_CALOC0_CALOFFVAL3_Pos /**< Select the calibration value for gain level 3 */ -}XMC_VADC_SHS_GAIN_LEVEL_t; +} XMC_VADC_SHS_GAIN_LEVEL_t; #endif /** @@ -736,7 +660,7 @@ typedef enum XMC_VADC_SHS_LOOP_CH { XMC_VADC_SHS_LOOP_CH_0 = SHS_LOOP_LPCH0_Pos, /**< Select Delta-sigma loop 0*/ XMC_VADC_SHS_LOOP_CH_1 = SHS_LOOP_LPCH1_Pos /**< Select Delta-sigma loop 1*/ -}XMC_VADC_SHS_LOOP_CH_t; +} XMC_VADC_SHS_LOOP_CH_t; /** * Provides the order in which the SHS should do the calibration @@ -745,7 +669,7 @@ typedef enum XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER { XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_POST_CONV = 0, /**< Calibration occur after conversion takes place */ XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_PRE_CONV /**< Calibration occur before conversion takes place */ -}XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t; +} XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t; #endif #if (XMC_VADC_BOUNDARY_FLAG_SELECT == 1U) @@ -762,7 +686,7 @@ typedef enum XMC_VADC_BOUNDARY_NODE XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_1, /**Range:[0x0 to 0x7] */ - uint32_t refill_needed : 1; /**< Conversion completed channel gets inserted back into the queue */ - uint32_t generate_interrupt : 1; /**< Generates a queue request source event */ - uint32_t external_trigger : 1; /**< Conversion requests are raised on an external trigger. */ - uint32_t : 24; - - }; - uint32_t qinr0; + uint32_t channel_num : 5; /**< Channel number associated with this queue entry.
    Range:[0x0 to 0x7] */ + uint32_t refill_needed : 1; /**< Conversion completed channel gets inserted back into the queue */ + uint32_t generate_interrupt : 1; /**< Generates a queue request source event */ + uint32_t external_trigger : 1; /**< Conversion requests are raised on an external trigger. */ + uint32_t : 24; + }; + uint32_t qinr0; + }; } XMC_VADC_QUEUE_ENTRY_t; /** @@ -963,46 +887,46 @@ typedef struct XMC_VADC_QUEUE_ENTRY */ typedef struct XMC_VADC_QUEUE_CONFIG { - uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request sources of the same + uint32_t conv_start_mode : 2; /**< One converter is shared between the queue and scan request sources of the same group. This field determines how queue request source would request for conversion. Uses @ref XMC_VADC_STARTMODE_t */ - uint32_t req_src_priority : 2; /**< Request source priority for the arbiter.Uses @ref XMC_VADC_GROUP_RS_PRIORITY_t */ - union + uint32_t req_src_priority : 2; /**< Request source priority for the arbiter.Uses @ref XMC_VADC_GROUP_RS_PRIORITY_t */ + union + { + struct { - struct - { #if(XMC_VADC_GROUP_SRCREG_AVAILABLE == (1U)) - uint32_t src_specific_result_reg : 4; /**< Uses any one Group related result register as the destination + uint32_t src_specific_result_reg : 4; /**< Uses any one Group related result register as the destination for all conversions results. To use the individual result register from each channel configuration, configure this field with 0x0 */ #else - uint32_t : 4; + uint32_t : 4; #endif - uint32_t : 4; - uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger. + uint32_t : 4; + uint32_t trigger_signal : 4; /**< Select one of the 16 possibilities for trigger. Uses @ref XMC_VADC_TRIGGER_INPUT_SELECT_t */ - uint32_t : 1; - uint32_t trigger_edge : 2; /**< Edge selection for trigger signal. + uint32_t : 1; + uint32_t trigger_edge : 2; /**< Edge selection for trigger signal. Uses @ref XMC_VADC_TRIGGER_EDGE_t */ - uint32_t : 1; - uint32_t gate_signal : 4; /**< Select one of the 16 possibilities for gating. + uint32_t : 1; + uint32_t gate_signal : 4; /**< Select one of the 16 possibilities for gating. Uses @ref XMC_VADC_GATE_INPUT_SELECT_t */ - uint32_t : 8; - uint32_t timer_mode : 1; /**< Timer mode for equi-distant sampling shall be activated or not? */ - uint32_t : 3; - }; - uint32_t qctrl0; + uint32_t : 8; + uint32_t timer_mode : 1; /**< Timer mode for equi-distant sampling shall be activated or not? */ + uint32_t : 3; }; - union + uint32_t qctrl0; + }; + union + { + struct { - struct - { - uint32_t : 2; - uint32_t external_trigger : 1; /**< Are external triggers supported? */ - uint32_t : 29; - }; - uint32_t qmr0; + uint32_t : 2; + uint32_t external_trigger : 1; /**< Are external triggers supported? */ + uint32_t : 29; }; + uint32_t qmr0; + }; } XMC_VADC_QUEUE_CONFIG_t; @@ -1012,29 +936,29 @@ typedef struct XMC_VADC_QUEUE_CONFIG */ typedef struct XMC_VADC_GLOBAL_CLASS { - union + union + { + struct { - struct - { - uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC + uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC
    Range: [0x0 to 0x1F] */ - uint32_t : 3; - uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. + uint32_t : 3; + uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. Uses @ref XMC_VADC_CONVMODE_t */ - uint32_t : 5; + uint32_t : 5; #if(XMC_VADC_EMUX_AVAILABLE == 1U) - uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX + uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX
    Range: [0x0 to 0x1F] */ - uint32_t : 3; - uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. + uint32_t : 3; + uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. Uses @ref XMC_VADC_CONVMODE_t */ - uint32_t : 5; + uint32_t : 5; #else - uint32_t : 16; + uint32_t : 16; #endif - }; - uint32_t globiclass; }; + uint32_t globiclass; + }; } XMC_VADC_GLOBAL_CLASS_t; #if (XMC_VADC_GROUP_AVAILABLE != 0U) @@ -1043,20 +967,20 @@ typedef struct XMC_VADC_GLOBAL_CLASS */ typedef struct XMC_VADC_GLOBAL_CLOCK { - union + union + { + struct { - struct - { - - uint32_t analog_clock_divider : 5; /**< Clock for the converter.
    Range: [0x0 to 0x1F] */ - uint32_t : 2; - uint32_t msb_conversion_clock : 1; /**< Additional clock cycle for analog converter */ - uint32_t arbiter_clock_divider : 2; /**< Request source arbiter clock divider.
    Range: [0x0 to 0x3] */ - uint32_t : 5; - uint32_t : 17; - }; - uint32_t globcfg; + + uint32_t analog_clock_divider : 5; /**< Clock for the converter.
    Range: [0x0 to 0x1F] */ + uint32_t : 2; + uint32_t msb_conversion_clock : 1; /**< Additional clock cycle for analog converter */ + uint32_t arbiter_clock_divider : 2; /**< Request source arbiter clock divider.
    Range: [0x0 to 0x3] */ + uint32_t : 5; + uint32_t : 17; }; + uint32_t globcfg; + }; } XMC_VADC_GLOBAL_CLOCK_t; #endif @@ -1066,47 +990,47 @@ typedef struct XMC_VADC_GLOBAL_CLOCK */ typedef struct XMC_VADC_GLOBAL_CONFIG { - union + union + { + struct { - struct - { - uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ - uint32_t : 4; - uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ - uint32_t : 4; - }; - uint32_t globbound; + uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; }; + uint32_t globbound; + }; #if (XMC_VADC_GROUP_AVAILABLE != 0U) - XMC_VADC_GLOBAL_CLOCK_t clock_config; /**< ADC clock configurations*/ + XMC_VADC_GLOBAL_CLOCK_t clock_config; /**< ADC clock configurations*/ #endif - XMC_VADC_GLOBAL_CLASS_t class0; /**< ADC input conversion configurations for GLOBICLASS[0]*/ - XMC_VADC_GLOBAL_CLASS_t class1; /**< ADC input conversion configurations for GLOBICLASS[1]*/ - union + XMC_VADC_GLOBAL_CLASS_t class0; /**< ADC input conversion configurations for GLOBICLASS[0]*/ + XMC_VADC_GLOBAL_CLASS_t class1; /**< ADC input conversion configurations for GLOBICLASS[1]*/ + union + { + struct { - struct - { - uint32_t : 16; - uint32_t data_reduction_control : 4; /**< Data reduction stages */ - uint32_t : 4; - uint32_t wait_for_read_mode : 1; /**< Results of the next conversion will not be overwritten in the + uint32_t : 16; + uint32_t data_reduction_control : 4; /**< Data reduction stages */ + uint32_t : 4; + uint32_t wait_for_read_mode : 1; /**< Results of the next conversion will not be overwritten in the result register until the previous value is read*/ - uint32_t : 6; - uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ - }; - uint32_t globrcr; + uint32_t : 6; + uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ }; - union + uint32_t globrcr; + }; + union + { + struct { - struct - { - uint32_t module_disable : 1; /**< Disables the module clock.*/ - uint32_t : 2; - uint32_t disable_sleep_mode_control : 1; /**< Set it to true in order to disable the Sleep mode */ - uint32_t : 28; - }; - uint32_t clc; + uint32_t module_disable : 1; /**< Disables the module clock.*/ + uint32_t : 2; + uint32_t disable_sleep_mode_control : 1; /**< Set it to true in order to disable the Sleep mode */ + uint32_t : 28; }; + uint32_t clc; + }; } XMC_VADC_GLOBAL_CONFIG_t; @@ -1116,25 +1040,25 @@ typedef struct XMC_VADC_GLOBAL_CONFIG */ typedef struct XMC_VADC_GROUP_CLASS { - union + union + { + struct { - struct - { - uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC + uint32_t sample_time_std_conv : 5; /**< Sample time for channels directly connected to VADC
    Range: [0x0 to 0x1F] */ - uint32_t : 3; - uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. + uint32_t : 3; + uint32_t conversion_mode_standard : 3; /**< Conversion mode for channels directly connected to VADC. Uses @ref XMC_VADC_CONVMODE_t */ - uint32_t : 5; - uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX + uint32_t : 5; + uint32_t sampling_phase_emux_channel : 5; /**< Sample time for channels connected via EMUX
    Range: [0x0 to 0x1F] */ - uint32_t : 3; - uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. + uint32_t : 3; + uint32_t conversion_mode_emux : 3; /**< Conversion mode for channels connected via EMUX to VADC. Uses @ref XMC_VADC_CONVMODE_t */ - uint32_t : 5; - }; - uint32_t g_iclass0; + uint32_t : 5; }; + uint32_t g_iclass0; + }; } XMC_VADC_GROUP_CLASS_t; @@ -1143,34 +1067,34 @@ typedef struct XMC_VADC_GROUP_CLASS */ typedef struct XMC_VADC_GROUP_EMUXCFG { - union + union + { + struct { - struct - { - uint32_t starting_external_channel : 3; /**< External channel number to which the VADC will + uint32_t starting_external_channel : 3; /**< External channel number to which the VADC will generate a control signal (needed to select the analog input in the analog multiplexer)*/ - uint32_t : 13; + uint32_t : 13; #if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) - uint32_t connected_channel : 10; /**< The Channel to which the EMUX is connected. */ + uint32_t connected_channel : 10; /**< The Channel to which the EMUX is connected. */ #else - uint32_t connected_channel : 5; /**< The Channel to which the EMUX is connected. */ - uint32_t : 5; + uint32_t connected_channel : 5; /**< The Channel to which the EMUX is connected. */ + uint32_t : 5; #endif - uint32_t emux_mode : 2; /**< Selects the external multiplexer modes: Steady, Single Mode, step etc + uint32_t emux_mode : 2; /**< Selects the external multiplexer modes: Steady, Single Mode, step etc Uses @ref XMC_VADC_GROUP_EMUXMODE_t*/ - uint32_t emux_coding : 1; /**< Select Binary or Gray coding. Uses @ref XMC_VADC_GROUP_EMUXCODE_t*/ - uint32_t stce_usage : 1; /**< Use STCE for each conversion of an external channel */ + uint32_t emux_coding : 1; /**< Select Binary or Gray coding. Uses @ref XMC_VADC_GROUP_EMUXCODE_t*/ + uint32_t stce_usage : 1; /**< Use STCE for each conversion of an external channel */ #if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) - uint32_t emux_channel_select_style : 1; /**< Selects the style of configuring the \b connected_channel + uint32_t emux_channel_select_style : 1; /**< Selects the style of configuring the \b connected_channel (Each bit represents the channel or entire field represents the channel number ) */ - uint32_t : 1; + uint32_t : 1; #else - uint32_t : 2; + uint32_t : 2; #endif - }; - uint32_t g_emuxctr; }; + uint32_t g_emuxctr; + }; } XMC_VADC_GROUP_EMUXCFG_t; @@ -1180,33 +1104,33 @@ typedef struct XMC_VADC_GROUP_EMUXCFG typedef struct XMC_VADC_GROUP_CONFIG { - XMC_VADC_GROUP_EMUXCFG_t emux_config; /**< External multiplexer related configurations */ - XMC_VADC_GROUP_CLASS_t class0; /**< ADC input conversion configurations for GxICLASS[0]*/ - XMC_VADC_GROUP_CLASS_t class1; /**< ADC input conversion configurations for GxICLASS[1]*/ - union + XMC_VADC_GROUP_EMUXCFG_t emux_config; /**< External multiplexer related configurations */ + XMC_VADC_GROUP_CLASS_t class0; /**< ADC input conversion configurations for GxICLASS[0]*/ + XMC_VADC_GROUP_CLASS_t class1; /**< ADC input conversion configurations for GxICLASS[1]*/ + union + { + struct { - struct - { - uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ - uint32_t : 4; - uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ - uint32_t : 4; - }; - uint32_t g_bound; + uint32_t boundary0 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; + uint32_t boundary1 : 12; /**< Boundary value for results comparison*/ + uint32_t : 4; }; - union + uint32_t g_bound; + }; + union + { + struct { - struct - { - uint32_t : 4; - uint32_t arbitration_round_length : 2; /**< Number of arbiter slots to be considered */ - uint32_t : 1; - uint32_t arbiter_mode : 1; /**< Arbiter mode - Select either Continuous mode or Demand based. + uint32_t : 4; + uint32_t arbitration_round_length : 2; /**< Number of arbiter slots to be considered */ + uint32_t : 1; + uint32_t arbiter_mode : 1; /**< Arbiter mode - Select either Continuous mode or Demand based. Uses @ref XMC_VADC_GROUP_ARBMODE_t */ - uint32_t : 24; - }; - uint32_t g_arbcfg; + uint32_t : 24; }; + uint32_t g_arbcfg; + }; } XMC_VADC_GROUP_CONFIG_t; /** @@ -1215,24 +1139,24 @@ typedef struct XMC_VADC_GROUP_CONFIG typedef struct XMC_VADC_RESULT_CONFIG { - union + union + { + struct { - struct - { - uint32_t : 16; - uint32_t data_reduction_control : 4; /**< Configures the data reduction stages */ - uint32_t post_processing_mode : 2; /**< Result data processing mode. Uses @ref XMC_VADC_DMM_t + uint32_t : 16; + uint32_t data_reduction_control : 4; /**< Configures the data reduction stages */ + uint32_t post_processing_mode : 2; /**< Result data processing mode. Uses @ref XMC_VADC_DMM_t For normal operation select XMC_VADC_DMM_t::XMC_VADC_DMM_REDUCTION_MODE and data_reduction_control as 0*/ - uint32_t : 2; - uint32_t wait_for_read_mode : 1; /**< Allow the conversion only after previous results are read*/ - uint32_t part_of_fifo : 2; /**< Make the result register a part of Result FIFO? */ - uint32_t : 4; - uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ - }; - uint32_t g_rcr; + uint32_t : 2; + uint32_t wait_for_read_mode : 1; /**< Allow the conversion only after previous results are read*/ + uint32_t part_of_fifo : 2; /**< Make the result register a part of Result FIFO? */ + uint32_t : 4; + uint32_t event_gen_enable : 1; /**< Generates an event on availability of new result. */ }; + uint32_t g_rcr; + }; } XMC_VADC_RESULT_CONFIG_t; #if(XMC_VADC_SHS_AVAILABLE == 1U) @@ -1246,35 +1170,35 @@ typedef struct XMC_VADC_GLOBAL_SHS_STEP_CONFIG { struct { - uint32_t sh_unit_step0 :3; /**< Select a Sample and hold unit for the stepper's step number 0. + uint32_t sh_unit_step0 : 3; /**< Select a Sample and hold unit for the stepper's step number 0. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step0 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step1 :3; /**< Select a Sample and hold unit for the stepper's step number 1. + uint32_t enable_step0 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step1 : 3; /**< Select a Sample and hold unit for the stepper's step number 1. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step1 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step2 :3; /**< Select a Sample and hold unit for the stepper's step number 2. + uint32_t enable_step1 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step2 : 3; /**< Select a Sample and hold unit for the stepper's step number 2. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step2 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step3 :3; /**< Select a Sample and hold unit for the stepper's step number 3. + uint32_t enable_step2 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step3 : 3; /**< Select a Sample and hold unit for the stepper's step number 3. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step3 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step4 :3; /**< Select a Sample and hold unit for the stepper's step number 4. + uint32_t enable_step3 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step4 : 3; /**< Select a Sample and hold unit for the stepper's step number 4. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step4 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step5 :3; /**< Select a Sample and hold unit for the stepper's step number 5. + uint32_t enable_step4 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step5 : 3; /**< Select a Sample and hold unit for the stepper's step number 5. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step5 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step6 :3; /**< Select a Sample and hold unit for the stepper's step number 6. + uint32_t enable_step5 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step6 : 3; /**< Select a Sample and hold unit for the stepper's step number 6. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step6 :1; /**< Should the step be added to the sequence */ - uint32_t sh_unit_step7 :3; /**< Select a Sample and hold unit for the stepper's step number 7. + uint32_t enable_step6 : 1; /**< Should the step be added to the sequence */ + uint32_t sh_unit_step7 : 3; /**< Select a Sample and hold unit for the stepper's step number 7. Uses @ref XMC_VADC_GROUP_INDEX_t*/ - uint32_t enable_step7 :1; /**< Should the step be added to the sequence */ + uint32_t enable_step7 : 1; /**< Should the step be added to the sequence */ }; uint32_t stepcfg; }; -}XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t; +} XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t; #endif /** * Sample and hold Initialization structure @@ -1286,62 +1210,85 @@ typedef struct XMC_VADC_GLOBAL_SHS_CONFIG struct { #if(XMC_VADC_SHS_FULL_SET_REG == 1U) - uint32_t shs_clock_divider :4; /**< The divider value for the SHS clock. Range: [0x0 to 0xF]*/ - uint32_t :6; + uint32_t shs_clock_divider : 4; /**< The divider value for the SHS clock. Range: [0x0 to 0xF]*/ + uint32_t : 6; #else - uint32_t :10; -#endif - uint32_t analog_reference_select :2; /**< It is possible to different reference voltage for the SHS modules*/ - uint32_t :20; + uint32_t : 10; +#endif + uint32_t analog_reference_select : 2; /**< It is possible to different reference voltage for the SHS modules*/ + uint32_t : 20; }; uint32_t shscfg; }; #if(XMC_VADC_SHS_FULL_SET_REG == 1U) XMC_VADC_GLOBAL_SHS_CALIBRATION_ORDER_t calibration_order; /**< order in which the calibration should be taken up*/ #endif -}XMC_VADC_GLOBAL_SHS_CONFIG_t; +} XMC_VADC_GLOBAL_SHS_CONFIG_t; #endif + /** - * Detailed result structure + * Detailed global result structure */ - typedef struct XMC_VADC_DETAILED_RESULT +typedef struct XMC_VADC_GLOBAL_DETAILED_RESULT { union { struct { - uint32_t result :16; /**< Result of the Analog to digital conversion*/ - uint32_t data_reduction_counter :4; /**< Results reduction counter value*/ - uint32_t channel_number :5; /**< Converted channel number*/ - uint32_t emux_channel_number :3; /**< Converted external multiplexer channel number. + uint32_t result : 16; /**< Result of the Analog to digital conversion*/ + uint32_t group_number : 4; /**< Indicates the group to which the channel_number refers*/ + uint32_t channel_number : 5; /**< Converted channel number*/ + uint32_t emux_channel_number : 3; /**< Converted external multiplexer channel number. Only applicable for GxRES[0] result register*/ - uint32_t converted_request_source :2; /**< Converted request source*/ - uint32_t fast_compare_result :1; /**< Fast compare result if conversion mode is fast compare mode.*/ - uint32_t vaild_result :1; /**< Valid flag is set when a new result is available*/ + uint32_t converted_request_source : 2; /**< Converted request source*/ + uint32_t fast_compare_result : 1; /**< Fast compare result if conversion mode is fast compare mode.*/ + uint32_t vaild_result : 1; /**< Valid flag is set when a new result is available*/ }; uint32_t res; }; -}XMC_VADC_DETAILED_RESULT_t; - +} XMC_VADC_GLOBAL_DETAILED_RESULT_t; + +/** + * Detailed channel result structure + */ +typedef struct XMC_VADC_DETAILED_RESULT +{ + union + { + struct + { + uint32_t result : 16; /**< Result of the Analog to digital conversion*/ + uint32_t data_reduction_counter : 4; /**< Results reduction counter value*/ + uint32_t channel_number : 5; /**< Converted channel number*/ + uint32_t emux_channel_number : 3; /**< Converted external multiplexer channel number. + Only applicable for GxRES[0] result register*/ + uint32_t converted_request_source : 2; /**< Converted request source*/ + uint32_t fast_compare_result : 1; /**< Fast compare result if conversion mode is fast compare mode.*/ + uint32_t vaild_result : 1; /**< Valid flag is set when a new result is available*/ + }; + uint32_t res; + }; +} XMC_VADC_DETAILED_RESULT_t; + /*Anonymous structure/union guard end*/ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * static inline functions ********************************************************************************************************************/ -#if (XMC_VADC_GROUP_AVAILABLE == 1U) +#if (XMC_VADC_GROUP_AVAILABLE == 1U) __STATIC_INLINE bool XMC_VADC_CHECK_GROUP_PTR(XMC_VADC_GROUP_t *const group_ptr) { #if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) - return((group_ptr == VADC_G0) || (group_ptr == VADC_G1) || (group_ptr == VADC_G2) || (group_ptr == VADC_G3)); + return ((group_ptr == VADC_G0) || (group_ptr == VADC_G1) || (group_ptr == VADC_G2) || (group_ptr == VADC_G3)); #else - return((group_ptr == VADC_G0) || (group_ptr == VADC_G1)); + return ((group_ptr == VADC_G0) || (group_ptr == VADC_G1)); #endif } #endif @@ -1510,9 +1457,6 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_ClockInit(XMC_VADC_GLOBAL_t *const global_p } #endif -#ifdef INCLUDE_UNUSED_FUNCTION_XMC_VADC_H -// Function not used in XMC-for-Arduino and commented out to remove compiler warnings -// TODO: If XMC Library is updated, check this function again /** * * @param global_ptr Constant pointer to the VADC module. @@ -1532,11 +1476,9 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_ClockInit(XMC_VADC_GLOBAL_t *const global_p * None * */ -#if( UC_SERIES != XMC11 ) + void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLASS_t config, - const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num); -#endif -#endif + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num); /** * @@ -1557,14 +1499,14 @@ void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const X * */ - __STATIC_INLINE void XMC_VADC_GLOBAL_ResultInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_CONFIG_t *config) - { +__STATIC_INLINE void XMC_VADC_GLOBAL_ResultInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_RESULT_CONFIG_t *config) +{ XMC_ASSERT("XMC_VADC_GLOBAL_ResultInit:Wrong Module Pointer", (global_ptr == VADC)) /* Configure GLOBRCR*/ global_ptr->GLOBRCR = config->g_rcr; - } - +} + /** * * @param global_ptr Constant pointer to the VADC module. @@ -1700,8 +1642,8 @@ void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, const ui * */ void XMC_VADC_GLOBAL_SetIndividualBoundary(XMC_VADC_GLOBAL_t *const global_ptr, - const XMC_VADC_CHANNEL_BOUNDARY_t selection, - const uint16_t boundary_value); + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value); #endif #if (XMC_VADC_EMUX_AVAILABLE== 1U) @@ -1736,6 +1678,8 @@ void XMC_VADC_GLOBAL_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const * the result register GLOBRES for the validity of the data. If the validity is assured, data is first read * the global result register, cached locally next and subsequently returned to the caller. * + * @note You can cast the return to a varible of type XMC_VADC_GLOBAL_DETAILED_RESULT_t to easily access the register bit fields + * * \parRelated APIs:
    * XMC_VADC_GLOBAL_GetResult() */ @@ -1743,7 +1687,7 @@ __STATIC_INLINE uint32_t XMC_VADC_GLOBAL_GetDetailedResult(XMC_VADC_GLOBAL_t *co { XMC_ASSERT("XMC_VADC_GLOBAL_GetDetailedResult:Wrong Module Pointer", (global_ptr == VADC)) - return(global_ptr->GLOBRES); + return (global_ptr->GLOBRES); } /** @@ -1822,8 +1766,8 @@ XMC_VADC_FAST_COMPARE_t XMC_VADC_GLOBAL_GetCompareResult(XMC_VADC_GLOBAL_t *cons __STATIC_INLINE void XMC_VADC_GLOBAL_TriggerEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) { XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Module Pointer", (global_ptr == VADC)) - XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Global Event", - ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) + XMC_ASSERT("XMC_VADC_GLOBAL_TriggerEvent:Wrong Global Event", + ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) global_ptr->GLOBEFLAG = event_type; } @@ -1846,8 +1790,8 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_TriggerEvent(XMC_VADC_GLOBAL_t *const globa __STATIC_INLINE void XMC_VADC_GLOBAL_ClearEvent(XMC_VADC_GLOBAL_t *const global_ptr, const uint32_t event_type) { XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Module Pointer", (global_ptr == VADC)) - XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Global Event", - ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) + XMC_ASSERT("XMC_VADC_GLOBAL_ClearEvent:Wrong Global Event", + ((XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE == event_type) || (XMC_VADC_GLOBAL_EVENT_RESULT == event_type))) global_ptr->GLOBEFLAG = ((uint32_t)(event_type << (uint32_t)16)); } @@ -1900,7 +1844,7 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co * \parRelated APIs:
    * None. */ - void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config); +void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -1914,61 +1858,61 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co * \parRelated APIs:
    * None. */ - __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetAnalogReference(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - const XMC_VADC_GLOBAL_SHS_AREF_t aref) - { +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetAnalogReference(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + const XMC_VADC_GLOBAL_SHS_AREF_t aref) +{ XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) - shs_ptr->SHSCFG |= (shs_ptr->SHSCFG & (uint32_t)~SHS_SHSCFG_AREF_Msk) | (uint32_t)aref; - } + shs_ptr->SHSCFG = (shs_ptr->SHSCFG & (uint32_t)~SHS_SHSCFG_AREF_Msk) | (uint32_t)aref | SHS_SHSCFG_SCWC_Msk; +} #if(XMC_VADC_SHS_FULL_SET_REG == 1U) - /** - * @param shs_ptr Constant pointer to the VADC Sample and hold module - * @param config Struct consisting of various step configurations. - * - * @return None - * - * \parDescription:
    - * Configures the stepper sequence for the converter.
    \n - * Stepper of the SHS can be configured to take up a specific sequence of groups for conversion. - * The stepper sequence is configured using this API. - * - * \parRelated APIs:
    - * None. - */ - __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetStepperSequence(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - const XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t *config) - { +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * @param config Struct consisting of various step configurations. + * + * @return None + * + * \parDescription:
    + * Configures the stepper sequence for the converter.
    \n + * Stepper of the SHS can be configured to take up a specific sequence of groups for conversion. + * The stepper sequence is configured using this API. + * + * \parRelated APIs:
    + * None. + */ +__STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetStepperSequence(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, + const XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t *config) +{ XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_StepperInit:Wrong config pointer", - (config == (XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t*)NULL)) + (config == (XMC_VADC_GLOBAL_SHS_STEP_CONFIG_t *)NULL)) shs_ptr->STEPCFG = (uint32_t) config->stepcfg; - } +} #endif - /** - * @param shs_ptr Constant pointer to the VADC Sample and hold module - * - * @return bool returns true if the analog converter is operable - * returns false if the analog converter is powered down - * - * \parDescription:
    - * Returns the converter status.
    \n - * Returns the ANRDY bit field of the SHSCFG register. - * - * \parRelated APIs:
    - * None. - */ - __STATIC_INLINE bool XMC_VADC_GLOBAL_SHS_IsConverterReady(XMC_VADC_GLOBAL_SHS_t *const shs_ptr) - { - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_IsConverterReady:Wrong SHS Pointer",(shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) - - return((bool)((shs_ptr->SHSCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1)); - } +/** + * @param shs_ptr Constant pointer to the VADC Sample and hold module + * + * @return bool returns true if the analog converter is operable + * returns false if the analog converter is powered down + * + * \parDescription:
    + * Returns the converter status.
    \n + * Returns the ANRDY bit field of the SHSCFG register. + * + * \parRelated APIs:
    + * None. + */ +__STATIC_INLINE bool XMC_VADC_GLOBAL_SHS_IsConverterReady(XMC_VADC_GLOBAL_SHS_t *const shs_ptr) +{ + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_IsConverterReady:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) + + return ((bool)((shs_ptr->SHSCFG >> (uint32_t)SHS_SHSCFG_ANRDY_Pos) & (uint32_t)0x1)); +} #if(XMC_VADC_SHS_FULL_SET_REG == 1U) /** @@ -1986,7 +1930,7 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co * \parRelated APIs:
    * None. */ -void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,XMC_VADC_GROUP_INDEX_t group_num); +void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -2002,7 +1946,7 @@ void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ * \parRelated APIs:
    * None. */ -void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr,XMC_VADC_GROUP_INDEX_t group_num); +void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -2022,8 +1966,8 @@ void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs * None. */ void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - uint8_t sst_value); + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t sst_value); #endif /** @@ -2043,7 +1987,7 @@ void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetClockDivider(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, uint8_t divs_value) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetClockDivider:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetClockDivider:Wrong divide factor selected", (divs_value < (uint32_t)0x10)) @@ -2088,10 +2032,10 @@ void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, * None. */ __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetMaxCalTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - uint32_t max_calibration_time) + uint32_t max_calibration_time) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetMaxCalTime:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) shs_ptr->CALCTR &= ~((uint32_t)SHS_CALCTR_CALMAX_Msk); shs_ptr->CALCTR |= ((uint32_t)max_calibration_time << SHS_CALCTR_CALMAX_Pos); @@ -2111,7 +2055,7 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_SetMaxCalTime(XMC_VADC_GLOBAL_SHS_t *co * XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations()
    . */ void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num); + XMC_VADC_GROUP_INDEX_t group_num); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -2126,7 +2070,7 @@ void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t * * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
    . */ void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num); + XMC_VADC_GROUP_INDEX_t group_num); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -2143,8 +2087,8 @@ void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t * XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue()
    . */ uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - XMC_VADC_SHS_GAIN_LEVEL_t gain_level); + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -2161,9 +2105,9 @@ uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *con * XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue()
    . */ void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - XMC_VADC_SHS_GAIN_LEVEL_t gain_level, - uint8_t offset_calibration_value); + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level, + uint8_t offset_calibration_value); #endif /** @@ -2183,9 +2127,9 @@ void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const * XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop()
    . */ void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - XMC_VADC_SHS_LOOP_CH_t loop_select, - uint8_t ch_num); + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_LOOP_CH_t loop_select, + uint8_t ch_num); /** * @param shs_ptr Constant pointer to the VADC Sample and hold module @@ -2201,12 +2145,12 @@ void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
    . */ __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_SHS_LOOP_CH_t loop_select) + XMC_VADC_SHS_LOOP_CH_t loop_select) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop:Wrong Delta sigma loop selected", - (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + (loop_select == XMC_VADC_SHS_LOOP_CH_0) || (loop_select == XMC_VADC_SHS_LOOP_CH_1)) shs_ptr->LOOP |= (uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select; } @@ -2225,12 +2169,12 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_EnableSigmaDeltaLoop(XMC_VADC_GLOBAL_SH * XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations()
    . */ __STATIC_INLINE void XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_SHS_LOOP_CH_t loop_select) + XMC_VADC_SHS_LOOP_CH_t loop_select) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableSigmaDeltaLoop:Wrong Delta sigma loop selected", - (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + (loop_select == XMC_VADC_SHS_LOOP_CH_0) || (loop_select == XMC_VADC_SHS_LOOP_CH_1)) shs_ptr->LOOP &= ~((uint32_t)SHS_LOOP_LPEN0_Msk << (uint32_t)loop_select); @@ -2323,6 +2267,24 @@ void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t mas */ void XMC_VADC_GROUP_SetPowerMode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_POWERMODE_t power_mode); +/** + * + * @param group_ptr Constant pointer to the VADC Group. + * + * @return + * XMC_VADC_GROUP_POWERMODE_t Current power mode + * + * \parDescription:
    + * Retrieves the power mode of a VADC group. + * + * \parRelated APIs:
    + * XMC_VADC_GROUP_SetPowerMode()
    + */ +__STATIC_INLINE int32_t XMC_VADC_GROUP_GetPowerMode(XMC_VADC_GROUP_t *const group_ptr) +{ + return ((group_ptr->ARBCFG & (uint32_t)VADC_G_ARBCFG_ANONS_Msk) >> VADC_G_ARBCFG_ANONS_Pos); +} + /** * * @param group_ptr Constant pointer to the VADC group. @@ -2398,8 +2360,8 @@ void XMC_VADC_GROUP_IgnoreSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint * XMC_VADC_GROUP_CheckSlaveReadiness()
    XMC_VADC_GROUP_IgnoreSlaveReadiness()
    */ void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr, - uint32_t eval_waiting_group, - uint32_t eval_origin_group); + uint32_t eval_waiting_group, + uint32_t eval_origin_group); /** * @@ -2425,7 +2387,7 @@ __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetSyncReadySignal(XMC_VADC_GROUP_t *con #else eval_mask = VADC_G_SYNCTR_EVALR1_Msk; #endif - return( group_ptr->SYNCTR & eval_mask); + return ( group_ptr->SYNCTR & eval_mask); } /** @@ -2526,8 +2488,8 @@ XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const gr * None * */ -void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t boundary0, +void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t boundary0, const uint32_t boundary1); /** @@ -2546,8 +2508,8 @@ void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, * None. */ void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, - const XMC_VADC_CHANNEL_BOUNDARY_t selection, - const uint16_t boundary_value); + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value); /** * @param group_ptr Constant pointer to the VADC group @@ -2564,9 +2526,9 @@ void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, * \parRelated APIs:
    * None */ -void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t sr_num, - const XMC_VADC_GROUP_IRQ_t type); +void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t sr_num, + const XMC_VADC_GROUP_IRQ_t type); /** * @@ -2584,18 +2546,18 @@ void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, * None */ __STATIC_INLINE void XMC_VADC_GROUP_ExternalMuxControlInit(XMC_VADC_GROUP_t *const group_ptr, - const XMC_VADC_GROUP_EMUXCFG_t emux_cfg) + const XMC_VADC_GROUP_EMUXCFG_t emux_cfg) { uint32_t emux_config; XMC_ASSERT("XMC_VADC_GROUP_ExternalMuxControlInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) emux_config = ((uint32_t)emux_cfg.starting_external_channel << (uint32_t)VADC_G_EMUXCTR_EMUXSET_Pos) | - ((uint32_t)emux_cfg.connected_channel << (uint32_t)VADC_G_EMUXCTR_EMUXCH_Pos); + ((uint32_t)emux_cfg.connected_channel << (uint32_t)VADC_G_EMUXCTR_EMUXCH_Pos); group_ptr->EMUXCTR = emux_config; emux_config = ((uint32_t)emux_cfg.emux_coding << (uint32_t)VADC_G_EMUXCTR_EMXCOD_Pos) | - ((uint32_t)emux_cfg.emux_mode << (uint32_t)VADC_G_EMUXCTR_EMUXMODE_Pos)| + ((uint32_t)emux_cfg.emux_mode << (uint32_t)VADC_G_EMUXCTR_EMUXMODE_Pos) | ((uint32_t)emux_cfg.stce_usage << (uint32_t)VADC_G_EMUXCTR_EMXST_Pos); #if (XMC_VADC_EMUX_CH_SEL_STYLE == 1U) @@ -2624,8 +2586,8 @@ __STATIC_INLINE void XMC_VADC_GROUP_ExternalMuxControlInit(XMC_VADC_GROUP_t *con * None. */ void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, - const uint8_t boundary_flag_num, - const XMC_VADC_BOUNDARY_NODE_t node); + const uint8_t boundary_flag_num, + const XMC_VADC_BOUNDARY_NODE_t node); #endif /** @@ -2660,11 +2622,11 @@ __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAlias(XMC_VADC_GROUP_t *const group_p * None. */ __STATIC_INLINE XMC_VADC_GROUP_CLASS_t XMC_VADC_GROUP_GetInputClass(XMC_VADC_GROUP_t *const group_ptr, - const XMC_VADC_CHANNEL_CONV_t conv_class) + const XMC_VADC_CHANNEL_CONV_t conv_class) { XMC_VADC_GROUP_CLASS_t input_value; XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong conv_class selected", + XMC_ASSERT("XMC_VADC_GROUP_GetInputClass:Wrong conv_class selected", (XMC_VADC_CHANNEL_CONV_GROUP_CLASS0 == conv_class) || (XMC_VADC_CHANNEL_CONV_GROUP_CLASS1 == conv_class)) input_value.g_iclass0 = (uint32_t) 0xFFFFFFFF; @@ -2946,7 +2908,7 @@ void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr); __STATIC_INLINE void XMC_VADC_GROUP_ScanAddChannelToSequence(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) { XMC_ASSERT("VADC_GSCAN_AddSingleChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_ScanAddChannelToSequence:Wrong Channel Number", + XMC_ASSERT("XMC_VADC_GROUP_ScanAddChannelToSequence:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) group_ptr->ASSEL |= (uint32_t)((uint32_t)1 << ch_num); } @@ -2999,7 +2961,7 @@ __STATIC_INLINE bool XMC_VADC_GROUP_ScanIsChannelPending(XMC_VADC_GROUP_t *const XMC_ASSERT("XMC_VADC_GROUP_ScanIsChannelPending:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_ScanIsChannelPending:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) - return( (bool)((uint32_t)(group_ptr->ASPND >> ch_num) & 1U)); + return ( (bool)((uint32_t)(group_ptr->ASPND >> ch_num) & 1U)); } /** @@ -3076,7 +3038,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_ScanClearReqSrcEvent(XMC_VADC_GROUP_t *const __STATIC_INLINE bool XMC_VADC_GROUP_ScanGetReqSrcEventStatus(XMC_VADC_GROUP_t *const group_ptr) { XMC_ASSERT("XMC_VADC_GSCAN_GetRSEvent:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - return( (bool)(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV1_Msk)); + return ( (bool)(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV1_Msk)); } /** @@ -3227,7 +3189,7 @@ void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const X * \parDescription:
    * Enables arbitration slot of the Background request source.
    \n * If the Background request source must have its conversion request considered by the arbiter, it must participate in - * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter + * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter * comes to the Background slot. Thus this must be enabled if any conversion need to take place. * A call to this API would configure the register bit field GxARBPR.ASEN2. * @@ -3249,7 +3211,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_BackgroundEnableArbitrationSlot(XMC_VADC_GRO * \parDescription:
    * Disables arbitration slot of the Background request source.
    \n * If the Background request source must have its conversion request considered by the arbiter, it must participate in - * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter + * the arbitration rounds. Even if a load event occurs the Background channel can only be converted when the arbiter * comes to the Background slot.A call to this API will lead to all conversions request by Background to be blocked. * A call to this API would configure the register bit field GxARBPR.ASEN2 * @@ -3338,7 +3300,7 @@ void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, * XMC_VADC_GLOBAL_BackgroundSelectGating(); */ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundSetGatingMode(XMC_VADC_GLOBAL_t *const global_ptr, - XMC_VADC_GATEMODE_t mode_sel) + XMC_VADC_GATEMODE_t mode_sel) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetGatingMode:Wrong Module Pointer", (global_ptr == VADC)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetGatingMode:Wrong mode selected", (mode_sel <= XMC_VADC_GATEMODE_ACTIVELOW)) @@ -3453,11 +3415,11 @@ void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr * XMC_VADC_GLOBAL_BackgroundAddMultipleChannels()
    */ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(XMC_VADC_GLOBAL_t *const global_ptr, - const uint32_t grp_num, - const uint32_t ch_num) + const uint32_t grp_num, + const uint32_t ch_num) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Module Pointer", (global_ptr == VADC)) - XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number",((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) @@ -3485,8 +3447,8 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundAddChannelToSequence(XMC_VADC_GLO * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
    */ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgndAddMultipleChannels(XMC_VADC_GLOBAL_t *const global_ptr, - const uint32_t grp_num, - const uint32_t ch_mask) + const uint32_t grp_num, + const uint32_t ch_mask) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Module Pointer", (global_ptr == VADC)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) @@ -3512,11 +3474,11 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgndAddMultipleChannels(XMC_VADC_GLOBAL_ * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
    */ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence(XMC_VADC_GLOBAL_t *const global_ptr, - const uint32_t grp_num, - const uint32_t ch_num) + const uint32_t grp_num, + const uint32_t ch_num) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Module Pointer", (global_ptr == VADC)) - XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number",((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundAddChannelToSequence:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) @@ -3544,8 +3506,8 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence(XMC_VAD * XMC_VADC_GLOBAL_BackgroundAddChannelToSequence()
    */ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels(XMC_VADC_GLOBAL_t *const global_ptr, - const uint32_t grp_num, - const uint32_t ch_mask) + const uint32_t grp_num, + const uint32_t ch_mask) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Module Pointer", (global_ptr == VADC)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgndAddMultipleChannels:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) @@ -3571,15 +3533,15 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels(XMC_VADC_GLOB * XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending()
    */ __STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundIsChannelPending(XMC_VADC_GLOBAL_t *const global_ptr, - const uint32_t grp_num, - const uint32_t ch_num) + const uint32_t grp_num, + const uint32_t ch_num) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Module Pointer", (global_ptr == VADC)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Group Number", ((grp_num) < XMC_VADC_MAXIMUM_NUM_GROUPS)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundIsChannelPending:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) - return( (bool)(global_ptr->BRSPND[grp_num] & (uint32_t)((uint32_t)1 << ch_num))); + return ( (bool)(global_ptr->BRSPND[grp_num] & (uint32_t)((uint32_t)1 << ch_num))); } /** @@ -3657,7 +3619,7 @@ __STATIC_INLINE void XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent(XMC_VADC_GLOBAL_ __STATIC_INLINE bool XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus(XMC_VADC_GLOBAL_t *const global_ptr) { XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus:Wrong Module Pointer", (global_ptr == VADC)) - return((bool)(global_ptr->GLOBEFLAG & (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk)); + return ((bool)(global_ptr->GLOBEFLAG & (uint32_t)VADC_GLOBEFLAG_SEVGLB_Msk)); } /** @@ -3850,7 +3812,7 @@ __STATIC_INLINE bool XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled(XMC_VADC_GROUP * \parRelated APIs:
    * XMC_VADC_GROUP_QueueSelectGating()
    XMC_VADC_GROUP_QueueEnableExternalTrigger()
    */ -void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, +void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_INPUT_SELECT_t input_num); /** @@ -4003,7 +3965,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_QueueFlushEntries(XMC_VADC_GROUP_t *const gr /* Initiate flushing of the queue */ group_ptr->QMR0 |= (uint32_t)VADC_G_QMR0_FLUSH_Msk; - while( !((group_ptr->QSR0)& (uint32_t)VADC_G_QSR0_EMPTY_Msk)) + while ( !((group_ptr->QSR0) & (uint32_t)VADC_G_QSR0_EMPTY_Msk)) { /* Wait until the queue is indeed flushed */ } @@ -4048,7 +4010,7 @@ void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr); * XMC_VADC_GROUP_QueueRemoveChannel()
    */ __STATIC_INLINE void XMC_VADC_GROUP_QueueInsertChannel(XMC_VADC_GROUP_t *const group_ptr, - const XMC_VADC_QUEUE_ENTRY_t entry) + const XMC_VADC_QUEUE_ENTRY_t entry) { XMC_ASSERT("XMC_VADC_GROUP_QueueInsertChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) /* Insert the channel physically and get the length of the queue*/ @@ -4152,7 +4114,7 @@ __STATIC_INLINE bool XMC_VADC_GROUP_QueueGetReqSrcEventStatus(XMC_VADC_GROUP_t * { XMC_ASSERT("XMC_VADC_GROUP_QueueGetReqSrcEventStatus:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - return(group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV0_Msk); + return (group_ptr->SEFLAG & (uint32_t)VADC_G_SEFLAG_SEV0_Msk); } /** @@ -4237,7 +4199,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_QueueDisableExternalTrigger(XMC_VADC_GROUP_t * None. */ void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, - const XMC_VADC_CHANNEL_CONFIG_t *config); + const XMC_VADC_CHANNEL_CONFIG_t *config); /** * @param group_ptr Constant pointer to the VADC group @@ -4264,11 +4226,41 @@ void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_ * feature that was previously selected this method can be used. * * \parRelated APIs:
    - * None. + * XMC_VADC_GROUP_GetChannelAlias(). + */ +__STATIC_INLINE void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t src_ch_num, + const uint32_t alias_ch_num) +{ + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Alias Channel", ((alias_ch_num == 0) || (alias_ch_num == 1U))) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Aliased Channel", ((src_ch_num < 8U))) + + group_ptr->ALIAS = (group_ptr->ALIAS & (uint32_t)~(VADC_G_ALIAS_ALIAS0_Msk << (VADC_G_ALIAS_ALIAS1_Pos * src_ch_num))) | + (alias_ch_num << (VADC_G_ALIAS_ALIAS1_Pos * src_ch_num)); +} + +/** + * @param group_ptr Constant pointer to the VADC group + * @param alias_ch_num This is the alias channel (Ch-0 or Ch-1) + *
    Range:[0x0, 0x1] + * @return + * uint8_t Channel which will be converted by \b alias_ch_num, when called by the request source. + * + * \parDescription:
    + * Gets the channel to convert when a conversion on alias channel(\b alias_ch_num) is requested.
    \n + * + * \parRelated APIs:
    + * XMC_VADC_GROUP_SetChannelAlias(). */ -void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t src_ch_num, - const uint32_t alias_ch_num); +__STATIC_INLINE uint8_t XMC_VADC_GROUP_GetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t alias_ch_num) +{ + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) + XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Alias Channel", ((alias_ch_num == 0) || (alias_ch_num == 1U))) + + return ((group_ptr->ALIAS >> (VADC_G_ALIAS_ALIAS1_Pos * alias_ch_num)) & VADC_G_ALIAS_ALIAS0_Msk); +} /** * @param group_ptr Constant pointer to the VADC group @@ -4308,7 +4300,7 @@ bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr * None. */ void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, - const XMC_VADC_CHANNEL_REF_t ref); + const XMC_VADC_CHANNEL_REF_t ref); /** * @param group_ptr Constant pointer to the VADC group @@ -4328,8 +4320,8 @@ void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, * None. */ void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const uint32_t result_reg_num); + const uint32_t ch_num, + const uint32_t result_reg_num); /** * @param group_ptr Constant pointer to the VADC group @@ -4350,7 +4342,7 @@ void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, */ void XMC_VADC_GROUP_ChannelSetIclass(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, - const XMC_VADC_CHANNEL_CONV_t conversion_class); + const XMC_VADC_CHANNEL_CONV_t conversion_class); /** * @param group_ptr Constant pointer to the VADC group @@ -4371,14 +4363,14 @@ void XMC_VADC_GROUP_ChannelSetIclass(XMC_VADC_GROUP_t *const group_ptr, * None. */ __STATIC_INLINE XMC_VADC_RESULT_ALIGN_t XMC_VADC_GROUP_ChannelGetResultAlignment(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num) + const uint32_t ch_num) { XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultAlignment:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_ChannelGetResultAlignment:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) return ((XMC_VADC_RESULT_ALIGN_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_RESPOS_Msk) >> - (uint32_t)VADC_G_CHCTR_RESPOS_Pos) ); + (uint32_t)VADC_G_CHCTR_RESPOS_Pos) ); } @@ -4399,14 +4391,14 @@ __STATIC_INLINE XMC_VADC_RESULT_ALIGN_t XMC_VADC_GROUP_ChannelGetResultAlignment * XMC_VADC_GROUP_ChannelSetIclass(). */ __STATIC_INLINE XMC_VADC_CHANNEL_CONV_t XMC_VADC_GROUP_ChannelGetInputClass(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num) + const uint32_t ch_num) { XMC_ASSERT("XMC_VADC_GROUP_ChannelGetInputClass:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_ChannelGetInputClass:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) return ((XMC_VADC_CHANNEL_CONV_t)((group_ptr->CHCTR[ch_num] & (uint32_t)VADC_G_CHCTR_ICLSEL_Msk) >> - (uint32_t)VADC_G_CHCTR_ICLSEL_Pos) ); + (uint32_t)VADC_G_CHCTR_ICLSEL_Pos) ); } /** @@ -4463,7 +4455,7 @@ void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const __STATIC_INLINE uint32_t XMC_VADC_GROUP_ChannelGetAssertedEvents(XMC_VADC_GROUP_t *const group_ptr) { XMC_ASSERT("XMC_VADC_GROUP_ChannelGetAssertedEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - return(group_ptr->CEFLAG); + return (group_ptr->CEFLAG); } /** @@ -4508,8 +4500,8 @@ __STATIC_INLINE void XMC_VADC_GROUP_ChannelClearEvent(XMC_VADC_GROUP_t *const gr * XMC_VADC_GROUP_ChannelTriggerEvent()
    XMC_VADC_GROUP_ChannelClearEvent() */ void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const XMC_VADC_SR_t sr); + const uint32_t ch_num, + const XMC_VADC_SR_t sr); /** * @param group_ptr Constant pointer to the VADC group @@ -4529,8 +4521,8 @@ void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_p * XMC_VADC_GROUP_ChannelSetEventInterruptNode()
    */ void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const XMC_VADC_CHANNEL_EVGEN_t criteria); + const uint32_t ch_num, + const XMC_VADC_CHANNEL_EVGEN_t criteria); /** @@ -4545,16 +4537,16 @@ void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria(XMC_VADC_GROUP_t *const group * \parDescription:
    * Configure the boundary selection for the given channel
    \n * The channel event can be generated under the following conditions - Always, Never, Result Out of bounds and Result - * inside the boundaries. The boundary values to which results are compared can be selected from several sources. + * inside the boundaries. The boundary values to which results are compared can be selected from several sources. * A call to this API would configure the register bit field GxCHCTR.BNDSELL or GxCHCTR.BNDSELU . * * \parRelated APIs:
    * None. */ void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - XMC_VADC_BOUNDARY_SELECT_t boundary_sel, - XMC_VADC_CHANNEL_BOUNDARY_t selection); + const uint32_t ch_num, + XMC_VADC_BOUNDARY_SELECT_t boundary_sel, + XMC_VADC_CHANNEL_BOUNDARY_t selection); /** * @param group_ptr Constant pointer to the VADC group @@ -4578,8 +4570,8 @@ void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_p * XMC_VADC_GROUP_AddResultToFifo()
    XMC_VADC_GROUP_EnableResultEvent()
    XMC_VADC_GROUP_DisableResultEvent()
    */ __STATIC_INLINE void XMC_VADC_GROUP_ResultInit(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg_num, - const XMC_VADC_RESULT_CONFIG_t *config) + const uint32_t res_reg_num, + const XMC_VADC_RESULT_CONFIG_t *config) { XMC_ASSERT("XMC_VADC_GROUP_ResultInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) group_ptr->RCR[res_reg_num] = config->g_rcr; @@ -4674,6 +4666,8 @@ __STATIC_INLINE void XMC_VADC_GROUP_DisableResultEvent(XMC_VADC_GROUP_t *const g * All these information will be returned back. And if the user is polling for the result he can use the * result if the valid bit is set. A call to this API would return the complete register GxRES. * + * @note You can cast the return to a varible of type XMC_VADC_DETAILED_RESULT_t to easily access the register bit fields + * * \parRelated APIs:
    * XMC_VADC_GROUP_GetResult(). */ @@ -4681,7 +4675,7 @@ __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetDetailedResult(XMC_VADC_GROUP_t *cons { XMC_ASSERT("XMC_VADC_GROUP_GetDetailedResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_GetDetailedResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) - return(group_ptr->RES[res_reg]); + return (group_ptr->RES[res_reg]); } /** @@ -4700,8 +4694,8 @@ __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetDetailedResult(XMC_VADC_GROUP_t *cons * \parRelated APIs:
    * XMC_VADC_GROUP_GetDetailedResult(). */ -__STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GROUP_GetResult(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg) +__STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GROUP_GetResult(XMC_VADC_GROUP_t *const group_ptr, + const uint32_t res_reg) { XMC_ASSERT("XMC_VADC_GROUP_GetResult:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_GetResult:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) @@ -4733,14 +4727,14 @@ __STATIC_INLINE XMC_VADC_RESULT_SIZE_t XMC_VADC_GROUP_GetResult(XMC_VADC_GROUP_t * XMC_VADC_GROUP_GetFastCompareResult(). */ void XMC_VADC_GROUP_SetResultFastCompareValue(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg, - const XMC_VADC_RESULT_SIZE_t compare_val); + const uint32_t res_reg, + const XMC_VADC_RESULT_SIZE_t compare_val); /** * @param group_ptr Constant pointer to the VADC group * @param res_reg Result Register for which the compare value is being set *
    Range: [0x0 to 0xF] - * @return + * @return * ::XMC_VADC_FAST_COMPARE_t If the input is greater or lower than the compare value returns the appropriate enum. * if the valid flag was not set then it would return XMC_VADC_FAST_COMPARE_UNKNOWN. * @@ -4757,7 +4751,7 @@ XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *co /** * * @param group_ptr Constant pointer to the VADC group - * @param subtraction_val 12 bit subtraction value + * @param subtraction_val 12 bit subtraction value *
    Range: [0x0 to 0xFFF] * @return * None @@ -4774,7 +4768,7 @@ XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *co * None. */ void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, - const uint16_t subtraction_val); + const uint16_t subtraction_val); /** * @param group_ptr Constant pointer to the VADC group * @param res_reg Result Register for which the result event is being asserted @@ -4814,7 +4808,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_TriggerResultEvent(XMC_VADC_GROUP_t *const g __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetAssertedResultEvents(XMC_VADC_GROUP_t *const group_ptr) { XMC_ASSERT("XMC_VADC_GROUP_GetAssertedResultEvents:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - return(group_ptr->REFLAG); + return (group_ptr->REFLAG); } /** @@ -4858,8 +4852,8 @@ __STATIC_INLINE void XMC_VADC_GROUP_ClearResultEvent(XMC_VADC_GROUP_t *const gro * XMC_VADC_GROUP_TriggerResultEvent()
    XMC_VADC_GROUP_ClearResultEvent() */ void XMC_VADC_GROUP_SetResultInterruptNode(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg, - const XMC_VADC_SR_t sr); + const uint32_t res_reg, + const XMC_VADC_SR_t sr); /** * @param group_ptr Constant pointer to the VADC group @@ -4897,7 +4891,7 @@ uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uin * \parRelated APIs:
    * XMC_VADC_GROUP_GetResultFifoHead()
    */ -uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr,const uint32_t res_reg); +uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg); /** * @@ -4934,13 +4928,13 @@ bool XMC_VADC_GROUP_IsResultRegisterFifoHead(XMC_VADC_GROUP_t *const group_ptr, * */ __STATIC_INLINE bool XMC_VADC_GROUP_IsResultRegisterInFifo(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg) + const uint32_t res_reg) { XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Result Register", + XMC_ASSERT("XMC_VADC_GROUP_IsResultRegisterInFifo:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) - return( (bool)(group_ptr->RCR[res_reg] & (uint32_t)VADC_G_RCR_FEN_Msk)); + return ( (bool)(group_ptr->RCR[res_reg] & (uint32_t)VADC_G_RCR_FEN_Msk)); } #if XMC_VADC_RESULT_PRIORITY_AVAILABLE == 1U @@ -4983,7 +4977,7 @@ __STATIC_INLINE void XMC_VADC_GROUP_SetResultRegPriority(XMC_VADC_GROUP_t *const __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetResultRegPriority(XMC_VADC_GROUP_t *const group_ptr) { XMC_ASSERT("XMC_VADC_GROUP_GetResultRegPriority:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - return(group_ptr->RRASS); + return (group_ptr->RRASS); } #endif #endif @@ -4995,10 +4989,6 @@ __STATIC_INLINE uint32_t XMC_VADC_GROUP_GetResultRegPriority(XMC_VADC_GROUP_t *c /** * @} */ - -/** - * @} - */ - + #endif diff --git a/cores/xmc_lib/XMCLib/inc/xmc_vadc_map.h b/cores/xmc_lib/XMCLib/inc/xmc_vadc_map.h index 05f74603..8d208dd8 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_vadc_map.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_vadc_map.h @@ -1,60 +1,43 @@ /** * @file xmc_vadc_map.h - * @date 2016-11-17 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-15: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-01: - * - Added: - * - XMC4300 device supported + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * - Fixed: - * - Wrong MACRO name corrected for XMC4200/4100 devices. - * XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-11-17: - * - Fixed: Add missing support for XMC47000 - * - Fixed: Renamed XMC_CCU_41_ST2 to XMC_CCU_41_ST3 - * - Added: New macros equivalent to th existing ones but with better naming. - * Old macros are kept for backward compatibility but they deprecated. - * - Added: ECAT support for XMC48/43 + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * @endcond + * @endcond * */ @@ -185,7 +168,7 @@ extern "C" { #define XMC_VADC_G1_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE */ #define XMC_VADC_G2_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE */ #define XMC_VADC_G3_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE */ -#endif +#endif #define XMC_CCU_80_SR0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR0 */ #define XMC_CCU_80_SR1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR1 */ #define XMC_ERU_1_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT0 */ @@ -199,7 +182,7 @@ extern "C" { #if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) #define XMC_CCU_42_SR3 XMC_VADC_REQ_TR_E /**< @deprecated use instead XMC_VADC_REQ_TR_CCU42_SR3 */ #define XMC_CCU_43_SR3 XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_CCU43_SR3 */ -#endif +#endif #define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */ #define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */ #define XMC_CCU_81_SR2 XMC_VADC_REQ_TR_K /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR2 */ @@ -244,7 +227,7 @@ extern "C" { #define XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 1 Gating input L */ #define XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 2 Gating input L */ #define XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 3 Gating input L */ -#endif +#endif #define XMC_VADC_REQ_GT_CCU80_SR0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */ #define XMC_VADC_REQ_GT_CCU80_SR1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */ #define XMC_VADC_REQ_GT_ERU1_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */ @@ -258,7 +241,7 @@ extern "C" { #if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41)) #define XMC_VADC_REQ_TR_CCU42_SR3 XMC_VADC_REQ_TR_E /**< VADC Trigger input E */ #define XMC_VADC_REQ_TR_CCU43_SR3 XMC_VADC_REQ_TR_F /**< VADC Trigger input F */ -#endif +#endif #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC43)) #define XMC_VADC_REQ_TR_ECAT_SYNC0 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */ #define XMC_VADC_REQ_TR_ECAT_SYNC1 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */ diff --git a/cores/xmc_lib/XMCLib/inc/xmc_wdt.h b/cores/xmc_lib/XMCLib/inc/xmc_wdt.h index 53287a05..a6c9f6a5 100644 --- a/cores/xmc_lib/XMCLib/inc/xmc_wdt.h +++ b/cores/xmc_lib/XMCLib/inc/xmc_wdt.h @@ -1,50 +1,42 @@ /** * @file xmc_wdt.h - * @date 2015-08-06 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
    - * - Documentation updates
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
    - * - * 2015-08-06: - * - Bug fix in XMC_WDT_SetDebugMode() API, Wrong register is being configured.
    + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * * @endcond */ @@ -57,29 +49,27 @@ #include "xmc_common.h" #include "xmc_scu.h" -/** - * @addtogroup XMClib XMC Peripheral Library - * @{ - */ + /** * @addtogroup WDT * @brief Watchdog driver for the XMC microcontroller family. * - * The watchdog unit (WDT) improves the system integrity, by triggering the system reset request to bring the system + * The watchdog unit (WDT) improves the system integrity, by triggering the system reset request to bring the system * back from the unresponsive state to normal operation. - * + * * This LLD provides the Configuration structure XMC_WDT_CONFIG_t and initialization function XMC_WDT_Init().\n * It can be used to: * -# Start or Stop the watchdog timer. (XMC_WDT_Start() and XMC_WDT_Stop()) * -# Service the watchdog timer. (XMC_WDT_Service()) * -# Configure the service window upper bound and lower bound timing values. (XMC_WDT_SetWindowBounds()) * -# Enable the generation of the pre-warning event for the first overflow of the timer. (XMC_WDT_SetMode()) - * -# Clear the pre-warning alarm event. It is mandatory to clear the flag during pre-warning alarm ISR, to stop + * -# Clear the pre-warning alarm event. It is mandatory to clear the flag during pre-warning alarm ISR, to stop generating reset request for the second overflow of the timer. (XMC_WDT_ClearAlarm()) * -# Suspend the watchdog timer during Debug HALT mode. (XMC_WDT_SetDebugMode()) * -# Configure service indication pulse width.(XMC_WDT_SetServicePulseWidth()) - * + * + * Also, the WDT block can be configured from the ModusToolbox™ Device Configurator: \ref section_personality_wdt * @{ */ @@ -87,7 +77,7 @@ * MACROS ********************************************************************************************************************/ -#define XMC_WDT_MAGIC_WORD (0xABADCAFEU) /* Magic word to be written in Service Register (SRV), +#define XMC_WDT_MAGIC_WORD (0xABADCAFEU) /* Magic word to be written in Service Register (SRV), to service or feed the watchdog. */ /********************************************************************************************************************* @@ -97,19 +87,19 @@ /** * Defines working modes for watchdog. Use type XMC_WDT_MODE_t for this enum. */ -typedef enum XMC_WDT_MODE +typedef enum XMC_WDT_MODE { - XMC_WDT_MODE_TIMEOUT = (uint32_t)0x0 << WDT_CTR_PRE_Pos, /**< Generates reset request as soon as the timer overflow + XMC_WDT_MODE_TIMEOUT = (uint32_t)0x0 << WDT_CTR_PRE_Pos, /**< Generates reset request as soon as the timer overflow occurs. */ - XMC_WDT_MODE_PREWARNING = (uint32_t)0x1 << WDT_CTR_PRE_Pos /**< Generates an alarm event for the first overflow. And - reset request after subsequent overflow, if not + XMC_WDT_MODE_PREWARNING = (uint32_t)0x1 << WDT_CTR_PRE_Pos /**< Generates an alarm event for the first overflow. And + reset request after subsequent overflow, if not serviced after first overflow. */ } XMC_WDT_MODE_t; /** * Defines debug behaviour of watchdog when the CPU enters HALT mode. Use type XMC_WDT_DEBUG_MODE_t for this enum. */ -typedef enum XMC_WDT_DEBUG_MODE +typedef enum XMC_WDT_DEBUG_MODE { XMC_WDT_DEBUG_MODE_STOP = (uint32_t)0x0 << WDT_CTR_DSP_Pos, /**< Watchdog counter is paused during debug halt. */ XMC_WDT_DEBUG_MODE_RUN = (uint32_t)0x1 << WDT_CTR_DSP_Pos /**< Watchdog counter is not paused during debug halt. */ @@ -118,25 +108,25 @@ typedef enum XMC_WDT_DEBUG_MODE /********************************************************************************************************************* * DATA STRUCTURES ********************************************************************************************************************/ - /* Anonymous structure/union guard start */ +/* Anonymous structure/union guard start */ #if defined(__CC_ARM) - #pragma push - #pragma anon_unions +#pragma push +#pragma anon_unions #elif defined(__TASKING__) - #pragma warning 586 +#pragma warning 586 #endif - + /** * Structure for initializing watchdog timer. Use type XMC_WDT_CONFIG_t for this structure. */ typedef struct XMC_WDT_CONFIG { - uint32_t window_upper_bound; /**< Upper bound for service window (WUB). Reset request is generated up on overflow of + uint32_t window_upper_bound; /**< Upper bound for service window (WUB). Reset request is generated up on overflow of timer. ALways upper bound value has to be more than lower bound value. If it is set lower than WLB, triggers a system reset after timer crossed upper bound value.\n Range: [0H to FFFFFFFFH] */ - uint32_t window_lower_bound; /**< Lower bound for servicing window (WLB). Setting the lower bound to 0H disables the - window mechanism.\n + uint32_t window_lower_bound; /**< Lower bound for servicing window (WLB). Setting the lower bound to 0H disables the + window mechanism.\n Range: [0H to FFFFFFFFH] */ union { @@ -147,20 +137,20 @@ typedef struct XMC_WDT_CONFIG uint32_t : 2; uint32_t run_in_debug_mode : 1; /**< Watchdog timer behaviour during debug (DSP). This accepts boolean values as input. */ uint32_t : 3; - uint32_t service_pulse_width : 8; /**< Service Indication Pulse Width (SPW). Generated Pulse width is of (SPW+1), + uint32_t service_pulse_width : 8; /**< Service Indication Pulse Width (SPW). Generated Pulse width is of (SPW+1), in fwdt cycles.\n Range: [0H to FFH] */ uint32_t : 16; }; - uint32_t wdt_ctr; /* Value of operation mode control register (CTR). It’s bit fields are represented by above + uint32_t wdt_ctr; /* Value of operation mode control register (CTR). It’s bit fields are represented by above union members. */ }; } XMC_WDT_CONFIG_t; /* Anonymous structure/union guard end */ #if defined(__CC_ARM) - #pragma pop +#pragma pop #elif defined(__TASKING__) - #pragma warning restore +#pragma warning restore #endif /********************************************************************************************************************* * API PROTOTYPES @@ -185,7 +175,7 @@ extern "C" { * \par * This API is invoked by XMC_WDT_Init() and therefore no need to call it explicitly during watchdog initialization * sequence. Invoke this API to enable watchdog once again if the watchdog is disabled by invoking XMC_WDT_Disable(). - * + * * \parNote:
    * \if XMC4 * 1. It is required to configure the watchdog, again after invoking XMC_WDT_Disable(). Since all the registers are @@ -218,7 +208,7 @@ void XMC_WDT_Enable(void); * 1. Resets the registers with default values. So XMC_WDT_Init() has to be invoked again to configure the watchdog. * \endif * \if XMC1 - * 1. After invoking XMC_WDT_Disable(), all register values are displayed with 0F in debugger. Once enabled by + * 1. After invoking XMC_WDT_Disable(), all register values are displayed with 0F in debugger. Once enabled by calling XMC_WDT_Enable(), previous configured register values are displayed. No need to invoke XMC_WDT_Init() again. * \endif @@ -238,8 +228,8 @@ void XMC_WDT_Disable(void); * \par * It invokes XMC_WDT_Enable() to enable clock and release reset. Then configures the lower and upper window bounds, * working mode (timeout/pre-warning), debug behaviour and service request indication pulse width. - * - * \parNote:
    + * + * \parNote:
    * 1. With out invoking this XMC_WDT_Init() or XMC_WDT_Enable(), invocation of other APIs like XMC_WDT_SetWindowBounds(), * XMC_WDT_SetMode(), XMC_WDT_SetServicePulseWidth(), XMC_WDT_SetDebugMode(), XMC_WDT_Start(), XMC_WDT_GetCounter(), * XMC_WDT_Service(), XMC_WDT_ClearAlarm() has no affect. @@ -247,10 +237,10 @@ void XMC_WDT_Disable(void); void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config); /** - * @param lower_bound specifies watchdog window lower bound in terms of watchdog clock (fWDT) cycles. + * @param lower_bound specifies watchdog window lower bound in terms of watchdog clock (fWDT) cycles. + * Range: [0H to FFFFFFFFH]. + * @param upper_bound specifies watchdog window upper bound in terms of watchdog clock (fWDT) cycles. * Range: [0H to FFFFFFFFH]. - * @param upper_bound specifies watchdog window upper bound in terms of watchdog clock (fWDT) cycles. - * Range: [0H to FFFFFFFFH]. * * @return None * @@ -262,7 +252,7 @@ void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config); * upper_bound or lower_bound = desired_boundary_time(sec) * fwdt(hz) * * \parNote: - * 1. Always ensure that upper_bound is greater than the lower_bound value. If not, whenever timer crosses the + * 1. Always ensure that upper_bound is greater than the lower_bound value. If not, whenever timer crosses the * upper_bound value it triggers the reset(wdt_rst_req) of the controller. */ __STATIC_INLINE void XMC_WDT_SetWindowBounds(uint32_t lower_bound, uint32_t upper_bound) @@ -289,7 +279,7 @@ __STATIC_INLINE void XMC_WDT_SetMode(XMC_WDT_MODE_t mode) } /** - * @param service_pulse_width specifies Service indication pulse width in terms of fwdt. + * @param service_pulse_width specifies Service indication pulse width in terms of fwdt. * Range: [0H – FFH]. * @return None * @@ -306,7 +296,7 @@ __STATIC_INLINE void XMC_WDT_SetServicePulseWidth(uint8_t service_pulse_width) } /** - * @param debug_mode running state of watchdog during debug halt mode. Refer @ref XMC_WDT_DEBUG_MODE_t for + * @param debug_mode running state of watchdog during debug halt mode. Refer @ref XMC_WDT_DEBUG_MODE_t for * valid values. * * @return None @@ -314,8 +304,8 @@ __STATIC_INLINE void XMC_WDT_SetServicePulseWidth(uint8_t service_pulse_width) * \parDescription:
    * Sets debug behaviour of watchdog by modifying DSP bit of CTR register.\n * \par - * Depending upon DSP bit, the watchdog timer stops when CPU is in HALT mode. The debug behaviour is initially set as - * XMC_WDT_DEBUG_MODE_STOP during initialization in XMC_WDT_Init(). Invoke this API to change the debug behaviour as + * Depending upon DSP bit, the watchdog timer stops when CPU is in HALT mode. The debug behaviour is initially set as + * XMC_WDT_DEBUG_MODE_STOP during initialization in XMC_WDT_Init(). Invoke this API to change the debug behaviour as * needed later in the program. */ __STATIC_INLINE void XMC_WDT_SetDebugMode(const XMC_WDT_DEBUG_MODE_t debug_mode) @@ -411,8 +401,8 @@ __STATIC_INLINE void XMC_WDT_Service(void) * \parDescription:
    * Clears pre-warning alarm by setting ALMC bit in WDTCLR register.\n * \par - * In pre-warning mode, first overflow of the timer upper window bound fires the pre-warning alarm. XMC_WDT_ClearAlarm() - * must be invoked to clear the alarm alarm. After clearing of the alarm, watchdog timer must be serviced within valid + * In pre-warning mode, first overflow of the timer upper window bound fires the pre-warning alarm. XMC_WDT_ClearAlarm() + * must be invoked to clear the alarm alarm. After clearing of the alarm, watchdog timer must be serviced within valid * time window. Otherwise watchdog timer triggers the reset request up on crossing the upper bound value in a subsequent * cycle. * diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s b/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s new file mode 100644 index 00000000..eefd88ea --- /dev/null +++ b/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_ARM/xmc_common_mdk.s @@ -0,0 +1,126 @@ +; @file xmc_common_mdk.s +; @brief Assembly routines for ARMCC. +; @cond +;------------------------------------------------------------------------------- +; XMClib - XMC Peripheral Driver Library +; +; Copyright (c) 2015-2022, Infineon Technologies AG +; All rights reserved. +; +; Boost Software License - Version 1.0 - August 17th, 2003 +; +; Permission is hereby granted, free of charge, to any person or organization +; obtaining a copy of the software and accompanying documentation covered by +; this license (the "Software") to use, reproduce, display, distribute, +; execute, and transmit the Software, and to prepare derivative works of the +; Software, and to permit third-parties to whom the Software is furnished to +; do so, all subject to the following: +; +; The copyright notices in the Software and this entire statement, including +; the above license grant, this restriction and the following disclaimer, +; must be included in all copies of the Software, in whole or in part, and +; all derivative works of the Software, unless such copies or derivative +; works are solely in the form of machine-executable object code generated by +; a source language processor. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT +; SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE +; FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +; DEALINGS IN THE SOFTWARE. +; +; To improve the quality of the software, users are encouraged to share +; modifications, enhancements or bug fixes with Infineon Technologies AG +; at XMCSupport@infineon.com. +;------------------------------------------------------------------------------- +; @endcond + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + +;------------------------------------------------------------------------------- +; Function Name: XMC_DelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32_t cycles: The number of cycles to delay. +; +;------------------------------------------------------------------------------- +; void XMC_DelayCycles(uint32_t cycles) + ALIGN 8 +XMC_DelayCycles FUNCTION + EXPORT XMC_DelayCycles + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to the nearest multiple of 4. + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags. + BEQ XMC_DelayCycles_done ; 2 2 Skip if 0. +XMC_DelayCycles_loop + SUBS r0, r0, #1 ; 1 2 Decrement the counter. + BNE XMC_DelayCycles_loop ; 3(1) 2 3 CPU cycles if branch is taken, and 1 cycle if branch is not taken + NOP ; 1 2 Loop alignment padding. + NOP ; 1 2 Loop alignment padding. +XMC_DelayCycles_done + BX lr ; 3 2 + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: XMC_EnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; XMC_EnterCriticalSection disables interrupts and returns a value +; indicating whether interrupts were previously enabled. +; +; Note Implementation of XMC_EnterCriticalSection manipulates the IRQ +; enable bit with interrupts still enabled. The test and set of the interrupt +; bits are not atomic. Therefore, to avoid a corrupting processor state, it must +; be the policy that all interrupt routines restore the interrupt enable bits as +; they were found on entry. +; +; Return: +; uint8_t +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8_t XMC_EnterCriticalSection(void) +XMC_EnterCriticalSection FUNCTION + EXPORT XMC_EnterCriticalSection + MRS r0, PRIMASK ; Save and return an interrupt state. + CPSID I ; Disable the interrupts. + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: XMC_ExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; XMC_ExitCriticalSection re-enables interrupts if they were enabled +; before XMC_EnterCriticalSection was called. The argument should be the +; value returned from XMC_EnterCriticalSection. +; +; Parameters: +; uint8_t savedIntrStatus: +; The saved interrupt status returned by the XMC_EnterCriticalSection +; function. +; +;------------------------------------------------------------------------------- +; void XMC_ExitCriticalSection(uint8_t savedIntrStatus) +XMC_ExitCriticalSection FUNCTION + EXPORT XMC_ExitCriticalSection + MSR PRIMASK, r0 ; Restore the interrupt state. + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S b/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S new file mode 100644 index 00000000..3b0e6086 --- /dev/null +++ b/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S @@ -0,0 +1,136 @@ +/** + * @file xmc_common_gcc.c + * @brief Assembly routines for GNU GCC. + * @cond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2022, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * @endcond + */ + + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: XMC_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* @param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void XMC_DelayCycles(uint32_t cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global XMC_DelayCycles +.func XMC_DelayCycles, XMC_DelayCycles +.type XMC_DelayCycles, %function +.thumb_func +XMC_DelayCycles: + /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ XMC_DelayCycles_done /* 2 2 Skip if 0 */ + +XMC_DelayCycles_loop: + SUBS r0, r0, #1 /* 1 2 Decrement counter */ + BNE XMC_DelayCycles_loop /* 3(1) 2 3 CPU cycles if branch is taken, and 1 cycle if branch is not taken */ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ + +XMC_DelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ + +.endfunc + + +/******************************************************************************* +* Function Name: XMC_EnterCriticalSection +****************************************************************************//** +* +* XMC_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of XMC_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t XMC_EnterCriticalSection(void) */ +.global XMC_EnterCriticalSection +.func XMC_EnterCriticalSection, XMC_EnterCriticalSection +.type XMC_EnterCriticalSection, %function +.thumb_func + +XMC_EnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + cpsid i /* Disable interrupts */ + BX lr + +.endfunc + + +/******************************************************************************* +* Function Name: XMC_ExitCriticalSection +****************************************************************************//** +* +* Re-enables interrupts if they were enabled before +* XMC_EnterCriticalSection() was called. The argument should be the value +* returned from \ref XMC_EnterCriticalSection(). +* +* \param uint8_t savedIntrStatus: +* Saved interrupt status returned by the \ref XMC_EnterCriticalSection(). +* +*******************************************************************************/ +/* void XMC_ExitCriticalSection(uint8_t savedIntrStatus) */ +.global XMC_ExitCriticalSection +.func XMC_ExitCriticalSection, XMC_ExitCriticalSection +.type XMC_ExitCriticalSection, %function +.thumb_func + +XMC_ExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr + +.endfunc + +.end + +/* [] END OF FILE */ diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s b/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s new file mode 100644 index 00000000..98c76662 --- /dev/null +++ b/cores/xmc_lib/XMCLib/src/COMPONENT_CM0/TOOLCHAIN_IAR/xmc_common_iar.s @@ -0,0 +1,116 @@ +/** + * @file xmc_common_iar.c + * @brief Assembly routines for IAR Embedded Workbench IDE. + * @cond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2022, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * @endcond + */ + + + SECTION .text:CODE:ROOT(4) + PUBLIC XMC_DelayCycles + PUBLIC XMC_EnterCriticalSection + PUBLIC XMC_ExitCriticalSection + THUMB + + +/******************************************************************************* +* Function Name: XMC_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* @param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void XMC_DelayCycles(uint32_t cycles) */ + +XMC_DelayCycles: + ADDS r0, r0, #2 + LSRS r0, r0, #2 + BEQ XMC_DelayCycles_done +XMC_DelayCycles_loop: + SUBS r0, r0, #1 + BNE XMC_DelayCycles_loop + NOP + NOP +XMC_DelayCycles_done: + BX lr + +/******************************************************************************* +* Function Name: XMC_EnterCriticalSection +****************************************************************************//** +* +* XMC_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of XMC_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. The test and set of the interrupt +* bits are not atomic. Therefore, to avoid corrupting processor state, it must +* be the policy that all interrupt routines restore the interrupt enable bits +* as they were found on entry. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t XMC_EnterCriticalSection(void) */ + +XMC_EnterCriticalSection: + MRS r0, PRIMASK ; Save and return an interrupt state. + CPSID I ; Disable interrupts. + BX lr + +/******************************************************************************* +* Function Name: XMC_ExitCriticalSection +****************************************************************************//** +* +* XMC_ExitCriticalSection re-enables the interrupts if they were enabled +* before XMC_EnterCriticalSection was called. The argument should be the +* value returned from XMC_EnterCriticalSection. +* +* \param uint8_t savedIntrStatus: +* The saved interrupt status returned by the +* \ref XMC_EnterCriticalSection(). +* +*******************************************************************************/ +/* void XMC_ExitCriticalSection(uint8_t savedIntrStatus) */ + +XMC_ExitCriticalSection: + MSR PRIMASK, r0 ; Restore the interrupt state. + BX lr + + END diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s b/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s new file mode 100644 index 00000000..4eb7c7dd --- /dev/null +++ b/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_ARM/xmc_common_mdk.s @@ -0,0 +1,126 @@ +; @file xmc_common_mdk.s +; @brief Assembly routines for ARMCC. +; @cond +;------------------------------------------------------------------------------- +; XMClib - XMC Peripheral Driver Library +; +; Copyright (c) 2015-2022, Infineon Technologies AG +; All rights reserved. +; +; Boost Software License - Version 1.0 - August 17th, 2003 +; +; Permission is hereby granted, free of charge, to any person or organization +; obtaining a copy of the software and accompanying documentation covered by +; this license (the "Software") to use, reproduce, display, distribute, +; execute, and transmit the Software, and to prepare derivative works of the +; Software, and to permit third-parties to whom the Software is furnished to +; do so, all subject to the following: +; +; The copyright notices in the Software and this entire statement, including +; the above license grant, this restriction and the following disclaimer, +; must be included in all copies of the Software, in whole or in part, and +; all derivative works of the Software, unless such copies or derivative +; works are solely in the form of machine-executable object code generated by +; a source language processor. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT +; SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE +; FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +; DEALINGS IN THE SOFTWARE. +; +; To improve the quality of the software, users are encouraged to share +; modifications, enhancements or bug fixes with Infineon Technologies AG +; at XMCSupport@infineon.com. +;------------------------------------------------------------------------------- +; @endcond + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + +;------------------------------------------------------------------------------- +; Function Name: XMC_DelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32_t cycles: The number of cycles to delay. +; +;------------------------------------------------------------------------------- +; void XMC_DelayCycles(uint32_t cycles) + ALIGN 8 +XMC_DelayCycles FUNCTION + EXPORT XMC_DelayCycles + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to the nearest multiple of 4. + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags. + BEQ XMC_DelayCycles_done ; 2 2 Skip if 0. +XMC_DelayCycles_loop + ADDS r0, r0, #1 ; 1 2 Increment the counter. + SUBS r0, r0, #2 ; 1 2 Decrement the counter by 2. + BNE XMC_DelayCycles_loop ; (1)2 2 2 CPU cycles (if branch is taken). + NOP ; 1 2 Loop alignment padding. +XMC_DelayCycles_done + BX lr ; 3 2 + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: XMC_EnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; XMC_EnterCriticalSection disables interrupts and returns a value +; indicating whether interrupts were previously enabled. +; +; Note Implementation of XMC_EnterCriticalSection manipulates the IRQ +; enable bit with interrupts still enabled. The test and set of the interrupt +; bits are not atomic. Therefore, to avoid a corrupting processor state, it must +; be the policy that all interrupt routines restore the interrupt enable bits as +; they were found on entry. +; +; Return: +; uint8_t +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8_t XMC_EnterCriticalSection(void) +XMC_EnterCriticalSection FUNCTION + EXPORT XMC_EnterCriticalSection + MRS r0, PRIMASK ; Save and return an interrupt state. + CPSID I ; Disable the interrupts. + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: XMC_ExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; XMC_ExitCriticalSection re-enables interrupts if they were enabled +; before XMC_EnterCriticalSection was called. The argument should be the +; value returned from XMC_EnterCriticalSection. +; +; Parameters: +; uint8_t savedIntrStatus: +; The saved interrupt status returned by the XMC_EnterCriticalSection +; function. +; +;------------------------------------------------------------------------------- +; void XMC_ExitCriticalSection(uint8_t savedIntrStatus) +XMC_ExitCriticalSection FUNCTION + EXPORT XMC_ExitCriticalSection + MSR PRIMASK, r0 ; Restore the interrupt state. + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S b/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S new file mode 100644 index 00000000..425cabef --- /dev/null +++ b/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/xmc_common_gcc.S @@ -0,0 +1,136 @@ +/** + * @file xmc_common_gcc.c + * @brief Assembly routines for GNU GCC. + * @cond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2022, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * @endcond + */ + + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: XMC_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* @param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void XMC_DelayCycles(uint32_t cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global XMC_DelayCycles +.func XMC_DelayCycles, XMC_DelayCycles +.type XMC_DelayCycles, %function +.thumb_func +XMC_DelayCycles: + /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ XMC_DelayCycles_done /* 2 2 Skip if 0 */ + +XMC_DelayCycles_loop: + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE XMC_DelayCycles_loop /* (1)2 2 2 CPU cycles (if branch is taken) */ + NOP /* 1 2 Loop alignment padding */ + +XMC_DelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ + +.endfunc + + +/******************************************************************************* +* Function Name: XMC_EnterCriticalSection +****************************************************************************//** +* +* XMC_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of XMC_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t XMC_EnterCriticalSection(void) */ +.global XMC_EnterCriticalSection +.func XMC_EnterCriticalSection, XMC_EnterCriticalSection +.type XMC_EnterCriticalSection, %function +.thumb_func + +XMC_EnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + cpsid i /* Disable interrupts */ + BX lr + +.endfunc + + +/******************************************************************************* +* Function Name: XMC_ExitCriticalSection +****************************************************************************//** +* +* Re-enables interrupts if they were enabled before +* XMC_EnterCriticalSection() was called. The argument should be the value +* returned from \ref XMC_EnterCriticalSection(). +* +* \param uint8_t savedIntrStatus: +* Saved interrupt status returned by the \ref XMC_EnterCriticalSection(). +* +*******************************************************************************/ +/* void XMC_ExitCriticalSection(uint8_t savedIntrStatus) */ +.global XMC_ExitCriticalSection +.func XMC_ExitCriticalSection, XMC_ExitCriticalSection +.type XMC_ExitCriticalSection, %function +.thumb_func + +XMC_ExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr + +.endfunc + +.end + +/* [] END OF FILE */ diff --git a/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s b/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s new file mode 100644 index 00000000..74d230c7 --- /dev/null +++ b/cores/xmc_lib/XMCLib/src/COMPONENT_CM4/TOOLCHAIN_IAR/xmc_common_iar.s @@ -0,0 +1,116 @@ +/** + * @file xmc_common_iar.c + * @brief Assembly routines for IAR Embedded Workbench IDE. + * @cond + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2022, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * @endcond + */ + + + SECTION .text:CODE:ROOT(4) + PUBLIC XMC_DelayCycles + PUBLIC XMC_EnterCriticalSection + PUBLIC XMC_ExitCriticalSection + THUMB + + +/******************************************************************************* +* Function Name: XMC_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* @param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void XMC_DelayCycles(uint32_t cycles) */ + +XMC_DelayCycles: + ADDS r0, r0, #2 + LSRS r0, r0, #2 + BEQ XMC_DelayCycles_done +XMC_DelayCycles_loop: + ADDS r0, r0, #1 + SUBS r0, r0, #2 + BNE XMC_DelayCycles_loop + NOP +XMC_DelayCycles_done: + BX lr + +/******************************************************************************* +* Function Name: XMC_EnterCriticalSection +****************************************************************************//** +* +* XMC_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of XMC_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. The test and set of the interrupt +* bits are not atomic. Therefore, to avoid corrupting processor state, it must +* be the policy that all interrupt routines restore the interrupt enable bits +* as they were found on entry. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t XMC_EnterCriticalSection(void) */ + +XMC_EnterCriticalSection: + MRS r0, PRIMASK ; Save and return an interrupt state. + CPSID I ; Disable interrupts. + BX lr + +/******************************************************************************* +* Function Name: XMC_ExitCriticalSection +****************************************************************************//** +* +* XMC_ExitCriticalSection re-enables the interrupts if they were enabled +* before XMC_EnterCriticalSection was called. The argument should be the +* value returned from XMC_EnterCriticalSection. +* +* \param uint8_t savedIntrStatus: +* The saved interrupt status returned by the +* \ref XMC_EnterCriticalSection(). +* +*******************************************************************************/ +/* void XMC_ExitCriticalSection(uint8_t savedIntrStatus) */ + +XMC_ExitCriticalSection: + MSR PRIMASK, r0 ; Restore the interrupt state. + BX lr + + END diff --git a/cores/xmc_lib/XMCLib/src/xmc1_eru.c b/cores/xmc_lib/XMCLib/src/xmc1_eru.c index aff6ff99..f8b637d2 100644 --- a/cores/xmc_lib/XMCLib/src/xmc1_eru.c +++ b/cores/xmc_lib/XMCLib/src/xmc1_eru.c @@ -1,43 +1,41 @@ /** * @file xmc1_eru.c - * @date 2015-02-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
    + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library + * + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ diff --git a/cores/xmc_lib/XMCLib/src/xmc1_flash.c b/cores/xmc_lib/XMCLib/src/xmc1_flash.c index 56321b85..2b419064 100644 --- a/cores/xmc_lib/XMCLib/src/xmc1_flash.c +++ b/cores/xmc_lib/XMCLib/src/xmc1_flash.c @@ -1,52 +1,43 @@ /** * @file xmc1_flash.c - * @date 2015-10-14 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-10: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-10-14: - * - Fixed defect in API XMC_FLASH_ErasePages, related to the errata NVM_CM.001 - * - NVM ROM user routine XMC1000_NvmErasePage(address) used for erase page. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * @endcond + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -111,14 +102,14 @@ void XMC_FLASH_DisableEvent(const uint32_t event_msk) NVM->NVMCONF &= (uint16_t)(~(uint16_t)event_msk); } -void XMC_FLASH_ErasePage(uint32_t *address) +int32_t XMC_FLASH_ErasePage(uint32_t *address) { - (void)XMC1000_NvmErasePage(address); + return XMC1000_NvmErasePage(address); } -void XMC_FLASH_ProgramVerifyPage(uint32_t *address, const uint32_t *data) +int32_t XMC_FLASH_ProgramVerifyPage(uint32_t *address, const uint32_t *data) { - (void)XMC1000_NvmProgVerify(data, address); + return XMC1000_NvmProgVerify(data, address); } /* Write blocks of data into flash*/ @@ -128,7 +119,7 @@ void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num uint32_t block; XMC_ASSERT("XMC_FLASH_WriteBlocks: Starting address not aligned to Block", - ((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U) + ((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U) /* Configure the continuous Write option command and reset the NVM error / verification status*/ NVM->NVMPROG &= (uint16_t)(~(uint16_t)NVM_NVMPROG_ACTION_Msk); @@ -151,7 +142,7 @@ void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num data++; address++; } - + while (XMC_FLASH_IsBusy() == true) { } @@ -162,26 +153,28 @@ void XMC_FLASH_WriteBlocks(uint32_t *address, const uint32_t *data, uint32_t num } /* Erase flash pages */ -void XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages) +int32_t XMC_FLASH_ErasePages(uint32_t *address, uint32_t num_pages) { uint32_t page; XMC_ASSERT("XMC_FLASH_ErasePages: Starting address not aligned to Page", - ((uint32_t)address & FLASH_PAGE_ADDR_MASK) == 0U) + ((uint32_t)address & FLASH_PAGE_ADDR_MASK) == 0U) + int32_t status = NVM_E_FAIL; for (page = 0U; page < num_pages; ++page) { - (void)XMC1000_NvmErasePage(address); - - while (XMC_FLASH_IsBusy() == true) + status = XMC1000_NvmErasePage(address); + if (status != NVM_PASS) { + return status; } /* Increment the page address for the next erase */ address += XMC_FLASH_WORDS_PER_PAGE; - } + return status; + } /* Write multiple data blocks and verify the written data */ @@ -191,12 +184,12 @@ void XMC_FLASH_VerifyBlocks(uint32_t *address, const uint32_t *data, uint32_t nu uint32_t block; XMC_ASSERT("XMC_FLASH_VerifyBlocks: Starting address not aligned to Block", - ((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U) + ((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U) /* Configure the Continuous write with verify option command and reset the NVM error / verification status*/ NVM->NVMPROG &= (uint16_t)~NVM_NVMPROG_ACTION_Msk; - NVM->NVMPROG |= (uint16_t)((uint16_t)NVM_NVMPROG_RSTVERR_Msk | - (uint16_t)NVM_NVMPROG_RSTECC_Msk | + NVM->NVMPROG |= (uint16_t)((uint16_t)NVM_NVMPROG_RSTVERR_Msk | + (uint16_t)NVM_NVMPROG_RSTECC_Msk | (uint16_t)FLASH_ACTION_CONTINUOUS_VERIFY_ONLY); for (block = 0U; block < num_blocks; ++block) @@ -224,7 +217,7 @@ void XMC_FLASH_ReadBlocks(uint32_t *address, uint32_t *data, uint32_t num_blocks uint32_t block; XMC_ASSERT("XMC_FLASH_ReadBlocks: Starting address not aligned to Block", - ((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U) + ((uint32_t)address & FLASH_BLOCK_ADDR_MASK) == 0U) for (block = 0U; block < num_blocks; ++block) { @@ -238,17 +231,17 @@ void XMC_FLASH_ReadBlocks(uint32_t *address, uint32_t *data, uint32_t num_blocks } /* Erase single sector */ -void XMC_FLASH_EraseSector(uint32_t *address) +int32_t XMC_FLASH_EraseSector(uint32_t *address) { XMC_ASSERT("XMC_FLASH_EraseSector: Starting address not aligned to Sector", - ((uint32_t)address & FLASH_SECTOR_ADDR_MASK) == 0U) - XMC_FLASH_ErasePages(address, XMC_FLASH_PAGES_PER_SECTOR); + ((uint32_t)address & FLASH_SECTOR_ADDR_MASK) == 0U) + return XMC_FLASH_ErasePages(address, XMC_FLASH_PAGES_PER_SECTOR); } /* Program single page */ -void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data) +int32_t XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data) { - XMC_FLASH_ProgramVerifyPage(address, data); + return XMC_FLASH_ProgramVerifyPage(address, data); } #endif diff --git a/cores/xmc_lib/XMCLib/src/xmc1_gpio.c b/cores/xmc_lib/XMCLib/src/xmc1_gpio.c index 3993fce4..266e7873 100644 --- a/cores/xmc_lib/XMCLib/src/xmc1_gpio.c +++ b/cores/xmc_lib/XMCLib/src/xmc1_gpio.c @@ -1,55 +1,50 @@ /** * @file xmc1_gpio.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond + * */ #include "xmc_gpio.h" #if UC_FAMILY == XMC1 - /******************************************************************************* * MACROS *******************************************************************************/ @@ -57,7 +52,7 @@ #define PORT_PHCR_Msk PORT0_PHCR0_PH0_Msk #define PORT_PHCR_Size PORT0_PHCR0_PH0_Msk #define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk - +#define XMC_GPIO_MODE_OE XMC_GPIO_MODE_OUTPUT_PUSH_PULL /******************************************************************************* * API IMPLEMENTATION @@ -68,39 +63,44 @@ void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPI XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port)); XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode)); XMC_ASSERT("XMC_GPIO_Init: Invalid input hysteresis", XMC_GPIO_CHECK_INPUT_HYSTERESIS(config->input_hysteresis)); - + /* Switch to input */ - port->IOCR[pin >> 2 ] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U))); + port->IOCR[pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U))); /* HW port control is disabled */ - port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1 )); + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); /* Set input hysteresis */ - port->PHCR[(uint32_t)pin >> 3 ] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U))); - port->PHCR[(uint32_t)pin >> 3 ] |= (uint32_t)config->input_hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)); - - /* Enable digital Input/Output depending on pin */ + port->PHCR[(uint32_t)pin >> 3U] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U))); + port->PHCR[(uint32_t)pin >> 3U] |= (uint32_t)config->input_hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)); + + /* Enable digital input */ if (XMC_GPIO_CHECK_ANALOG_PORT(port)) - { + { port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); } - /* Set output level */ - port->OMR = (uint32_t)config->output_level << pin; - + + if ((config->mode & XMC_GPIO_MODE_OE) != 0) + { + /* If output is enabled */ + + /* Set output level */ + port->OMR = (uint32_t)config->output_level << pin; + } + /* Set mode */ - port->IOCR[pin >> 2 ] |= (uint32_t)config->mode << (PORT_IOCR_PC_Size * (pin & 0x3U)); + port->IOCR[pin >> 2U] |= (uint32_t)config->mode << (PORT_IOCR_PC_Size * (pin & 0x3U)); } - -void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, - const uint8_t pin, +void XMC_GPIO_SetInputHysteresis(XMC_GPIO_PORT_t *const port, + const uint8_t pin, const XMC_GPIO_INPUT_HYSTERESIS_t hysteresis) { XMC_ASSERT("XMC_GPIO_SetInputHysteresis: Invalid port", XMC_GPIO_CHECK_PORT(port)); XMC_ASSERT("XMC_GPIO_SetInputHysteresis: Invalid input hysteresis", XMC_GPIO_CHECK_INPUT_HYSTERESIS(hysteresis)); - port->PHCR[(uint32_t)pin >> 3 ] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U))); - port->PHCR[(uint32_t)pin >> 3 ] |= (uint32_t)hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)); + port->PHCR[(uint32_t)pin >> 3U] &= ~(uint32_t)((uint32_t)PORT_PHCR_Msk << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U))); + port->PHCR[(uint32_t)pin >> 3U] |= (uint32_t)hysteresis << ((uint32_t)PORT_PHCR_Size * ((uint32_t)pin & 0x7U)); } #endif /* UC_FAMILY == XMC1 */ diff --git a/cores/xmc_lib/XMCLib/src/xmc1_rtc.c b/cores/xmc_lib/XMCLib/src/xmc1_rtc.c index 4bb3fc5d..6c3d68e6 100644 --- a/cores/xmc_lib/XMCLib/src/xmc1_rtc.c +++ b/cores/xmc_lib/XMCLib/src/xmc1_rtc.c @@ -1,52 +1,43 @@ /** * @file xmc1_rtc.c - * @date 2016-03-09 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-05-20: - * - XMC_RTC_Init() function is modified - * by adding RTC running condition check + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2016-03-09: - * - Optimize write only registers + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * @endcond + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -60,10 +51,10 @@ /********************************************************************************************************************* * HEADER FILES *********************************************************************************************************************/ -#include +#include "xmc_rtc.h" #if UC_FAMILY == XMC1 -#include +#include "xmc_scu.h" /********************************************************************************************************************* * API IMPLEMENTATION @@ -78,30 +69,30 @@ XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config) if (XMC_RTC_IsEnabled() == false) { XMC_RTC_Enable(); - } - + } + XMC_RTC_SetPrescaler(config->prescaler); - while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U) - { + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U) + { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } RTC->TIM0 = config->time.raw0; RTC->TIM1 = config->time.raw1; - + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } - RTC->ATIM0 = config->alarm.raw0; - RTC->ATIM1 = config->alarm.raw1; + RTC->ATIM0 = config->alarm.raw0; + RTC->ATIM1 = config->alarm.raw1; } return XMC_RTC_STATUS_OK; } /* * Ungates a clock node for RTC - */ + */ void XMC_RTC_Enable(void) { XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_RTC); @@ -109,7 +100,7 @@ void XMC_RTC_Enable(void) /* * Gates a clock node for RTC - */ + */ void XMC_RTC_Disable(void) { XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_RTC); @@ -117,7 +108,7 @@ void XMC_RTC_Disable(void) /* * Suspends RTC function during CPU HALT mode - */ + */ void XMC_RTC_SetDebugMode(const XMC_RTC_DEBUG_MODE_t debug_mode) { uint32_t regval; @@ -127,7 +118,7 @@ void XMC_RTC_SetDebugMode(const XMC_RTC_DEBUG_MODE_t debug_mode) /* * Enable RTC periodic and alarm event(s) - */ + */ void XMC_RTC_EnableEvent(const uint32_t event) { RTC->MSKSR |= event; diff --git a/cores/xmc_lib/XMCLib/src/xmc1_scu.c b/cores/xmc_lib/XMCLib/src/xmc1_scu.c index 9a45e50e..ae3465da 100644 --- a/cores/xmc_lib/XMCLib/src/xmc1_scu.c +++ b/cores/xmc_lib/XMCLib/src/xmc1_scu.c @@ -1,75 +1,41 @@ /** * @file xmc1_scu.c - * @date 2017-06-24 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-02-20: - * - Initial
    - * - * 2015-05-20: - * - XMC_SCU_StartTempMeasurement API is modified - * - XMC_ASSERT statements are added in XMC_SCU_INTERRUPT_SetEventHandler - * - * 2015-06-20: - * - XMC_SCU_INTERRUPT_EnableEvent,XMC_SCU_INTERRUPT_DisableEvent, - * - XMC_SCU_INTERRUPT_TriggerEvent,XMC_SCU_INTERUPT_GetEventStatus, - * - XMC_SCU_INTERRUPT_ClearEventStatus APIs are added - * - * 2015-09-23: - * - XMC1400 support added - * - * 2015-11-30: - * - Documentation improved - * - * 2016-02-29: - * - Fixed XMC_SCU_CLOCK_ScaleMCLKFrequency - * It solves issues with down clock frequency scaling - * - * 2016-04-15: - * - Fixed XMC_SCU_CLOCK_Init for XMC1400 - * It solves issues when trying to disable the OSCHP and use the XTAL pins as GPIO - * - * 2017-02-09 - * - At XMC_SCU_CLOCK_Init() fixed issue while reading oscillator watchdog status - * - * 2017-04-11: - * - Added XMC_SCU_SetBMI() - * - * 2017-06-24 - * - Changed XMC_SCU_SetBMI() for XMC11/XMC12/XMC13 to set to 1 the bit 11 of BMI + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -98,7 +64,7 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_scu.h" #if UC_FAMILY == XMC1 @@ -157,7 +123,7 @@ #define ROM_CalcTSEVAR \ (*((uint32_t (**)(uint32_t temperature))0x00000120U)) /**< Pointer to Calculate target level for temperature comparison routine is available inside ROM. */ - + /********************************************************************************************************************* * LOCAL DATA ********************************************************************************************************************/ @@ -174,7 +140,7 @@ static XMC_SCU_INTERRUPT_EVENT_t event_masks[SCU_IRQ_NUM] = #if defined(USIC1) XMC_SCU_INTERRUPT_EVENT_PEUSIC1 | #endif -#if defined(CAN) +#if defined(CAN_xmc) XMC_SCU_INTERRUPT_EVENT_PEMCAN | #endif #if UC_SERIES == XMC14 @@ -203,24 +169,24 @@ static XMC_SCU_INTERRUPT_EVENT_t event_masks[SCU_IRQ_NUM] = ( #if UC_SERIES != XMC11 - XMC_SCU_INTERRUPT_EVENT_ORC0 | - XMC_SCU_INTERRUPT_EVENT_ORC1 | - XMC_SCU_INTERRUPT_EVENT_ORC2 | - XMC_SCU_INTERRUPT_EVENT_ORC3 | - XMC_SCU_INTERRUPT_EVENT_ORC4 | - XMC_SCU_INTERRUPT_EVENT_ORC5 | - XMC_SCU_INTERRUPT_EVENT_ORC6 | - XMC_SCU_INTERRUPT_EVENT_ORC7 | + XMC_SCU_INTERRUPT_EVENT_ORC0 | + XMC_SCU_INTERRUPT_EVENT_ORC1 | + XMC_SCU_INTERRUPT_EVENT_ORC2 | + XMC_SCU_INTERRUPT_EVENT_ORC3 | + XMC_SCU_INTERRUPT_EVENT_ORC4 | + XMC_SCU_INTERRUPT_EVENT_ORC5 | + XMC_SCU_INTERRUPT_EVENT_ORC6 | + XMC_SCU_INTERRUPT_EVENT_ORC7 | #endif #if defined(COMPARATOR) - XMC_SCU_INTERRUPT_EVENT_ACMP0 | - XMC_SCU_INTERRUPT_EVENT_ACMP1 | - XMC_SCU_INTERRUPT_EVENT_ACMP2 | + XMC_SCU_INTERRUPT_EVENT_ACMP0 | + XMC_SCU_INTERRUPT_EVENT_ACMP1 | + XMC_SCU_INTERRUPT_EVENT_ACMP2 | #if UC_SERIES == XMC14 - XMC_SCU_INTERRUPT_EVENT_ACMP3 | + XMC_SCU_INTERRUPT_EVENT_ACMP3 | #endif #endif - 0) + 0) }; /**< Defines list of events that can generate SCU interrupt and also indicates SCU events mapping to corresponding service request number. These event mask values can be used to verify which event is triggered that corresponds to service request number during runtime. All the event items are tabulated as per service request sources list @@ -252,18 +218,17 @@ static uint32_t XMC_SCU_CalcTSEVAR(uint32_t temperature) limit = ROM_CalcTSEVAR(temperature - 1U); } } - + return (limit); } #if UC_SERIES == XMC14 /* This is a local function used to generate the delay until register get updated with new configured value. */ -static void delay(uint32_t cycles) +__STATIC_FORCEINLINE void delay(uint32_t cycles) { - while(cycles > 0U) + while (--cycles > 0U) { __NOP(); - cycles--; } } #endif @@ -271,7 +236,7 @@ static void delay(uint32_t cycles) /********************************************************************************************************************* * API IMPLEMENTATION ********************************************************************************************************************/ - #ifdef XMC_ASSERT_ENABLE +#ifdef XMC_ASSERT_ENABLE /* API to verify SCU event weather it is valid event or not */ __STATIC_INLINE bool XMC_SCU_INTERRUPT_IsValidEvent(XMC_SCU_INTERRUPT_EVENT_t event) { @@ -282,7 +247,7 @@ __STATIC_INLINE bool XMC_SCU_INTERRUPT_IsValidEvent(XMC_SCU_INTERRUPT_EVENT_t ev #if defined(USIC1) (event == XMC_SCU_INTERRUPT_EVENT_PEUSIC1) || #endif -#if defined(CAN) +#if defined(CAN_xmc) (event == XMC_SCU_INTERRUPT_EVENT_PEMCAN) || #endif #if UC_SERIES == XMC14 @@ -324,7 +289,7 @@ __STATIC_INLINE bool XMC_SCU_INTERRUPT_IsValidEvent(XMC_SCU_INTERRUPT_EVENT_t ev (event == XMC_SCU_INTERRUPT_EVENT_TSE_HIGH) || (event == XMC_SCU_INTERRUPT_EVENT_TSE_LOW)); } - #endif +#endif /* API to enable the SCU event */ void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event) @@ -385,7 +350,7 @@ void XMC_SCU_UnlockProtectedBits(void) { SCU_GENERAL->PASSWD = SCU_GCU_PASSWD_PROT_DISABLE; - while(((SCU_GENERAL->PASSWD) & SCU_GENERAL_PASSWD_PROTS_Msk)) + while (((SCU_GENERAL->PASSWD) & SCU_GENERAL_PASSWD_PROTS_Msk)) { /* Loop until the lock is removed */ } @@ -402,25 +367,25 @@ void XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj) anavdel |= (uint32_t)((obj-> ext_supply_threshold) << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos); anavdel |= (uint32_t)((obj->ext_supply_monitor_speed) << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos); - if(true == (obj->enable_at_init)) + if (true == (obj->enable_at_init)) { anavdel |= (uint32_t)SCU_ANALOG_ANAVDEL_VDEL_EN_Msk; } - SCU_ANALOG->ANAVDEL = (uint16_t) anavdel; + SCU_ANALOG->ANAVDEL = (uint16_t) anavdel; irqmask = 0UL; - if(true == (obj->enable_prewarning_int)) + if (true == (obj->enable_prewarning_int)) { irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDDPI_Msk; } - if(true == (obj->enable_vdrop_int)) + if (true == (obj->enable_vdrop_int)) { irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VDROPI_Msk; } - if(true == (obj->enable_vclip_int)) + if (true == (obj->enable_vclip_int)) { irqmask |= (uint32_t)SCU_INTERRUPT_SRMSK_VCLIPI_Msk; } @@ -434,7 +399,7 @@ XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit) limit = XMC_SCU_CalcTSEVAR(limit); - if (limit != 0) + if (limit != 0) { SCU_ANALOG->ANATSEIL = (uint16_t)limit; } @@ -445,7 +410,7 @@ XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit) return (status); } - + /* API to program higher temperature limit */ XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit(uint32_t limit) { @@ -453,14 +418,14 @@ XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit(uint32_t limit) limit = XMC_SCU_CalcTSEVAR(limit); - if (limit != 0) + if (limit != 0) { SCU_ANALOG->ANATSEIH = (uint16_t)limit; } else { status = XMC_SCU_STATUS_ERROR; - } + } return (status); } @@ -534,19 +499,31 @@ void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) do { - /* Restart OSC_HP oscillator watchdog */ + /* clear the status bit before restarting the detection. */ SCU_INTERRUPT->SRCLR1 = SCU_INTERRUPT_SRCLR1_LOECI_Msk; - /* Enable OSC_HP oscillator watchdog*/ + /* According to errata SCU_CM.023, to reset the XOWD it is needed to disable/enable the watchdog, + keeping in between at least one DCO2 cycle */ + + /* Disable XOWD */ SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_XOWDEN_Msk; - SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk; - /* Wait a few DCO2 cycles for the update of the clock detection result */ - delay(2500); + /* Clock domains synchronization, at least 1 DCO2 cycle */ + /* delay value calculation assuming worst case DCO1=48Mhz and 3cycles per delay iteration */ + delay(538); + + /* Enable XOWD */ + SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk | SCU_CLK_OSCCSR_XOWDRES_Msk; + + /* OSCCSR.XOWDRES bit will be automatically reset to 0 after XOWD is reset */ + while (SCU_CLK->OSCCSR & SCU_CLK_OSCCSR_XOWDRES_Msk); + + /* Wait a at least 5 DCO2 cycles for the update of the XTAL OWD result */ + /* delay value calculation assuming worst case DCO1=48Mhz and 3cycles per delay iteration */ + delay(2685); - /* check clock is ok */ } - while(SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk); + while (SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk); } else /* (config->oschp_mode == XMC_SCU_CLOCK_OSCHP_MODE_DISABLED) */ { @@ -554,6 +531,13 @@ void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) } SCU_ANALOG->ANAOSCLPCTRL = (uint16_t)config->osclp_mode; +#ifndef DISABLE_WAIT_RTC_XTAL_OSC_STARTUP + if (config->osclp_mode == XMC_SCU_CLOCK_OSCLP_MODE_OSC) + { + /* Wait oscillator startup time ~5s */ + delay(6500000); + } +#endif SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & ~SCU_CLK_CLKCR1_DCLKSEL_Msk) | config->dclk_src; @@ -596,6 +580,17 @@ void XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t so XMC_SCU_LockProtectedBits(); } +#if (UC_SERIES == XMC14) +void XMC_SCU_CLOCK_SetAdcClockSrc(XMC_SCU_CLOCK_ADCCLKSRC_t adcclk_src) +{ + XMC_SCU_UnlockProtectedBits(); + + SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & ~SCU_CLK_CLKCR1_ADCCLKSEL_Msk) | adcclk_src; + + XMC_SCU_LockProtectedBits(); +} +#endif + /* API which gates a clock node at its source */ void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral) { @@ -632,11 +627,11 @@ void XMC_SCU_CLOCK_SetMCLKFrequency(uint32_t freq_khz) #if UC_SERIES == XMC14 if (((SCU_CLK->CLKCR1) & SCU_CLK_CLKCR1_DCLKSEL_Msk) == 0U) { - ratio = DCO1_DIV2_FREQUENCY_KHZ_Q22_10 / freq_khz; + ratio = DCO1_DIV2_FREQUENCY_KHZ_Q22_10 / freq_khz; } else { - ratio = ((OSCHP_GetFrequency() / 1000U) << 10U) / freq_khz; + ratio = ((OSCHP_GetFrequency() / 1000U) << 10U) / freq_khz; } /* Manage overflow */ @@ -648,7 +643,7 @@ void XMC_SCU_CLOCK_SetMCLKFrequency(uint32_t freq_khz) ratio_int = ratio >> 10U; ratio_frac = ratio & 0x3ffU; #else - ratio = DCO1_DIV2_FREQUENCY_KHZ_Q24_8 / freq_khz; + ratio = DCO1_DIV2_FREQUENCY_KHZ_Q24_8 / freq_khz; /* Manage overflow */ if (ratio > 0xffffU) @@ -677,7 +672,7 @@ void XMC_SCU_CLOCK_ScaleMCLKFrequency(uint32_t idiv, uint32_t fdiv) #if (UC_SERIES == XMC14) SCU_CLK->CLKCR1 = (SCU_CLK->CLKCR1 & (uint32_t)~(SCU_CLK_CLKCR1_FDIV_Msk)) | - (uint32_t)((fdiv >> 8U) << SCU_CLK_CLKCR1_FDIV_Pos); + (uint32_t)((fdiv >> 8U) << SCU_CLK_CLKCR1_FDIV_Pos); SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_FDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) | (uint32_t)((fdiv & 0xffU) << SCU_CLK_CLKCR_FDIV_Pos) | @@ -693,7 +688,7 @@ void XMC_SCU_CLOCK_ScaleMCLKFrequency(uint32_t idiv, uint32_t fdiv) /* Spin until the core supply stabilizes */ } - if(curr_idiv <= idiv) + if (curr_idiv <= idiv) { /* Requested IDIV is greater than currently programmed IDIV. So downscale the frequency */ XMC_SCU_CLOCK_lFrequencyDownScaling(curr_idiv, idiv); @@ -726,12 +721,12 @@ static void XMC_SCU_CLOCK_lFrequencyUpScaling(uint32_t curr_idiv, uint32_t targe curr_idiv = (uint32_t)(curr_idiv >> 2UL); /* Divide by 4. */ SCU_CLK->CLKCR = (SCU_CLK->CLKCR & (uint32_t)~(SCU_CLK_CLKCR_IDIV_Msk | SCU_CLK_CLKCR_CNTADJ_Msk)) | - (uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) | + (uint32_t)(curr_idiv << SCU_CLK_CLKCR_IDIV_Pos) | (uint32_t)(1023UL << SCU_CLK_CLKCR_CNTADJ_Pos); while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk) { - /* Wait voltage suply stabilization */ + /* Wait voltage suply stabilization */ } } } @@ -742,7 +737,7 @@ static void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t tar while ((curr_idiv * 4UL) < target_idiv) { - if(0U == curr_idiv) + if (0U == curr_idiv) { curr_idiv = 1U; } @@ -753,7 +748,7 @@ static void XMC_SCU_CLOCK_lFrequencyDownScaling(uint32_t curr_idiv, uint32_t tar while (SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk) { - /* Wait voltage suply stabilization */ + /* Wait voltage suply stabilization */ } } } @@ -781,10 +776,10 @@ void XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature(int32_t temperature) int32_t e; int32_t offset; - a = *((uint8_t*)DCO_ADJLO_T2); - b = *((uint8_t*)DCO_ADJLO_T1); - d = *((uint8_t*)ANA_TSE_T1); - e = *((uint8_t*)ANA_TSE_T2); + a = *((uint8_t *)DCO_ADJLO_T2); + b = *((uint8_t *)DCO_ADJLO_T1); + d = *((uint8_t *)ANA_TSE_T1); + e = *((uint8_t *)ANA_TSE_T2); offset = b + (((a - b) * (temperature - d)) / (e - d)); offset &= SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Msk; @@ -863,7 +858,7 @@ uint32_t XMC_SCU_SetBMI(uint32_t flags, uint8_t timeout) #if (UC_SERIES == XMC14) return ROM_BmiInstallationReq((flags & 0x0fffU) | ((timeout << 12) & 0xf000U)); #else - return ROM_BmiInstallationReq((flags & 0x07ffU) | ((timeout << 12) & 0xf000U) | 0x0800U); + return ROM_BmiInstallationReq((flags & 0x07ffU) | ((timeout << 12) & 0xf000U) | 0x08c0U); #endif } @@ -875,8 +870,8 @@ void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration(XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_ XMC_SCU_UnlockProtectedBits(); SCU_ANALOG->ANASYNC2 = (uint16_t)(prescaler << SCU_ANALOG_ANASYNC2_PRESCALER_Pos); SCU_ANALOG->ANASYNC1 = (uint16_t)(syn_preload | - sync_clk | - SCU_ANALOG_ANASYNC1_SYNC_DCO_EN_Msk); + sync_clk | + SCU_ANALOG_ANASYNC1_SYNC_DCO_EN_Msk); XMC_SCU_LockProtectedBits(); @@ -897,38 +892,6 @@ bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady(void) return (bool)((SCU_ANALOG->ANASYNC2 & SCU_ANALOG_ANASYNC2_SYNC_READY_Msk) != 0U); } -/** - * This function enables the watchdog on the DCO1 frequency - */ -void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void) -{ - SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDEN_Msk; -} - -/** - * This function disables the watchdog on the DCO1 frequency - */ -void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void) -{ - SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_OWDEN_Msk; -} - -/** - * This function clears the status of the watchdog on the DCO1 frequency - */ -void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void) -{ - SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDRES_Msk; -} - -/** - * This function checks if the DCO1 frequency is in the limits of the watchdog. - */ -bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void) -{ - return ((SCU_CLK->OSCCSR & (SCU_CLK_OSCCSR_OSC2L_Msk | SCU_CLK_OSCCSR_OSC2H_Msk)) == 0U); -} - /* This function selects service request source for a NVIC interrupt node */ void XMC_SCU_SetInterruptControl(uint8_t irq_number, XMC_SCU_IRQCTRL_t source) { @@ -949,5 +912,20 @@ void XMC_SCU_SetInterruptControl(uint8_t irq_number, XMC_SCU_IRQCTRL_t source) } } +void XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode(XMC_SCU_CLOCK_OSCHP_MODE_t mode) +{ + XMC_SCU_UnlockProtectedBits(); + SCU_ANALOG->ANAOSCHPCTRL = (SCU_ANALOG->ANAOSCHPCTRL & (uint32_t)~(SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk | SCU_ANALOG_ANAOSCHPCTRL_SHBY_Msk)) + | mode; + XMC_SCU_LockProtectedBits(); +} + +void XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode(XMC_SCU_CLOCK_OSCLP_MODE_t mode) +{ + SCU_ANALOG->ANAOSCLPCTRL = mode; +} + + + #endif #endif /* UC_FAMILY == XMC1 */ diff --git a/cores/xmc_lib/XMCLib/src/xmc4_eru.c b/cores/xmc_lib/XMCLib/src/xmc4_eru.c index e73691be..6f3978f6 100644 --- a/cores/xmc_lib/XMCLib/src/xmc4_eru.c +++ b/cores/xmc_lib/XMCLib/src/xmc4_eru.c @@ -1,43 +1,41 @@ /** * @file xmc4_eru.c - * @date 2015-02-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -62,7 +60,7 @@ void XMC_ERU_Enable(XMC_ERU_t *const eru) } #else XMC_UNUSED_ARG(eru); - #endif +#endif } /* Disable the clock and Reset the ERU module. */ @@ -73,8 +71,8 @@ void XMC_ERU_Disable(XMC_ERU_t *const eru) { XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1); #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1); - #endif + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1); +#endif } #else XMC_UNUSED_ARG(eru); diff --git a/cores/xmc_lib/XMCLib/src/xmc4_flash.c b/cores/xmc_lib/XMCLib/src/xmc4_flash.c index be97e96e..57df283c 100644 --- a/cores/xmc_lib/XMCLib/src/xmc4_flash.c +++ b/cores/xmc_lib/XMCLib/src/xmc4_flash.c @@ -1,66 +1,43 @@ /** * @file xmc4_flash.c - * @date 2016-01-08 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-10: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-08-17: - * - Added the below API's to the public interface. - * 1. XMC_FLASH_Reset - * 2. XMC_FLASH_ErasePhysicalSector - * 3. XMC_FLASH_EraseUCB - * 4. XMC_FLASH_ResumeProtection - * 5. XMC_FLASH_RepairPhysicalSector + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-01-08: - * - Wait until operation is finished for the next functions: - * 1. XMC_FLASH_InstallProtection - * 2. XMC_FLASH_ConfirmProtection - * 3. XMC_FLASH_ProgramPage - * 4. XMC_FLASH_EraseSector - * 5. XMC_FLASH_ErasePhysicalSector - * 6. XMC_FLASH_EraseUCB - * - Fix XMC_FLASH_VerifyReadProtection and XMC_FLASH_VerifyWriteProtection + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * @endcond + * @endcond * */ @@ -74,6 +51,9 @@ #define XMC_FLASH_PROTECTION_CONFIGURATION_WORDS (8UL) /* Used to upadte the assembly buffer during protection configuration */ +#define XMC_FLASH_BMI_STRING_WORDS (10UL) /* Used to upadte the assembly buffer during BMI String + configuration */ + #define XMC_FLASH_PROT_CONFIRM_OFFSET (512UL) /* Offset address for UCB page */ #define XMC_FLASH_PROT_CONFIRM_WORDS (4UL) #define XMC_FLASH_PROT_CONFIRM_CODE (0x8AFE15C3UL) @@ -93,7 +73,7 @@ void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address); void XMC_FLASH_lClearStatusCommand(void); /* - * Command to program the PFLASH in to page mode, so that assembly buffer is used + * Command to program the PFLASH in to page mode, so that assembly buffer is used */ void XMC_FLASH_lEnterPageModeCommand(void) { @@ -104,7 +84,7 @@ void XMC_FLASH_lEnterPageModeCommand(void) } /* - * Command to load the data into the page assembly buffer + * Command to load the data into the page assembly buffer */ void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word) { @@ -231,9 +211,9 @@ void XMC_FLASH_lClearStatusCommand(void) * API IMPLEMENTATION ********************************************************************************************************************/ - /* - * This API shall clear Program, erase and error flags(PFOPER, SQER, PROER, PFDBER, ORIER, VER) of FSR register. - */ +/* +* This API shall clear Program, erase and error flags(PFOPER, SQER, PROER, PFDBER, ORIER, VER) of FSR register. +*/ void XMC_FLASH_ClearStatus(void) { XMC_FLASH_lClearStatusCommand(); @@ -248,7 +228,7 @@ uint32_t XMC_FLASH_GetStatus(void) } /* - * This API enables the events which required to trigger the ISR + * This API enables the events which required to trigger the ISR */ void XMC_FLASH_EnableEvent(const uint32_t event_msk) { @@ -256,7 +236,7 @@ void XMC_FLASH_EnableEvent(const uint32_t event_msk) } /* - * This API disables the event generation + * This API disables the event generation */ void XMC_FLASH_DisableEvent(const uint32_t event_msk) { @@ -270,7 +250,7 @@ void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data) { uint32_t idx; - XMC_FLASH_lClearStatusCommand(); + XMC_FLASH_lClearStatusCommand(); XMC_FLASH_lEnterPageModeCommand(); for (idx = 0U; idx < XMC_FLASH_WORDS_PER_PAGE; idx += 2U) @@ -278,10 +258,10 @@ void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data) XMC_FLASH_lLoadPageCommand(data[idx], data[idx + 1U]); } - XMC_FLASH_lWritePageCommand(address); + XMC_FLASH_lWritePageCommand(address); /* wait until the operation is completed */ - while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} } /* @@ -293,7 +273,7 @@ void XMC_FLASH_EraseSector(uint32_t *address) XMC_FLASH_lEraseSectorCommand(address); /* wait until the operation is completed */ - while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} } /* @@ -339,16 +319,16 @@ void XMC_FLASH_lRepairPhysicalSectorCommand(void) *address = 0x40U; } - /* - * This API erase the physical sector - */ +/* + * This API erase the physical sector + */ void XMC_FLASH_ErasePhysicalSector(uint32_t *address) { XMC_FLASH_lClearStatusCommand(); XMC_FLASH_lErasePhysicalSectorCommand(address); /* wait until the operation is completed */ - while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} } /* @@ -381,7 +361,7 @@ void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address) *address = 0xc0U; /* wait until the operation is completed */ - while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} } /* @@ -395,16 +375,47 @@ void XMC_FLASH_Reset(void) *address = 0xf0U; } +#define BMI_STRING_BYTE_CNT 30 + +void XMC_FLASH_InstallBMI(XMC_FLASH_BMI_STRING_t *const bmi_string) +{ + uint32_t checksum = 0; + for (int i = 0; i < BMI_STRING_BYTE_CNT; ++i) + { + checksum ^= ((const uint8_t *)bmi_string)[i]; + } + + bmi_string->reserved = checksum; + + XMC_FLASH_lEnterPageModeCommand(); + + XMC_FLASH_lLoadPageCommand(((const uint32_t *)bmi_string)[0], ((const uint32_t *)bmi_string)[1]); + XMC_FLASH_lLoadPageCommand(((const uint32_t *)bmi_string)[2], ((const uint32_t *)bmi_string)[3]); + XMC_FLASH_lLoadPageCommand(((const uint32_t *)bmi_string)[4], ((const uint32_t *)bmi_string)[5]); + XMC_FLASH_lLoadPageCommand(((const uint32_t *)bmi_string)[6], ((const uint32_t *)bmi_string)[7]); + XMC_FLASH_lLoadPageCommand(((const uint32_t *)bmi_string)[8], 0); + + for (uint32_t idx = 0U; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_BMI_STRING_WORDS); idx += 2U) + { + XMC_FLASH_lLoadPageCommand(0UL, 0UL); + } + + XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB2 + XMC_FLASH_BYTES_PER_PAGE)); + + /* wait until the operation is completed */ + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} +} + /* * This API install the global read and sector write protection for the specified user */ void XMC_FLASH_InstallProtection(uint8_t user, uint32_t protection_mask, - uint32_t password_0, + uint32_t password_0, uint32_t password_1) { uint32_t idx; - + XMC_ASSERT(" XMC_FLASH_ConfigureProtection: User level out of range", (user < 3U)) XMC_FLASH_lEnterPageModeCommand(); @@ -413,7 +424,7 @@ void XMC_FLASH_InstallProtection(uint8_t user, XMC_FLASH_lLoadPageCommand(protection_mask, 0UL); XMC_FLASH_lLoadPageCommand(password_0, password_1); XMC_FLASH_lLoadPageCommand(password_0, password_1); - + for (idx = 0U; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIGURATION_WORDS); idx += 2U) { XMC_FLASH_lLoadPageCommand(0UL, 0UL); @@ -422,7 +433,7 @@ void XMC_FLASH_InstallProtection(uint8_t user, XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + (user * XMC_FLASH_BYTES_PER_UCB))); /* wait until the operation is completed */ - while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} } /* @@ -445,11 +456,11 @@ void XMC_FLASH_ConfirmProtection(uint8_t user) XMC_FLASH_lLoadPageCommand(0UL, 0UL); } - XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + + XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + (user * XMC_FLASH_BYTES_PER_UCB) + XMC_FLASH_PROT_CONFIRM_OFFSET)); /* wait until the operation is completed */ - while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){} + while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U) {} } /* @@ -458,10 +469,10 @@ void XMC_FLASH_ConfirmProtection(uint8_t user) bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1) { bool status = false; - + /* Check if read protection is installed */ if ((XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED) != 0U) - { + { XMC_FLASH_lClearStatusCommand(); XMC_FLASH_lDisableReadProtectionCommand(password_0, password_1); @@ -472,25 +483,25 @@ bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1) } /* - * This API verify sector write protection configuration. And returns true if passwords are matching for the + * This API verify sector write protection configuration. And returns true if passwords are matching for the * specified user. */ bool XMC_FLASH_VerifyWriteProtection(uint32_t user, - uint32_t protection_mask, - uint32_t password_0, + uint32_t protection_mask, + uint32_t password_0, uint32_t password_1) { bool status = false; - uint32_t *flash_procon_ptr = (uint32_t *)(void*)(&(FLASH0->PROCON0) + user); + uint32_t *flash_procon_ptr = (uint32_t *)(void *)(&(FLASH0->PROCON0) + user); XMC_ASSERT(" XMC_FLASH_VerifyWriteProtection: User level out of range", (user < 2U)) /* Check if write protection for selected user is installed */ if ((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPROIN0_Pos + user))) != 0U) - { + { XMC_FLASH_lClearStatusCommand(); XMC_FLASH_lDisableSectorWriteProtectionCommand(user, password_0, password_1); - + status = (bool)((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPRODIS0_Pos + user)))) && (*flash_procon_ptr == (protection_mask & (uint32_t)(~(uint32_t)XMC_FLASH_PROTECTION_READ_GLOBAL))); } diff --git a/cores/xmc_lib/XMCLib/src/xmc4_gpio.c b/cores/xmc_lib/XMCLib/src/xmc4_gpio.c index 5d26ea36..9698bd45 100644 --- a/cores/xmc_lib/XMCLib/src/xmc4_gpio.c +++ b/cores/xmc_lib/XMCLib/src/xmc4_gpio.c @@ -1,48 +1,44 @@ /** * @file xmc4_gpio.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond + * */ #include "xmc_gpio.h" @@ -56,7 +52,7 @@ #define PORT_PDR_Msk PORT0_PDR0_PD0_Msk #define PORT_PDR_Size (4U) #define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk - +#define XMC_GPIO_MODE_OE XMC_GPIO_MODE_OUTPUT_PUSH_PULL /******************************************************************************* * API IMPLEMENTATION @@ -66,40 +62,45 @@ void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPI { XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port)); XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode)); - + /* Switch to input */ - port->IOCR[pin >> 2 ] &= (uint32_t)~(PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U))); + port->IOCR[pin >> 2U] &= (uint32_t)~(PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U))); /* HW port control is disabled */ - port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1 )); + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); - /* Enable digital input (input ONLY) */ + /* Enable digital input */ if (XMC_GPIO_CHECK_ANALOG_PORT(port)) { port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin); } else { - /* Set output level */ - port->OMR = (uint32_t)config->output_level << pin; + if ((config->mode & XMC_GPIO_MODE_OE) != 0) + { + /* If output is enabled */ + + /* Set output level */ + port->OMR = (uint32_t)config->output_level << pin; - /* Set output driver strength */ - port->PDR[pin >> 3 ] &= (uint32_t)~(PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); - port->PDR[pin >> 3 ] |= (uint32_t)config->output_strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); + /* Set output driver strength */ + port->PDR[pin >> 3U] &= (uint32_t)~(PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); + port->PDR[pin >> 3U] |= (uint32_t)config->output_strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); + } } + /* Set mode */ - port->IOCR[pin >> 2 ] |= (uint32_t)config->mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); + port->IOCR[pin >> 2U] |= (uint32_t)config->mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); } - void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength) { XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port)); XMC_ASSERT("XMC_GPIO_Init: Invalid output strength", XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength)); - port->PDR[pin >> 3 ] &= (uint32_t)~((uint32_t)PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); - port->PDR[pin >> 3 ] |= (uint32_t)strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); + port->PDR[pin >> 3U] &= (uint32_t)~((uint32_t)PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U))); + port->PDR[pin >> 3U] |= (uint32_t)strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)); } #endif /* UC_FAMILY == XMC4 */ diff --git a/cores/xmc_lib/XMCLib/src/xmc4_rtc.c b/cores/xmc_lib/XMCLib/src/xmc4_rtc.c index b4d7848b..01e17207 100644 --- a/cores/xmc_lib/XMCLib/src/xmc4_rtc.c +++ b/cores/xmc_lib/XMCLib/src/xmc4_rtc.c @@ -1,52 +1,43 @@ /** * @file xmc4_rtc.c - * @date 2017-08-04 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2016-03-09: - * - Optimize write only registers - * - * 2017-08-04: - * - Changed XMC_RTC_EnableHibernationWakeUp() and XMC_RTC_DisableHibernationWakeUpcheck() - * Check SCU_MIRRSTS to ensure that no transfer over serial interface is pending to the RTC_CTR register + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -58,14 +49,14 @@ /********************************************************************************************************************* * HEADER FILES *********************************************************************************************************************/ -#include +#include "xmc_rtc.h" #if UC_FAMILY == XMC4 -#include +#include "xmc_scu.h" /********************************************************************************************************************* * API IMPLEMENTATION - *********************************************************************************************************************/ + *********************************************************************************************************************/ /* * Enables RTC peripheral for programming its registers @@ -105,39 +96,39 @@ XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config) { XMC_SCU_HIB_EnableHibernateDomain(); } - + XMC_RTC_SetPrescaler(config->prescaler); - + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } RTC->TIM0 = config->time.raw0; - + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } RTC->TIM1 = config->time.raw1; - + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } RTC->ATIM0 = config->alarm.raw0; - + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } - RTC->ATIM1 = config->alarm.raw1; - } + RTC->ATIM1 = config->alarm.raw1; + } return XMC_RTC_STATUS_OK; } /* * Enable RTC periodic and alarm event(s) - */ + */ void XMC_RTC_EnableEvent(const uint32_t event) { while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U) @@ -149,7 +140,7 @@ void XMC_RTC_EnableEvent(const uint32_t event) /* * Disable RTC periodic and alarm event(s) - */ + */ void XMC_RTC_DisableEvent(const uint32_t event) { while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U) @@ -161,7 +152,7 @@ void XMC_RTC_DisableEvent(const uint32_t event) /* * Clear RTC periodic and alarm event(s) - */ + */ void XMC_RTC_ClearEvent(const uint32_t event) { while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk) != 0U) @@ -173,7 +164,7 @@ void XMC_RTC_ClearEvent(const uint32_t event) void XMC_RTC_EnableHibernationWakeUp(const uint32_t event) { - while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } @@ -182,7 +173,7 @@ void XMC_RTC_EnableHibernationWakeUp(const uint32_t event) void XMC_RTC_DisableHibernationWakeUp(const uint32_t event) { - while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } diff --git a/cores/xmc_lib/XMCLib/src/xmc4_scu.c b/cores/xmc_lib/XMCLib/src/xmc4_scu.c index ca9fa37a..a590562d 100644 --- a/cores/xmc_lib/XMCLib/src/xmc4_scu.c +++ b/cores/xmc_lib/XMCLib/src/xmc4_scu.c @@ -1,97 +1,49 @@ /** * @file xmc4_scu.c - * @date 2016-06-15 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-05-20: - * - XMC_ASSERT() hanging issues have fixed.
    - * - Line indentation aligned with 120 characters.
    - * - * 2015-06-20: - * - XMC_SCU_INTERRUPT_EnableEvent,XMC_SCU_INTERRUPT_DisableEvent, - * - XMC_SCU_INTERRUPT_TriggerEvent,XMC_SCU_INTERUPT_GetEventStatus, - * - XMC_SCU_INTERRUPT_ClearEventStatus are added - * - Added Weak implementation for OSCHP_GetFrequency() + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-11-30: - * - Documentation improved
    - * - Following API functionalities are improved - * XMC_SCU_CLOCK_GatePeripheralClock, XMC_SCU_CLOCK_UngatePeripheralClock, XMC_SCU_CLOCK_IsPeripheralClockGated - * XMC_SCU_RESET_AssertPeripheralReset, XMC_SCU_RESET_DeassertPeripheralReset, XMC_SCU_RESET_IsPeripheralResetAsserted + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-12-08: - * - XMC_SCU_GetTemperature renamed to XMC_SCU_GetTemperatureMeasurement + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-03-09: - * - Optimize write only registers - * - Added XMC_SCU_HIB_SetPinMode - * - Added XMC_SCU_HIB_GetHibernateControlStatus, - * XMC_SCU_HIB_GetEventStatus, XMC_SCU_HIB_ClearEventStatus, XMC_SCU_HIB_TriggerEvent, - * XMC_SCU_HIB_EnableEvent, XMC_SCU_HIB_DisableEvent - * - Added XMC_SCU_HIB_SetWakeupTriggerInput, XMC_SCU_HIB_SetPinMode, XMC_SCU_HIB_SetOutputPinLevel, - * XMC_SCU_HIB_SetInput0, XMC_SCU_HIB_EnterHibernateState + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2016-04-06: - * - Fixed XMC_SCU_ReadFromRetentionMemory functionality - * - * 2016-05-19: - * - Changed XMC_SCU_CLOCK_StartSystemPll to avoid using floating point calculation which might have an impact on interrupt latency if ISR uses also the FPU - * - Added XMC_SCU_CLOCK_IsLowPowerOscillatorStable() and XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() - * - Added XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus() - * - Added XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput(), - * XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus() - * - * 2016-06-15: - * - Added XMC_SCU_HIB_EnterHibernateStateEx() which allows to select between external or internal hibernate mode. This last mode only available in XMC44, XMC42 and XMC41 series. - * - Extended wakeup hibernate events using LPAC wakeup on events. Only available in XMC44, XMC42 and XMC41 series - * - Added LPAC APIs. Only available in XMC44, XMC42 and XMC41 series. - * - * @endcond + * @endcond * */ /** * - * @brief SCU low level driver API prototype definition for XMC4 family of microcontrollers. + * @brief SCU low level driver API prototype definition for XMC4 family of microcontrollers. * * Detailed description of file:
    * APIs provided in this file cover the following functional blocks of SCU:
    @@ -115,7 +67,7 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_scu.h" #if UC_FAMILY == XMC4 @@ -164,7 +116,7 @@ provided ADC group number lies within specified ADC start and end group number or not. */ - + #define XMC_SCU_CHECK_CHNUM(CH_NUM) (((CH_NUM) == XMC_SCU_ORC_START_ADC_CHANNEL) || \ ((CH_NUM) == XMC_SCU_ORC_END_ADC_CHANNEL) ) /**< Used to verify whether provided ADC channel number lies @@ -183,14 +135,14 @@ /********************************************************************************************************************* * LOCAL DATA ********************************************************************************************************************/ -XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_INTERRUPT_EVENT_MAX]; /**< For registering callback - functions on SCU event - occurrence. */ +static XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler_list[XMC_SCU_INTERRUPT_EVENT_MAX]; /**< For registering callback + functions on SCU event + occurrence. */ /********************************************************************************************************************* * LOCAL ROUTINES ********************************************************************************************************************/ - #if defined(UC_ID) +#if defined(UC_ID) /* This is a non-weak function, which retrieves high precision external oscillator frequency. */ __WEAK uint32_t OSCHP_GetFrequency(void) { @@ -276,18 +228,18 @@ void XMC_SCU_WriteGPR(const uint32_t index, const uint32_t data) /* API to enable Out of Range Comparator(ORC) for a desired group and a desired channel input */ void XMC_SCU_EnableOutOfRangeComparator(const uint32_t group, const uint32_t channel) { - XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Group Number",XMC_SCU_CHECK_GRPNUM(group)); - XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Channel Number",XMC_SCU_CHECK_CHNUM(channel)); - + XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Group Number", XMC_SCU_CHECK_GRPNUM(group)); + XMC_ASSERT("XMC_SCU_EnableOutOfangeComparator:Wrong Channel Number", XMC_SCU_CHECK_CHNUM(channel)); + SCU_GENERAL->GORCEN[group] |= (uint32_t)(1UL << channel); } /* API to enable Out of Range Comparator(ORC) for a desired group and a desired channel input */ void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t channel) { - XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Group Number",XMC_SCU_CHECK_GRPNUM(group)); - XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Channel Number",XMC_SCU_CHECK_CHNUM(channel)); - + XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Group Number", XMC_SCU_CHECK_GRPNUM(group)); + XMC_ASSERT("XMC_SCU_DisableOutOfRangeComparator:Wrong Channel Number", XMC_SCU_CHECK_CHNUM(channel)); + SCU_GENERAL->GORCEN[group] &= (uint32_t)~(1UL << channel); } @@ -295,9 +247,9 @@ void XMC_SCU_DisableOutOfRangeComparator(const uint32_t group, const uint32_t ch void XMC_SCU_CalibrateTemperatureSensor(uint32_t offset, uint32_t gain) { SCU_GENERAL->DTSCON = ((uint32_t)(offset << SCU_GENERAL_DTSCON_OFFSET_Pos) | - (uint32_t)(gain << SCU_GENERAL_DTSCON_GAIN_Pos) | - (uint32_t)(0x4UL << SCU_GENERAL_DTSCON_REFTRIM_Pos) | - (uint32_t)(0x8UL << SCU_GENERAL_DTSCON_BGTRIM_Pos)); + (uint32_t)(gain << SCU_GENERAL_DTSCON_GAIN_Pos) | + (uint32_t)(0x4UL << SCU_GENERAL_DTSCON_REFTRIM_Pos) | + (uint32_t)(0x8UL << SCU_GENERAL_DTSCON_BGTRIM_Pos)); } /* API to enable die temperature measurement by powering the DTS module. */ void XMC_SCU_EnableTemperatureSensor(void) @@ -331,7 +283,7 @@ XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void) { status = XMC_SCU_STATUS_ERROR; } - + if (XMC_SCU_IsTemperatureSensorBusy() == true) { status = XMC_SCU_STATUS_BUSY; @@ -339,7 +291,7 @@ XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement(void) /* And start the measurement */ SCU_GENERAL->DTSCON |= (uint32_t)SCU_GENERAL_DTSCON_START_Msk; - + return (status); } @@ -356,7 +308,7 @@ uint32_t XMC_SCU_GetTemperatureMeasurement(void) { temperature = (uint32_t)((SCU_GENERAL->DTSSTAT & SCU_GENERAL_DTSSTAT_RESULT_Msk) >> SCU_GENERAL_DTSSTAT_RESULT_Pos); } - + return ((uint32_t)temperature); } @@ -367,7 +319,7 @@ bool XMC_SCU_IsTemperatureSensorBusy(void) } -#if defined(SCU_GENERAL_DTEMPLIM_LOWER_Msk) && defined(SCU_GENERAL_DTEMPLIM_UPPER_Msk) +#if ((UC_SERIES == XMC41) || (UC_SERIES == XMC42) || (UC_SERIES == XMC44)) /* API to determine if device temperature has gone past the ceiling */ bool XMC_SCU_HighTemperature(void) { @@ -379,8 +331,8 @@ bool XMC_SCU_HighTemperature(void) ret_val = false; - /* Any audit makes sense only if the DTS were powered up */ - if(dtscon) + /* Any audit makes sense only if the DTS were powered up */ + if (dtscon) { /* Powered down - return false */ ret_val = false; @@ -390,8 +342,8 @@ bool XMC_SCU_HighTemperature(void) /* Powered up - Read the overflow bit and decide accordingly*/ dtempalarm = SCU_GENERAL->DTEMPALARM; dtempalarm = dtempalarm & SCU_GENERAL_DTEMPALARM_OVERFL_Msk; - - if(dtempalarm) + + if (dtempalarm) { ret_val = true; } @@ -424,8 +376,8 @@ bool XMC_SCU_LowTemperature(void) ret_val = false; - /* Any audit makes sense only if the DTS were powered up */ - if(dtscon) + /* Any audit makes sense only if the DTS were powered up */ + if (dtscon) { /* Powered down - return false */ ret_val = false; @@ -435,8 +387,8 @@ bool XMC_SCU_LowTemperature(void) /* Powered up - Read the overflow bit and decide accordingly*/ dtempalarm = SCU_GENERAL->DTEMPALARM; dtempalarm = dtempalarm & SCU_GENERAL_DTEMPALARM_UNDERFL_Msk; - - if(dtempalarm) + + if (dtempalarm) { ret_val = true; } @@ -445,30 +397,30 @@ bool XMC_SCU_LowTemperature(void) ret_val = false; } } - + return (ret_val); } -#endif +#endif /* API to write into Retention memory in hibernate domain */ void XMC_SCU_WriteToRetentionMemory(uint32_t address, uint32_t data) { uint32_t rmacr; - - /* Get the address right */ + + /* Get the address right */ rmacr = (uint32_t)((address << SCU_GENERAL_RMACR_ADDR_Pos) & (uint32_t)SCU_GENERAL_RMACR_ADDR_Msk); - + /* Transfer from RMDATA to Retention memory */ rmacr |= (uint32_t)(SCU_GENERAL_RMACR_RDWR_Msk); - - /* Write desired data into RMDATA register */ + + /* Write desired data into RMDATA register */ SCU_GENERAL->RMDATA = data; - - /* Write address & direction of transfer into RMACR register */ + + /* Write address & direction of transfer into RMACR register */ SCU_GENERAL->RMACR = rmacr; - + /* Wait until the update of RMX register in hibernate domain is completed */ - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) { } } @@ -478,17 +430,17 @@ uint32_t XMC_SCU_ReadFromRetentionMemory(uint32_t address) { uint32_t rmacr; - /* Get the address right */ + /* Get the address right */ rmacr = ((uint32_t)(address << SCU_GENERAL_RMACR_ADDR_Pos) & (uint32_t)SCU_GENERAL_RMACR_ADDR_Msk); - + /* Transfer from RMDATA to Retention memory */ rmacr &= ~((uint32_t)(SCU_GENERAL_RMACR_RDWR_Msk)); - - /* Writing an adress & direction of transfer into RMACR register */ + + /* Writing an adress & direction of transfer into RMACR register */ SCU_GENERAL->RMACR = rmacr; - + /* Wait until the update of RMX register in hibernate domain is completed */ - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_RMX_Msk) { } @@ -504,21 +456,21 @@ void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) XMC_ASSERT("", config->fperipheral_clkdiv != 0); XMC_ASSERT("", ((config->syspll_config.p_div != 0) && (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL)) || - (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); XMC_ASSERT("", ((config->syspll_config.n_div != 0) && (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL)) || - (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR)); XMC_ASSERT("", (config->syspll_config.k_div != 0) && - ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || - (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); + ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); XMC_ASSERT("", ((config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_PLL) || - (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_OFI)) && - ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || - (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); + (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_OFI)) && + ((config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL) || + (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR))); XMC_ASSERT("", ((config->fstdby_clksrc == XMC_SCU_HIB_STDBYCLKSRC_OSCULP) && (config->enable_osculp == true)) || - (config->fstdby_clksrc != XMC_SCU_HIB_STDBYCLKSRC_OSCULP)); + (config->fstdby_clksrc != XMC_SCU_HIB_STDBYCLKSRC_OSCULP)); XMC_ASSERT("", ((config->syspll_config.clksrc == XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) && - (config->enable_oschp == true)) || (config->syspll_config.clksrc != XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP)); + (config->enable_oschp == true)) || (config->syspll_config.clksrc != XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP)); XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_OFI); @@ -529,11 +481,11 @@ void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) XMC_SCU_CLOCK_EnableLowPowerOscillator(); while (XMC_SCU_CLOCK_IsLowPowerOscillatorStable() == false); } - - XMC_SCU_HIB_SetStandbyClockSource(config->fstdby_clksrc); + + XMC_SCU_HIB_SetStandbyClockSource(config->fstdby_clksrc); while (XMC_SCU_GetMirrorStatus() != 0) { - /* Wait until update of the stanby clock source is done in the HIB domain */ + /* Wait until update of the stanby clock source is done in the HIB domain */ } XMC_SCU_CLOCK_SetBackupClockCalibrationMode(config->calibration_mode); @@ -546,12 +498,16 @@ void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) if (config->enable_oschp == true) { XMC_SCU_CLOCK_EnableHighPerformanceOscillator(); - while(XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() == false); + while (XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable() == false); } if (config->syspll_config.mode == XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED) { - XMC_SCU_CLOCK_DisableSystemPll(); + /* Do not enable PLL Power Down Mode when the OSC Watchdog is enabled */ + if (config->enable_oschp == false) + { + XMC_SCU_CLOCK_DisableSystemPll(); + } } else { @@ -567,7 +523,7 @@ void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config) /* use SYSPLL? */ if (config->fsys_clksrc == XMC_SCU_CLOCK_SYSCLKSRC_PLL) { - XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_PLL); + XMC_SCU_CLOCK_SetSystemClockSource(XMC_SCU_CLOCK_SYSCLKSRC_PLL); } SystemCoreClockUpdate(); } @@ -605,37 +561,37 @@ void XMC_SCU_TRAP_ClearStatus(const uint32_t trap) /* API to clear parity error event */ void XMC_SCU_PARITY_ClearStatus(const uint32_t memory) { - SCU_PARITY->PEFLAG |= (uint32_t)memory; + SCU_PARITY->PEFLAG |= (uint32_t)memory; } /* API to determine if the specified parity error has occured or not */ uint32_t XMC_SCU_PARITY_GetStatus(void) { return (SCU_PARITY->PEFLAG); -} +} /* API to enable parity error checking for the selected on-chip RAM type */ void XMC_SCU_PARITY_Enable(const uint32_t memory) { - SCU_PARITY->PEEN |= (uint32_t)memory; + SCU_PARITY->PEEN |= (uint32_t)memory; } /* API to disable parity error checking for the selected on-chip RAM type */ void XMC_SCU_PARITY_Disable(const uint32_t memory) { - SCU_PARITY->PEEN &= (uint32_t)~memory; + SCU_PARITY->PEEN &= (uint32_t)~memory; } /* API to enable trap assertion for the parity error source */ void XMC_SCU_PARITY_EnableTrapGeneration(const uint32_t memory) { - SCU_PARITY->PETE |= (uint32_t)memory; + SCU_PARITY->PETE |= (uint32_t)memory; } /* API to disable the assertion of trap for the parity error source */ void XMC_SCU_PARITY_DisableTrapGeneration(const uint32_t memory) { - SCU_PARITY->PETE &= (uint32_t)~memory; + SCU_PARITY->PETE &= (uint32_t)~memory; } /* Enables a NMI source */ @@ -656,7 +612,7 @@ void XMC_SCU_RESET_AssertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t periph uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); - *(uint32_t *)(&(SCU_RESET->PRSET0) + (index * 3U)) = (uint32_t)mask; + *(volatile uint32_t *)(&(SCU_RESET->PRSET0) + (index * 3U)) = (uint32_t)mask; } /* API to manually de-assert a reset request */ @@ -665,7 +621,7 @@ void XMC_SCU_RESET_DeassertPeripheralReset(const XMC_SCU_PERIPHERAL_RESET_t peri uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); - *(uint32_t *)(&(SCU_RESET->PRCLR0) + (index * 3U)) = (uint32_t)mask; + *(volatile uint32_t *)(&(SCU_RESET->PRCLR0) + (index * 3U)) = (uint32_t)mask; } /* Find out if the peripheral reset is asserted */ @@ -674,7 +630,7 @@ bool XMC_SCU_RESET_IsPeripheralResetAsserted(const XMC_SCU_PERIPHERAL_RESET_t pe uint32_t index = (uint32_t)((((uint32_t)peripheral) & 0xf0000000UL) >> 28UL); uint32_t mask = (((uint32_t)peripheral) & ((uint32_t)~0xf0000000UL)); - return ((*(uint32_t *)(&(SCU_RESET->PRSTAT0) + (index * 3U)) & mask) != 0U); + return ((*(const volatile uint32_t *)(&(SCU_RESET->PRSTAT0) + (index * 3U)) & mask) != 0U); } /* @@ -688,18 +644,18 @@ uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency(void) uint32_t k2_div; clock_frequency = XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(); - if(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) { /* Prescalar mode - fOSC is the parent*/ - clock_frequency = (uint32_t)(clock_frequency / - ((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1UL)); + clock_frequency = (uint32_t)(clock_frequency / + ((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1UL)); } else { p_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1UL); n_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1UL); k2_div = (uint32_t)((((SCU_PLL->PLLCON1) & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1UL); - + clock_frequency = (clock_frequency * n_div) / (p_div * k2_div); } @@ -714,7 +670,7 @@ uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void) uint32_t clock_frequency; /* Prescalar mode - fOSC is the parent*/ - if((SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) == (uint32_t)XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) + if ((SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) == (uint32_t)XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP) { clock_frequency = OSCHP_GetFrequency(); } @@ -722,7 +678,7 @@ uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency(void) { clock_frequency = OFI_FREQUENCY; } - + return (clock_frequency); } @@ -734,14 +690,14 @@ uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency(void) uint32_t clock_frequency; uint32_t n_div; uint32_t p_div; - + clock_frequency = OSCHP_GetFrequency(); - if((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) + if ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) { /* Normal mode - fVCO is the parent*/ n_div = (uint32_t)((((SCU_PLL->USBPLLCON) & SCU_PLL_USBPLLCON_NDIV_Msk) >> SCU_PLL_USBPLLCON_NDIV_Pos) + 1UL); p_div = (uint32_t)((((SCU_PLL->USBPLLCON) & SCU_PLL_USBPLLCON_PDIV_Msk) >> SCU_PLL_USBPLLCON_PDIV_Pos) + 1UL); - clock_frequency = (uint32_t)((clock_frequency * n_div)/ (uint32_t)(p_div * 2UL)); + clock_frequency = (uint32_t)((clock_frequency * n_div) / (uint32_t)(p_div * 2UL)); } return (clock_frequency); } @@ -753,9 +709,9 @@ uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency(void) { uint32_t frequency = 0UL; frequency = XMC_SCU_CLOCK_GetSystemClockFrequency(); - + return (uint32_t)(frequency >> ((uint32_t)((SCU_CLK->CCUCLKCR & SCU_CLK_CCUCLKCR_CCUDIV_Msk) >> - SCU_CLK_CCUCLKCR_CCUDIV_Pos))); + SCU_CLK_CCUCLKCR_CCUDIV_Pos))); } /* @@ -781,7 +737,7 @@ uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void) } return (uint32_t)(frequency / (((SCU_CLK->USBCLKCR & SCU_CLK_USBCLKCR_USBDIV_Msk) >> - SCU_CLK_USBCLKCR_USBDIV_Pos) + 1UL)); + SCU_CLK_USBCLKCR_USBDIV_Pos) + 1UL)); } #if defined(EBU) @@ -791,8 +747,8 @@ uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency(void) uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency(void) { uint32_t frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); - - return (uint32_t)((frequency /(((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> + + return (uint32_t)((frequency / (((SCU_CLK->EBUCLKCR & SCU_CLK_EBUCLKCR_EBUDIV_Msk) >> SCU_CLK_EBUCLKCR_EBUDIV_Pos) + 1UL))); } #endif @@ -846,7 +802,7 @@ uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency(void) } return (uint32_t)((frequency / (((SCU_CLK->WDTCLKCR & SCU_CLK_WDTCLKCR_WDTDIV_Msk) >> - SCU_CLK_WDTCLKCR_WDTDIV_Pos) + 1UL))); + SCU_CLK_WDTCLKCR_WDTDIV_Pos) + 1UL))); } /** @@ -863,9 +819,9 @@ uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void) if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL) { frequency = XMC_SCU_CLOCK_GetSystemPllClockFrequency(); - + frequency = (uint32_t)((frequency / ((((SCU_CLK->EXTCLKCR) & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> - SCU_CLK_EXTCLKCR_ECKDIV_Pos)+ 1UL))); + SCU_CLK_EXTCLKCR_ECKDIV_Pos) + 1UL))); } else if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS) { @@ -874,9 +830,9 @@ uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void) else if (clksrc == XMC_SCU_CLOCK_EXTOUTCLKSRC_USB) { frequency = XMC_SCU_CLOCK_GetUsbPllClockFrequency(); - + frequency = (uint32_t)((frequency / ((((SCU_CLK->EXTCLKCR) & SCU_CLK_EXTCLKCR_ECKDIV_Msk) >> - SCU_CLK_EXTCLKCR_ECKDIV_Pos)+ 1UL))); + SCU_CLK_EXTCLKCR_ECKDIV_Pos) + 1UL))); } else { @@ -892,7 +848,7 @@ uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency(void) uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void) { return (uint32_t)(XMC_SCU_CLOCK_GetCpuClockFrequency() >> - ((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos)); + ((SCU_CLK->PBCLKCR & SCU_CLK_PBCLKCR_PBDIV_Msk) >> SCU_CLK_PBCLKCR_PBDIV_Pos)); } /* API to select fSYS */ @@ -939,9 +895,9 @@ void XMC_SCU_CLOCK_SetSystemPllClockSource(const XMC_SCU_CLOCK_SYSPLLCLKSRC_t so /* API to select fRTC */ void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source) -{ +{ /* Wait until the update of HDCR register in hibernate domain is completed */ - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { } @@ -952,7 +908,7 @@ void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source) /* API to select fSTDBY */ void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } @@ -964,7 +920,7 @@ void XMC_SCU_HIB_SetStandbyClockSource(const XMC_SCU_HIB_STDBYCLKSRC_t source) void XMC_SCU_CLOCK_SetSystemClockDivider(const uint32_t divider) { XMC_ASSERT("XMC_SCU_CLOCK_SetSystemClockDivider:Wrong clock divider value", - (divider <= (SCU_CLK_SYSCLKCR_SYSDIV_Msk + 1UL)) ); + (divider <= (SCU_CLK_SYSCLKCR_SYSDIV_Msk + 1UL)) ); SCU_CLK->SYSCLKCR = (SCU_CLK->SYSCLKCR & ((uint32_t)~SCU_CLK_SYSCLKCR_SYSDIV_Msk)) | ((uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_SYSCLKCR_SYSDIV_Pos)); @@ -1001,10 +957,10 @@ void XMC_SCU_CLOCK_SetPeripheralClockDivider(const uint32_t divider) void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t divider) { XMC_ASSERT("XMC_SCU_CLOCK_SetSdmmcClockDivider:Wrong clock divider value", - (divider <= (SCU_CLK_USBCLKCR_USBDIV_Msk + 1UL)) ); + (divider <= (SCU_CLK_USBCLKCR_USBDIV_Msk + 1UL)) ); SCU_CLK->USBCLKCR = (SCU_CLK->USBCLKCR & ((uint32_t)~SCU_CLK_USBCLKCR_USBDIV_Msk)) | - (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_USBCLKCR_USBDIV_Pos); + (uint32_t)((uint32_t)(divider - 1UL) << SCU_CLK_USBCLKCR_USBDIV_Pos); } #if defined(EBU) @@ -1012,7 +968,7 @@ void XMC_SCU_CLOCK_SetUsbClockDivider(const uint32_t divider) void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t divider) { XMC_ASSERT("XMC_SCU_CLOCK_SetEbuClockDivider:Wrong clock divider value", - (divider <= (SCU_CLK_EBUCLKCR_EBUDIV_Msk + 1UL) ) ); + (divider <= (SCU_CLK_EBUCLKCR_EBUDIV_Msk + 1UL) ) ); SCU_CLK->EBUCLKCR = (SCU_CLK->EBUCLKCR & ((uint32_t)~SCU_CLK_EBUCLKCR_EBUDIV_Msk)) | (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_EBUCLKCR_EBUDIV_Pos); @@ -1023,7 +979,7 @@ void XMC_SCU_CLOCK_SetEbuClockDivider(const uint32_t divider) void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t divider) { XMC_ASSERT("XMC_SCU_CLOCK_SetWdtClockDivider:Wrong clock divider value", - (divider <= (SCU_CLK_WDTCLKCR_WDTDIV_Msk + 1UL) ) ); + (divider <= (SCU_CLK_WDTCLKCR_WDTDIV_Msk + 1UL) ) ); SCU_CLK->WDTCLKCR = (SCU_CLK->WDTCLKCR & ((uint32_t)~SCU_CLK_WDTCLKCR_WDTDIV_Msk)) | (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_WDTCLKCR_WDTDIV_Pos); @@ -1033,7 +989,7 @@ void XMC_SCU_CLOCK_SetWdtClockDivider(const uint32_t divider) void XMC_SCU_CLOCK_SetExternalOutputClockDivider(const uint32_t divider) { XMC_ASSERT("XMC_SCU_CLOCK_SetExternalOutputClockDivider:Wrong clock divider value", - (divider <= (SCU_CLK_EXTCLKCR_ECKDIV_Msk + 1UL) ) ); + (divider <= (SCU_CLK_EXTCLKCR_ECKDIV_Msk + 1UL) ) ); SCU_CLK->EXTCLKCR = (SCU_CLK->EXTCLKCR & ((uint32_t)~SCU_CLK_EXTCLKCR_ECKDIV_Msk)) | (uint32_t)(((uint32_t)(divider - 1UL)) << SCU_CLK_EXTCLKCR_ECKDIV_Pos); @@ -1073,7 +1029,7 @@ void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripher uint32_t index = (peripheral & 0xf0000000UL) >> 28UL; uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); - *(uint32_t *)((&(SCU_CLK->CGATSET0)) + (index * 3U)) = (uint32_t)mask; + *(volatile uint32_t *)((&(SCU_CLK->CGATSET0)) + (index * 3U)) = (uint32_t)mask; } /* API to ungate a given module clock */ @@ -1082,7 +1038,7 @@ void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t periph uint32_t index = (uint32_t)((peripheral & 0xf0000000UL) >> 28UL); uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); - *(uint32_t *)(&(SCU_CLK->CGATCLR0) + (index * 3U)) = (uint32_t)mask; + *(volatile uint32_t *)(&(SCU_CLK->CGATCLR0) + (index * 3U)) = (uint32_t)mask; } /* API to ungate a given module clock */ @@ -1091,7 +1047,7 @@ bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t perip uint32_t index = ((peripheral & 0xf0000000UL) >> 28UL); uint32_t mask = (peripheral & (uint32_t)~0xf0000000UL); - return ((*(uint32_t *)(&(SCU_CLK->CGATSTAT0) + (index * 3U)) & mask) != 0U); + return ((*(const volatile uint32_t *)(&(SCU_CLK->CGATSTAT0) + (index * 3U)) & mask) != 0U); } #endif @@ -1122,13 +1078,17 @@ void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv) { /* Go to bypass the USB PLL */ SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_VCOBYP_Msk; + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) + { + /* wait for prescaler mode */ + } /* disconnect Oscillator from USB PLL */ SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_FINDIS_Msk; /* Setup Divider settings for USB PLL */ - SCU_PLL->USBPLLCON = (uint32_t)((uint32_t)((ndiv -1U) << SCU_PLL_USBPLLCON_NDIV_Pos) | - (uint32_t)((pdiv - 1U) << SCU_PLL_USBPLLCON_PDIV_Pos)); + SCU_PLL->USBPLLCON = (uint32_t)((uint32_t)((ndiv - 1U) << SCU_PLL_USBPLLCON_NDIV_Pos) | + (uint32_t)((pdiv - 1U) << SCU_PLL_USBPLLCON_PDIV_Pos)); /* Set OSCDISCDIS */ SCU_PLL->USBPLLCON |= (uint32_t)SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; @@ -1144,6 +1104,17 @@ void XMC_SCU_CLOCK_StartUsbPll(uint32_t pdiv, uint32_t ndiv) /* wait for PLL Lock */ } + /* Disable bypass- put PLL clock back */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_VCOBYP_Msk; + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } + + /* Reset OSCDISCDIS */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_UVCOLCKT_Msk; } /* API to disable USB PLL operation */ @@ -1191,7 +1162,25 @@ void XMC_SCU_POWER_DisableUsb(void) SCU_POWER->PWRCLR = (uint32_t)(SCU_POWER_PWRCLR_USBOTGEN_Msk | SCU_POWER_PWRSET_USBPHYPDQ_Msk); #else SCU_POWER->PWRCLR = (uint32_t)SCU_POWER_PWRCLR_USBPHYPDQ_Msk; -#endif +#endif +} + +/* API to check status of USB weak pull-up activation */ +bool XMC_SCU_PCU_IsEnabledUsbPullUp(void) +{ + return (0UL != (SCU_POWER->PWRSTAT & SCU_POWER_PWRSET_USBPUWQ_Msk)); +} + +/* API to enable USB weak pull-up */ +void XMC_SCU_PCU_EnableUsbPullUp(void) +{ + SCU_POWER->PWRSET = SCU_POWER_PWRSET_USBPUWQ_Msk; +} + +/* API to disable USB weak pull-up */ +void XMC_SCU_PCU_DisableUsbPullUp(void) +{ + SCU_POWER->PWRCLR = SCU_POWER_PWRCLR_USBPUWQ_Msk; } /* API to check USB PLL is locked or not */ @@ -1204,21 +1193,21 @@ bool XMC_SCU_CLOCK_IsUsbPllLocked(void) void XMC_SCU_HIB_EnableHibernateDomain(void) { /* Power up HIB domain if and only if it is currently powered down */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) + if ((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) { SCU_POWER->PWRSET = (uint32_t)SCU_POWER_PWRSET_HIB_Msk; - - while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) + + while ((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0UL) { /* wait until HIB domain is enabled */ - } + } } - + /* Remove the reset only if HIB domain were in a state of reset */ - if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) + if ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) { SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_HIBRS_Msk; - while((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk) != 0UL) + while ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk) != 0UL) { /* wait until HIB domain is enabled */ } @@ -1228,25 +1217,25 @@ void XMC_SCU_HIB_EnableHibernateDomain(void) /* API to power down the hibernation domain */ void XMC_SCU_HIB_DisableHibernateDomain(void) { - /* Disable hibernate domain */ + /* Disable hibernate domain */ SCU_POWER->PWRCLR = (uint32_t)SCU_POWER_PWRCLR_HIB_Msk; - /* Reset of hibernate domain reset */ + /* Reset of hibernate domain reset */ SCU_RESET->RSTSET = (uint32_t)SCU_RESET_RSTSET_HIBRS_Msk; } /* API to check the hibernation domain is enabled or not */ bool XMC_SCU_HIB_IsHibernateDomainEnabled(void) { - return ((bool)(SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) && + return ((bool)(SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) && !(bool)(SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)); } /* API to enable internal slow clock - fOSI (32.768kHz) in hibernate domain */ void XMC_SCU_HIB_EnableInternalSlowClock(void) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) { - /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ + /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->OSCSICTRL &= (uint32_t)~(SCU_HIBERNATE_OSCSICTRL_PWD_Msk); } @@ -1254,29 +1243,29 @@ void XMC_SCU_HIB_EnableInternalSlowClock(void) /* API to disable internal slow clock - fOSI (32.768kHz) in hibernate domain */ void XMC_SCU_HIB_DisableInternalSlowClock(void) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk) { - /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ + /* Wait until OSCSICTRL register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->OSCSICTRL |= (uint32_t)SCU_HIBERNATE_OSCSICTRL_PWD_Msk; } void XMC_SCU_HIB_ClearEventStatus(int32_t event) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCLR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCLR_Msk) { - /* Wait until HDCLR register in hibernate domain is ready to accept a write */ + /* Wait until HDCLR register in hibernate domain is ready to accept a write */ } - SCU_HIBERNATE->HDCLR = event; + SCU_HIBERNATE->HDCLR = (uint32_t)event; } void XMC_SCU_HIB_TriggerEvent(int32_t event) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDSET_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDSET_Msk) { - /* Wait until HDSET register in hibernate domain is ready to accept a write */ + /* Wait until HDSET register in hibernate domain is ready to accept a write */ } - SCU_HIBERNATE->HDSET = event; + SCU_HIBERNATE->HDSET = (uint32_t)event; } void XMC_SCU_HIB_EnableEvent(int32_t event) @@ -1292,11 +1281,11 @@ void XMC_SCU_HIB_EnableEvent(int32_t event) #endif #endif - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } - SCU_HIBERNATE->HDCR |= event; + SCU_HIBERNATE->HDCR |= (uint32_t)event; } void XMC_SCU_HIB_DisableEvent(int32_t event) @@ -1312,18 +1301,18 @@ void XMC_SCU_HIB_DisableEvent(int32_t event) #endif #endif - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } - SCU_HIBERNATE->HDCR &= ~event; + SCU_HIBERNATE->HDCR &= (uint32_t)~event; } -void XMC_SCU_HIB_EnterHibernateState(void) +void XMC_SCU_HIB_EnterHibernateState(void) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_HIB_Msk; } @@ -1337,7 +1326,7 @@ void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode) #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) if (mode == XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HINTSET_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HINTSET_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } @@ -1348,9 +1337,9 @@ void XMC_SCU_HIB_EnterHibernateStateEx(XMC_SCU_HIB_HIBERNATE_MODE_t mode) void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } if (pin == XMC_SCU_HIB_IO_0) @@ -1359,15 +1348,15 @@ void XMC_SCU_HIB_SetWakeupTriggerInput(XMC_SCU_HIB_IO_t pin) } else { - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_WKUPSEL_Msk; + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_WKUPSEL_Msk; } } void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ~(SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk << (SCU_HIBERNATE_HDCR_HIBIOSEL_Size * pin))) | (mode << (SCU_HIBERNATE_HDCR_HIBIOSEL_Size * pin)); @@ -1375,9 +1364,9 @@ void XMC_SCU_HIB_SetPinMode(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode) void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ~(SCU_HIBERNATE_HDCR_HIBIO0POL_Msk << pin)) | (level << pin); @@ -1385,9 +1374,9 @@ void XMC_SCU_HIB_SetPinOutputLevel(XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_L void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { - /* Wait until HDCR register in hibernate domain is ready to accept a write */ + /* Wait until HDCR register in hibernate domain is ready to accept a write */ } if (pin == XMC_SCU_HIB_IO_0) @@ -1396,21 +1385,21 @@ void XMC_SCU_HIB_SetInput0(XMC_SCU_HIB_IO_t pin) } else { - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_GPI0SEL_Msk; + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_GPI0SEL_Msk; } } void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) - SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk)) | + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk)) | #else - SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk)) | -#endif + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk)) | +#endif input; } @@ -1419,18 +1408,18 @@ void XMC_SCU_HIB_SetSR0Input(XMC_SCU_HIB_SR0_INPUT_t input) #if ((UC_SERIES == XMC44) && (UC_PACKAGE == LQFP100)) void XMC_SCU_HIB_SetSR1Input(XMC_SCU_HIB_SR1_INPUT_t input) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } - SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI0SEL_Msk | SCU_HIBERNATE_HDCR_ADIG0SEL_Msk | SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk)) | + SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & (uint32_t)~(SCU_HIBERNATE_HDCR_GPI1SEL_Msk | SCU_HIBERNATE_HDCR_ADIG1SEL_Msk | SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk)) | input; } #endif void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } @@ -1440,7 +1429,7 @@ void XMC_SCU_HIB_LPAC_SetInput(XMC_SCU_HIB_LPAC_INPUT_t input) void XMC_SCU_HIB_LPAC_SetTrigger(XMC_SCU_HIB_LPAC_TRIGGER_t trigger) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } @@ -1460,14 +1449,14 @@ void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint config |= interval_count << SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos; config |= settle_count << SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos; - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCONF_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->LPACCONF = (SCU_HIBERNATE->LPACCONF & (uint32_t)~(SCU_HIBERNATE_LPACCONF_CONVDEL_Msk | - SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk | - SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk)) | + SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk | + SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk)) | config; } @@ -1475,7 +1464,7 @@ void XMC_SCU_HIB_LPAC_SetTiming(bool enable_delay, uint16_t interval_count, uint void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH0_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH0_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } @@ -1489,7 +1478,7 @@ void XMC_SCU_HIB_LPAC_SetVBATThresholds(uint8_t lower, uint8_t upper) void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } @@ -1503,7 +1492,7 @@ void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds(uint8_t lower, uint8_t upper) void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds(uint8_t lower, uint8_t upper) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACTH1_Msk) { /* Wait until HDCR register in hibernate domain is ready to accept a write */ } @@ -1521,7 +1510,7 @@ int32_t XMC_SCU_HIB_LPAC_GetStatus(void) void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCLR_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACCLR_Msk) { /* Wait until LPACCLR register in hibernate domain is ready to accept a write */ } @@ -1530,7 +1519,7 @@ void XMC_SCU_HIB_LPAC_ClearStatus(int32_t status) void XMC_SCU_HIB_LPAC_TriggerCompare(XMC_SCU_HIB_LPAC_INPUT_t input) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACSET_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_LPACSET_Msk) { /* Wait until LPACSET register in hibernate domain is ready to accept a write */ } @@ -1549,59 +1538,48 @@ bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable(void) void XMC_SCU_CLOCK_EnableLowPowerOscillator(void) { /* Enable OSC_ULP */ - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) - { - /* Wait until no pending update to OSCULCTRL register in hibernate domain */ - } + XMC_SCU_INTERRUPT_ClearEventStatus(XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED); SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; + while ((XMC_SCU_INTERUPT_GetEventStatus() & XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED) == 0); - /* Enable OSC_ULP Oscillator Watchdog*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDCR |= (uint32_t)SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - - /* Enable OSC_ULP Oscillator Watchdog*/ - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDSET_Msk) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - SCU_HIBERNATE->HDSET = (uint32_t)SCU_HIBERNATE_HDSET_ULPWDG_Msk; + /* Clear ULP WDG status */ + XMC_SCU_INTERRUPT_ClearEventStatus(XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED); + SCU_HIBERNATE->HDCLR = (uint32_t)SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while ((XMC_SCU_INTERUPT_GetEventStatus() & XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED) == 0); - while (XMC_SCU_GetMirrorStatus() != 0) - { - /* Wait until update of the stanby clock source is done in the HIB domain */ - } + /* Enable ULP WDG */ + XMC_SCU_INTERRUPT_ClearEventStatus(XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED); + SCU_HIBERNATE->HDCR |= (uint32_t)SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while ((XMC_SCU_INTERUPT_GetEventStatus() & XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED) == 0); } /* API to configure the 32khz Ultra Low Power oscillator */ void XMC_SCU_CLOCK_DisableLowPowerOscillator(void) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) { - /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->OSCULCTRL |= (uint32_t)SCU_HIBERNATE_OSCULCTRL_MODE_Msk; } void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput(void) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) { - /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->OSCULCTRL |= SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk | SCU_HIBERNATE_OSCULCTRL_MODE_Msk; } void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput(void) { - while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + while ((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) { - /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ + /* Wait until OSCULCTRL register in hibernate domain is ready to accept a write */ } SCU_HIBERNATE->OSCULCTRL = (SCU_HIBERNATE->OSCULCTRL & ~(uint32_t)(SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk | SCU_HIBERNATE_OSCULCTRL_MODE_Msk)) | - (SCU_HIBERNATE_OSCULCTRL_MODE_OSC_POWER_DOWN << SCU_HIBERNATE_OSCULCTRL_MODE_Pos); + (SCU_HIBERNATE_OSCULCTRL_MODE_OSC_POWER_DOWN << SCU_HIBERNATE_OSCULCTRL_MODE_Pos); } uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus(void) @@ -1688,6 +1666,10 @@ void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, /* Switch to prescaler mode */ SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) == 0U) + { + /* wait for prescaler mode */ + } /* disconnect Oscillator from PLL */ SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_FINDIS_Msk; @@ -1695,8 +1677,8 @@ void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, /* Setup divider settings for main PLL */ SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~(SCU_PLL_PLLCON1_NDIV_Msk | SCU_PLL_PLLCON1_K2DIV_Msk | SCU_PLL_PLLCON1_PDIV_Msk)) | ((ndiv - 1UL) << SCU_PLL_PLLCON1_NDIV_Pos) | - ((kdiv_temp - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos) | - ((pdiv - 1UL)<< SCU_PLL_PLLCON1_PDIV_Pos)); + ((kdiv_temp - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos) | + ((pdiv - 1UL) << SCU_PLL_PLLCON1_PDIV_Pos)); /* Set OSCDISCDIS, OSC clock remains connected to the VCO in case of loss of lock */ SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_OSCDISCDIS_Msk; @@ -1736,7 +1718,12 @@ void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, else { SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~SCU_PLL_PLLCON1_K1DIV_Msk) | - ((kdiv -1UL) << SCU_PLL_PLLCON1_K1DIV_Pos)); + ((kdiv - 1UL) << SCU_PLL_PLLCON1_K1DIV_Pos)); + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K1RDY_Msk) == 0U) + { + /* wait until K1-divider operates on the configured value */ + } /* Switch to prescaler mode */ SCU_PLL->PLLCON0 |= (uint32_t)SCU_PLL_PLLCON0_VCOBYP_Msk; @@ -1746,6 +1733,8 @@ void XMC_SCU_CLOCK_StartSystemPll(XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, /* wait for prescaler mode */ } } + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; } /* API to stop main PLL operation */ @@ -1758,7 +1747,12 @@ void XMC_SCU_CLOCK_StopSystemPll(void) void XMC_SCU_CLOCK_StepSystemPllFrequency(uint32_t kdiv) { SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~SCU_PLL_PLLCON1_K2DIV_Msk) | - ((kdiv - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos)); + ((kdiv - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos)); + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) + { + /* wait until K2-divider operates on the configured value */ + } XMC_SCU_lDelay(50U); } @@ -1773,17 +1767,17 @@ bool XMC_SCU_CLOCK_IsSystemPllLocked(void) * API to assign the event handler function to be executed on occurrence of the selected event. */ XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, - const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler) + const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler) { uint32_t index; XMC_SCU_STATUS_t status; - + index = 0U; while (((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) == 0U) && (index < XMC_SCU_INTERRUPT_EVENT_MAX)) { index++; } - + if (index == XMC_SCU_INTERRUPT_EVENT_MAX) { status = XMC_SCU_STATUS_ERROR; @@ -1791,9 +1785,9 @@ XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT else { event_handler_list[index] = handler; - status = XMC_SCU_STATUS_OK; + status = XMC_SCU_STATUS_OK; } - + return (status); } @@ -1805,26 +1799,26 @@ void XMC_SCU_IRQHandler(uint32_t sr_num) uint32_t index; XMC_SCU_INTERRUPT_EVENT_t event; XMC_SCU_INTERRUPT_EVENT_HANDLER_t event_handler; - + XMC_UNUSED_ARG(sr_num); - + index = 0U; event = XMC_SCU_INTERUPT_GetEventStatus(); while (index < XMC_SCU_INTERRUPT_EVENT_MAX) - { + { if ((event & ((XMC_SCU_INTERRUPT_EVENT_t)1 << index)) != 0U) { event_handler = event_handler_list[index]; if (event_handler != NULL) { - (event_handler)(); + (event_handler)(); } - + XMC_SCU_INTERRUPT_ClearEventStatus((uint32_t)(1UL << index)); - + break; - } - index++; + } + index++; } } diff --git a/cores/xmc_lib/XMCLib/src/xmc_acmp.c b/cores/xmc_lib/XMCLib/src/xmc_acmp.c index 38f34a3c..cc91fda3 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_acmp.c +++ b/cores/xmc_lib/XMCLib/src/xmc_acmp.c @@ -1,61 +1,43 @@ /** * @file xmc_acmp.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2014-12-10: - * - Initial
    - * 2015-02-20: - * - Removed unused declarations
    - * 2015-05-08: - * - Fixed sequence problem of low power mode in XMC_ACMP_Init() API
    - * - Fixed wrong register setting in XMC_ACMP_SetInput() API
    - * - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API.
    - * Additional call to XMC_ACMP_EnableComparator() API needed to start Comparator after Init.
    - * 2015-06-04: - * - Removed return type variable and by default comparator enable from XMC_ACMP_Init() API.
    - * - Divided XMC_ACMP_SetInput into two 3 APIs to reduce the code size and complexity as stated below
    - * (a)XMC_ACMP_EnableReferenceDivider
    - * (b)XMC_ACMP_DisableReferenceDivider
    - * (c)XMC_ACMP_SetInput
    - * - Optimized enable and disable API's and moved to header file as static inline APIs. - * - XMC_ACMP_t typedef changed to structure which overrides the standard header file structure. - * 2015-06-20: - * - Removed definition of GetDriverVersion API - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -63,7 +45,7 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_acmp.h" /* If ACMP is available*/ #if defined (COMPARATOR) @@ -100,9 +82,9 @@ void XMC_ACMP_SetInput(XMC_ACMP_t *const peripheral, uint32_t instance, XMC_ACMP { XMC_ASSERT("XMC_ACMP_SetInput:Wrong module pointer", XMC_ACMP_CHECK_MODULE_PTR(peripheral)) XMC_ASSERT("XMC_ACMP_SetInput:Wrong instance number", ((instance != XMC_ACMP_INSTANCE_1) && - XMC_ACMP_CHECK_INSTANCE(instance)) ) + XMC_ACMP_CHECK_INSTANCE(instance)) ) XMC_ASSERT("XMC_ACMP_SetInput:Wrong input source", ((source == XMC_ACMP_INP_SOURCE_STANDARD_PORT) || - (source == XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT)) ) + (source == XMC_ACMP_INP_SOURCE_ACMP1_INP_PORT)) ) /* * Three options of Input Setting are listed below diff --git a/cores/xmc_lib/XMCLib/src/xmc_bccu.c b/cores/xmc_lib/XMCLib/src/xmc_bccu.c index 99d5449e..cefe6e73 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_bccu.c +++ b/cores/xmc_lib/XMCLib/src/xmc_bccu.c @@ -1,55 +1,41 @@ /** * @file xmc_bccu.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-19: - * - Initial draft
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-05-08: - * - Minor bug fixes in following APIs: XMC_BCCU_ConcurrentStartDimming(), XMC_BCCU_ConcurrentAbortDimming(), - * XMC_BCCU_SetGlobalDimmingLevel()
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * Detailed description of file:
    - * APIs for the functional blocks of BCCU have been defined:
    - * -- GLOBAL configuration
    - * -- Clock configuration, Function/Event configuration, Interrupt configuration
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -58,10 +44,10 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_bccu.h" #if defined(BCCU0) -#include +#include "xmc_scu.h" /********************************************************************************************************************* * MACROS @@ -99,9 +85,9 @@ void XMC_BCCU_GlobalInit(XMC_BCCU_t *const bccu, const XMC_BCCU_GLOBAL_CONFIG_t XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_BCCU0); bccu->GLOBCON = config->globcon; - + bccu->GLOBCLK = config->globclk; - bccu->GLOBDIM = config->global_dimlevel; + bccu->GLOBDIM = config->global_dimlevel; } @@ -147,7 +133,7 @@ void XMC_BCCU_ConfigSuspendMode (XMC_BCCU_t *const bccu, XMC_BCCU_SUSPEND_MODE_t void XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_no) { XMC_ASSERT("XMC_BCCU_SetFlickerWDThreshold: Invalid threshold no", (threshold_no <= BCCU_GLOBCON_WDMBN_Msk)); - + bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_WDMBN_Msk); bccu->GLOBCON |= (uint32_t)(threshold_no << BCCU_GLOBCON_WDMBN_Pos); } @@ -158,10 +144,10 @@ void XMC_BCCU_SetFlickerWDThreshold (XMC_BCCU_t *const bccu, uint32_t threshold_ void XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div) { XMC_ASSERT("XMC_BCCU_SetFastClockPrescaler: Invalid divider value", (div <= BCCU_GLOBCLK_FCLK_PS_Msk)); - + bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_FCLK_PS_Msk); bccu->GLOBCLK |= div; - + } /* @@ -173,7 +159,7 @@ void XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div) bccu->GLOBCLK &= ~(uint32_t)(BCCU_GLOBCLK_DCLK_PS_Msk); bccu->GLOBCLK |= (uint32_t)(div << BCCU_GLOBCLK_DCLK_PS_Pos); - + } /* @@ -210,7 +196,7 @@ void XMC_BCCU_ConcurrentDisableChannels (XMC_BCCU_t *const bccu, uint32_t mask) void XMC_BCCU_ConcurrentSetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_mask, XMC_BCCU_CH_ACTIVE_LEVEL_t level) { XMC_ASSERT("XMC_BCCU_ConcurrentSetOutputPassiveLevel: Invalid channel mask", (chan_mask <= XMC_BCCU_CHANNEL_MASK)); - + bccu->CHOCON &= ~(uint32_t)(chan_mask); bccu->CHOCON |= (chan_mask * (uint32_t)level); } @@ -241,7 +227,7 @@ void XMC_BCCU_ConcurrentDisableTrap (XMC_BCCU_t *const bccu, uint32_t mask) void XMC_BCCU_ConcurrentConfigTrigger (XMC_BCCU_t *const bccu, XMC_BCCU_TRIG_CONFIG_t *trig) { uint32_t reg; - + XMC_ASSERT("XMC_BCCU_ConcurrentConfigTrigger: Invalid channel mask", (trig->mask_chans <= XMC_BCCU_CHANNEL_MASK)); bccu->GLOBCON &= ~(uint32_t)(BCCU_GLOBCON_TM_Msk | BCCU_GLOBCON_TRDEL_Msk); @@ -327,7 +313,7 @@ void XMC_BCCU_SetGlobalDimmingLevel (XMC_BCCU_t *const bccu, uint32_t level) */ void XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no) { - XMC_ASSERT("XMC_BCCU_EnableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_EnableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHEN |= (uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no); } @@ -337,7 +323,7 @@ void XMC_BCCU_EnableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no) */ void XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no) { - XMC_ASSERT("XMC_BCCU_DisableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_DisableChannel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHEN &= ~(uint32_t)(BCCU_CHEN_ECH0_Msk << chan_no); } @@ -347,7 +333,7 @@ void XMC_BCCU_DisableChannel (XMC_BCCU_t *const bccu, uint32_t chan_no) */ void XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_ACTIVE_LEVEL_t level) { - XMC_ASSERT("XMC_BCCU_SetOutputPassiveLevel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_SetOutputPassiveLevel: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHOCON |= ((uint32_t)level << chan_no); } @@ -357,7 +343,7 @@ void XMC_BCCU_SetOutputPassiveLevel(XMC_BCCU_t *const bccu, uint32_t chan_no, XM */ void XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no) { - XMC_ASSERT("XMC_BCCU_EnableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_EnableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHOCON |= (uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no); } @@ -367,7 +353,7 @@ void XMC_BCCU_EnableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no) */ void XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no) { - XMC_ASSERT("XMC_BCCU_DisableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_DisableTrap: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHOCON &= ~(uint32_t)(BCCU_CHOCON_CH0TPE_Msk << chan_no); } @@ -378,7 +364,7 @@ void XMC_BCCU_DisableTrap (XMC_BCCU_t *const bccu, uint32_t chan_no) void XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XMC_BCCU_CH_TRIGOUT_t trig_line) { uint32_t reg; - XMC_ASSERT("XMC_BCCU_EnableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_EnableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_TOS0_Msk << chan_no); reg = (uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no); @@ -391,7 +377,7 @@ void XMC_BCCU_EnableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no, XM */ void XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no) { - XMC_ASSERT("XMC_BCCU_DisableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS-1))); + XMC_ASSERT("XMC_BCCU_DisableChannelTrigger: Invalid channel number", (chan_no <= (XMC_BCCU_NO_OF_CHANNELS - 1))); bccu->CHTRIG &= ~(uint32_t)(BCCU_CHTRIG_ET0_Msk << chan_no); } @@ -402,9 +388,9 @@ void XMC_BCCU_DisableChannelTrigger (XMC_BCCU_t *const bccu, uint32_t chan_no) void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t *const config) { channel->CHCONFIG = config->chconfig; - + channel->PKCMP = config->pkcmp; - + channel->PKCNTR = config->pkcntr; } @@ -413,9 +399,9 @@ void XMC_BCCU_CH_Init (XMC_BCCU_CH_t *const channel, const XMC_BCCU_CH_CONFIG_t */ void XMC_BCCU_CH_ConfigTrigger (XMC_BCCU_CH_t *const channel, XMC_BCCU_CH_TRIG_EDGE_t edge, uint32_t force_trig_en) { - uint32_t reg; + uint32_t reg; channel->CHCONFIG &= ~(uint32_t)(BCCU_CH_CHCONFIG_TRED_Msk | BCCU_CH_CHCONFIG_ENFT_Msk); - + reg = ((uint32_t)edge << BCCU_CH_CHCONFIG_TRED_Pos); reg |= (uint32_t)(force_trig_en << BCCU_CH_CHCONFIG_ENFT_Pos); channel->CHCONFIG |= reg; @@ -443,7 +429,7 @@ void XMC_BCCU_CH_SetTargetIntensity (XMC_BCCU_CH_t *const channel, uint32_t ch_i */ uint32_t XMC_BCCU_CH_ReadIntensity (XMC_BCCU_CH_t *const channel) { - return (uint32_t)(channel->INT & BCCU_CH_INT_CHINT_Msk); + return (uint32_t)(channel->INT &BCCU_CH_INT_CHINT_Msk); } /* diff --git a/cores/xmc_lib/XMCLib/src/xmc_can.c b/cores/xmc_lib/XMCLib/src/xmc_can.c index 0c97c379..68eb4d12 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_can.c +++ b/cores/xmc_lib/XMCLib/src/xmc_can.c @@ -1,73 +1,52 @@ /** * @file xmc_can.c - * @date 2016-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-05-20: - * - New API added: XMC_CAN_MO_ReceiveData()
    - * - XMC_CAN_MO_Config() signature has changed
    - * - Minor fix in XMC_CAN_TXFIFO_ConfigMOSlaveObject().
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-09-01: - * - Removed fCANB clock support
    + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2015-09-08: - * - Fixed bug in XMC_CAN_Init()
    - * - * 2016-06-07: - * - Changed XMC_CAN_AllocateMOtoNodeList to wait for ready status of list controller - * - * 2015-06-20: - * - Fixed bug in XMC_CAN_MO_Config()
    * @endcond * - */ + */ /******************************************************************************* * HEADER FILES *******************************************************************************/ #include "xmc_can.h" -#if defined(CAN) +#if defined(CAN_xmc) #include "xmc_scu.h" __STATIC_INLINE uint32_t max(uint32_t a, uint32_t b) @@ -84,9 +63,102 @@ __STATIC_INLINE uint32_t min(uint32_t a, uint32_t b) * API IMPLEMENTATION *******************************************************************************/ +/* The max prescaler is the equal to max BRP setting (64) multiply by 8 (DIV8) */ +#define XMC_CAN_NODE_MAX_PRESCALER 512 + +/* maximum TSEG1 is 16 and maximum TSEG2 is 8, plus one fix sync tq */ +#define XMC_CAN_NODE_MAX_NTQ 25 +#define XMC_CAN_NODE_MIN_NTQ 8 + +#define XMC_CAN_NODE_MIN_TSEG1 3 +#define XMC_CAN_NODE_MIN_TSEG2 2 + +#define XMC_CAN_NODE_MAX_TSEG1 15 +#define XMC_CAN_NODE_MAX_TSEG2 7 + + +int32_t XMC_CAN_NODE_NominalBitTimeConfigureEx(XMC_CAN_NODE_t *const can_node, + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const bit_time_config) +{ + /* Check that the CAN frequency is a multiple of the required baudrate */ + if ((bit_time_config->can_frequency % bit_time_config->baudrate) == 0) + { + uint32_t prescaler = 0; + uint32_t div8 = 0; + + /* Calculate the factor between can frequency and required baudrate, this is equal to (prescaler x ntq) */ + uint32_t fcan_div = bit_time_config->can_frequency / bit_time_config->baudrate; + + /* start with highest ntq, i.e as much as possible time quanta should be used to construct a bit time */ + uint32_t ntq = XMC_CAN_NODE_MAX_NTQ; + uint32_t tseg1 = 0; + uint32_t tseg2 = 0; + while (ntq >= XMC_CAN_NODE_MIN_NTQ) + { + /* consider this ntq, only if fcan_div is multiple of ntq */ + if ((fcan_div % ntq) == 0) + { + div8 = 0; + prescaler = fcan_div / ntq; + if ((prescaler > 0) && (prescaler <= XMC_CAN_NODE_MAX_PRESCALER)) + { + if (prescaler >= 64) + { + /* consider prescaler >=64, if it is integer divisible by 8*/ + if ((prescaler & 0x7U) != 0) + { + --ntq; + continue; + } + else + { + div8 = 1; + } + } + + tseg1 = ((ntq - 1) * bit_time_config->sample_point) / 10000; + tseg2 = ntq - tseg1 - 1; + + if ((XMC_CAN_NODE_MIN_TSEG1 <= tseg1) && (tseg1 <= XMC_CAN_NODE_MAX_TSEG1) && + (XMC_CAN_NODE_MIN_TSEG2 <= tseg2) && (tseg2 < XMC_CAN_NODE_MAX_TSEG2) && (tseg2 >= bit_time_config->sjw)) + { + break; + } + + + } + } + --ntq; + } + + if (ntq >= XMC_CAN_NODE_MIN_NTQ) + { + + XMC_ASSERT("XMC_CAN_NODE_NominalBitTimeConfigureEx: prescaler", (prescaler != 0)); + XMC_ASSERT("XMC_CAN_NODE_NominalBitTimeConfigureEx: tseg1", (tseg1 != 0)); + XMC_ASSERT("XMC_CAN_NODE_NominalBitTimeConfigureEx: tseg2", (tseg2 != 0)); + + XMC_CAN_NODE_EnableConfigurationChange(can_node); + + /* Configure bit timing register */ + can_node->NBTR = (((tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) | + (((bit_time_config->sjw - 1U) << CAN_NODE_NBTR_SJW_Pos) & (uint32_t)CAN_NODE_NBTR_SJW_Msk) | + (((tseg1 - 1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk) | + ((((prescaler >> (3 * div8)) - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk) | + ((div8 << CAN_NODE_NBTR_DIV8_Pos) & (uint32_t)CAN_NODE_NBTR_DIV8_Msk); + + XMC_CAN_NODE_DisableConfigurationChange(can_node); + + return XMC_CAN_STATUS_SUCCESS; + } + } + + return XMC_CAN_STATUS_ERROR; +} + /* Baudrate Configuration */ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, - const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time) + const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time) { uint32_t temp_brp = 12U ; uint32_t temp_tseg1 = 12U; @@ -104,7 +176,7 @@ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, can_bit_time->can_frequency > 5000000U); XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: sample point not supported", (can_bit_time->sample_point < 10000U) && ((can_bit_time->sample_point > 0U))); - + /* * Bit timing & sampling * Tq = (BRP+1)/Fcan if DIV8 = 0 @@ -129,46 +201,46 @@ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, uint32_t temp_baudrate; uint32_t error; - if((temp_tbaud % 10U) > 5U) - { - temp_tbaud = (uint32_t)(temp_tbaud / 10U); - temp_tbaud++; - } - else - { - temp_tbaud = (uint32_t)(temp_tbaud / 10U); - } - - if(temp_tbaud > 0U) - { - temp_baudrate = (uint32_t) (f_quanta / (temp_tbaud * 10U)); - } - else - { - temp_baudrate = f_quanta / 10U; - temp_tbaud = 1; - } + if ((temp_tbaud % 10U) > 5U) + { + temp_tbaud = (uint32_t)(temp_tbaud / 10U); + temp_tbaud++; + } + else + { + temp_tbaud = (uint32_t)(temp_tbaud / 10U); + } - if(temp_baudrate >= can_bit_time->baudrate) - { - error = temp_baudrate - can_bit_time->baudrate; - } - else - { - error = can_bit_time->baudrate - temp_baudrate; - } + if (temp_tbaud > 0U) + { + temp_baudrate = (uint32_t) (f_quanta / (temp_tbaud * 10U)); + } + else + { + temp_baudrate = f_quanta / 10U; + temp_tbaud = 1; + } - if ((temp_tbaud <= 20U) && (best_error > error)) - { - best_brp = temp_brp; - best_tbaud = temp_tbaud; - best_error = (error); + if (temp_baudrate >= can_bit_time->baudrate) + { + error = temp_baudrate - can_bit_time->baudrate; + } + else + { + error = can_bit_time->baudrate - temp_baudrate; + } - if (error < 1000U) + if ((temp_tbaud <= 20U) && (best_error > error)) { - break; + best_brp = temp_brp; + best_tbaud = temp_tbaud; + best_error = (error); + + if (error < 1000U) + { + break; + } } - } } /* search for best sample point */ best_error = 10000U; @@ -176,15 +248,15 @@ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, for (temp_tseg1 = 64U; temp_tseg1 >= 3U; temp_tseg1--) { uint32_t tempSamplePoint = ((temp_tseg1 + 1U) * 10000U) / best_tbaud; - uint32_t error; - if (tempSamplePoint >= can_bit_time->sample_point) - { + uint32_t error; + if (tempSamplePoint >= can_bit_time->sample_point) + { error = tempSamplePoint - can_bit_time->sample_point; - } - else - { - error = can_bit_time->sample_point - tempSamplePoint; - } + } + else + { + error = can_bit_time->sample_point - tempSamplePoint; + } if (best_error > error) { best_tseg1 = temp_tseg1; @@ -201,9 +273,9 @@ void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node, XMC_CAN_NODE_EnableConfigurationChange(can_node); /* Configure bit timing register */ can_node->NBTR = (((uint32_t)(best_tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) | - ((((uint32_t)((uint32_t)(can_bit_time->sjw)-1U) << CAN_NODE_NBTR_SJW_Pos)) & (uint32_t)CAN_NODE_NBTR_SJW_Msk)| - (((uint32_t)(best_tseg1-1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk)| - (((uint32_t)(best_brp - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk)| + ((((uint32_t)((uint32_t)(can_bit_time->sjw) - 1U) << CAN_NODE_NBTR_SJW_Pos)) & (uint32_t)CAN_NODE_NBTR_SJW_Msk) | + (((uint32_t)(best_tseg1 - 1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk) | + (((uint32_t)(best_brp - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk) | (((uint32_t)0U << CAN_NODE_NBTR_DIV8_Pos) & (uint32_t)CAN_NODE_NBTR_DIV8_Msk); XMC_CAN_NODE_DisableConfigurationChange(can_node); } @@ -217,7 +289,7 @@ void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, }; /* Panel Command for allocation of MO to node list */ - XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U)); + XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE, mo_num, (node_num + 1U)); } /* Disable XMC_CAN Peripheral */ @@ -249,34 +321,8 @@ void XMC_CAN_Enable(XMC_CAN_t *const obj) /*Do nothing*/ }; } -#if defined(MULTICAN_PLUS) -uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj) -{ - uint32_t frequency; - - switch(XMC_CAN_GetBaudrateClockSource(obj)) - { -#if UC_FAMILY == XMC4 - case XMC_CAN_CANCLKSRC_FPERI: - frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); - break; -#else - case XMC_CAN_CANCLKSRC_MCLK: - frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); - break; -#endif - case XMC_CAN_CANCLKSRC_FOHP: - frequency = OSCHP_GetFrequency(); - break; - - default: - frequency = 0; - break; - } - - return frequency; -} +#if defined(MULTICAN_PLUS) void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency) { uint32_t step_n, step_f; @@ -319,16 +365,6 @@ void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can } -void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source) -{ - obj->MCR = (obj->MCR & ~CAN_MCR_CLKSEL_Msk) | source ; -} - -XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj) -{ - return ((XMC_CAN_CANCLKSRC_t)((obj->MCR & CAN_MCR_CLKSEL_Msk) >> CAN_MCR_CLKSEL_Pos)); -} - #else /* Initialization of XMC_CAN GLOBAL Object */ void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency) @@ -370,18 +406,95 @@ void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency) } #endif +void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj, const XMC_CAN_CANCLKSRC_t source) +{ +#if defined(MULTICAN_PLUS) + obj->MCR = (obj->MCR & ~CAN_MCR_CLKSEL_Msk) | source ; +#else + XMC_UNUSED_ARG(obj); + XMC_UNUSED_ARG(source); +#endif +} + +XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj) +{ +#if defined(MULTICAN_PLUS) + return ((XMC_CAN_CANCLKSRC_t)((obj->MCR & CAN_MCR_CLKSEL_Msk) >> CAN_MCR_CLKSEL_Pos)); +#elif (UC_FAMILY == XMC4) + XMC_UNUSED_ARG(obj); + return XMC_CAN_CANCLKSRC_FPERI; +#endif +} + +uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj) +{ + uint32_t frequency = 0; + +#if defined(MULTICAN_PLUS) + switch (XMC_CAN_GetBaudrateClockSource(obj)) + { +#if UC_FAMILY == XMC4 + case XMC_CAN_CANCLKSRC_FPERI: + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + break; +#else + case XMC_CAN_CANCLKSRC_MCLK: + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + break; +#endif + case XMC_CAN_CANCLKSRC_FOHP: + frequency = OSCHP_GetFrequency(); + break; + } +#else + XMC_UNUSED_ARG(obj); + frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); +#endif + + return frequency; +} + +uint32_t XMC_CAN_InitEx(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency) +{ + uint32_t step_n; + uint32_t freq_n; + uint32_t peripheral_frequency; + + /*Enabling the module*/ + XMC_CAN_Enable(obj); + + XMC_CAN_SetBaudrateClockSource(obj, clksrc); + peripheral_frequency = XMC_CAN_GetBaudrateClockFrequency(obj); + XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency); + + /* Normal divider mode */ + step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U); + freq_n = (uint32_t)(peripheral_frequency / (1024U - step_n)); + + obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk); + obj->FDR |= ((uint32_t)XMC_CAN_DM_NORMAL << CAN_FDR_DM_Pos) | ((uint32_t)step_n << CAN_FDR_STEP_Pos); + + return freq_n; +} + +uint32_t XMC_CAN_GetClockFrequency(XMC_CAN_t *const obj) +{ + uint32_t step_n = (obj->FDR & CAN_FDR_STEP_Msk) >> CAN_FDR_STEP_Pos; + return (XMC_CAN_GetBaudrateClockFrequency(obj) * (1024U - step_n)); +} + /* Sets the Identifier of the MO */ void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier) { if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk) { can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) | - ((can_identifier << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)CAN_MO_MOAR_ID_Msk); + ((can_identifier << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)CAN_MO_MOAR_ID_Msk); } else { can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) | - (can_identifier & (uint32_t)CAN_MO_MOAR_ID_Msk); + (can_identifier & (uint32_t)CAN_MO_MOAR_ID_Msk); } can_mo->can_identifier = can_identifier; } @@ -393,11 +506,11 @@ uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo) uint32_t identifier; if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk) { - identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; + identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; } else { - identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)); + identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)); } return identifier; } @@ -407,7 +520,7 @@ uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo) { uint32_t identifier_mask; if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk) - && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) + && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) { identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos; } @@ -418,20 +531,22 @@ uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo) return identifier_mask; } -/* Gets the acceptance mask of the MO */ -void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask) +/* Sets the acceptance mask of the MO */ +void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo, const uint32_t can_id_mask) { - if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk) - && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)) + if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != 0) + && ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) == 0)) { - can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | - (can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos); + /* Message object n receives frames only with matching IDE bit. */ + can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | + ((can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)XMC_CAN_MO_MOAR_STDID_Msk); } else { - can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | - (can_id_mask & (uint32_t)CAN_MO_MOAMR_AM_Msk); + can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) | + (can_id_mask & (uint32_t)CAN_MO_MOAMR_AM_Msk); } + can_mo->can_id_mask = can_id_mask; } @@ -439,19 +554,19 @@ void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_ void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo) { uint32_t reg; - + /* Configure MPN */ - uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U)/0x0020U; - uint32_t set = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos)); + uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U) / 0x0020U; + uint32_t set = (((uint32_t)(num / 32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num % 32) << CAN_MO_MOIPR_MPN_Pos)); can_mo->can_mo_ptr->MOIPR &= ~(CAN_MO_MOIPR_MPN_Msk); can_mo->can_mo_ptr->MOIPR |= set; - + if (((can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_STANDARD_11BITS) && (can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_EXTENDED_29BITS)) || ((can_mo->can_mo_type != XMC_CAN_MO_TYPE_RECMSGOBJ) && (can_mo->can_mo_type != XMC_CAN_MO_TYPE_TRANSMSGOBJ))) { - ; /*Do nothing*/ + /*Do nothing*/ } else { @@ -481,16 +596,21 @@ void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo) /* Set MO as Transmit message object */ XMC_CAN_MO_UpdateData(can_mo); can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETDIR_Msk; + + /* Reset RTSEL and Set MSGVAL, TXEN0 and TXEN1 bits */ + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk | + CAN_MO_MOCTR_RESRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk); } else { /* Set MO as Receive message object and set RXEN bit */ can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESDIR_Msk; + + /* Reset RTSEL, TXEN1 and TXEN2 and Set MSGVAL and RXEN bits */ + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_RESTXEN0_Msk | CAN_MO_MOCTR_RESTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk | + CAN_MO_MOCTR_SETRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk); } - /* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */ - can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk | - CAN_MO_MOCTR_SETRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk); } } @@ -509,7 +629,7 @@ XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo) can_mo->can_mo_ptr->MODATAL = can_mo->can_data[0]; can_mo->can_mo_ptr->MODATAH = can_mo->can_data[1]; /* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */ - can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETNEWDAT_Msk| CAN_MO_MOCTR_SETMSGVAL_Msk |CAN_MO_MOCTR_RESRTSEL_Msk); + can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETNEWDAT_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk | CAN_MO_MOCTR_RESRTSEL_Msk); error = XMC_CAN_STATUS_SUCCESS; } else @@ -572,7 +692,8 @@ XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo) rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos); new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos); - } while ((rx_pnd != 0U) && (new_data != 0U)); + } + while ((rx_pnd != 0U) || (new_data != 0U)); error = XMC_CAN_STATUS_SUCCESS; } @@ -609,7 +730,7 @@ XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo) can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS; can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos; can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos; - if(can_mo->can_ide_mask == 1U) + if (can_mo->can_ide_mask == 1U) { can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos; } @@ -632,7 +753,8 @@ XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo) rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos); new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos); - } while ((rx_pnd != 0U) && (new_data != 0U)); + } + while ((rx_pnd != 0U) && (new_data != 0U)); can_mo->can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ; error = XMC_CAN_STATUS_SUCCESS; @@ -643,7 +765,7 @@ XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo) /* Function to enable node event */ void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event) { - if(event != XMC_CAN_NODE_EVENT_CFCIE) + if (event != XMC_CAN_NODE_EVENT_CFCIE) { can_node->NCR |= (uint32_t)event; } @@ -656,7 +778,7 @@ void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE /* Function to disable node event */ void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event) { - if(event != XMC_CAN_NODE_EVENT_CFCIE) + if (event != XMC_CAN_NODE_EVENT_CFCIE) { can_node->NCR &= ~(uint32_t)event; } @@ -672,7 +794,7 @@ XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo) uint32_t mo_type = ((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos); uint32_t mo_transmission_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos; uint32_t mo_cur = (uint32_t)(can_mo->can_mo_ptr-> MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos; - CAN_MO_TypeDef* mo = (CAN_MO_TypeDef *)(CAN_BASE + 0x1000UL + (mo_cur * 0x0020UL)); + CAN_MO_TypeDef *mo = (CAN_MO_TypeDef *)(CAN_BASE + 0x1000UL + (mo_cur * 0x0020UL)); /* check if message is disabled */ if (mo_type == 0U) { @@ -692,44 +814,44 @@ XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo) } /* Function to initialize the transmit FIFO MO base object */ -void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_FIFO_CONFIG_t can_fifo) { can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | (((uint32_t)0x2U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_BOT_Msk | - CAN_MO_MOFGPR_TOP_Msk | - CAN_MO_MOFGPR_CUR_Msk)) | + CAN_MO_MOFGPR_TOP_Msk | + CAN_MO_MOFGPR_CUR_Msk)) | (((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t) CAN_MO_MOFGPR_CUR_Msk) | (((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t) CAN_MO_MOFGPR_TOP_Msk); } /* Function to Initialize the receive FIFO MO base object */ -void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_FIFO_CONFIG_t can_fifo) { can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | (((uint32_t)0x1U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~( uint32_t)(CAN_MO_MOFGPR_BOT_Msk | - CAN_MO_MOFGPR_TOP_Msk | - CAN_MO_MOFGPR_CUR_Msk)) | + CAN_MO_MOFGPR_TOP_Msk | + CAN_MO_MOFGPR_CUR_Msk)) | (((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | (((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk); } /* Function to Initialize the FIFO MO slave object */ -void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo) +void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_FIFO_CONFIG_t can_fifo) { can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) | (((uint32_t)0x3U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk); can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_CUR_Msk)) | (((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk); - can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETTXEN0_Msk| + can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_RESTXEN1_Msk; } /* Function to Initialize the Gateway Source Object */ -void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway) +void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo, const XMC_CAN_GATEWAY_CONFIG_t can_gateway) { can_mo->can_mo_ptr->MOFCR = (((uint32_t)0x4U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk) | ((((uint32_t)can_gateway.gateway_data_frame_send) << CAN_MO_MOFCR_GDFS_Pos) & (uint32_t)CAN_MO_MOFCR_GDFS_Msk) | @@ -737,8 +859,8 @@ void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC ((((uint32_t)can_gateway.gateway_identifier_copy) << CAN_MO_MOFCR_IDC_Pos) & (uint32_t)CAN_MO_MOFCR_IDC_Msk) | ((((uint32_t)can_gateway.gateway_data_copy) << CAN_MO_MOFCR_DATC_Pos) & (uint32_t)CAN_MO_MOFCR_DATC_Msk) ; can_mo->can_mo_ptr->MOFGPR = (uint32_t)((((uint32_t)can_gateway.gateway_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) | - (((uint32_t)can_gateway.gateway_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | - (((uint32_t)can_gateway.gateway_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk)); + (((uint32_t)can_gateway.gateway_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) | + (((uint32_t)can_gateway.gateway_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk)); } #endif /* XMC_CAN_H */ diff --git a/cores/xmc_lib/XMCLib/src/xmc_ccu4.c b/cores/xmc_lib/XMCLib/src/xmc_ccu4.c index 4846e8c3..c502a50f 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_ccu4.c +++ b/cores/xmc_lib/XMCLib/src/xmc_ccu4.c @@ -1,71 +1,45 @@ /** * @file xmc_ccu4.c - * @date 2017-04-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-07-01: - * - In XMC_CCU4_SLICE_StartConfig(), Options in XMC_ASSERT check for start mode is corrected.
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-07-24: - * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
    - * - * 2015-08-17: - * - Start of prescaler XMC_CCU4_StartPrescaler() is invoked in XMC_CCU4_Init() API.
    - * - Bug fix XMC_CCU4_SLICE_ConfigureEvent() during the level setting for XMC14 devices.
    - * - XMC_CCU4_EnableShadowTransfer() definition is removed, since the API is made as inline.
    - * - * 2015-10-07: - * - XMC_CCU4_SLICE_GetEvent() is made as inline. - * - DOC updates for the newly added APIs. - * - * 2017-02-25: - * - XMC_CCU4_lAssertReset(), XMC_CCU4_lDeassertReset(), XMC_CCU4_lGateClock() and XMC_CCU4_lUngateClock() fix compilation warnings. - * - * 2017-04-27: - * - XMC_CCU4_SLICE_SetPrescaler() changed div_val parameter to type XMC_CCU4_SLICE_PRESCALER_t + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ - + /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ @@ -290,7 +264,7 @@ void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module) /* Enable CCU4 module clock */ XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU); #endif - + #if defined(CLOCK_GATING_SUPPORTED) XMC_CCU4_lUngateClock(module); #endif @@ -307,7 +281,7 @@ void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module) #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_CCU4_lAssertReset(module); #endif - + #if defined(CLOCK_GATING_SUPPORTED) XMC_CCU4_lGateClock(module); #endif @@ -317,7 +291,7 @@ void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module) void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action) { uint32_t gctrl; - + XMC_ASSERT("XMC_CCU4_Init:Invalid module pointer", XMC_CCU4_IsValidModule(module)); XMC_ASSERT("XMC_CCU4_Init:Invalid mcs action", XMC_CCU4_SLICE_CHECK_MCS_ACTION(mcs_action)); @@ -325,11 +299,11 @@ void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_AC XMC_CCU4_EnableModule(module); /* Start the prescaler */ XMC_CCU4_StartPrescaler(module); - + gctrl = module->GCTRL; gctrl &= ~((uint32_t) CCU4_GCTRL_MSDE_Msk); gctrl |= ((uint32_t) mcs_action) << CCU4_GCTRL_MSDE_Pos; - + module->GCTRL = gctrl; } @@ -344,7 +318,7 @@ void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLO gctrl = module->GCTRL; gctrl &= ~((uint32_t) CCU4_GCTRL_PCIS_Msk); gctrl |= ((uint32_t) clock) << CCU4_GCTRL_PCIS_Pos; - + module->GCTRL = gctrl; } @@ -354,7 +328,7 @@ void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, uint32_t gctrl; XMC_ASSERT("XMC_CCU4_SetMultiChannelShadowTransferMode:Invalid module Pointer", XMC_CCU4_IsValidModule(module)); - + gctrl = module->GCTRL; gctrl &= ~((uint32_t)slice_mode_msk >> 16U); gctrl |= ((uint32_t)slice_mode_msk & 0xFFFFU); @@ -385,7 +359,7 @@ void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice, /* API to configure CC4 Slice for Capture */ void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init) + const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init) { XMC_ASSERT("XMC_CCU4_SLICE_CaptureInit:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_CaptureInit:Capture Init Pointer is NULL", @@ -404,16 +378,16 @@ void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice, /* API to configure the Start trigger function of a slice */ void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_t event, const XMC_CCU4_SLICE_START_MODE_t start_mode) { uint32_t cmc; uint32_t tc; - + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); - XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Start Mode", - ((start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) ||\ + XMC_ASSERT("XMC_CCU4_SLICE_StartConfig:Invalid Start Mode", + ((start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) || \ (start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START))); /* First, Bind the event with the stop function */ cmc = slice->CMC; @@ -421,7 +395,7 @@ void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, cmc |= ((uint32_t) event) << CCU4_CC4_CMC_STRTS_Pos; slice->CMC = cmc; - + tc = slice->TC; /* Next, Configure the start mode */ if (start_mode == XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR) @@ -432,29 +406,29 @@ void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice, { tc &= ~((uint32_t)CCU4_CC4_TC_STRM_Msk); } - + slice->TC = tc; } /* API to configure the Stop trigger function of a slice */ void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_t event, const XMC_CCU4_SLICE_END_MODE_t end_mode) { uint32_t cmc; uint32_t tc; - + XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); XMC_ASSERT("XMC_CCU4_SLICE_StopConfig:Invalid Start Mode", XMC_CCU4_CHECK_END_MODE(end_mode)); - + /* First, Bind the event with the stop function */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_ENDS_Msk); cmc |= ((uint32_t) event) << CCU4_CC4_CMC_ENDS_Pos; slice->CMC = cmc; - + /* Next, Configure the stop mode */ tc = slice->TC; tc &= ~((uint32_t) CCU4_CC4_TC_ENDM_Msk); @@ -467,10 +441,10 @@ void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice, void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_LoadConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); - + /* Bind the event with the load function */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_LDS_Msk); @@ -487,21 +461,21 @@ void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, { uint32_t cmc; uint32_t tc; - + XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); XMC_ASSERT("XMC_CCU4_SLICE_ModulationConfig:Invalid Modulation Mode", - ((mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) ||\ + ((mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) || \ (mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT))); - + tc = slice->TC; cmc = slice->CMC; - + /* First, Bind the event with the modulation function */ cmc &= ~((uint32_t) CCU4_CC4_CMC_MOS_Msk); cmc |= ((uint32_t) event) << CCU4_CC4_CMC_MOS_Pos; slice->CMC = cmc; - + /* Next, Modulation mode */ if (mod_mode == XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT) { @@ -521,7 +495,7 @@ void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, { tc &= ~((uint32_t) CCU4_CC4_TC_EMS_Msk); } - + slice->TC = tc; } @@ -529,7 +503,7 @@ void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice, void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_CountConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_CountConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); @@ -545,10 +519,10 @@ void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SL void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_GateConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_GateConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); - + /* Bind the event with the gate function */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_GATES_Msk); @@ -561,10 +535,10 @@ void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLI void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_Capture0Config:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_Capture0Config:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); - + /* Bind the event with the gate function */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_CAP0S_Msk); @@ -577,10 +551,10 @@ void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4 void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_Capture1Config:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_Capture1Config:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); - + /* Bind the event with the gate function */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_CAP1S_Msk); @@ -593,15 +567,15 @@ void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4 void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_DirectionConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_DirectionConfig:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); - + /* Bind the event with the direction function */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_UDS_Msk); cmc |= ((uint32_t) event) << CCU4_CC4_CMC_UDS_Pos; - + slice->CMC = cmc; } @@ -609,12 +583,12 @@ void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU void XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice) { uint32_t cmc; - + XMC_ASSERT("XMC_CCU4_SLICE_StatusBitOverrideConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - + /* Bind the event with the override function */ cmc = slice->CMC; - /* Map status bit trigger override to Event 1 & + /* Map status bit trigger override to Event 1 & status bit value override to Event 2 */ cmc &= ~((uint32_t) CCU4_CC4_CMC_OFS_Msk); cmc |= ((uint32_t) 1) << CCU4_CC4_CMC_OFS_Pos; @@ -629,17 +603,17 @@ void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, { uint32_t cmc; uint32_t tc; - + XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC) ||\ - (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW))); - + XMC_ASSERT("XMC_CCU4_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC) || \ + (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW))); + /* First, Map trap function to Event 2 */ cmc = slice->CMC; cmc &= ~((uint32_t) CCU4_CC4_CMC_TS_Msk); cmc |= ((uint32_t) 1) << CCU4_CC4_CMC_TS_Pos; slice->CMC = cmc; - + /* Next, Configure synchronization option */ tc = slice->TC; @@ -651,7 +625,7 @@ void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, { tc &= ~((uint32_t) CCU4_CC4_TC_TRPSE_Msk); } - + /* Configure exit mode */ if (exit_mode == XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW) { @@ -661,35 +635,35 @@ void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice, { tc &= ~((uint32_t) CCU4_CC4_TC_TRPSW_Msk); } - + slice->TC = tc; } /* API to configure a slice Status Bit Override event */ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, - const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config) + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config) { uint32_t ins; XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", - XMC_CCU4_SLICE_IsInputvalid(ev1_config->mapped_input)); + XMC_CCU4_SLICE_IsInputvalid(ev1_config->mapped_input)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", - ((ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + ((ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) || \ (ev1_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", XMC_CCU4_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", - XMC_CCU4_SLICE_IsInputvalid(ev2_config->mapped_input)); + XMC_CCU4_SLICE_IsInputvalid(ev2_config->mapped_input)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", - ((ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + ((ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) || \ (ev2_config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); - XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", XMC_CCU4_SLICE_CHECK_EVENT_FILTER(ev2_config->duration)); #if defined(CCU4V3) /* Defined for XMC1400 devices only */ ins = slice->INS2; @@ -697,19 +671,19 @@ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slic /* Configure the edge sensitivity for event 1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS2_EV1EM_Pos); ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS2_EV1EM_Pos; - + /* Configure the edge sensitivity for event 2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS2_EV2EM_Pos); ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS2_EV2EM_Pos; - + /* Configure the level sensitivity for event 1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS2_EV1LM_Pos); ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS2_EV1LM_Pos; - + /* Configure the level sensitivity for event 2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS2_EV2LM_Pos); ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS2_EV2LM_Pos; - + /* Configure the debounce filter for event 1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS2_LPF1M_Pos); ins |= ((uint32_t) ev1_config->duration) << CCU4_CC4_INS2_LPF1M_Pos; @@ -717,11 +691,11 @@ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slic /* Configure the debounce filter for event 2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS2_LPF2M_Pos); ins |= ((uint32_t) ev2_config->duration) << CCU4_CC4_INS2_LPF2M_Pos; - + slice->INS2 = ins; - + ins = slice->INS1; - + /* Next, the input for Event1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS1_EV1IS_Pos); ins |= ((uint32_t) ev1_config->mapped_input) << CCU4_CC4_INS1_EV1IS_Pos; @@ -729,7 +703,7 @@ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slic /* Finally, the input for Event2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS1_EV2IS_Pos); ins |= ((uint32_t) ev2_config->mapped_input) << CCU4_CC4_INS1_EV2IS_Pos; - + slice->INS1 = ins; #else ins = slice->INS; @@ -737,19 +711,19 @@ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slic /* Configure the edge sensitivity for event 1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS_EV1EM_Pos); ins |= ((uint32_t) ev1_config->edge) << CCU4_CC4_INS_EV1EM_Pos; - + /* Configure the edge sensitivity for event 2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << CCU4_CC4_INS_EV2EM_Pos); ins |= ((uint32_t) ev2_config->edge) << CCU4_CC4_INS_EV2EM_Pos; - + /* Configure the level sensitivity for event 1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS_EV1LM_Pos); ins |= ((uint32_t) ev1_config->level) << CCU4_CC4_INS_EV1LM_Pos; - + /* Configure the level sensitivity for event 2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << CCU4_CC4_INS_EV2LM_Pos); ins |= ((uint32_t) ev2_config->level) << CCU4_CC4_INS_EV2LM_Pos; - + /* Configure the debounce filter for event 1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS_LPF1M_Pos); ins |= ((uint32_t) ev1_config->duration) << CCU4_CC4_INS_LPF1M_Pos; @@ -757,7 +731,7 @@ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slic /* Configure the debounce filter for event 2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU4_CC4_INS_LPF2M_Pos); ins |= ((uint32_t) ev2_config->duration) << CCU4_CC4_INS_LPF2M_Pos; - + /* Next, the input for Event1 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS_EV1IS_Pos); ins |= ((uint32_t) ev1_config->mapped_input) << CCU4_CC4_INS_EV1IS_Pos; @@ -765,7 +739,7 @@ void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slic /* Finally, the input for Event2 */ ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU4_CC4_INS_EV2IS_Pos); ins |= ((uint32_t) ev2_config->mapped_input) << CCU4_CC4_INS_EV2IS_Pos; - + slice->INS = ins; #endif } @@ -785,13 +759,13 @@ void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Edge Sensitivity", XMC_CCU4_SLICE_CHECK_EDGE_SENSITIVITY(config->edge)); XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Level Sensitivity", - ((config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + ((config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) || \ (config->level == XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); - XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Debounce Period", + XMC_ASSERT("XMC_CCU4_SLICE_ConfigureEvent:Invalid Debounce Period", XMC_CCU4_SLICE_CHECK_EVENT_FILTER(config->duration)); /* Calculate offset with reference to event */ offset = ((uint8_t) event) - 1U; - + #if defined(CCU4V3) /* Defined for XMC1400 devices only */ ins = slice->INS2; @@ -823,17 +797,17 @@ void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, #else ins = slice->INS; - + /* First, configure the edge sensitivity */ pos = ((uint8_t) CCU4_CC4_INS_EV0EM_Pos) + (uint8_t)(offset << 1U); ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_EDGE_CONFIG_MASK) << pos); ins |= ((uint32_t) config->edge) << pos; - + /* Next, the level */ pos = ((uint8_t) CCU4_CC4_INS_EV0LM_Pos) + offset; ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_LEVEL_CONFIG_MASK) << pos); ins |= ((uint32_t) config->level) << pos; - + /* Next, the debounce filter */ pos = ((uint8_t) CCU4_CC4_INS_LPF0M_Pos) + (uint8_t)(offset << 1U); ins &= ~(((uint32_t) XMC_CCU4_SLICE_EVENT_FILTER_CONFIG_MASK) << pos); @@ -850,7 +824,7 @@ void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice, /* API to bind an input to a slice trigger event */ void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_EVENT_t event, + const XMC_CCU4_SLICE_EVENT_t event, const XMC_CCU4_SLICE_INPUT_t input) { uint32_t ins; @@ -860,7 +834,7 @@ void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice, XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Event ID", XMC_CCU4_SLICE_CHECK_EVENT_ID(event)); XMC_ASSERT("XMC_CCU4_SLICE_SetInput:Invalid Input", XMC_CCU4_SLICE_IsInputvalid(input)); - + /* Calculate offset with reference to event */ offset = ((uint8_t) event) - 1U; @@ -888,9 +862,9 @@ void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_ { XMC_ASSERT("XMC_CCU4_SLICE_SetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", - ((mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT) ||\ - (mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE))); - + ((mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT) || \ + (mode == XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE))); + if (XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) { slice->TC &= ~((uint32_t) CCU4_CC4_TC_TSSM_Msk); @@ -905,9 +879,9 @@ void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_ void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode) { XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", ((mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA) ||\ - (mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA))); - + XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", ((mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA) || \ + (mode == XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA))); + if (XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA == mode) { slice->TC &= ~((uint32_t) CCU4_CC4_TC_TCM_Msk); @@ -923,23 +897,23 @@ uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const sl { XMC_ASSERT("XMC_CCU4_SLICE_GetCaptureRegisterValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_GetCaptureRegisterValue:Invalid register number", (reg_num < 4U)); - return(slice->CV[reg_num]); + return (slice->CV[reg_num]); } /* @brief Retrieves the latest captured timer value */ XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_CAP_REG_SET_t set, - uint32_t *val_ptr) + const XMC_CCU4_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr) { XMC_CCU4_STATUS_t retval; uint8_t i; uint8_t start; uint8_t end; - + XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Register Set", ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) ||\ - (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); - + XMC_ASSERT("XMC_CCU4_SLICE_GetLastCapturedTimerValue:Invalid Register Set", ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) || \ + (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); + retval = XMC_CCU4_STATUS_ERROR; /* First check if extended capture mode is enabled */ @@ -964,7 +938,7 @@ XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_ } } - for(i=start; i < end; i++) + for (i = start; i < end; i++) { if ( (slice->CV[i]) & CCU4_CC4_CV_FFL_Msk ) { @@ -978,12 +952,12 @@ XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_ } /* Retrieves timer capture value from a FIFO made of capture registers */ -#if defined(CCU4V1) /* Defined for XMC4500, XMC400, XMC4200, XMC4100 devices only */ +#if defined(CCU4V1) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */ int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number) { int32_t cap; uint32_t extracted_slice; - + XMC_ASSERT("XMC_CCU4_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module)); /* First read the global fifo register */ @@ -992,7 +966,7 @@ int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, extracted_slice = (((uint32_t) cap) & ((uint32_t) CCU4_ECRD_SPTR_Msk)) >> CCU4_ECRD_SPTR_Pos; /* Return captured result only if it were applicable to this slice */ - if(extracted_slice != ((uint32_t)slice_number)) + if (extracted_slice != ((uint32_t)slice_number)) { cap = -1; } @@ -1001,16 +975,16 @@ int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, } #else uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice, - const XMC_CCU4_SLICE_CAP_REG_SET_t set) + const XMC_CCU4_SLICE_CAP_REG_SET_t set) { uint32_t cap; XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Register Set", - ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) ||\ - (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); + XMC_ASSERT("XMC_CCU4_SLICE_GetCapturedValueFromFifo:Invalid Register Set", + ((set == XMC_CCU4_SLICE_CAP_REG_SET_LOW) || \ + (set == XMC_CCU4_SLICE_CAP_REG_SET_HIGH))); - if(XMC_CCU4_SLICE_CAP_REG_SET_LOW == set) + if (XMC_CCU4_SLICE_CAP_REG_SET_LOW == set) { cap = slice->ECRD0; } @@ -1046,7 +1020,7 @@ void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice, } slice->TC = tc; - + XMC_CCU4_SLICE_SetDitherCompareValue((XMC_CCU4_SLICE_t *)slice, (uint8_t)spread); } @@ -1054,15 +1028,15 @@ void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice, void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_PRESCALER_t div_val) { uint32_t fpc; - + XMC_ASSERT("XMC_CCU4_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); fpc = slice->FPC; fpc &= ~((uint32_t) CCU4_CC4_FPC_PVAL_Msk); fpc |= ((uint32_t) div_val) << CCU4_CC4_FPC_PVAL_Pos; slice->FPC = fpc; - /* - * In any case, update the initial value of the divider which is to be loaded once the prescaler increments to the + /* + * In any case, update the initial value of the divider which is to be loaded once the prescaler increments to the * compare value. */ slice->PSC = (uint32_t) div_val; @@ -1074,16 +1048,14 @@ void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_SR_ID_t sr) { uint32_t srs; - uint32_t pos; + int32_t pos; uint32_t mask; XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid SR ID ", XMC_CCU4_SLICE_CHECK_SR_ID(sr)); XMC_ASSERT("XMC_CCU4_SLICE_SetInterruptNode:Invalid event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event)); - - srs = slice->SRS; - - switch(event) + + switch (event) { case XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH: case XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH: @@ -1107,31 +1079,41 @@ void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice, pos = CCU4_CC4_SRS_E1SR_Pos; break; - default: + case XMC_CCU4_SLICE_IRQ_ID_EVENT2: + case XMC_CCU4_SLICE_IRQ_ID_TRAP: mask = ((uint32_t) CCU4_CC4_SRS_E2SR_Msk); pos = CCU4_CC4_SRS_E2SR_Pos; break; + + default: + mask = 0; + pos = 0; + break; + } + + if (mask != 0) + { + srs = slice->SRS; + srs &= ~mask; + srs |= (uint32_t)sr << pos; + slice->SRS = srs; } - - srs &= ~mask; - srs |= (uint32_t)sr << pos; - slice->SRS = srs; } /* Asserts passive level for the slice output */ void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level) { - uint32_t psl; - + uint32_t psl; + XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Passive level", ((level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) ||\ - (level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); - + XMC_ASSERT("XMC_CCU4_SLICE_SetPassiveLevel:Invalid Passive level", ((level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) || \ + (level == XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); + psl = slice->PSL; psl &= ~((uint32_t) CCU4_CC4_PSL_PSL_Msk); psl |= (uint32_t) level; - + /* Program CC4 slice output passive level */ slice->PSL = psl; } diff --git a/cores/xmc_lib/XMCLib/src/xmc_ccu8.c b/cores/xmc_lib/XMCLib/src/xmc_ccu8.c index ecd69a5a..f786bbce 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_ccu8.c +++ b/cores/xmc_lib/XMCLib/src/xmc_ccu8.c @@ -1,68 +1,41 @@ /** * @file xmc_ccu8.c - * @date 2017-04-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API
    - * - Added XMC_CCU8_SLICE_LoadSelector() API, to select which compare register value has to be loaded - * during external load event. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-07-24: - * - XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device.
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-08-17: - * - XMC_CCU8_SLICE_CHC_CONFIG_MASK is not applicable to XMC14 devices.
    - * - Start of prescaler XMC_CCU8_StartPrescaler() is invoked in XMC_CCU8_Init() API.
    - * - In XMC_CCU8_SLICE_CompareInit(), CHC register is updated according to the device.
    - * - Bug fix XMC_CCU8_SLICE_ConfigureEvent() during the level setting for XMC14 devices.
    - * - XMC_CCU8_EnableShadowTransfer() definition is removed, since the API is made as inline.
    - * - * 2015-10-07: - * - XMC_CCU8_SLICE_GetEvent() is made as inline. - * - DOC updates for the newly added APIs. - * - * 2017-02-25: - * - XMC_CCU8_lAssertReset(), XMC_CCU8_lDeassertReset(), XMC_CCU8_lGateClock() and XMC_CCU8_lUngateClock() fix compilation warnings. - * - * 2017-04-27: - * - XMC_CCU8_SLICE_SetPrescaler() changed div_val parameter to type XMC_CCU8_SLICE_PRESCALER_t + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -313,11 +286,11 @@ void XMC_CCU8_Init(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_SLICE_MCMS_AC XMC_CCU8_EnableModule(module); /* Start the prescaler */ XMC_CCU8_StartPrescaler(module); - + gctrl = module->GCTRL; gctrl &= ~((uint32_t) CCU8_GCTRL_MSDE_Msk); gctrl |= (uint32_t)mcs_action << CCU8_GCTRL_MSDE_Pos; - + module->GCTRL = gctrl; } @@ -366,11 +339,11 @@ void XMC_CCU8_SLICE_CompareInit(XMC_CCU8_SLICE_t *const slice, } /* API to configure CC8 Slice in Capture mode */ -void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, +void XMC_CCU8_SLICE_CaptureInit(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_SLICE_CAPTURE_CONFIG_t *const capture_init) { XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Capture Init Pointer is NULL", + XMC_ASSERT("XMC_CCU8_SLICE_CaptureInit:Capture Init Pointer is NULL", (XMC_CCU8_SLICE_CAPTURE_CONFIG_t *) NULL != capture_init); /* Stops the timer */ XMC_CCU8_SLICE_StopTimer(slice); @@ -406,7 +379,7 @@ void XMC_CCU8_SetMultiChannelShadowTransferMode(XMC_CCU8_MODULE_t *const module, uint32_t gctrl; XMC_ASSERT("XMC_CCU8_SetMultiChannelShadowTransferMode:Invalid module Pointer", XMC_CCU8_IsValidModule(module)); - + gctrl = module->GCTRL; gctrl &= ~((uint32_t)slice_mode_msk >> 16U); gctrl |= ((uint32_t)slice_mode_msk & 0xFFFFU); @@ -424,8 +397,8 @@ void XMC_CCU8_SLICE_StartConfig(XMC_CCU8_SLICE_t *const slice, XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); - XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Start Mode", - ((start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START) ||\ + XMC_ASSERT("XMC_CCU8_SLICE_StartConfig:Invalid Start Mode", + ((start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START) || \ (start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR))); cmc = slice->CMC; @@ -436,7 +409,7 @@ void XMC_CCU8_SLICE_StartConfig(XMC_CCU8_SLICE_t *const slice, tc = slice->TC; - if(start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR) + if (start_mode == XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR) { tc |= (uint32_t) CCU8_CC8_TC_STRM_Msk; } @@ -521,10 +494,10 @@ void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Event ID", XMC_CCU8_SLICE_CHECK_EVENT_ID(event)); - XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid channel for modulation", + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid channel for modulation", XMC_CCU8_SLICE_CHECK_MODULATION_CHANNEL(channel)); - XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Modulation Mode", - ((mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT) ||\ + XMC_ASSERT("XMC_CCU8_SLICE_ModulationConfig:Invalid Modulation Mode", + ((mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT) || \ (mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT))); cmc = slice->CMC; @@ -538,7 +511,7 @@ void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, tc = slice->TC; /* Next, Modulation mode */ - if(mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT) + if (mod_mode == XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT) { tc |= (uint32_t) CCU8_CC8_TC_EMT_Msk; } @@ -548,7 +521,7 @@ void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, } /* Synchronization of modulation effect with PWM cycle */ - if(synch_with_pwm == true) + if (synch_with_pwm == true) { tc |= (uint32_t) CCU8_CC8_TC_EMS_Msk; } @@ -556,7 +529,7 @@ void XMC_CCU8_SLICE_ModulationConfig(XMC_CCU8_SLICE_t *const slice, { tc &= ~((uint32_t) CCU8_CC8_TC_EMS_Msk); } - + /* Configure on which channel external modulation to be applied */ tc &= ~((uint32_t) CCU8_CC8_TC_EME_Msk); tc |= (uint32_t)channel << CCU8_CC8_TC_EME_Pos; @@ -676,8 +649,8 @@ void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, uint32_t tc; XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC) ||\ - (exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW))); + XMC_ASSERT("XMC_CCU8_SLICE_TrapConfig:Invalid Exit Mode", ((exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC) || \ + (exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW))); cmc = slice->CMC; @@ -690,7 +663,7 @@ void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, tc = slice->TC; /* Configure synchronization option */ - if(synch_with_pwm == true) + if (synch_with_pwm == true) { tc |= (uint32_t) CCU8_CC8_TC_TRPSE_Msk; } @@ -700,7 +673,7 @@ void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, } /* Configure exit mode */ - if(exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW) + if (exit_mode == XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW) { tc |= (uint32_t) CCU8_CC8_TC_TRPSW_Msk; } @@ -714,27 +687,27 @@ void XMC_CCU8_SLICE_TrapConfig(XMC_CCU8_SLICE_t *const slice, /* API to configure a slice Status Bit Override event */ void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, - const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config) + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev1_config, + const XMC_CCU8_SLICE_EVENT_CONFIG_t *const ev2_config) { uint32_t ins; XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", - XMC_CCU8_SLICE_IsInputvalid(ev1_config->mapped_input)); - XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", + XMC_CCU8_SLICE_IsInputvalid(ev1_config->mapped_input)); + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev1_config->edge)); - XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", - ((ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", + ((ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) || \ (ev1_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", - XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); + XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev1_config->duration)); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Input", - XMC_CCU8_SLICE_IsInputvalid(ev2_config->mapped_input)); + XMC_CCU8_SLICE_IsInputvalid(ev2_config->mapped_input)); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Edge Sensitivity", - XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); + XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(ev2_config->edge)); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Level Sensitivity", - ((ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + ((ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) || \ (ev2_config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent:Invalid Debounce Period", XMC_CCU8_SLICE_CHECK_EVENT_FILTER(ev2_config->duration)); @@ -765,8 +738,8 @@ void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slic /* Configure the debounce filter for event 2 */ ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_FILTER_CONFIG_MASK) << CCU8_CC8_INS2_LPF2M_Pos); ins |= ((uint32_t) ev2_config->duration) << CCU8_CC8_INS2_LPF2M_Pos; - - slice->INS2 = ins; + + slice->INS2 = ins; ins = slice->INS1; /* Next, the input for Event1 */ @@ -777,7 +750,7 @@ void XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU8_SLICE_t *const slic ins &= ~(((uint32_t) XMC_CCU8_SLICE_EVENT_INPUT_CONFIG_MASK) << CCU8_CC8_INS1_EV2IS_Pos); ins |= ((uint32_t) ev2_config->mapped_input) << CCU8_CC8_INS1_EV2IS_Pos; - slice->INS1 = ins; + slice->INS1 = ins; #else ins = slice->INS; @@ -831,8 +804,8 @@ void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Input", XMC_CCU8_SLICE_IsInputvalid(config->mapped_input)); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Edge Sensitivity", XMC_CCU8_SLICE_CHECK_EDGE_SENSITIVITY(config->edge)); - XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Level Sensitivity", - ((config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) ||\ + XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Level Sensitivity", + ((config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH) || \ (config->level == XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW))); XMC_ASSERT("XMC_CCU8_SLICE_ConfigureEvent:Invalid Debounce Period", XMC_CCU8_SLICE_CHECK_EVENT_FILTER(config->duration)); @@ -898,7 +871,7 @@ void XMC_CCU8_SLICE_ConfigureEvent(XMC_CCU8_SLICE_t *const slice, /* API to bind an input to a slice trigger event */ void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_EVENT_t event, + const XMC_CCU8_SLICE_EVENT_t event, const XMC_CCU8_SLICE_INPUT_t input) { uint32_t ins; @@ -932,18 +905,18 @@ void XMC_CCU8_SLICE_SetInput(XMC_CCU8_SLICE_t *const slice, /* API to program timer repeat mode - Single shot vs repeat */ void XMC_CCU8_SLICE_SetTimerRepeatMode(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t mode) + const XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t mode) { uint32_t tc; XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", - ((mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT) ||\ - (mode == (mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT)))); + XMC_ASSERT("XMC_CCU8_SLICE_SetTimerRepeatMode:Invalid Timer Repeat Mode", + ((mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT) || \ + (mode == XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE))); tc = slice->TC; - if(XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) + if (XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT == mode) { tc &= ~((uint32_t) CCU8_CC8_TC_TSSM_Msk); } @@ -962,12 +935,12 @@ void XMC_CCU8_SLICE_SetTimerCountingMode(XMC_CCU8_SLICE_t *const slice, const XM XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCountingMode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCountingMode:Invalid Timer Count Mode", - ((mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA) ||\ + ((mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA) || \ (mode == XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA))); tc = slice->TC; - if(XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA == mode) + if (XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA == mode) { tc &= ~((uint32_t) CCU8_CC8_TC_TCM_Msk); } @@ -991,13 +964,13 @@ uint32_t XMC_CCU8_SLICE_GetCaptureRegisterValue(const XMC_CCU8_SLICE_t *const sl { XMC_ASSERT("XMC_CCU8_SLICE_GetCaptureRegisterValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_GetCaptureRegisterValue:Invalid register number", (reg_num < 4U)); - return(slice->CV[reg_num]); + return (slice->CV[reg_num]); } /* @brief Retrieves the latest captured timer value */ XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_CAP_REG_SET_t set, - uint32_t *val_ptr) + const XMC_CCU8_SLICE_CAP_REG_SET_t set, + uint32_t *val_ptr) { XMC_CCU8_STATUS_t retval; @@ -1007,13 +980,13 @@ XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_ XMC_ASSERT("XMC_CCU8_SLICE_GetLastCapturedTimerValue:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_GetLastCapturedTimerValue:Invalid Register Set", - ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) ||\ + ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) || \ (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH))); retval = XMC_CCU8_STATUS_ERROR; /* First check if extended capture mode is enabled */ - if((slice->TC) & CCU8_CC8_TC_ECM_Msk) + if ((slice->TC) & CCU8_CC8_TC_ECM_Msk) { /* Extended capture mode has been enabled. So start with the lowest capture register and work your way up */ start = 0U; @@ -1022,7 +995,7 @@ XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_ else { /* Extended capture mode is not enabled */ - if(set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH) + if (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH) { start = ((uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE) >> 1U; end = (uint8_t) XMC_CCU8_NUM_SLICES_PER_MODULE; @@ -1034,9 +1007,9 @@ XMC_CCU8_STATUS_t XMC_CCU8_SLICE_GetLastCapturedTimerValue(const XMC_CCU8_SLICE_ } } - for(i=start; iCV[i]) & CCU8_CC8_CV_FFL_Msk ) + if ( (slice->CV[i]) & CCU8_CC8_CV_FFL_Msk ) { *val_ptr = slice->CV[i]; retval = XMC_CCU8_STATUS_OK; @@ -1052,16 +1025,16 @@ int32_t XMC_CCU8_GetCapturedValueFromFifo(const XMC_CCU8_MODULE_t *const module, { int32_t cap; uint32_t extracted_slice; - + XMC_ASSERT("XMC_CCU8_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU8_IsValidModule(module)); /* First read the global fifo register */ cap = (int32_t) module->ECRD; - + extracted_slice = (((uint32_t) cap) & ((uint32_t) CCU8_ECRD_SPTR_Msk)) >> CCU8_ECRD_SPTR_Pos; /* Return captured result only if it were applicable to this slice */ - if(extracted_slice != ((uint32_t)slice_number)) + if (extracted_slice != ((uint32_t)slice_number)) { cap = -1; } @@ -1075,11 +1048,11 @@ uint32_t XMC_CCU8_SLICE_GetCapturedValueFromFifo(const XMC_CCU8_SLICE_t *const s uint32_t cap; XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); - XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Register Set", - ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) ||\ + XMC_ASSERT("XMC_CCU8_SLICE_GetCapturedValueFromFifo:Invalid Register Set", + ((set == XMC_CCU8_SLICE_CAP_REG_SET_LOW) || \ (set == XMC_CCU8_SLICE_CAP_REG_SET_HIGH))); - if(XMC_CCU8_SLICE_CAP_REG_SET_LOW == set) + if (XMC_CCU8_SLICE_CAP_REG_SET_LOW == set) { cap = slice->ECRD0; } @@ -1105,11 +1078,11 @@ void XMC_CCU8_SLICE_EnableDithering(XMC_CCU8_SLICE_t *const slice, tc = slice->TC; tc &= ~((uint32_t) CCU8_CC8_TC_DITHE_Msk); - if(true == period_dither) + if (true == period_dither) { tc |= (((uint32_t) XMC_CCU8_SLICE_DITHER_PERIOD_MASK) << CCU8_CC8_TC_DITHE_Pos); } - if(true == duty_dither) + if (true == duty_dither) { tc |= (((uint32_t) XMC_CCU8_SLICE_DITHER_DUTYCYCLE_MASK) << CCU8_CC8_TC_DITHE_Pos); } @@ -1141,8 +1114,8 @@ void XMC_CCU8_SLICE_SetPrescaler(XMC_CCU8_SLICE_t *const slice, const XMC_CCU8_S /* Programs timer compare match value for channel 1 or 2 */ void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, - const uint16_t compare_val) + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel, + const uint16_t compare_val) { XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_SetTimerCompareMatch:Invalid channel", XMC_CCU8_SLICE_CHECK_COMP_CHANNEL(channel)); @@ -1159,7 +1132,7 @@ void XMC_CCU8_SLICE_SetTimerCompareMatch(XMC_CCU8_SLICE_t *const slice, /* Returns the timer compare match value for channel 1 or 2 */ uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice, - const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel) + const XMC_CCU8_SLICE_COMPARE_CHANNEL_t channel) { uint16_t compare_value; @@ -1175,7 +1148,7 @@ uint16_t XMC_CCU8_SLICE_GetTimerCompareMatch(const XMC_CCU8_SLICE_t *const slice compare_value = (uint16_t) slice->CR2; } - return(compare_value); + return (compare_value); } /* Binds a capcom event to an NVIC node */ @@ -1185,15 +1158,13 @@ void XMC_CCU8_SLICE_SetInterruptNode(XMC_CCU8_SLICE_t *const slice, { uint32_t srs; uint32_t mask; - uint32_t pos; + int32_t pos; XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid SR ID ", XMC_CCU8_SLICE_CHECK_SR_ID(sr)); XMC_ASSERT("XMC_CCU8_SLICE_SetInterruptNode:Invalid event", XMC_CCU8_SLICE_CHECK_INTERRUPT(event)); - srs = slice->SRS; - - switch(event) + switch (event) { case XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH: case XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH: @@ -1223,16 +1194,25 @@ void XMC_CCU8_SLICE_SetInterruptNode(XMC_CCU8_SLICE_t *const slice, pos = CCU8_CC8_SRS_E1SR_Pos; break; - default: + case XMC_CCU8_SLICE_IRQ_ID_EVENT2: + case XMC_CCU8_SLICE_IRQ_ID_TRAP: mask = ((uint32_t) CCU8_CC8_SRS_E2SR_Msk); pos = CCU8_CC8_SRS_E2SR_Pos; break; + + default: + mask = 0; + pos = 0; + break; + } + + if (mask != 0) + { + srs = slice->SRS; + srs &= ~mask; + srs |= (uint32_t)sr << pos; + slice->SRS = srs; } - - srs &= ~mask; - srs |= (uint32_t)sr << pos; - - slice->SRS = srs; } /* Asserts passive level for the slice output */ @@ -1245,7 +1225,7 @@ void XMC_CCU8_SLICE_SetPassiveLevel(XMC_CCU8_SLICE_t *const slice, XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Slice Pointer", XMC_CCU8_IsValidSlice(slice)); XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Slice Output", XMC_CCU8_SLICE_CHECK_OUTPUT(out)); XMC_ASSERT("XMC_CCU8_SLICE_SetPassiveLevel:Invalid Passive Level", - ((level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) ||\ + ((level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW) || \ (level == XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH))); psl = slice->PSL; @@ -1296,7 +1276,7 @@ void XMC_CCU8_SLICE_SetDeadTimeValue(XMC_CCU8_SLICE_t *const slice, } else { - slice->DC2R = (((uint32_t) fall_value) << CCU8_CC8_DC2R_DT2F_Pos) | ((uint32_t) rise_value); + slice->DC2R = (((uint32_t) fall_value) << CCU8_CC8_DC2R_DT2F_Pos) | ((uint32_t) rise_value); } } diff --git a/cores/xmc_lib/XMCLib/src/xmc_common.c b/cores/xmc_lib/XMCLib/src/xmc_common.c index d3727e8e..04a6d2e8 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_common.c +++ b/cores/xmc_lib/XMCLib/src/xmc_common.c @@ -1,62 +1,48 @@ /** * @file xmc_common.c - * @date 2017-02-25 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2017-02-25: - * - Remove the need to define XMC_USER_ASSERT_FUNCTION - * - XMC_AssertHandler fixed compilation warnings + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ #include "xmc_common.h" -/******************************************************************************* - * DATA STRUCTURES - *******************************************************************************/ -struct list -{ - struct list *next; -}; - /******************************************************************************* * API IMPLEMENTATION *******************************************************************************/ @@ -67,153 +53,32 @@ __WEAK void XMC_AssertHandler(const char *const msg, const char *const file, uin XMC_UNUSED_ARG(file); XMC_UNUSED_ARG(line); - while(1) + while (1) { /* Endless loop */ } } #endif -void XMC_LIST_Init(XMC_LIST_t *list) -{ - *list = NULL; -} +#define XMC_DELAY_MAX_CYCLES (0xFFFFFFFFUL - 2UL) /* To avoid an overflow during rounding inside the XMC_DelayCycles */ -void *XMC_LIST_GetHead(XMC_LIST_t *list) +void XMC_Delay(uint32_t milliseconds) { - return *list; -} + uint32_t clocksMs = SystemCoreClock / 1000UL; /* SystemCoreClock in kiloHertzs */ + uint32_t maxDelay = XMC_DELAY_MAX_CYCLES / clocksMs; /* maximum XMC_DelayCycles delay in milliseconds */ -void *XMC_LIST_GetTail(XMC_LIST_t *list) -{ - struct list *tail; - - if (*list == NULL) - { - tail = NULL; - } - else - { - for (tail = (struct list *)*list; tail->next != NULL; tail = tail->next) - { - /* Loop through the list */ - } - } - - return tail; -} - -void XMC_LIST_Add(XMC_LIST_t *list, void *item) -{ - struct list *tail; - - ((struct list *)item)->next = NULL; - tail = (struct list *)XMC_LIST_GetTail(list); - - if (tail == NULL) - { - *list = item; - } - else - { - tail->next = (struct list *)item; - } -} - -void XMC_LIST_Remove(XMC_LIST_t *list, void *item) -{ - struct list *right, *left; - - if (*list != NULL) - { - left = NULL; - for(right = (struct list *)*list; right != NULL; right = right->next) + /* This loop prevents an overflow in value passed to XMC_DelayCycles() API. */ + while(milliseconds > maxDelay) { - if(right == item) - { - if(left == NULL) - { - /* First on list */ - *list = right->next; - } - else - { - /* Not first on list */ - left->next = right->next; - } - right->next = NULL; - break; - } - left = right; + XMC_DelayCycles(XMC_DELAY_MAX_CYCLES); + milliseconds -= maxDelay; } - } -} -void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item) -{ - if (prev_item == NULL) - { - ((struct list *)new_item)->next = (struct list *)*list; - *list = new_item; - } - else - { - ((struct list *)new_item)->next = ((struct list *)prev_item)->next; - ((struct list *)prev_item)->next = (struct list *)new_item; - } + XMC_DelayCycles(milliseconds * clocksMs); } -void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray) +void XMC_DelayUs(uint16_t microseconds) { - XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL); - - /* Initialize head, next points to tail, previous to NULL and the priority is MININT */ - prioarray->items[prioarray->size].next = prioarray->size + 1; - prioarray->items[prioarray->size].previous = -1; - prioarray->items[prioarray->size].priority = INT32_MAX; - - /* Initialize tail, next points to NULL, previous is the head and the priority is MAXINT */ - prioarray->items[prioarray->size + 1].next = -1; - prioarray->items[prioarray->size + 1].previous = prioarray->size; - prioarray->items[prioarray->size + 1].priority = INT32_MIN; - + XMC_DelayCycles(microseconds * XMC_DIV_ROUNDUP(SystemCoreClock, 1000000UL)); /* microseconds * SystemCoreClock in MHz units */ } -void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority) -{ - int32_t next; - int32_t previous; - - XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size)); - - next = XMC_PRIOARRAY_GetHead(prioarray); - while (XMC_PRIOARRAY_GetItemPriority(prioarray, next) > priority) - { - next = XMC_PRIOARRAY_GetItemNext(prioarray, next); - } - - previous = prioarray->items[next].previous; - - prioarray->items[item].next = next; - prioarray->items[item].previous = previous; - prioarray->items[item].priority = priority; - - prioarray->items[previous].next = item; - prioarray->items[next].previous = item; -} - -void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item) -{ - int32_t next; - int32_t previous; - - XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size)); - - next = prioarray->items[item].next; - previous = prioarray->items[item].previous; - - prioarray->items[previous].next = next; - prioarray->items[next].previous = previous; -} - - diff --git a/cores/xmc_lib/XMCLib/src/xmc_dac.c b/cores/xmc_lib/XMCLib/src/xmc_dac.c index 238c08e6..9876c613 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_dac.c +++ b/cores/xmc_lib/XMCLib/src/xmc_dac.c @@ -1,54 +1,43 @@ /** * @file xmc_dac.c - * @date 2015-06-19 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-18: - * - Initial version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-19: - * - Removed GetDriverVersion API - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -56,8 +45,8 @@ * HEADER FILES *******************************************************************************/ -#include -#include +#include "xmc_dac.h" +#include "xmc_scu.h" /* DAC peripheral is not available on XMC1X devices. */ #if defined(DAC) @@ -78,7 +67,7 @@ void XMC_DAC_Enable(XMC_DAC_t *const dac) { XMC_UNUSED_ARG(dac); - + #if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC); #endif @@ -104,7 +93,7 @@ bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac) XMC_UNUSED_ARG(dac); status = XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DAC); - if(status == true) + if (status == true) { status = false; } @@ -130,8 +119,8 @@ void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_ /* API to set the waveform frequency except in Ramp and Pattern generation mode. */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, - const uint8_t channel, - const uint32_t frequency) + const uint8_t channel, + const uint32_t frequency) { uint32_t divider; XMC_DAC_CH_STATUS_t status; @@ -148,7 +137,8 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, { status = XMC_DAC_CH_STATUS_ERROR_FREQ2LOW; } - else { + else + { dac->DACCFG[channel].low = (dac->DACCFG[channel].low & (uint32_t)(~DAC_DAC0CFG0_FREQ_Msk)) | (divider << DAC_DAC0CFG0_FREQ_Pos); status = XMC_DAC_CH_STATUS_OK; @@ -159,8 +149,8 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac, /* API to set the waveform frequency in Ramp Mode. */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac, - const uint8_t channel, - const uint32_t frequency) + const uint8_t channel, + const uint32_t frequency) { uint32_t stop; uint32_t start; @@ -185,9 +175,9 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const /* API to start the operation in Data Mode. */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, - const uint8_t channel, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency) + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) { XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; @@ -213,11 +203,11 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac, /* API to start the operation in Ramp Mode. */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, - const uint8_t channel, - const uint16_t start, - const uint16_t stop, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency) + const uint8_t channel, + const uint16_t start, + const uint16_t stop, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) { XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; @@ -246,11 +236,11 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac, /* API to start the operation in Pattern Mode. */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, - const uint8_t channel, - const uint8_t *const pattern, - const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency) + const uint8_t channel, + const uint8_t *const pattern, + const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) { XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; @@ -285,9 +275,9 @@ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac, /* API to start the operation in Noise Mode. */ XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac, - const uint8_t channel, - const XMC_DAC_CH_TRIGGER_t trigger, - const uint32_t frequency) + const uint8_t channel, + const XMC_DAC_CH_TRIGGER_t trigger, + const uint32_t frequency) { XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK; @@ -322,14 +312,14 @@ void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, uint8_t channel, const uint8_t XMC_ASSERT("XMC_DAC_CH_SetPattern: dac module not enabled\n", XMC_DAC_IsEnabled(dac)); temp = data[0U]; - for(index = 1U; index < 6U; ++index) + for (index = 1U; index < 6U; ++index) { temp |= (uint32_t)data[index] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE); } dac->DACPAT[channel].low = temp; temp = data[6U]; - for(index = 1U; index < 6U; ++index) + for (index = 1U; index < 6U; ++index) { temp |= (uint32_t)data[index + 6U] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_dma.c b/cores/xmc_lib/XMCLib/src/xmc_dma.c index f16dd4c8..2d9a3a5c 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_dma.c +++ b/cores/xmc_lib/XMCLib/src/xmc_dma.c @@ -1,67 +1,42 @@ /** * @file xmc_dma.c - * @date 2016-04-08 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-05-20: - * - Add the declarations for the following APIs:
    - * XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine,
    - * XMC_DMA_CH_ClearSourcePeripheralRequest,
    - * XMC_DMA_CH_ClearDestinationPeripheralRequest
    - * - Remove PRIOARRAY
    - * - Documentation updates
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-06-20: - * - Removed GetDriverVersion API
    - * - Updated XMC_DMA_CH_Init() to support scatter/gather functionality (only - * on advanced DMA channels)
    - * - Updated XMC_DMA_CH_Disable()
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-03-09: - * - Optimize write only registers - * - * 2016-04-08: - * - Update XMC_DMA_CH_EnableEvent and XMC_DMA_CH_DisableEvent. - * Write optimization of MASKCHEV - * - Fix XMC_DMA_IRQHandler, clear channel event status before processing the event handler. - * It corrects event losses if the DMA triggered in the event handler finished before returning from handler. + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -95,13 +70,13 @@ *******************************************************************************/ #if defined (GPDMA0) -XMC_DMA_CH_EVENT_HANDLER_t dma0_event_handlers[XMC_DMA0_NUM_CHANNELS]; +static XMC_DMA_CH_EVENT_HANDLER_t dma0_event_handlers[XMC_DMA0_NUM_CHANNELS]; #endif #if defined (GPDMA1) -XMC_DMA_CH_EVENT_HANDLER_t dma1_event_handlers[XMC_DMA1_NUM_CHANNELS]; +static XMC_DMA_CH_EVENT_HANDLER_t dma1_event_handlers[XMC_DMA1_NUM_CHANNELS]; #endif - + /******************************************************************************* * API IMPLEMENTATION *******************************************************************************/ @@ -201,6 +176,8 @@ void XMC_DMA_EnableRequestLine(XMC_DMA_t *const dma, uint8_t line, uint8_t perip #if defined(GPDMA1) if (dma == XMC_DMA0) { +#else + XMC_UNUSED_ARG(dma); #endif DLR->SRSEL0 = ((DLR->SRSEL0 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) | ((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE))); @@ -221,6 +198,8 @@ void XMC_DMA_DisableRequestLine(XMC_DMA_t *const dma, uint8_t line) #if defined(GPDMA1) if (dma == XMC_DMA0) { +#else + XMC_UNUSED_ARG(dma); #endif DLR->LNEN &= ~(0x1UL << line); #if defined(GPDMA1) @@ -237,15 +216,17 @@ void XMC_DMA_ClearRequestLine(XMC_DMA_t *const dma, uint8_t line) #if defined(GPDMA1) if (dma == XMC_DMA0) { +#else + XMC_UNUSED_ARG(dma); #endif DLR->LNEN &= ~(0x1UL << line); - DLR->LNEN |= 0x1UL << line; + DLR->LNEN |= 0x1UL << line; #if defined(GPDMA1) } else { DLR->LNEN &= ~(0x100UL << line); - DLR->LNEN |= 0x100UL << line; + DLR->LNEN |= 0x100UL << line; } #endif } @@ -258,6 +239,8 @@ bool XMC_DMA_GetOverrunStatus(XMC_DMA_t *const dma, uint8_t line) #if defined(GPDMA1) if (dma == XMC_DMA0) { +#else + XMC_UNUSED_ARG(dma); #endif status = (bool)(DLR->OVRSTAT & (0x1UL << line)); #if defined(GPDMA1) @@ -277,6 +260,8 @@ void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line) #if defined(GPDMA1) if (dma == XMC_DMA0) { +#else + XMC_UNUSED_ARG(dma); #endif DLR->OVRCLR = (uint32_t)(0x1UL << line); #if defined(GPDMA1) @@ -292,7 +277,7 @@ void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line) void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel) { dma->CHENREG = (uint32_t)(0x100UL << channel); - while((dma->CHENREG & (uint32_t)(0x1UL << channel)) != 0U) + while ((dma->CHENREG & (uint32_t)(0x1UL << channel)) != 0U) { /* wait until channel is disabled */ } @@ -383,12 +368,12 @@ XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_SRC_Msk; } } - + XMC_DMA_CH_ClearEventStatus(dma, channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_ERROR)); + (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_ERROR)); switch (config->transfer_type) { @@ -443,11 +428,11 @@ XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, status = XMC_DMA_CH_STATUS_BUSY; } } - else + else { status = XMC_DMA_CH_STATUS_ERROR; } - + return status; } @@ -474,7 +459,7 @@ void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const u { uint32_t event_idx; - for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + for (event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) { if (event & ((uint32_t)0x1UL << event_idx)) { @@ -488,7 +473,7 @@ void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const { uint32_t event_idx; - for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + for (event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) { if (event & ((uint32_t)0x1UL << event_idx)) { @@ -502,7 +487,7 @@ void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, co { uint32_t event_idx; - for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + for (event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) { if (event & (uint32_t)((uint32_t)0x1UL << event_idx)) { @@ -518,7 +503,7 @@ uint32_t XMC_DMA_CH_GetEventStatus(XMC_DMA_t *const dma, const uint8_t channel) uint32_t event_idx; uint32_t status = 0UL; - for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) + for (event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx) { status |= (uint32_t)((dma->STATUSCHEV[event_idx * 2UL] & (uint32_t)((uint32_t)0x1UL << (uint32_t)channel)) ? ((uint32_t)0x1UL << event_idx) : (uint32_t)0UL); @@ -557,23 +542,23 @@ void XMC_DMA_CH_DisableDestinationScatter(XMC_DMA_t *const dma, const uint8_t ch void XMC_DMA_CH_TriggerSourceRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last) { if ((uint32_t)type == (uint32_t)XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) - { + { dma->SGLREQSRCREG = ((uint32_t)0x101UL << channel); } if (last == true) { - dma->LSTSRCREG = (uint32_t)0x101UL << channel; + dma->LSTSRCREG = (uint32_t)0x101UL << channel; } - + dma->REQSRCREG = (uint32_t)0x101UL << channel; } /* Trigger destination request */ void XMC_DMA_CH_TriggerDestinationRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last) { - if(type == XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) - { + if (type == XMC_DMA_CH_TRANSACTION_TYPE_SINGLE) + { dma->SGLREQDSTREG = (uint32_t)0x101UL << channel; } @@ -613,6 +598,7 @@ void XMC_DMA_CH_DisableDestinationAddressReload(XMC_DMA_t *const dma, const uint void XMC_DMA_CH_RequestLastMultiblockTransfer(XMC_DMA_t *const dma, const uint8_t channel) { dma->CH[channel].CFGL &= (uint32_t)~(GPDMA0_CH_CFGL_RELOAD_SRC_Msk | GPDMA0_CH_CFGL_RELOAD_DST_Msk); + dma->CH[channel].CTLL &= (uint32_t)~(GPDMA0_CH_CTLL_LLP_SRC_EN_Msk | GPDMA0_CH_CTLL_LLP_DST_EN_Msk); } /* Set event handler */ @@ -621,6 +607,8 @@ void XMC_DMA_CH_SetEventHandler(XMC_DMA_t *const dma, const uint8_t channel, XMC #if defined(GPDMA1) if (dma == XMC_DMA0) { +#else + XMC_UNUSED_ARG(dma); #endif dma0_event_handlers[channel] = event_handler; #if defined(GPDMA1) @@ -669,7 +657,7 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) dma_event_handlers = dma1_event_handlers; } #endif - + event = XMC_DMA_GetEventStatus(dma); channel = 0; @@ -689,7 +677,7 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) { event_handler(XMC_DMA_CH_EVENT_ERROR); } - + break; } ++channel; @@ -703,10 +691,10 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) mask = (uint32_t)1U << channel; if (event & mask) { - XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); + XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); /* Call user callback to handle event */ event_handler = dma_event_handlers[channel]; @@ -714,7 +702,7 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) { event_handler(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE); } - + break; } ++channel; @@ -729,8 +717,8 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) if (event & mask) { XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | - (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); + (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | + (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE)); /* Call user callback to handle event */ event_handler = dma_event_handlers[channel]; @@ -760,7 +748,7 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) { event_handler(XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE); } - + break; } ++channel; @@ -781,7 +769,7 @@ void XMC_DMA_IRQHandler(XMC_DMA_t *const dma) if (event_handler != NULL) { event_handler(XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE); - } + } break; } diff --git a/cores/xmc_lib/XMCLib/src/xmc_dsd.c b/cores/xmc_lib/XMCLib/src/xmc_dsd.c index 0641d492..ea33b609 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_dsd.c +++ b/cores/xmc_lib/XMCLib/src/xmc_dsd.c @@ -1,57 +1,43 @@ /** * @file xmc_dsd.c - * @date 2015-09-18 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-03-30: - * - Initial version - * - * 2015-06-19: - * - Removed GetDriverVersion API
    - * - * 2015-09-18: - * - Support added for XMC4800 microcontroller family
    - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -134,25 +120,25 @@ bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd) bool status; XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd)); XMC_UNUSED_ARG(dsd); - - #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC48)||(UC_SERIES == XMC47)) - if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) + +#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC48)||(UC_SERIES == XMC47)) + if (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) { - if(XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_DSD) == false) + if (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_DSD) == false) { status = true; } - else - { + else + { status = false; - } + } } else { status = false; } - #else - if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) +#else + if (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false) { status = true; } @@ -160,8 +146,8 @@ bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd) { status = false; } - #endif - +#endif + return (status); } @@ -185,23 +171,23 @@ XMC_DSD_STATUS_t XMC_DSD_CH_Init( XMC_DSD_CH_t *const channel, const XMC_DSD_CH_ XMC_ASSERT("XMC_DSD_CH_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); XMC_ASSERT("XMC_DSD_CH_Init:NULL Pointer", (config != (XMC_DSD_CH_CONFIG_t *)NULL) ); - if (config->filter != (XMC_DSD_CH_FILTER_CONFIG_t*)NULL) + if (config->filter != (XMC_DSD_CH_FILTER_CONFIG_t *)NULL) { XMC_DSD_CH_MainFilter_Init(channel, config->filter); - if (config->aux != (XMC_DSD_CH_AUX_FILTER_CONFIG_t*)NULL) + if (config->aux != (XMC_DSD_CH_AUX_FILTER_CONFIG_t *)NULL) { XMC_DSD_CH_AuxFilter_Init(channel, config->aux); } - if (config->integrator != (XMC_DSD_CH_INTEGRATOR_CONFIG_t*)NULL) + if (config->integrator != (XMC_DSD_CH_INTEGRATOR_CONFIG_t *)NULL) { XMC_DSD_CH_Integrator_Init(channel, config->integrator); } - if (config->rectify != (XMC_DSD_CH_RECTIFY_CONFIG_t*)NULL) + if (config->rectify != (XMC_DSD_CH_RECTIFY_CONFIG_t *)NULL) { XMC_DSD_CH_Rectify_Init(channel, config->rectify); } - if (config->timestamp != (XMC_DSD_CH_TIMESTAMP_CONFIG_t*)NULL) + if (config->timestamp != (XMC_DSD_CH_TIMESTAMP_CONFIG_t *)NULL) { XMC_DSD_CH_Timestamp_Init(channel, config->timestamp); } @@ -226,8 +212,7 @@ void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FI XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value >= XMC_DSD_MIN_FILTER_START)); XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value <= config->decimation_factor)); XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Decimation Factor", - ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR))); - XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid divider",(((uint32_t)config->clock_divider <= XMC_DSD_CH_CLK_DIV_32))); + ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR))); /*Set Channel frequency*/ channel->MODCFG = ((uint32_t)config->clock_divider << DSD_CH_MODCFG_DIVM_Pos) | (uint32_t)DSD_CH_MODCFG_DWC_Msk; @@ -236,14 +221,14 @@ void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FI channel->DICFG = config->demodulator_conf | (uint32_t)DSD_CH_DICFG_DSWC_Msk | (uint32_t)DSD_CH_DICFG_SCWC_Msk; /*The decimation factor of the Main CIC filter is CFMDF + 1.*/ - decimation_factor_temp = config->decimation_factor-1U; - filter_start_value_temp = config->filter_start_value-1U; + decimation_factor_temp = config->decimation_factor - 1U; + filter_start_value_temp = config->filter_start_value - 1U; /* Filter setup*/ channel->FCFGC = (decimation_factor_temp | - (filter_start_value_temp << (uint32_t)DSD_CH_FCFGC_CFMSV_Pos)| - config->main_filter_conf| - (uint32_t)DSD_CH_FCFGC_CFEN_Msk); + (filter_start_value_temp << (uint32_t)DSD_CH_FCFGC_CFMSV_Pos) | + config->main_filter_conf | + (uint32_t)DSD_CH_FCFGC_CFEN_Msk); /* Offset */ channel->OFFM = (uint16_t)config->offset; @@ -257,7 +242,7 @@ void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIM XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_TIMESTAMP_CONFIG_t *)NULL) ); temp = (channel->DICFG | (uint32_t)DSD_CH_DICFG_TRWC_Msk); - temp &= ~((uint32_t)DSD_CH_DICFG_TSTRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk); + temp &= ~((uint32_t)DSD_CH_DICFG_TSTRMODE_Msk | (uint32_t)DSD_CH_DICFG_TRSEL_Msk); temp |= config->timestamp_conf; channel->DICFG = temp; } @@ -270,11 +255,11 @@ void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel)); XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_AUX_FILTER_CONFIG_t *)NULL) ); XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid Decimation Factor", - ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR_AUX))); + ((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR_AUX))); channel->BOUNDSEL = config->boundary_conf; /*The decimation factor of the Aux CIC filter is CFMDF + 1.*/ - decimation_factor_temp = config->decimation_factor-1U; + decimation_factor_temp = config->decimation_factor - 1U; channel->FCFGA = (decimation_factor_temp | config->aux_filter_conf); } @@ -293,7 +278,7 @@ void XMC_DSD_CH_Integrator_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_IN | ((config->counted_values - 1U) << DSD_CH_IWCTR_NVALINT_Pos); /*To ensure proper operation, ensure that bit field ITRMODE is zero before selecting any other trigger mode.*/ - temp = (channel->DICFG & ~((uint32_t)DSD_CH_DICFG_ITRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk)) | (uint32_t)DSD_CH_DICFG_TRWC_Msk; + temp = (channel->DICFG & ~((uint32_t)DSD_CH_DICFG_ITRMODE_Msk | (uint32_t)DSD_CH_DICFG_TRSEL_Msk)) | (uint32_t)DSD_CH_DICFG_TRWC_Msk; channel->DICFG = temp; @@ -310,14 +295,14 @@ void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTI channel->RECTCFG = config->rectify_config | (uint32_t)DSD_CH_RECTCFG_RFEN_Msk; channel->CGSYNC = (((uint32_t) config->delay << (uint32_t)DSD_CH_CGSYNC_SDPOS_Pos) - | (((uint32_t)config->delay + (uint32_t)config->half_cycle) << (uint32_t)DSD_CH_CGSYNC_SDNEG_Pos)); + | (((uint32_t)config->delay + (uint32_t)config->half_cycle) << (uint32_t)DSD_CH_CGSYNC_SDNEG_Pos)); } /* API to get the result of the last conversion */ -void XMC_DSD_CH_GetResult_TS(XMC_DSD_CH_t* const channel, - int16_t* dsd_result, - uint8_t* dsd_filter_count, - uint8_t* dsd_integration_count) +void XMC_DSD_CH_GetResult_TS(XMC_DSD_CH_t *const channel, + int16_t *dsd_result, + uint8_t *dsd_filter_count, + uint8_t *dsd_integration_count) { uint32_t timestamp; uint16_t result; @@ -325,12 +310,12 @@ void XMC_DSD_CH_GetResult_TS(XMC_DSD_CH_t* const channel, timestamp = channel->TSTMP; result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk); *dsd_result = (int16_t)(result); - *dsd_filter_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_CFMDCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_CFMDCNT_Pos); - *dsd_integration_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_NVALCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_NVALCNT_Pos); + *dsd_filter_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_CFMDCNT_Msk) >> (uint32_t)DSD_CH_TSTMP_CFMDCNT_Pos); + *dsd_integration_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_NVALCNT_Msk) >> (uint32_t)DSD_CH_TSTMP_NVALCNT_Pos); } /* API to get the result of the last conversion with the time */ -void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t* const channel, int16_t* dsd_Result, uint32_t* time) +void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t *const channel, int16_t *dsd_Result, uint32_t *time) { uint32_t timestamp; uint16_t filter_count; @@ -340,12 +325,12 @@ void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t* const channel, int16_t* dsd_Resu timestamp = channel->TSTMP; decimation = (uint16_t)(channel->FCFGC & DSD_CH_FCFGC_CFMDF_Msk); - filter_count = (uint16_t)((timestamp & DSD_CH_TSTMP_CFMDCNT_Msk)>>DSD_CH_TSTMP_CFMDCNT_Pos); + filter_count = (uint16_t)((timestamp & DSD_CH_TSTMP_CFMDCNT_Msk) >> DSD_CH_TSTMP_CFMDCNT_Pos); /* Integration enabled? */ if ((channel->IWCTR & DSD_CH_IWCTR_INTEN_Msk)) { - integrator_count = (uint16_t) ((timestamp & DSD_CH_TSTMP_NVALCNT_Msk)>>DSD_CH_TSTMP_NVALCNT_Pos); + integrator_count = (uint16_t) ((timestamp & DSD_CH_TSTMP_NVALCNT_Msk) >> DSD_CH_TSTMP_NVALCNT_Pos); /*See Errata number: xxyy */ if (filter_count == decimation) diff --git a/cores/xmc_lib/XMCLib/src/xmc_ebu.c b/cores/xmc_lib/XMCLib/src/xmc_ebu.c index 5e986149..0c671520 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_ebu.c +++ b/cores/xmc_lib/XMCLib/src/xmc_ebu.c @@ -1,59 +1,51 @@ /** * @file xmc_ebu.c - * @date 2017-06-24 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-06-20: - * - Removed GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2017-06-24: - * - Changed XMC_EBU_Init() adding checks for the clock acknoledgment. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * @endcond + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ - + /********************************************************************************************************************* * HEADER FILES *********************************************************************************************************************/ - -#include + +#include "xmc_ebu.h" #if defined(EBU) @@ -64,11 +56,11 @@ /* * Initialize the EBU peripheral */ -XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu,const XMC_EBU_CONFIG_t *const config) +XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu, const XMC_EBU_CONFIG_t *const config) { XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_CONFIG_t *)NULL)); - + /* Enable EBU */ XMC_EBU_Enable(ebu); @@ -79,7 +71,7 @@ XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu,const XMC_EBU_CONFIG_t *const /*EBU Mode Configuration */ ebu->MODCON = config->ebu_mode_config.raw0; - + /* Address Bits available for GPIO function */ ebu->USERCON = config->ebu_free_pins_to_gpio.raw0; @@ -89,11 +81,11 @@ XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu,const XMC_EBU_CONFIG_t *const /* * Configures the SDRAM with operating modes and refresh parameters */ -void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu,const XMC_EBU_SDRAM_CONFIG_t *const config) +void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu, const XMC_EBU_SDRAM_CONFIG_t *const config) { XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_SDRAM_CONFIG_t *)NULL)); - + /* EBU SDRAM Refresh Configuration Parameters */ ebu->SDRMREF = config->raw2; /* EBU SDRAM General Configuration Parameters */ @@ -105,12 +97,12 @@ void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu,const XMC_EBU_SDRAM_CONFIG_t *c /* * Configures the SDRAM region for read and write operation */ -void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu,const XMC_EBU_REGION_t *const region) +void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu, const XMC_EBU_REGION_t *const region) { - + XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu)); XMC_ASSERT("XMC_EBU_Init:Null Pointer", (region != (XMC_EBU_REGION_t *)NULL)); - + /* Read configuration of the region*/ ebu->BUS[region->read_config.ebu_region_no].RDCON = region->read_config.ebu_bus_read_config.raw0; diff --git a/cores/xmc_lib/XMCLib/src/xmc_ecat.c b/cores/xmc_lib/XMCLib/src/xmc_ecat.c index a5bd4c33..ee97a60c 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_ecat.c +++ b/cores/xmc_lib/XMCLib/src/xmc_ecat.c @@ -1,50 +1,42 @@ /** * @file xmc_ecat.c - * @date 2017-04-27 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-10-21: - * - Initial Version + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-27: - * - Add clock gating control in enable/disable APIs + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2017-04-27: - * - Changed XMC_ECAT_ReadPhy() and XMC_ECAT_WritePhy() to release the MII access and check that the master enables take over of MII management control + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -53,11 +45,11 @@ * HEADER FILES *******************************************************************************/ -#include +#include "xmc_ecat.h" #if defined (ECAT0) -#include +#include "xmc_scu.h" /******************************************************************************* * MACROS @@ -83,14 +75,14 @@ void XMC_ECAT_Enable(void) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0); XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0); - while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true){} + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true) {} } /* EtherCAT module clock gating and assert reset API (Disables ECAT)*/ void XMC_ECAT_Disable(void) { XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0); - while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false){} + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false) {} XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0); } @@ -101,7 +93,7 @@ void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config) XMC_ECAT_Enable(); /* The process memory is not accessible until the ESC Configuration Area is loaded successfully. */ - + /* words 0x0-0x3 */ ECAT0->EEP_DATA[0U] = config->dword[0U]; ECAT0->EEP_DATA[1U] = config->dword[1U]; @@ -139,13 +131,13 @@ uint32_t XMC_ECAT_GetEventStatus(void) /* EtherCAT SyncManager channel disable function*/ void XMC_ECAT_DisableSyncManChannel(const uint8_t channel) { - ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U; + ((ECAT0_SM_Type *)(void *)((uint8_t *)(void *)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U; } /* EtherCAT SyncManager channel enable function*/ void XMC_ECAT_EnableSyncManChannel(const uint8_t channel) { - ((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U); + ((ECAT0_SM_Type *)(void *)((uint8_t *)(void *)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U); } @@ -156,7 +148,7 @@ XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t if ((ECAT0->MII_ECAT_ACS_STATE != 0) || ((ECAT0->MII_PDI_ACS_STATE & ECAT_MII_PDI_ACS_STATE_FORCE_PDI_ACS_S_Msk) != 0)) { - status = XMC_ECAT_STATUS_ERROR; + status = XMC_ECAT_STATUS_ERROR; } else { @@ -166,7 +158,7 @@ XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t ECAT0->MII_PHY_REG_ADR = reg_addr; ECAT0->MII_CONT_STAT = 0x0100U; /* read instruction */ - while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){} + while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U) {} if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U) { @@ -192,7 +184,7 @@ XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t if ((ECAT0->MII_ECAT_ACS_STATE != 0) || ((ECAT0->MII_PDI_ACS_STATE & ECAT_MII_PDI_ACS_STATE_FORCE_PDI_ACS_S_Msk) != 0)) { - status = XMC_ECAT_STATUS_ERROR; + status = XMC_ECAT_STATUS_ERROR; } else { @@ -203,7 +195,7 @@ XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t ECAT0->MII_PHY_DATA = data; ECAT0->MII_CONT_STAT = 0x0200U; /* write instruction */ - while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){} + while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U) {} if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U) { diff --git a/cores/xmc_lib/XMCLib/src/xmc_eru.c b/cores/xmc_lib/XMCLib/src/xmc_eru.c index c6df9f18..20ec1093 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_eru.c +++ b/cores/xmc_lib/XMCLib/src/xmc_eru.c @@ -1,49 +1,41 @@ /** * @file xmc_eru.c - * @date 2016-03-10 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-03-10: - * - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation.
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -119,7 +111,7 @@ (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER) || \ (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH) || \ (service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH)) - + /********************************************************************************************************************* * API IMPLEMENTATION ********************************************************************************************************************/ @@ -127,16 +119,16 @@ void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_CONFIG_t *const config) -{ +{ XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Channel Number", (channel < 4U)); XMC_ERU_Enable(eru); - eru->EXISEL = (eru->EXISEL & + eru->EXISEL = (eru->EXISEL & ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) | (config->input << (channel * (uint32_t)ERU_EXISEL_BITSIZE)); - + eru->EXICON[channel] = config->raw; } @@ -168,11 +160,11 @@ void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru, (((uint32_t)input_a | (uint32_t)(input_b << ERU_EXISEL_INPUT_BITSIZE)) << (channel * ERU_EXISEL_BITSIZE)); } -/* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits of +/* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits of EXICONx(x = [0 to 3]) register */ void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru, - const uint8_t channel, - const XMC_ERU_ETL_SOURCE_t source) + const uint8_t channel, + const XMC_ERU_ETL_SOURCE_t source) { XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Channel Number", (channel < 4U)); @@ -213,7 +205,7 @@ void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru, eru->EXICON_b[channel].LD = (uint8_t)mode; } -/* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by +/* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by * ETLx(Event Trigger Logic, x = [0 to 3]) by setting (OCS and PE) bit fields. */ void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel, @@ -260,20 +252,20 @@ void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t cha /* Configures peripheral trigger input, by setting (ISS) bit. */ void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru, - const uint8_t channel, - const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger) + const uint8_t channel, + const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger) { XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Channel Number", (channel < 4U)); - XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Peripheral Trigger Input", - XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(peripheral_trigger)); + XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Peripheral Trigger Input", + XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(peripheral_trigger)); eru->EXOCON_b[channel].ISS = (uint8_t)peripheral_trigger; } /* Disables event generation based on peripheral trigger by clearing (ISS) bit. */ void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru, - const uint8_t channel) + const uint8_t channel) { XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru)); XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Channel Number", (channel < 4U)); diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_mac.c b/cores/xmc_lib/XMCLib/src/xmc_eth_mac.c index 95a15b2f..96b09dbf 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_eth_mac.c +++ b/cores/xmc_lib/XMCLib/src/xmc_eth_mac.c @@ -1,93 +1,42 @@ /** * @file xmc_eth_mac.c - * @date 2017-08-03 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-09-01: - * - Add clock gating control in enable/disable APIs - * - Add transmit polling if run out of buffers + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-11-30: - * - Fix XMC_ETH_MAC_GetRxFrameSize return value in case of errors + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-03-16: - * - Fix XMC_ETH_MAC_DisableEvent - * - * 2016-05-19: - * - Changed XMC_ETH_MAC_ReturnTxDescriptor and XMC_ETH_MAC_ReturnRxDescriptor - * - * 2016-08-30: - * - Changed XMC_ETH_MAC_Init() to disable MMC interrupt events - * - * 2016-11-22: - * - Changed XMC_ETH_MAC_Init() to optimize access to bus - * - * 2017-02-25: - * - XMC_ETH_MAC_Enable() and XMC_ETH_MAC_Disable(), fixed compilation warnings - * - * 2017-03-27: - * - Changed XMC_ETH_MAC_Init() to disable PMT and timestamp interrupt events - * - * 2017-04-02: - * - Added XMC_ETH_MAC_InitPTPEx() - * - Added XMC_ETH_MAC_SetPTPTime() - * - Added XMC_ETH_MAC_UpdateAddend() - * - Fixed XMC_ETH_MAC_InitPTP(), XMC_ETH_MAC_UpdatePTPTime(), XMC_ETH_MAC_SetPTPAlarm() - * - nanoseconds initializazion - * - added polling to wait for setup - * - * 2017-04-04: - * - Changed XMC_ETH_MAC_Init() to disable MMC IPC receive interrupt events - * - * 2017-04-11: - * - Fixed XMC_ETH_MAC_SetPTPAlarm() nanoseconds conversion - * - * 2017-04-17: - * - Changed XMC_ETH_MAC_GetTxTimeStamp() and XMC_ETH_MAC_GetRxTimeStamp() return the timestamp depending on status bit in descriptor - * - * 2017-04-27: - * - Fixed XMC_ETH_MAC_GetRxTimeStamp() and XMC_ETH_MAC_GetTxTimeStamp() fixed returned nanoseconds value - * - * 2017-08-03: - * - Changed XMC_ETH_MAC_InitPTP(), XMC_ETH_MAC_InitPTPEx(), XMC_ETH_MAC_GetPTPTime(), XMC_ETH_MAC_UpdatePTPTime(), XMC_ETH_MAC_SetPTPAlarm(), XMC_ETH_MAC_GetRxTimeStamp(), XMC_ETH_MAC_GetTxTimeStamp() - * rollover mode of nanosecond counter from binary to digital mode, i.e 1ns resolution + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -95,12 +44,12 @@ /******************************************************************************* * HEADER FILES *******************************************************************************/ -#include +#include "xmc_eth_mac.h" #if defined (ETH0) #include -#include +#include "xmc_scu.h" /******************************************************************************* * MACROS @@ -186,20 +135,20 @@ __STATIC_INLINE bool XCM_ETH_MAC_IsNormalEvent(uint32_t event) /* Check if the event passed is an abnormal event */ __STATIC_INLINE bool XCM_ETH_MAC_IsAbnormalEvent(uint32_t event) { - return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED | - (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT | - (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW | - (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW | - (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE | - (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED | - (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT | - (uint32_t)XMC_ETH_MAC_EVENT_EARLY_TRANSMIT | - (uint32_t)XMC_ETH_MAC_EVENT_BUS_ERROR)) != (uint32_t)0); - } - -#ifdef XMC_ASSERT_ENABLE - -/* Check if the passed argument is a valid ETH module */ + return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW | + (uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED | + (uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT | + (uint32_t)XMC_ETH_MAC_EVENT_EARLY_TRANSMIT | + (uint32_t)XMC_ETH_MAC_EVENT_BUS_ERROR)) != (uint32_t)0); +} + +#ifdef XMC_ASSERT_ENABLE + +/* Check if the passed argument is a valid ETH module */ __STATIC_INLINE bool XMC_ETH_MAC_IsValidModule(ETH_GLOBAL_TypeDef *const eth) { return (eth == ETH0); @@ -207,20 +156,12 @@ __STATIC_INLINE bool XMC_ETH_MAC_IsValidModule(ETH_GLOBAL_TypeDef *const eth) #endif -/* ETH MAC initialize */ -XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac) +void XMC_ETH_MAC_InitEx(XMC_ETH_MAC_t *const eth_mac) { - XMC_ETH_MAC_STATUS_t status; - - XMC_ASSERT("XMC_ETH_MAC_Init: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_InitEx: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); - XMC_ETH_MAC_Enable(eth_mac); XMC_ETH_MAC_Reset(eth_mac); - status = XMC_ETH_MAC_SetManagmentClockDivider(eth_mac); - - XMC_ETH_MAC_SetAddress(eth_mac, eth_mac->address); - /* Initialize MAC configuration */ eth_mac->regs->MAC_CONFIGURATION = (uint32_t)ETH_MAC_CONFIGURATION_IPC_Msk; @@ -253,6 +194,21 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac) eth_mac->regs->INTERRUPT_MASK = ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk; eth_mac->frame_end = NULL; +} + +/* ETH MAC initialize */ +XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac) +{ + XMC_ETH_MAC_STATUS_t status; + + XMC_ASSERT("XMC_ETH_MAC_Init: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + + XMC_ETH_MAC_Enable(eth_mac); + status = XMC_ETH_MAC_SetManagmentClockDivider(eth_mac); + + XMC_ETH_MAC_InitEx(eth_mac); + + XMC_ETH_MAC_SetAddress(eth_mac, eth_mac->address); return status; } @@ -271,17 +227,26 @@ void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac) */ for (i = 0U; i < eth_mac->num_rx_buf; ++i) { - eth_mac->rx_desc[i].status = (uint32_t)ETH_MAC_DMA_RDES0_OWN; - eth_mac->rx_desc[i].length = (uint32_t)ETH_MAC_DMA_RDES1_RCH | (uint32_t)XMC_ETH_MAC_BUF_SIZE; - eth_mac->rx_desc[i].buffer1 = (uint32_t)&(eth_mac->rx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + eth_mac->rx_desc[i].status = (uint32_t)ETH_MAC_DMA_RDES0_OWN; + eth_mac->rx_desc[i].length = (uint32_t)ETH_MAC_DMA_RDES1_RCH | (uint32_t)XMC_ETH_MAC_BUF_SIZE; + + if (eth_mac->rx_buf != NULL) + { + eth_mac->rx_desc[i].buffer1 = (uint32_t) & (eth_mac->rx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + } + else + { + eth_mac->rx_desc[i].buffer1 = 0; + } + next = i + 1U; if (next == eth_mac->num_rx_buf) { next = 0U; } - eth_mac->rx_desc[i].buffer2 = (uint32_t)&(eth_mac->rx_desc[next]); + eth_mac->rx_desc[i].buffer2 = (uint32_t) & (eth_mac->rx_desc[next]); } - eth_mac->regs->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->rx_desc[0]); + eth_mac->regs->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t) & (eth_mac->rx_desc[0]); eth_mac->rx_index = 0U; } @@ -296,24 +261,52 @@ void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac) /* Chained structure (ETH_MAC_DMA_TDES0_TCH), second address in the descriptor (buffer2) is the next descriptor address */ for (i = 0U; i < eth_mac->num_tx_buf; ++i) { - eth_mac->tx_desc[i].status = ETH_MAC_DMA_TDES0_TCH | ETH_MAC_DMA_TDES0_LS | ETH_MAC_DMA_TDES0_FS; - eth_mac->tx_desc[i].buffer1 = (uint32_t)&(eth_mac->tx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + eth_mac->tx_desc[i].status = ETH_MAC_DMA_TDES0_TCH | ETH_MAC_DMA_TDES0_LS | ETH_MAC_DMA_TDES0_FS | ETH_MAC_DMA_TDES0_IC; + + if (eth_mac->tx_buf != NULL) + { + eth_mac->tx_desc[i].buffer1 = (uint32_t) & (eth_mac->tx_buf[i * XMC_ETH_MAC_BUF_SIZE]); + } + else + { + eth_mac->tx_desc[i].buffer1 = 0; + } + next = i + 1U; if (next == eth_mac->num_tx_buf) { - next = 0U; + next = 0U; } - eth_mac->tx_desc[i].buffer2 = (uint32_t)&(eth_mac->tx_desc[next]); + eth_mac->tx_desc[i].buffer2 = (uint32_t) & (eth_mac->tx_desc[next]); } - eth_mac->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->tx_desc[0]); + eth_mac->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t) & (eth_mac->tx_desc[0]); eth_mac->tx_index = 0U; } +void XMC_ETH_MAC_SetAddressEx(XMC_ETH_MAC_t *const eth_mac, const uint8_t *const addr) +{ + eth_mac->regs->MAC_ADDRESS0_HIGH = addr[4] | (addr[5] << 8); + eth_mac->regs->MAC_ADDRESS0_LOW = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); +} + +void XMC_ETH_MAC_GetAddressEx(XMC_ETH_MAC_t *const eth_mac, uint8_t *const addr) +{ + uint32_t low_addr = eth_mac->regs->MAC_ADDRESS0_LOW; + uint32_t high_addr = eth_mac->regs->MAC_ADDRESS0_HIGH; + + addr[0] = low_addr & 0xff; + addr[1] = (low_addr >> 8) & 0xff; + addr[2] = (low_addr >> 16) & 0xff; + addr[3] = (low_addr >> 24) & 0xff; + addr[4] = high_addr & 0xff; + addr[5] = (high_addr >> 8) & 0xff; +} + /* Set address perfect filter */ void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, - uint8_t index, - const uint64_t addr, - uint32_t flags) + uint8_t index, + const uint64_t addr, + uint32_t flags) { __IO uint32_t *reg; @@ -325,6 +318,21 @@ void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac, reg[index + 1U] = (uint32_t)addr; } +void XMC_ETH_MAC_SetAddressPerfectFilterEx(XMC_ETH_MAC_t *const eth_mac, + uint8_t index, + uint8_t *const addr, + uint32_t flags) +{ + __IO uint32_t *reg; + + XMC_ASSERT("XMC_ETH_MAC_SetAddressPerfectFilter: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); + XMC_ASSERT("XMC_ETH_MAC_SetAddressFilter: index is out of range", ((index > 0) && (index < 4))); + + reg = &(eth_mac->regs->MAC_ADDRESS0_HIGH); + reg[index] = addr[4] | (addr[5] << 8) | flags; + reg[index + 1U] = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); +} + /* Set address hash filter */ void XMC_ETH_MAC_SetAddressHashFilter(XMC_ETH_MAC_t *const eth_mac, const uint64_t hash) { @@ -386,12 +394,12 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, const u if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_EVENT) { - ctrl |= ETH_MAC_DMA_TDES0_IC; + ctrl |= ETH_MAC_DMA_TDES0_IC; } if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_TIMESTAMP) { - ctrl |= ETH_MAC_DMA_TDES0_TTSE; + ctrl |= ETH_MAC_DMA_TDES0_TTSE; } eth_mac->tx_ts_index = eth_mac->tx_index; @@ -400,7 +408,7 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, const u eth_mac->tx_index++; if (eth_mac->tx_index == eth_mac->num_tx_buf) { - eth_mac->tx_index = 0U; + eth_mac->tx_index = 0U; } eth_mac->frame_end = NULL; @@ -440,8 +448,8 @@ uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *frame, uin if (eth_mac->regs->STATUS & ETH_STATUS_RU_Msk) { /* Receive buffer unavailable, resume DMA */ - eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk; - eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; + eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk; + eth_mac->regs->RECEIVE_POLL_DEMAND = 0U; } return (len); @@ -462,12 +470,12 @@ uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac) } else if (((status & ETH_MAC_DMA_RDES0_ES) != 0U) || ((status & ETH_MAC_DMA_RDES0_FS) == 0U) || - ((status & ETH_MAC_DMA_RDES0_LS) == 0U)) + ((status & ETH_MAC_DMA_RDES0_LS) == 0U)) { /* Error, this block is invalid */ len = 0xFFFFFFFFU; } - else + else { /* Subtract CRC */ len = ((status & ETH_MAC_DMA_RDES0_FL) >> 16U) - 4U; @@ -551,9 +559,9 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_add XMC_ASSERT("XMC_ETH_MAC_PhyRead: Parameter error", data != NULL); eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) | - (uint32_t)ETH_GMII_ADDRESS_MB_Msk | - (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | - (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); + (uint32_t)ETH_GMII_ADDRESS_MB_Msk | + (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | + (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); /* Poll busy bit during max PHY_TIMEOUT time */ retries = 0U; @@ -565,7 +573,8 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_add return XMC_ETH_MAC_STATUS_OK; } ++retries; - } while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); + } + while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); return XMC_ETH_MAC_STATUS_ERROR; } @@ -577,12 +586,12 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_ad eth_mac->regs->GMII_DATA = data; eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) | - (uint32_t)ETH_GMII_ADDRESS_MB_Msk | - (uint32_t)ETH_GMII_ADDRESS_MW_Msk | - (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | - (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); + (uint32_t)ETH_GMII_ADDRESS_MB_Msk | + (uint32_t)ETH_GMII_ADDRESS_MW_Msk | + (uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) | + (uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos)); - /* Poll busy bit during max PHY_TIMEOUT time */ + /* Poll busy bit during max PHY_TIMEOUT time */ retries = 0U; do { @@ -591,7 +600,8 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_ad return XMC_ETH_MAC_STATUS_OK; } ++retries; - } while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); + } + while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES); return XMC_ETH_MAC_STATUS_ERROR; } @@ -636,12 +646,12 @@ void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event) event &= (uint16_t)0x7fffU; if (XCM_ETH_MAC_IsNormalEvent(event)) { - event |= (uint32_t)ETH_INTERRUPT_ENABLE_NIE_Msk; + event |= (uint32_t)ETH_INTERRUPT_ENABLE_NIE_Msk; } if (XCM_ETH_MAC_IsAbnormalEvent(event)) { - event |= (uint32_t)ETH_INTERRUPT_ENABLE_AIE_Msk; + event |= (uint32_t)ETH_INTERRUPT_ENABLE_AIE_Msk; } eth_mac->regs->INTERRUPT_ENABLE |= event; @@ -681,11 +691,11 @@ uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac) { uint32_t temp_status = 0; XMC_ASSERT("XMC_ETH_MAC_GetEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); - + temp_status = (eth_mac->regs->STATUS & (uint32_t)0x7ffUL); return ((uint32_t)((eth_mac->regs->INTERRUPT_STATUS & (ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk)) << 16U) | - temp_status); + temp_status); } /* Return RX descriptor */ @@ -696,7 +706,7 @@ void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac) if (eth_mac->rx_index == eth_mac->num_rx_buf) { eth_mac->rx_index = 0U; - } + } } /* Return TX descriptor */ @@ -704,22 +714,22 @@ void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac) { eth_mac->tx_ts_index = eth_mac->tx_index; - eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_CIC |ETH_MAC_DMA_TDES0_OWN; + eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_CIC | ETH_MAC_DMA_TDES0_OWN; eth_mac->tx_index++; if (eth_mac->tx_index == eth_mac->num_tx_buf) { eth_mac->tx_index = 0U; - } + } eth_mac->frame_end = NULL; } /* Set VLAN tag */ -void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag) +void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint32_t tag) { XMC_ASSERT("XMC_ETH_MAC_SetVLANTag: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); - eth_mac->regs->VLAN_TAG = (uint32_t)tag; + eth_mac->regs->VLAN_TAG = tag; } /* Initialize PTP */ @@ -737,7 +747,7 @@ void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config) { /* Program sub-second increment register based on PTP clock frequency ~ 50MHz */ eth_mac->regs->SUB_SECOND_INCREMENT = 20; - + /* fSYS = Reference Clock for the Time Stamp Update Logic*/ float ratio = (float)XMC_SCU_CLOCK_GetSystemClockFrequency() / (float)XMC_ETH_SUB_SECOND_UPDATE_FREQ; eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)(((float)0x100000000ULL / ratio) + 0.5F); @@ -750,12 +760,12 @@ void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config) } else { - /* Program sub-second increment register based on PTP clock frequency = fSYS/2 */ - eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)(((float)1000000000 / (float)XMC_SCU_CLOCK_GetSystemClockFrequency()) + 0.5F); + /* Program sub-second increment register based on PTP clock frequency = fSYS/2 */ + eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)(((float)1000000000 / (float)XMC_SCU_CLOCK_GetSystemClockFrequency()) + 0.5F); } - + eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk; - while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk); } /* Initialize PTP using a given time */ @@ -834,7 +844,7 @@ void XMC_ETH_MAC_AdjustPTPClock(XMC_ETH_MAC_t *const eth_mac, uint32_t correctio eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk; /* Poll the Timestamp Control register until the bit TSADDREG is cleared */ - while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); + while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk); } /* Update Addend */ @@ -878,13 +888,13 @@ XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetRxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XM if ((rx_desc->status & (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) == (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) { time->nanoseconds = (int32_t)(rx_desc->time_stamp_nanoseconds); - time->seconds = rx_desc->time_stamp_seconds; + time->seconds = rx_desc->time_stamp_seconds; status = XMC_ETH_MAC_STATUS_OK; } else { - status = XMC_ETH_MAC_STATUS_ERROR; + status = XMC_ETH_MAC_STATUS_ERROR; } } diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c b/cores/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c index 486b1a56..53f42c08 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c +++ b/cores/xmc_lib/XMCLib/src/xmc_eth_phy_dp83848.c @@ -1,47 +1,41 @@ /** * @file xmc_eth_phy_dp83848.c - * @date 2015-12-15 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-15: - * - Added Reset and exit power down - * - Reset function called in Init function + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -50,7 +44,7 @@ * HEADER FILES *******************************************************************************/ #if defined(XMC_ETH_PHY_DP83848C) -#include +#include "xmc_eth_phy.h" /******************************************************************************* * MACROS @@ -123,7 +117,7 @@ * API IMPLEMENTATION *******************************************************************************/ - /* Check if the device identifier is valid */ +/* Check if the device identifier is valid */ static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) { uint16_t phy_id1; @@ -154,17 +148,18 @@ static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t /* PHY initialize */ int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) { + uint32_t retries = 0xffffffffUL; int32_t status; uint16_t reg_val; - status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + while (((status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr)) != XMC_ETH_PHY_STATUS_OK) && --retries); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) { status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); - + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_val = 0U; if (config->speed == XMC_ETH_LINK_SPEED_100M) { @@ -187,11 +182,11 @@ int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const X } status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_val); - + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) { - /* Configure interface mode */ - switch (config->interface) + /* Configure interface mode */ + switch (config->interface) { case XMC_ETH_LINK_INTERFACE_MII: reg_val = 0x0001; @@ -201,7 +196,7 @@ int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const X break; } status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_RBR, reg_val); - } + } } } @@ -217,14 +212,15 @@ int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) /* Reset PHY*/ status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { /* Wait for the reset to complete */ - do + do { status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); - } while ((reg_bmcr & BMCR_RESET) != 0); + } + while ((reg_bmcr & BMCR_RESET) != 0); } - + return status; } @@ -236,7 +232,7 @@ int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_bmcr |= BMCR_POWER_DOWN; status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); } @@ -249,9 +245,9 @@ int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr int32_t status; uint16_t reg_bmcr; - status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_bmcr &= ~BMCR_POWER_DOWN; status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c b/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c index cebfaab4..0e6d7139 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c +++ b/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8031rnl.c @@ -1,47 +1,41 @@ /** * @file xmc_eth_phy_ksz8031ml.c - * @date 2015-12-15 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-15: - * - Added Reset and exit power down - * - Reset function called in Init function + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -50,7 +44,7 @@ * HEADER FILES *******************************************************************************/ #if defined(XMC_ETH_PHY_KSZ8031RNL) -#include +#include "xmc_eth_phy.h" /******************************************************************************* * MACROS @@ -106,7 +100,7 @@ * API IMPLEMENTATION *******************************************************************************/ - /* Check if the device identifier is valid */ +/* Check if the device identifier is valid */ static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) { uint16_t phy_id1; @@ -137,15 +131,16 @@ static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t /* PHY initialize */ int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) { + uint32_t retries = 0xffffffffUL; int32_t status; uint16_t reg_bmcr; - status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); - + while (((status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr)) != XMC_ETH_PHY_STATUS_OK) && --retries); + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) { status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); - + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) { reg_bmcr = 0U; @@ -185,14 +180,15 @@ int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) /* Reset PHY*/ status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { /* Wait for the reset to complete */ - do + do { status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); - } while ((reg_bmcr & BMCR_RESET) != 0); + } + while ((reg_bmcr & BMCR_RESET) != 0); } - + return status; } @@ -204,7 +200,7 @@ int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_bmcr |= BMCR_POWER_DOWN; status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); } @@ -217,9 +213,9 @@ int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr int32_t status; uint16_t reg_bmcr; - status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_bmcr &= ~BMCR_POWER_DOWN; status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c b/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c index e6e02b8f..fd8ad50b 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c +++ b/cores/xmc_lib/XMCLib/src/xmc_eth_phy_ksz8081rnb.c @@ -1,47 +1,41 @@ /** * @file xmc_eth_phy_ksz8081rnb.c - * @date 2015-12-15 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Initial + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-12-15: - * - Added Reset and exit power down - * - Reset function called in Init function + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ @@ -50,7 +44,7 @@ * HEADER FILES *******************************************************************************/ #if defined(XMC_ETH_PHY_KSZ8081RNB) -#include +#include "xmc_eth_phy.h" /******************************************************************************* * MACROS @@ -106,7 +100,7 @@ * API IMPLEMENTATION *******************************************************************************/ - /* Check if the device identifier is valid */ +/* Check if the device identifier is valid */ static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) { uint16_t phy_id1; @@ -137,15 +131,16 @@ static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t /* PHY initialize */ int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config) { + uint32_t retries = 0xffffffffUL; int32_t status; uint16_t reg_bmcr; - status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr); + while (((status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr)) != XMC_ETH_PHY_STATUS_OK) && --retries); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) { status = XMC_ETH_PHY_Reset(eth_mac, phy_addr); - + if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) { reg_bmcr = 0U; @@ -185,14 +180,15 @@ int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) /* Reset PHY*/ status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { /* Wait for the reset to complete */ - do + do { status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); - } while ((reg_bmcr & BMCR_RESET) != 0); + } + while ((reg_bmcr & BMCR_RESET) != 0); } - + return status; } @@ -204,7 +200,7 @@ int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr) status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_bmcr |= BMCR_POWER_DOWN; status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); } @@ -217,9 +213,9 @@ int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr int32_t status; uint16_t reg_bmcr; - status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); + status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, ®_bmcr); if (status == (int32_t)XMC_ETH_PHY_STATUS_OK) - { + { reg_bmcr &= ~BMCR_POWER_DOWN; status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_fce.c b/cores/xmc_lib/XMCLib/src/xmc_fce.c index 427b837d..54ffa477 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_fce.c +++ b/cores/xmc_lib/XMCLib/src/xmc_fce.c @@ -1,57 +1,53 @@ /** * @file xmc_fce.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-06-20: - * - Removed GetDriverVersion API - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ /********************************************************************************************************************** * HEADER FILES *********************************************************************************************************************/ -#include +#include "xmc_fce.h" #if defined (FCE) -#include +#include "xmc_scu.h" /******************************************************************************* * API IMPLEMENTATION @@ -65,7 +61,7 @@ XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine) { engine->kernel_ptr->CFG = engine->fce_cfg_update.regval; engine->kernel_ptr->CRC = engine->seedvalue; - + return XMC_FCE_STATUS_OK; } @@ -73,7 +69,7 @@ XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine) void XMC_FCE_Disable(void) { FCE->CLC |= (uint32_t)FCE_CLC_DISR_Msk; - + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE); #if defined(CLOCK_GATING_SUPPORTED) @@ -97,11 +93,11 @@ void XMC_FCE_Enable(void) /* Calculate and return the SAE J1850 CRC8 checksum */ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, const uint8_t *data, - uint32_t length, - uint8_t *result) + uint32_t length, + uint8_t *result) { XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; - + XMC_ASSERT("XMC_FCE_CalculateCRC8: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC8)); if (length == 0UL) @@ -112,7 +108,7 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, { while (0UL != length) { - engine->kernel_ptr->IR = *data; + engine->kernel_ptr->IR = (uint32_t) * data; data++; length -= 1U; } @@ -126,18 +122,17 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine, /* Calculate and return calculated CCITT CRC16 checksum */ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, const uint16_t *data, - uint32_t length, - uint16_t *result) + uint32_t length, + uint16_t *result) { XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; - + XMC_ASSERT("XMC_FCE_CalculateCRC16: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC16)); XMC_ASSERT("XMC_FCE_CalculateCRC16: Length field is empty", (length != 0)); - XMC_ASSERT("XMC_FCE_CalculateCRC16: Length is not aligned", ((length & 0x01) == 0)); - XMC_ASSERT("XMC_FCE_CalculateCRC16: Buffer is not aligned", (((uint32_t)data % 2U) == 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length is not aligned", ((length & 0x1U) == 0)); - /* Check if data and length are word aligned */ - if (((length & 0x01U) != 0U) || (((uint32_t)length % 2U) != 0U)) + /* Check length is a multiple of 2 */ + if ((length == 0) || ((length & 0x1U) != 0U)) { status = XMC_FCE_STATUS_ERROR; } @@ -145,11 +140,43 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, { while (0UL != length) { - engine->kernel_ptr->IR = *data; + engine->kernel_ptr->IR = (uint32_t) * data; data++; length -= 2U; } - + + *result = (uint16_t)engine->kernel_ptr->CRC; + } + + return status; +} + +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16Ex(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint16_t *const result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC16: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC16)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length field is empty", (length != 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC16: Length is not aligned", ((length & 0x1U) == 0)); + + /* Check length is a multiple of 2 */ + if ((length == 0) || ((length & 0x1U) != 0U)) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + const uint16_t *p = (const uint16_t *)data; + while (0UL != length) + { + engine->kernel_ptr->IR = __REV16(*p); + ++p; + length -= 2U; + } + *result = (uint16_t)engine->kernel_ptr->CRC; } @@ -159,19 +186,18 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine, /* Calculate and return the IEEE 802.3 Ethernet CRC32 checksum */ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, const uint32_t *data, - uint32_t length, - uint32_t *result) + uint32_t length, + uint32_t *result) { XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; - + XMC_ASSERT("XMC_FCE_CalculateCRC32: Wrong FCE kernel used", ((engine->kernel_ptr == XMC_FCE_CRC32_0) || - (engine->kernel_ptr == XMC_FCE_CRC32_1))); + (engine->kernel_ptr == XMC_FCE_CRC32_1))); XMC_ASSERT("XMC_FCE_CalculateCRC32: Length field is empty", (length != 0)); - XMC_ASSERT("XMC_FCE_CalculateCRC32: Length is not aligned", ((length & 0x03) == 0)); - XMC_ASSERT("XMC_FCE_CalculateCRC32: Buffer is not aligned", (((uint32_t)data % 4U) == 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length is not aligned", ((length & 0x3U) == 0)); - /* Check if data and length are word aligned */ - if (((length & 0x03U) != 0U) || (((uint32_t)length % 4U) != 0U)) + /* Check length is a multiple of 4 */ + if ((length == 0) || ((length & 0x3U) != 0U)) { status = XMC_FCE_STATUS_ERROR; } @@ -186,7 +212,41 @@ XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine, *result = engine->kernel_ptr->CRC; } - + + return status; +} + +/* Calculate and return the IEEE 802.3 Ethernet CRC32 checksum */ +XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32Ex(const XMC_FCE_t *const engine, + const uint8_t *data, + uint32_t length, + uint32_t *const result) +{ + XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK; + + XMC_ASSERT("XMC_FCE_CalculateCRC32: Wrong FCE kernel used", ((engine->kernel_ptr == XMC_FCE_CRC32_0) || + (engine->kernel_ptr == XMC_FCE_CRC32_1))); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length field is empty", (length != 0)); + XMC_ASSERT("XMC_FCE_CalculateCRC32: Length is not aligned", ((length & 0x3U) == 0)); + + /* Check length is a multiple of 4 */ + if ((length == 0) || ((length & 0x3U) != 0U)) + { + status = XMC_FCE_STATUS_ERROR; + } + else + { + const uint32_t *p = (const uint32_t *)data; + while (0UL != length) + { + engine->kernel_ptr->IR = __REV(*p); + ++p; + length -= 4U; + } + + *result = engine->kernel_ptr->CRC; + } + return status; } @@ -200,7 +260,7 @@ void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t t } /* Change endianness of 16-bit input buffer */ -void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length) +void XMC_FCE_LittleEndian16bit(uint8_t *inbuffer, uint16_t *outbuffer, uint16_t length) { uint16_t counter = 0U; uint16_t bytecounter = 0U; @@ -227,11 +287,11 @@ void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t } /* Change endianness of 32-bit input buffer */ -void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length) +void XMC_FCE_LittleEndian32bit(uint8_t *inbuffer, uint32_t *outbuffer, uint16_t length) { uint16_t counter = 0U; uint16_t bytecounter = 0U; - + if ((length & 0x03U) == 0) { for (counter = 0U; counter < (length >> 2U); counter++) diff --git a/cores/xmc_lib/XMCLib/src/xmc_gpio.c b/cores/xmc_lib/XMCLib/src/xmc_gpio.c index 7751bbf9..b8414cc6 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_gpio.c +++ b/cores/xmc_lib/XMCLib/src/xmc_gpio.c @@ -1,55 +1,51 @@ /** * @file xmc_gpio.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond + * */ /******************************************************************************* * HEADER FILES *******************************************************************************/ -#include +#include "xmc_gpio.h" /******************************************************************************* * MACROS @@ -57,7 +53,6 @@ #define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk - /******************************************************************************* * API IMPLEMENTATION *******************************************************************************/ @@ -67,8 +62,8 @@ void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_ XMC_ASSERT("XMC_GPIO_SetMode: Invalid port", XMC_GPIO_CHECK_PORT(port)); XMC_ASSERT("XMC_GPIO_SetMode: Invalid mode", XMC_GPIO_IsModeValid(mode)); - port->IOCR[(uint32_t)pin >> 2 ] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U))); - port->IOCR[(uint32_t)pin >> 2 ] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); + port->IOCR[(uint32_t)pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U))); + port->IOCR[(uint32_t)pin >> 2U] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)); } void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl) @@ -76,6 +71,6 @@ void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid port", XMC_GPIO_CHECK_PORT(port)); XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid hwctrl", XMC_GPIO_CHECK_HWCTRL(hwctrl)); - port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1 )); - port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1 ); + port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U)); + port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1U); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_hrpwm.c b/cores/xmc_lib/XMCLib/src/xmc_hrpwm.c index 4501930c..ae502f1e 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_hrpwm.c +++ b/cores/xmc_lib/XMCLib/src/xmc_hrpwm.c @@ -1,69 +1,44 @@ /** * @file xmc_hrpwm.c - * @date 2015-07-14 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-18: - * - Variable g_hrpwm_char_data[] defined in startup file is used in place of trim data macro
    - * - * 2015-05-12: - * - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input.
    - * - In XMC_HRPWM_Init() api macros used to check 'ccu_clock' frequency are renamed for readability
    - * - 80MHz HRC operation would need a minimum of 70 Mhz CCU clock.
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
    - * - Updated copyright and change history section.
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-07-06: - * - CSG trimming data assignment is corrected.
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-07-14: - * - Redundant code removed in XMC_HRPWM_HRC_ConfigSourceSelect0() and XMC_HRPWM_HRC_ConfigSourceSelect1() API's.
    - * - Enums and masks are type casted to uint32_t type. + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * @endcond + * @endcond * */ @@ -81,10 +56,10 @@ /*********************************************************************************************************************** * HEADER FILES **********************************************************************************************************************/ -#include +#include "xmc_hrpwm.h" #if defined(HRPWM0) -#include +#include "xmc_scu.h" /*********************************************************************************************************************** * MACROS @@ -114,7 +89,7 @@ /********************************************************************************************************************* * LOCAL ROUTINES ********************************************************************************************************************/ - static void XMC_HRPWM_lDelay(void); +static void XMC_HRPWM_lDelay(void); /*********************************************************************************************************************** * API IMPLEMENTATION - GENERAL @@ -143,12 +118,12 @@ XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) XMC_HRPWM_STATUS_t status; XMC_ASSERT("XMC_HRPWM_Init:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + status = XMC_HRPWM_STATUS_ERROR; - /* Apply reset to HRPWM module */ + /* Apply reset to HRPWM module */ XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0); - + /* Release reset for HRPWM module */ XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0); @@ -158,31 +133,48 @@ XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) hrpwm->GLBANA = (uint32_t)0x00004A4E; /* Initialization sequence */ hrpwm->HRBSC |= (uint32_t)HRPWM0_HRBSC_HRBE_Msk; /* Enable Bias Generator of HRPWM */ - + /* Update CSG0 memory data */ - csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS; - *csg_memory = g_hrpwm_char_data[0]; - /* write csg memory bits[14:11] with 0b1100 */ - *csg_memory &= (uint32_t)(0xFFFF87FF); - *csg_memory |= (uint32_t)(0x00006000); + if (g_hrpwm_char_data[0] != 0xffffffff) + { + csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[0]; + +#if defined(XMC_HRPWM_CSG_LOW_SPEED) + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); +#endif + } /* Update CSG1 trimming data */ - csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS; - *csg_memory = g_hrpwm_char_data[1]; - /* write csg memory bits[14:11] with 0b1100 */ - *csg_memory &= (uint32_t)(0xFFFF87FF); - *csg_memory |= (uint32_t)(0x00006000); + if (g_hrpwm_char_data[1] != 0xffffffff) + { + csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[1]; + +#if defined(XMC_HRPWM_CSG_LOW_SPEED) + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); +#endif + } /* Update CSG2 trimming data */ - csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS; - *csg_memory = g_hrpwm_char_data[2]; - /* write csg memory bits[14:11] with 0b1100 */ - *csg_memory &= (uint32_t)(0xFFFF87FF); - *csg_memory |= (uint32_t)(0x00006000); - + if (g_hrpwm_char_data[2] != 0xffffffff) + { + csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS; + *csg_memory = g_hrpwm_char_data[2]; +#if defined(XMC_HRPWM_CSG_LOW_SPEED) + /* write csg memory bits[14:11] with 0b1100 */ + *csg_memory &= (uint32_t)(0xFFFF87FF); + *csg_memory |= (uint32_t)(0x00006000); +#endif + } + /* Set CSG units to high speed mode */ hrpwm->CSGCFG = (uint32_t)(0x0000003F); - + /* Read CCU clock frequency */ ccu_clock = XMC_SCU_CLOCK_GetCcuClockFrequency(); @@ -207,14 +199,14 @@ XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) { /* Program HRC clock configuration with clock frequency information */ hrpwm->HRCCFG |= (clkc << HRPWM0_HRCCFG_CLKC_Pos); - + hrpwm->HRCCFG |= (uint32_t)HRPWM0_HRCCFG_HRCPM_Msk; /* Release HR generation from power down mode */ - + XMC_HRPWM_lDelay(); /* As per Initialization sequence */ - + /* Enable global high resolution generation / Force charge pump down */ hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk; - + XMC_HRPWM_lDelay(); /* Check High resolution ready bit field */ @@ -228,7 +220,7 @@ XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) { status = XMC_HRPWM_STATUS_ERROR; /* Clock frequency is invalid */ } - + return (status); } @@ -236,7 +228,7 @@ XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm) void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm) { XMC_ASSERT("XMC_HRPWM_EnableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + /* Enable global high resolution generation / Force charge pump down */ hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk; @@ -247,7 +239,7 @@ void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm) void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm) { XMC_ASSERT("XMC_HRPWM_DisableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + /* Enable global high resolution generation / Force charge pump down */ hrpwm->GLBANA &= ~((uint32_t)HRPWM0_GLBANA_GHREN_Msk); } @@ -261,7 +253,7 @@ XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm) XMC_HRPWM_HR_LOGIC_t status; XMC_ASSERT("XMC_HRPWM_GetHRGenReadyStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm)); - + if (hrpwm->HRGHRS) { status = XMC_HRPWM_HR_LOGIC_WORKING; @@ -278,12 +270,12 @@ XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm) **********************************************************************************************************************/ /* Initialize HRPWM HRC channel */ void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config) -{ +{ XMC_ASSERT("XMC_HRPWM_HRC_Init:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); - + /* Setting of HRCy mode configuration */ hrc->GC = config->gc; - + /* Passive level configuration */ hrc->PL = config->psl; } @@ -294,7 +286,7 @@ void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP uint32_t reg; XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect0:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); - + /* HRC mode config for source selector 0 */ hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM0_Msk); hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM0_Pos; @@ -303,8 +295,8 @@ void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP * HRCy global control selection (HRCyGSEL) ****************************************************************************/ reg = 0U; - - if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + + if (config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) { reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C0SS_Pos; reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S0M_Pos; /* comparator output controls the set config */ @@ -324,9 +316,9 @@ void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP /***************************************************************************** * HRCy timer selection (HRCyTSEL) ****************************************************************************/ - reg = (uint32_t)config->timer_sel; + reg = (uint32_t)config->timer_sel << HRPWM0_HRC_TSEL_TSEL0_Pos; reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS0E_Pos; - hrc->TSEL &= (uint32_t)0xFFFEFFF8; + hrc->TSEL &= (uint32_t)~(HRPWM0_HRC_TSEL_TSEL0_Msk | HRPWM0_HRC_TSEL_TS0E_Msk); hrc->TSEL |= reg; } @@ -336,7 +328,7 @@ void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP uint32_t reg; XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc)); - + /* HRC mode config for source selector 1 */ hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM1_Msk); hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM1_Pos; @@ -345,8 +337,8 @@ void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP * HRCy global control selection (HRCyGSEL) ****************************************************************************/ reg = 0U; - - if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) + + if (config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) { reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C1SS_Pos; reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S1M_Pos; /* comparator output controls the set config*/ @@ -366,9 +358,9 @@ void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP /***************************************************************************** * HRCy timer selection (HRCyTSEL) ****************************************************************************/ - reg = (uint32_t)config->timer_sel; + reg = (uint32_t)config->timer_sel << HRPWM0_HRC_TSEL_TSEL1_Pos; reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS1E_Pos; - hrc->TSEL &= (uint32_t)0xFFFDFFC7; + hrc->TSEL &= (uint32_t)~(HRPWM0_HRC_TSEL_TSEL1_Msk | HRPWM0_HRC_TSEL_TS1E_Msk); hrc->TSEL |= reg; } @@ -376,7 +368,7 @@ void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRP * API IMPLEMENTATION - HRPWM CSG GLOBAL **********************************************************************************************************************/ /* No api's for CSG GLOBAL in xmc_hrpwm.c file */ - + /*********************************************************************************************************************** * API IMPLEMENTATION - HRPWM CSG SLICE **********************************************************************************************************************/ @@ -386,19 +378,19 @@ void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t uint32_t reg; XMC_ASSERT("XMC_HRPWM_CSG_Init:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + /* Passive level configuration */ csg->PLC = config->cmp_config.plc; - + /* DAC Reference values */ csg->SDSV1 = config->dac_config.dac_dsv1; csg->DSV2 = config->dac_config.dac_dsv2; /* Pulse Swallow value */ csg->SPC = config->sgen_config.pulse_swallow_val; - + /* Slope generation control (CSGySC) */ - if(config->sgen_config.ctrl_mode != (uint32_t) XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC) + if (config->sgen_config.ctrl_mode != (uint32_t) XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC) { /* Dynamic Slope Generation */ csg->SC = config->sgen_config.sc; @@ -422,7 +414,7 @@ void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input) { XMC_ASSERT("XMC_HRPWM_CSG_SetCMPInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + if (input == XMC_HRPWM_CSG_CMP_INPUT_CINA) { /* Inverting comparator input connected to CINA */ @@ -430,7 +422,7 @@ void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_C } else { - /* Inverting comparator input connected to CINB */ + /* Inverting comparator input connected to CINB */ csg->CC |= (uint32_t)HRPWM0_CSG_CC_IMCS_Msk; } } @@ -439,11 +431,11 @@ void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_C void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) { uint32_t reg; - + XMC_ASSERT("XMC_HRPWM_CSG_SelBlankingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + reg = csg->CC; - + if ((reg & HRPWM0_CSG_CC_EBE_Msk) != 0U) /* external blanking trigger enabled? */ { reg &= ~((uint32_t)HRPWM0_CSG_CC_IBS_Msk); @@ -478,7 +470,7 @@ void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_ void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) { XMC_ASSERT("XMC_HRPWM_CSG_StartSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STRIS_Msk); csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STRIS_Pos; csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STRES_Msk); @@ -489,7 +481,7 @@ void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRP void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) { XMC_ASSERT("XMC_HRPWM_CSG_StopSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STPIS_Msk); csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STPIS_Pos; csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STPES_Msk); @@ -500,7 +492,7 @@ void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPW void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) { XMC_ASSERT("XMC_HRPWM_CSG_TriggerDACConvConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_TRGIS_Msk); csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_TRGIS_Pos; csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_TRGES_Msk); @@ -511,7 +503,7 @@ void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HR void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) { XMC_ASSERT("XMC_HRPWM_CSG_TriggerShadowXferConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STIS_Msk); csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STIS_Pos; csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STES_Msk); @@ -522,7 +514,7 @@ void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config) { XMC_ASSERT("XMC_HRPWM_CSG_DACRefValSwitchingConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SVIS_Msk); csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_SVIS_Pos; csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_SVLS_Msk); @@ -533,17 +525,17 @@ void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XM void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk) { XMC_ASSERT("XMC_HRPWM_CSG_SelSlopeGenClkInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SCS_Msk); csg->DCI |= ((uint32_t)input_clk) << HRPWM0_CSG0_DCI_SCS_Pos; } /* Set the service request interrupt node */ void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event, - const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr) + const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr) { XMC_ASSERT("XMC_HRPWM_CSG_SetSRNode:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg)); - + switch (event) { case (XMC_HRPWM_CSG_IRQ_ID_VLS1): diff --git a/cores/xmc_lib/XMCLib/src/xmc_i2c.c b/cores/xmc_lib/XMCLib/src/xmc_i2c.c index 3609a4c5..bda41992 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_i2c.c +++ b/cores/xmc_lib/XMCLib/src/xmc_i2c.c @@ -1,67 +1,50 @@ /** * @file xmc_i2c.c - * @date 2015-10-02 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-05-20: - - Modified XMC_I2C_CH_Stop() API for not setting to IDLE the channel if it is busy
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-08-14: - * - updated the XMC_I2C_CH_SetBaudrate API to support dynamic change from 400K to low frequencies
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-09-01: - * - Modified XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() for supporting multiple events configuration
    + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2015-10-02: - * - Fixed 10bit addressing - * - * @endcond + * @endcond * */ /********************************************************************************************************************* * HEADER FILES *********************************************************************************************************************/ -#include +#include "xmc_i2c.h" /********************************************************************************************************************* * MACROS @@ -105,10 +88,10 @@ typedef enum XMC_I2C_CH_CLOCK_OVERSAMPLING * API IMPLEMENTATION *********************************************************************************************************************/ /* Initializes the USIC channel by setting the data format, slave address, baudrate, transfer buffer */ -void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config) +void XMC_I2C_CH_InitEx(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config, bool init_brg) { XMC_USIC_CH_Enable(channel); - + /* Data format configuration */ channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision mode */ ((uint32_t)WORDLENGTH << (uint32_t)USIC_CH_SCTR_WLE_Pos) | /* 8 data bits */ @@ -117,8 +100,13 @@ void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *co USIC_CH_SCTR_PDL_Msk; /* Passive Data Level */ XMC_I2C_CH_SetSlaveAddress(channel, config->address); - (void)XMC_I2C_CH_SetBaudrate(channel, config->baudrate); - + + if (init_brg) + { + (void)XMC_I2C_CH_SetBaudrateEx(channel, config->baudrate, config->normal_divider_mode); + } + + /* Enable transfer buffer */ channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk; @@ -128,23 +116,26 @@ void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *co /* Disable parity generation */ channel->CCR = 0x0U; } + /* Sets the slave address */ void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address) { if ((address & XMC_I2C_10BIT_ADDR_MASK) == XMC_I2C_10BIT_ADDR_GROUP) { - channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U); + channel->PCR_IICMode = (channel->PCR_IICMode & (uint32_t)~USIC_CH_PCR_IICMode_SLAD_Msk) | + (address & 0x00ffU) | ((address << 1) & 0xfe00U); } else { - channel->PCR_IICMode = ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos; + channel->PCR_IICMode = (channel->PCR_IICMode & (uint32_t)~USIC_CH_PCR_IICMode_SLAD_Msk) | + ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos; } } /* Read the slave address */ uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel) { uint32_t address = channel->PCR_IICMode & (uint32_t)USIC_CH_PCR_IICMode_SLAD_Msk; - + if ((address & 0xffU) == 0U) { address = address >> XMC_I2C_7BIT_ADDR_Pos; @@ -153,19 +144,20 @@ uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel) { address = (address & 0xffU) | ((address >> 1) & 0x0300U); } - + return (uint16_t)address; } + /* Sets the baudrate and oversampling based on standard speed or fast speed */ XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate) { XMC_I2C_CH_STATUS_t status; - + status = XMC_I2C_CH_STATUS_ERROR; - + if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD) { - channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk; + channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk; if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD) == XMC_USIC_CH_STATUS_OK) { status = XMC_I2C_CH_STATUS_OK; @@ -179,18 +171,58 @@ XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_ status = XMC_I2C_CH_STATUS_OK; } } - else + else { status = XMC_I2C_CH_STATUS_ERROR; } - + return status; } + +/* Sets the baudrate and oversampling based on standard speed or fast speed */ +XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, bool normal_divider_mode) +{ + XMC_USIC_CH_STATUS_t status; + + if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD) + { + channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk; + if (normal_divider_mode) + { + status = XMC_USIC_CH_SetBaudrateEx(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD); + } + else + { + /* Fractional divider mode */ + status = XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD); + } + } + else if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_FAST) + { + channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_STIM_Msk; + if (normal_divider_mode) + { + status = XMC_USIC_CH_SetBaudrateEx(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST); + } + else + { + /* Fractional divider mode */ + status = XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST); + } + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return (XMC_I2C_CH_STATUS_t)status; +} + /* Sends master start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */ void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command) { uint32_t temp; - + temp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_START; if (command == XMC_I2C_CH_CMD_READ) { @@ -201,7 +233,7 @@ void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, c if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) { while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) - { + { /* check TDV, wait until TBUF is ready */ } @@ -227,9 +259,9 @@ void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) - { + { while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) - { + { /* check TDV, wait until TBUF is ready */ } @@ -271,9 +303,9 @@ void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) { /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) - { + { while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) - { + { /* check TDV, wait until TBUF is ready */ } @@ -293,11 +325,11 @@ void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) { /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) - { - while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) - { + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { /* check TDV, wait until TBUF is ready */ - } + } /* clear PSR_TBIF */ XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); @@ -313,11 +345,11 @@ void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data) /* Sends master receive ack command to IN/TBUF register based on FIFO/non-FIFO modes. */ void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel) { -/* Check FIFO size */ + /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) - { - while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) - { + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { /* check TDV, wait until TBUF is ready */ } @@ -337,9 +369,9 @@ void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel) { /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) - { - while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) - { + { + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + { /* check TDV, wait until TBUF is ready */ } @@ -348,7 +380,7 @@ void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel) channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK; } - else + else { channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK; } @@ -377,7 +409,7 @@ XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel) { XMC_I2C_CH_STATUS_t status = XMC_I2C_CH_STATUS_OK; - if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + if (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { status = XMC_I2C_CH_STATUS_BUSY; } @@ -391,12 +423,12 @@ XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel) void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR |= (event&0x1fc00U); + channel->CCR |= (event & 0x1fc00U); channel->PCR_IICMode |= ((event) & 0x41fc0000U); } void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->CCR &= (uint32_t)~(event & 0x1fc00U); channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_i2s.c b/cores/xmc_lib/XMCLib/src/xmc_i2s.c index 17e66de1..f6d85b06 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_i2s.c +++ b/cores/xmc_lib/XMCLib/src/xmc_i2s.c @@ -1,63 +1,41 @@ /** * @file xmc_i2s.c - * @date 2015-06-30 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* - * - * Change History - * -------------- - * - * 2015-08-21: - * - Initial
    - * - * 2015-09-01: - * - Modified XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() for supporting multiple events configuration
    - * - * 2015-09-14: - * - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length. - * - Removed parity configuration
    - * - * 2015-09-28: - * - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs
    - * - * 2015-11-04: - * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API
    - * - * 2016-06-30: - * - Modified XMC_I2S_CH_Init: - * + change default passive level to 0 - * + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length. - * - Modified XMC_I2S_CH_SetBaudrate: - * + Optional Master clock output signal generated with a fixed phase relation to SCLK. + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -71,8 +49,8 @@ * HEADER FILES ********************************************************************************************************************/ -#include -#include +#include "xmc_scu.h" +#include "xmc_i2s.h" /********************************************************************************************************************* * MACROS @@ -85,21 +63,21 @@ ********************************************************************************************************************/ /* Initializes the selected I2S channel with the config structure. */ -void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config) +void XMC_I2S_CH_InitEx(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config, bool init_brg) { - XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(config->data_delayed_sclk_periods > 0U) && - (config->data_delayed_sclk_periods < config->frame_length)); + XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid", (config->data_delayed_sclk_periods > 0U) && + (config->data_delayed_sclk_periods < config->frame_length)); XMC_USIC_CH_Enable(channel); - if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) + if ((config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) && init_brg) { /* Configure baud rate */ - (void)XMC_I2S_CH_SetBaudrate(channel, config->baudrate); + (void)XMC_I2S_CH_SetBaudrateEx(channel, config->baudrate, config->normal_divider_mode); } /* Configuration of USIC Shift Control */ /* Transmission Mode (TRM) = 1 */ channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) | - (uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) | + (uint32_t)((config->frame_length - 1U) << USIC_CH_SCTR_FLE_Pos) | (uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) | USIC_CH_SCTR_SDIR_Msk; @@ -108,14 +86,14 @@ void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *co /* TBUF Data Single Shot Mode (TDSSM) = 1 */ /* WA mode enabled(WAMD) = 1 */ channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk | - USIC_CH_TCSR_SELMD_Msk | - USIC_CH_TCSR_FLEMD_Msk | - USIC_CH_TCSR_HPCMD_Msk))) | - USIC_CH_TCSR_WAMD_Msk | - (0x01UL << USIC_CH_TCSR_TDEN_Pos) | - USIC_CH_TCSR_TDSSM_Msk); - - if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) + USIC_CH_TCSR_SELMD_Msk | + USIC_CH_TCSR_FLEMD_Msk | + USIC_CH_TCSR_HPCMD_Msk))) | + USIC_CH_TCSR_WAMD_Msk | + (0x01UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk); + + if (config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER) { /* Configuration of Protocol Control Register */ channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk; @@ -123,7 +101,7 @@ void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *co /* Configuration of Protocol Control Register */ channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk | - (uint32_t)config->wa_inversion) | + (uint32_t)config->wa_inversion) | ((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos); XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length); @@ -144,7 +122,7 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const u if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK) { channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) | - (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) | + (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) | USIC_CH_BRG_PPPEN_Msk; status = XMC_I2S_CH_STATUS_OK; @@ -154,7 +132,37 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const u return status; } -void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length) +XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode) +{ + XMC_USIC_CH_STATUS_t status; + + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) + { + if (normal_divider_mode) + { + status = XMC_USIC_CH_SetBaudrateEx(channel, rate, XMC_I2S_CH_OVERSAMPLING); + } + else + { + status = XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING); + } + + if (status == XMC_USIC_CH_STATUS_OK) + { + channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) | + (0x2UL << USIC_CH_BRG_CTQSEL_Pos)) | + USIC_CH_BRG_PPPEN_Msk; + } + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return (XMC_I2S_CH_STATUS_t)status; +} + +void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel, uint32_t sclk_cycles_system_word_length) { uint32_t sclk_cycles_system_word_length_temp; uint8_t dctq_temp; @@ -163,15 +171,15 @@ void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_c uint8_t pctq = 1U; uint8_t best_error = 64U; uint8_t error; - XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U)); + XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid", (sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U)); - for (dctq_temp =1U; dctq_temp < 33U ; dctq_temp++) + for (dctq_temp = 1U; dctq_temp < 33U ; dctq_temp++) { - for (pctq_temp =1U; pctq_temp < 5U ; pctq_temp++) + for (pctq_temp = 1U; pctq_temp < 5U ; pctq_temp++) { sclk_cycles_system_word_length_temp = ((uint32_t)dctq_temp) * ((uint32_t)pctq_temp); - if(sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length) + if (sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length) { dctq = dctq_temp; pctq = pctq_temp; @@ -186,18 +194,18 @@ void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_c error = (uint8_t)(sclk_cycles_system_word_length - sclk_cycles_system_word_length_temp); } - if(error < best_error) + if (error < best_error) { - best_error = error; - dctq = dctq_temp; - pctq = pctq_temp; + best_error = error; + dctq = dctq_temp; + pctq = pctq_temp; } } } - channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk | - USIC_CH_BRG_PCTQ_Msk))) | - (uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq- 1U) << USIC_CH_BRG_DCTQ_Pos) | - (uint32_t)((uint32_t)((uint32_t)pctq- 1U) << USIC_CH_BRG_PCTQ_Pos))); + channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PCTQ_Msk))) | + (uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq - 1U) << USIC_CH_BRG_DCTQ_Pos) | + (uint32_t)((uint32_t)((uint32_t)pctq - 1U) << USIC_CH_BRG_PCTQ_Pos))); } /* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */ @@ -206,7 +214,7 @@ void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, cons /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) { - while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { } @@ -242,7 +250,7 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel) { XMC_I2S_CH_STATUS_t status = XMC_I2S_CH_STATUS_OK; - if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + if (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { status = XMC_I2S_CH_STATUS_BUSY; } @@ -257,12 +265,12 @@ XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel) void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR |= (event&0x1fc00U); + channel->CCR |= (event & 0x1fc00U); channel->PCR_IISMode |= ((event >> 2U) & 0x8070U); } void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->CCR &= (uint32_t)~(event & 0x1fc00U); channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_ledts.c b/cores/xmc_lib/XMCLib/src/xmc_ledts.c index 9ba25d9c..8a444c7a 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_ledts.c +++ b/cores/xmc_lib/XMCLib/src/xmc_ledts.c @@ -1,55 +1,41 @@ /** * @file xmc_ledts.c - * @date 2017-02-25 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
    - * - New API added: XMC_LEDTS_SetActivePADNo()
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2017-02-25: - * - XMC_LEDTS_InitGlobal() fixed compilation warnings + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * Detailed description of file:
    - * APIs for the functional blocks of LEDTS have been defined:
    - * -- GLOBAL (APIs prefixed with LEDTS_GLOBAL_)
    - * -- Clock configuration, Function/Event configuration, Interrupt configuration + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -58,7 +44,7 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_ledts.h" #if defined(LEDTS0) #include "xmc_scu.h" @@ -99,20 +85,20 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDT if (ledts == XMC_LEDTS0) { #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS0); + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS0); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS0); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS0); #endif } #if defined(LEDTS1) else if (ledts == XMC_LEDTS1) { #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS1); + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS1); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS1); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS1); #endif } #endif @@ -120,10 +106,10 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDT else if (ledts == XMC_LEDTS2) { #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS2); + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS2); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS2); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS2); #endif } #endif @@ -132,7 +118,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDT XMC_ASSERT("XMC_LEDTS_InitGlobal:Invalid Module Pointer", 0); } - if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + if ((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) { return XMC_LEDTS_STATUS_RUNNING; } @@ -150,7 +136,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_L XMC_ASSERT("XMC_LEDTS_LED_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); XMC_ASSERT("XMC_LEDTS_LED_Init:Null Pointer", (config != (XMC_LEDTS_LED_CONFIG_t *)NULL)); - if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + if ((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) { return XMC_LEDTS_STATUS_RUNNING; } @@ -174,13 +160,13 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LED XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_BASIC_t *)NULL)); - if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + if ((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) { return XMC_LEDTS_STATUS_RUNNING; } reg = ~(LEDTS_FNCTL_ACCCNT_Msk | LEDTS_FNCTL_TSCCMP_Msk | LEDTS_FNCTL_TSCTRR_Msk | LEDTS_FNCTL_TSCTRSAT_Msk | - LEDTS_FNCTL_NR_TSIN_Msk); + LEDTS_FNCTL_NR_TSIN_Msk); ledts->FNCTL &= (reg); ledts->FNCTL |= (config->fnctl); @@ -200,7 +186,7 @@ XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_ADVANCED_t *)NULL)); - if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) + if ((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING) { return XMC_LEDTS_STATUS_RUNNING; } @@ -223,7 +209,7 @@ void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler) { XMC_ASSERT("XMC_LEDTS_Start_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); - ledts->GLOBCTL |= prescaler<<16U; + ledts->GLOBCTL |= prescaler << 16U; } /** @@ -300,10 +286,10 @@ void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUM XMC_ASSERT("XMC_LEDTS_Set_Column_Brightness:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); - reg = ledts->LDCMP[reg_index]; - reg &= (~(0xff << bit_shift_count)); - reg |= brightness << bit_shift_count; - ledts->LDCMP[reg_index] = reg; + reg = ledts->LDCMP[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= brightness << bit_shift_count; + ledts->LDCMP[reg_index] = reg; } /** @@ -373,10 +359,10 @@ void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_T XMC_ASSERT("XMC_LEDTS_Set_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts)); - reg = ledts->TSCMP[reg_index]; - reg &= (~(0xff << bit_shift_count)); - reg |= size << bit_shift_count; - ledts->TSCMP[reg_index] = reg; + reg = ledts->TSCMP[reg_index]; + reg &= (~(0xff << bit_shift_count)); + reg |= size << bit_shift_count; + ledts->TSCMP[reg_index] = reg; } #endif /* LEDTS0 */ diff --git a/cores/xmc_lib/XMCLib/src/xmc_math.c b/cores/xmc_lib/XMCLib/src/xmc_math.c index 3e7adc78..98d5b815 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_math.c +++ b/cores/xmc_lib/XMCLib/src/xmc_math.c @@ -1,70 +1,51 @@ /** * @file xmc_math.c - * @date 2017-04-20 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
    - * - Updated copyright and change history section. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-09-23: - * - Added SQRT functions + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-10-08: - * - Return values for sin(), cos(), sinh(), cosh(), arctan() are corrected. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2017-04-20: - * - Foward declaration of __aeabi_* to fix link time optimization (-flto) compilation errors - * * @endcond * */ /** * - * @brief MATH driver - API implementation for XMC13 family MATH libraries.
    - * + * @brief MATH driver - API implementation for XMC13/14 family MATH libraries.
    + * * Detailed description of file
    * APIs provided in this file cover the following functional blocks of MATH:
    * @@ -73,7 +54,7 @@ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_math.h" #if defined (MATH) /********************************************************************************************************************* @@ -107,6 +88,18 @@ /********************************************************************************************************************* * API IMPLEMENTATION - Utility functions ********************************************************************************************************************/ +__attribute__((always_inline)) __STATIC_INLINE uint32_t critical_section_enter(void) +{ + uint32_t status; + status = __get_PRIMASK(); + __disable_irq (); + return status; +} + +__attribute__((always_inline)) __STATIC_INLINE void critical_section_exit(uint32_t status) +{ + __set_PRIMASK(status); +} /* Utility function to check if the DIV unit is busy */ bool XMC_MATH_DIV_IsBusy(void) @@ -114,11 +107,11 @@ bool XMC_MATH_DIV_IsBusy(void) bool status; if (MATH->DIVST & MATH_DIVST_BSY_Msk) { - status = true; /* DIV unit is busy running a division operation */ + status = true; /* DIV unit is busy running a division operation */ } else { - status = false; /* DIV unit is idle */ + status = false; /* DIV unit is idle */ } return (status); @@ -130,11 +123,11 @@ bool XMC_MATH_CORDIC_IsBusy(void) bool status; if (MATH->STATC & MATH_STATC_BSY_Msk) { - status = true; /* CORDIC unit is busy running an operation */ + status = true; /* CORDIC unit is busy running an operation */ } else { - status = false; /* CORDIC unit is idle */ + status = false; /* CORDIC unit is idle */ } return (status); @@ -158,10 +151,17 @@ bool XMC_MATH_GetEventStatus(const XMC_MATH_EVENT_t event) #ifndef XMC_MATH_DISABLE_DIV_ABI /* Forward prototypes. */ +#if defined ( __GNUC__ ) && !defined( __ARMCC_VERSION ) uint32_t __aeabi_uidiv(uint32_t dividend, uint32_t divisor) __attribute__((externally_visible)); int32_t __aeabi_idiv(int32_t dividend, int32_t divisor) __attribute__((externally_visible)); uint64_t __aeabi_uidivmod(uint32_t dividend, uint32_t divisor) __attribute__((externally_visible)); int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor) __attribute__((externally_visible)); +#else +uint32_t __aeabi_uidiv(uint32_t dividend, uint32_t divisor); +int32_t __aeabi_idiv(int32_t dividend, int32_t divisor); +uint64_t __aeabi_uidivmod(uint32_t dividend, uint32_t divisor); +int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor); +#endif /*********************************************************************************************************************** * API IMPLEMENTATION - aeabi routines @@ -169,49 +169,77 @@ int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor) __attribute__((extern /* This function performs unsigned integer division */ uint32_t __aeabi_uidiv(uint32_t dividend, uint32_t divisor) { + uint32_t result; + uint32_t ics; + ics = critical_section_enter(); + MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION; MATH->DVD = dividend; MATH->DVS = divisor; - return ((uint32_t) MATH->QUOT); + result = MATH->QUOT; + + critical_section_exit(ics); + + return result; } /* This function performs signed integer division */ int32_t __aeabi_idiv(int32_t dividend, int32_t divisor) { + uint32_t result; + uint32_t ics; + ics = critical_section_enter(); + MATH->DIVCON = XMC_MATH_SIGNED_DIVISION; MATH->DVD = dividend; MATH->DVS = divisor; - return ((int32_t) MATH->QUOT); + result = MATH->QUOT; + + critical_section_exit(ics); + + return result; } /* This function performs unsigned integer division modulo */ uint64_t __aeabi_uidivmod(uint32_t dividend, uint32_t divisor) { uint64_t remainder; + uint64_t quot; + uint32_t ics; + ics = critical_section_enter(); MATH->DIVCON = XMC_MATH_UNSIGNED_DIVISION; MATH->DVD = dividend; MATH->DVS = divisor; - remainder = ((uint64_t) MATH->RMD) << 32U; - return (remainder | MATH->QUOT); + remainder = (uint64_t)MATH->RMD; + quot = (uint64_t)MATH->QUOT; + + critical_section_exit(ics); + + return ((remainder << 32) | quot); } /* This function performs signed integer division modulo */ int64_t __aeabi_idivmod(int32_t dividend, int32_t divisor) { uint64_t remainder; - uint64_t result; + uint64_t quot; + uint32_t ics; + ics = critical_section_enter(); MATH->DIVCON = XMC_MATH_SIGNED_DIVISION; MATH->DVD = dividend; MATH->DVS = divisor; - remainder = ((uint64_t) MATH->RMD) << 32U; - result = (remainder | MATH->QUOT); - return ((int64_t) result); + remainder = (uint64_t)MATH->RMD;; + quot = (uint64_t)MATH->QUOT; + + critical_section_exit(ics); + + return ((int64_t)((remainder << 32) | quot)); } #endif diff --git a/cores/xmc_lib/XMCLib/src/xmc_pau.c b/cores/xmc_lib/XMCLib/src/xmc_pau.c index bd123881..09179cd0 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_pau.c +++ b/cores/xmc_lib/XMCLib/src/xmc_pau.c @@ -1,47 +1,43 @@ /** * @file xmc_pau.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-06-20: - * - Removed GetDriverVersion API - * @endcond + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -68,7 +64,7 @@ void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral) { uint32_t reg_num; - + reg_num = ((uint32_t)peripheral & 0xf0000000U) >> 28U; XMC_PAU->PRIVDIS[reg_num] &= (uint32_t)~((uint32_t)peripheral & 0x0fffffffUL); } @@ -85,7 +81,7 @@ void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral) } /* - * Check if peripheral access is enabled + * Check if peripheral access is enabled */ bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral) { diff --git a/cores/xmc_lib/XMCLib/src/xmc_posif.c b/cores/xmc_lib/XMCLib/src/xmc_posif.c index 9088bd48..8413e70d 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_posif.c +++ b/cores/xmc_lib/XMCLib/src/xmc_posif.c @@ -1,75 +1,54 @@ /** * @file xmc_posif.c - * @date 2017-02-25 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-18: - * - Initial version - * - * 2015-02-20: - * - Driver description added
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-04-30: - * - XMC_POSIF_Enable and XMC_POSIF_Disable APIs updated for POSIF1 peripheral check
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-06-19: - * - Removed GetDriverVersion API
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2017-02-25: - * - XMC_POSIF_Enable() and XMC_POSIF_Disable() fixed compilation warnings + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * @endcond + * @endcond * */ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_posif.h" /* POSIF is not available on XMC1100 and XMC1200 */ #if defined(POSIF0) -#include +#include "xmc_scu.h" /********************************************************************************************************************* * MACROS @@ -86,11 +65,11 @@ __STATIC_INLINE bool XMC_POSIF_IsPeripheralValid(const XMC_POSIF_t *const periph bool tmp; tmp = (peripheral == POSIF0); -#if defined(POSIF1) +#if defined(POSIF1) tmp |= (peripheral == POSIF1); #endif - return tmp; + return tmp; } #endif /********************************************************************************************************************* @@ -110,17 +89,17 @@ void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); #endif } #if defined(POSIF1) else if (peripheral == POSIF1) { #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); #endif } #endif @@ -136,20 +115,20 @@ void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral) if (peripheral == POSIF0) { #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0); #endif #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0); #endif } #if defined(POSIF1) else if (peripheral == POSIF1) { #if defined(PERIPHERAL_RESET_SUPPORTED) - XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); + XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1); #endif #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1); #endif } #endif @@ -176,10 +155,10 @@ void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t *con } /* API to initialize hall sensor interface */ -XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config) +XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t *const config) { XMC_POSIF_STATUS_t retval; - + XMC_ASSERT("XMC_POSIF_HSC_Init:Invalid module pointer\n", XMC_POSIF_IsPeripheralValid(peripheral)); XMC_ASSERT("XMC_POSIF_HSC_Init:NULL Pointer\n", (config != (XMC_POSIF_HSC_CONFIG_t *)NULL) ); @@ -196,11 +175,11 @@ XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_P } /* API to initialize quadrature decoder interface */ -XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config) +XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t *const config) { uint8_t reg; XMC_POSIF_STATUS_t retval; - + XMC_ASSERT("XMC_POSIF_QD_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); XMC_ASSERT("XMC_POSIF_QD_Init:NULL Pointer", (config != (XMC_POSIF_QD_CONFIG_t *)NULL) ); @@ -216,14 +195,14 @@ XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_PO { retval = XMC_POSIF_STATUS_ERROR; } - + return retval; } /* API to initialize multi-channel mode. * This is used in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode */ -XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config) +XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t *const config) { XMC_POSIF_STATUS_t retval; @@ -244,7 +223,7 @@ XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_P /* API to configure input source */ void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0, - const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2) + const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2) { uint32_t reg; XMC_ASSERT("XMC_POSIF_SelectInputSource:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); @@ -253,8 +232,8 @@ void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input2", (input2 < XMC_POSIF_INSEL_MAX)); reg = (uint32_t)((((uint32_t)input0 << POSIF_PCONF_INSEL0_Pos) & (uint32_t)POSIF_PCONF_INSEL0_Msk) | - (((uint32_t)input1 << POSIF_PCONF_INSEL1_Pos) & (uint32_t)POSIF_PCONF_INSEL1_Msk) | - (((uint32_t)input2 << POSIF_PCONF_INSEL2_Pos) & (uint32_t)POSIF_PCONF_INSEL2_Msk)); + (((uint32_t)input1 << POSIF_PCONF_INSEL1_Pos) & (uint32_t)POSIF_PCONF_INSEL1_Msk) | + (((uint32_t)input2 << POSIF_PCONF_INSEL2_Pos) & (uint32_t)POSIF_PCONF_INSEL2_Msk)); peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)XMC_POSIF_PCONF_INSEL_Msk) | reg); } @@ -262,11 +241,11 @@ void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr) { uint32_t reg; - + XMC_ASSERT("XMC_POSIF_SetInterruptNode:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral)); XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong IRQ event", (event <= XMC_POSIF_IRQ_EVENT_PCLK) ); XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong SR ID", (sr <= XMC_POSIF_SR_ID_1) ); - + reg = peripheral->PFLGE; reg &= ~((uint32_t)1 << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos)); reg |= (uint32_t)sr << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos); diff --git a/cores/xmc_lib/XMCLib/src/xmc_prng.c b/cores/xmc_lib/XMCLib/src/xmc_prng.c index 9438fab9..82ccc46f 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_prng.c +++ b/cores/xmc_lib/XMCLib/src/xmc_prng.c @@ -1,52 +1,46 @@ /** * @file xmc_prng.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - Removed GetDriverVersion API
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20 - * - Removed definition of GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ - + #include "xmc_prng.h" #if defined (PRNG) @@ -54,7 +48,7 @@ /********************************************************************************************************************* * API IMPLEMENTATION *********************************************************************************************************************/ - + /* * Initializes the PRNG peripheral with the settings in the * initialization structure XMC_PRNG_INIT_t @@ -64,7 +58,7 @@ XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng) volatile uint16_t read_warm_up; uint16_t reg_val, iter; XMC_PRNG_INIT_STATUS_t status = XMC_PRNG_INITIALIZED; - + XMC_ASSERT("XMC_PRNG_Init:Null Pointer", (prng != (XMC_PRNG_INIT_t *)NULL)); /* Configure block size for key loading mode */ @@ -79,7 +73,7 @@ XMC_PRNG_INIT_STATUS_t XMC_PRNG_Init(const XMC_PRNG_INIT_t *prng) XMC_PRNG_LoadKeyWords(prng->key_words[iter]); while (PRNG_CHK_RDV_Msk != XMC_PRNG_CheckValidStatus()); } - + XMC_PRNG_EnableStreamingMode(); /* Warm up phase: Read and discard 64 bits */ diff --git a/cores/xmc_lib/XMCLib/src/xmc_rtc.c b/cores/xmc_lib/XMCLib/src/xmc_rtc.c index 89f040e0..8b505274 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_rtc.c +++ b/cores/xmc_lib/XMCLib/src/xmc_rtc.c @@ -1,51 +1,43 @@ /** * @file xmc_rtc.c - * @date 2015-05-19 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-06-20: - * - Removed GetDriverVersion API - * - * 2016-05-19: - * - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat() + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -58,7 +50,7 @@ /********************************************************************************************************************* * HEADER FILES *********************************************************************************************************************/ - + #include "xmc_scu.h" #include "xmc_rtc.h" @@ -66,9 +58,9 @@ * MACROS *********************************************************************************************************************/ -#define XMC_RTC_MAXSECONDS (59U) /**< RTC time : Maximum seconds */ -#define XMC_RTC_MAXMINUTES (59U) /**< RTC time : Maximum minutes */ -#define XMC_RTC_MAXHOURS (23U) /**< RTC time : Maximum hours */ +#define XMC_RTC_MAXSECONDS (60U) /**< RTC time : Maximum seconds */ +#define XMC_RTC_MAXMINUTES (60U) /**< RTC time : Maximum minutes */ +#define XMC_RTC_MAXHOURS (24U) /**< RTC time : Maximum hours */ #define XMC_RTC_MAXDAYS (31U) /**< RTC time : Maximum days */ #define XMC_RTC_MAXDAYSOFWEEK (7U) /**< RTC time : Maximum days of week */ #define XMC_RTC_MAXMONTH (12U) /**< RTC time : Maximum month */ @@ -92,7 +84,7 @@ */ void XMC_RTC_Start(void) { - while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } @@ -104,7 +96,7 @@ void XMC_RTC_Start(void) */ void XMC_RTC_Stop(void) { - while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } @@ -117,8 +109,8 @@ void XMC_RTC_Stop(void) void XMC_RTC_SetPrescaler(uint16_t prescaler) { XMC_ASSERT("XMC_RTC_SetPrescaler:Wrong prescaler value", (prescaler < XMC_RTC_MAXPRESCALER)); - - while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U) { /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ } @@ -134,32 +126,31 @@ void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const time) XMC_ASSERT("XMC_RTC_SetTime:Wrong seconds value", ((uint32_t)time->seconds < XMC_RTC_MAXSECONDS)); XMC_ASSERT("XMC_RTC_SetTime:Wrong minutes value", ((uint32_t)time->minutes < XMC_RTC_MAXMINUTES)); XMC_ASSERT("XMC_RTC_SetTime:Wrong hours value", ((uint32_t)time->hours < XMC_RTC_MAXHOURS)); - XMC_ASSERT("XMC_RTC_SetTime:Wrong month day value", ((uint32_t)time->days < XMC_RTC_MAXDAYS)); XMC_ASSERT("XMC_RTC_SetTime:Wrong week day value", ((uint32_t)time->daysofweek < XMC_RTC_MAXDAYSOFWEEK)); XMC_ASSERT("XMC_RTC_SetTime:Wrong month value", ((uint32_t)time->month < XMC_RTC_MAXMONTH)); XMC_ASSERT("XMC_RTC_SetTime:Wrong year value", ((uint32_t)time->year < XMC_RTC_MAXYEAR)); - #if (XMC_RTC_INIT_SEQUENCE == 1U) - while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - RTC->TIM0 = time->raw0; - - while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - RTC->TIM1 = time->raw1; - #endif - #if (XMC_RTC_INIT_SEQUENCE == 0U) - while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - RTC->TIM0 = time->raw0; - RTC->TIM1 = time->raw1; ; - #endif +#if (XMC_RTC_INIT_SEQUENCE == 1U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = time->raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM1 = time->raw1; +#endif +#if (XMC_RTC_INIT_SEQUENCE == 0U) + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->TIM0 = time->raw0; + RTC->TIM1 = time->raw1; ; +#endif } /* @@ -198,7 +189,7 @@ void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime) XMC_RTC_TIME_t time; time.raw0 = RTC->TIM0; time.raw1 = RTC->TIM1; - + stdtime->tm_sec = (int8_t)time.seconds; stdtime->tm_min = (int8_t)time.minutes; stdtime->tm_hour = (int8_t)time.hours; @@ -216,31 +207,30 @@ void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm) XMC_ASSERT("XMC_RTC_SetAlarm:Wrong seconds value", ((uint32_t)alarm->seconds < XMC_RTC_MAXSECONDS)); XMC_ASSERT("XMC_RTC_SetAlarm:Wrong minutes value", ((uint32_t)alarm->minutes < XMC_RTC_MAXMINUTES)); XMC_ASSERT("XMC_RTC_SetAlarm:Wrong hours value", ((uint32_t)alarm->hours < XMC_RTC_MAXHOURS)); - XMC_ASSERT("XMC_RTC_SetAlarm:Wrong days value", ((uint32_t)alarm->days < XMC_RTC_MAXDAYS)); XMC_ASSERT("XMC_RTC_SetAlarm:Wrong month value", ((uint32_t)alarm->month < XMC_RTC_MAXMONTH)); XMC_ASSERT("XMC_RTC_SetAlarm:Wrong year value", ((uint32_t)alarm->year < XMC_RTC_MAXYEAR)); - #if (XMC_RTC_INIT_SEQUENCE == 1U) - while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - RTC->ATIM0 = alarm->raw0; - - while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - RTC->ATIM1 = alarm->raw1; - #endif - #if (XMC_RTC_INIT_SEQUENCE == 0U) - while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U) - { - /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ - } - RTC->ATIM0 = alarm->raw0; - RTC->ATIM1 = alarm->raw1; - #endif +#if (XMC_RTC_INIT_SEQUENCE == 1U) + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = alarm->raw0; + + while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM1 = alarm->raw1; +#endif +#if (XMC_RTC_INIT_SEQUENCE == 0U) + while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + RTC->ATIM0 = alarm->raw0; + RTC->ATIM1 = alarm->raw1; +#endif } /* @@ -259,7 +249,7 @@ void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm) void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime) { XMC_RTC_ALARM_t alarm; - + alarm.seconds = stdtime->tm_sec; alarm.minutes = stdtime->tm_min; @@ -277,7 +267,7 @@ void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime) void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime) { XMC_RTC_ALARM_t alarm; - + alarm.raw0 = RTC->ATIM0; alarm.raw1 = RTC->ATIM1; diff --git a/cores/xmc_lib/XMCLib/src/xmc_sdmmc.c b/cores/xmc_lib/XMCLib/src/xmc_sdmmc.c index ae2ff49b..2962c88b 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_sdmmc.c +++ b/cores/xmc_lib/XMCLib/src/xmc_sdmmc.c @@ -1,73 +1,57 @@ /** * @file xmc_sdmmc.c - * @date 2016-07-11 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2023, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - Removed GetDriverVersion API
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2016-03-14: - * - Values are directly assigned to the int status registers
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2016-07-11: - * - XMC_SDMMC_SetDataTransferMode() shall not invoke SetDateLineTimeout()
    + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ - -/** - * @addtogroup XMClib - * @{ - */ + /** * @addtogroup SDMMC * @brief SDMMC driver * @{ */ - + /******************************************************************************* * HEADER FILES *******************************************************************************/ - + #include "xmc_sdmmc.h" /* @@ -158,7 +142,7 @@ /******************************************************************************* * API IMPLEMENTATION *******************************************************************************/ - + /* Get power status of the SDMMC peripheral */ bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc) { @@ -171,23 +155,28 @@ bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc) * De-assert the peripheral reset. The SDMMC peripheral * needs to be initialized */ -void XMC_SDMMC_Enable( ) +void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc) { + XMC_ASSERT("XMC_SDMMC_Enable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_UNUSED_ARG(sdmmc); + #if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC); -#endif +#endif } /* Assert the peripheral reset */ -void XMC_SDMMC_Disable( ) +void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc) { + XMC_ASSERT("XMC_SDMMC_Disable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); + XMC_UNUSED_ARG(sdmmc); #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC); -#endif +#endif #if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC); #endif @@ -199,13 +188,13 @@ XMC_SDMMC_STATUS_t XMC_SDMMC_Init(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONF XMC_ASSERT("XMC_SDMMC_Init: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); XMC_ASSERT("XMC_SDMMC_Init: Invalid clock divider value", XMC_SDMMC_CHECK_SDCLK_FREQ(config->clock_divider)); XMC_ASSERT("XMC_SDMMC_Init: Invalid bus width", XMC_SDMMC_CHECK_DATA_LINES(config->bus_width)); - + /* Enable SDMMC peripheral */ XMC_SDMMC_Enable(sdmmc); - + /* Write internal clock divider register */ sdmmc->CLOCK_CTRL |= (uint16_t)((uint32_t)config->clock_divider << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos); - + /* Set bus width */ sdmmc->HOST_CTRL = (uint8_t)((sdmmc->HOST_CTRL & (uint8_t)~SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk) | ((uint8_t)config->bus_width << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos)); @@ -237,7 +226,7 @@ void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event) void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) { XMC_ASSERT("XMC_SDMMC_EnableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + XMC_SDMMC_EnableEventStatus(sdmmc, event); sdmmc->EN_INT_SIGNAL_NORM |= (uint16_t)event; @@ -266,9 +255,9 @@ void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event) /* Get the status of an SDMMC event */ bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event) -{ +{ bool status; - + XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid SDMMC event", XMC_SDMMC_CHECK_EVENT(event)); @@ -280,7 +269,7 @@ bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event) { status = (bool)(sdmmc->INT_STATUS_ERR & (uint16_t)((uint32_t)event >> 16U)); } - + return status; } @@ -288,7 +277,7 @@ bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event) void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *const response) { XMC_ASSERT("XMC_SDMMC_GetR2Response: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + response->response_0 = sdmmc->RESPONSE[0]; response->response_2 = sdmmc->RESPONSE[1]; response->response_4 = sdmmc->RESPONSE[2]; @@ -299,10 +288,10 @@ void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *con XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_COMMAND_t *cmd, uint32_t arg) { XMC_ASSERT("XMC_SDMMC_SendCommand: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); - + sdmmc->ARGUMENT1 = arg; sdmmc->COMMAND = (uint16_t)(*(uint16_t *)cmd); - + return XMC_SDMMC_STATUS_SUCCESS; } @@ -311,10 +300,10 @@ void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_ { XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc)); XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid transfer type", XMC_SDMMC_CHECK_TRANSFER_MODE(response->type)); - + /* Block size */ sdmmc->BLOCK_SIZE = (uint16_t)(response->block_size); - + /* Number of blocks */ sdmmc->BLOCK_COUNT = (uint16_t)(response->num_blocks); @@ -342,6 +331,3 @@ void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_ * @} */ -/** - * @} - */ diff --git a/cores/xmc_lib/XMCLib/src/xmc_spi.c b/cores/xmc_lib/XMCLib/src/xmc_spi.c index f615f79f..8dde5a49 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_spi.c +++ b/cores/xmc_lib/XMCLib/src/xmc_spi.c @@ -1,57 +1,43 @@ /** * @file xmc_spi.c - * @date 2015-11-04 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-05-20: - * - Modified XMC_SPI_CH_Stop() API for not setting to IDLE the channel if it is busy - * - Modified XMC_SPI_CH_SetInterwordDelay() implementation in order to gain accuracy
    - * - * 2015-06-20: - * - Removed GetDriverVersion API
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-09-01: - * - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-11-04: - * - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag
    - * @endcond + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ /** @@ -63,8 +49,8 @@ * HEADER FILES ********************************************************************************************************************/ -#include -#include +#include "xmc_scu.h" +#include "xmc_spi.h" /********************************************************************************************************************* * MACROS @@ -74,40 +60,49 @@ /********************************************************************************************************************* * API IMPLEMENTATION ********************************************************************************************************************/ - + /* Initializes the selected SPI channel with the config structure. */ -void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config) +void XMC_SPI_CH_InitEx(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config, bool init_brg) { XMC_USIC_CH_Enable(channel); - - if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) + + if ((config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) && init_brg) { /* Configure baud rate */ - (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); + if (config->normal_divider_mode) + { + /* Normal divider mode */ + (void)XMC_USIC_CH_SetBaudrateEx(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); + } + else + { + /* Fractional divider mode */ + (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING); + } } - + /* Configuration of USIC Shift Control */ /* Transmission Mode (TRM) = 1 */ /* Passive Data Level (PDL) = 1 */ channel->SCTR = USIC_CH_SCTR_PDL_Msk | (0x1UL << USIC_CH_SCTR_TRM_Pos) | - (0x3fUL << USIC_CH_SCTR_FLE_Pos)| + (0x3fUL << USIC_CH_SCTR_FLE_Pos) | (0x7UL << USIC_CH_SCTR_WLE_Pos); /* Configuration of USIC Transmit Control/Status Register */ /* TBUF Data Enable (TDEN) = 1 */ /* TBUF Data Single Shot Mode (TDSSM) = 1 */ channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk | - (0x01UL << USIC_CH_TCSR_TDEN_Pos) | - USIC_CH_TCSR_TDSSM_Msk); + (0x01UL << USIC_CH_TCSR_TDEN_Pos) | + USIC_CH_TCSR_TDSSM_Msk); - if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) + if (config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER) { /* Configuration of Protocol Control Register */ channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk | - USIC_CH_PCR_SSCMode_SELCTR_Msk | - (uint32_t)config->selo_inversion | - USIC_CH_PCR_SSCMode_FEM_Msk); + USIC_CH_PCR_SSCMode_SELCTR_Msk | + (uint32_t)config->selo_inversion | + USIC_CH_PCR_SSCMode_FEM_Msk); } /* Clear protocol status */ @@ -120,19 +115,44 @@ void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *co XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate) { XMC_SPI_CH_STATUS_t status; - + status = XMC_SPI_CH_STATUS_ERROR; - + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) { if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK) { status = XMC_SPI_CH_STATUS_OK; } - } + } return status; } +XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, const uint32_t rate, bool normal_divider_mode) +{ + XMC_USIC_CH_STATUS_t status; + + if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U)) + { + if (normal_divider_mode) + { + /* Normal divider mode */ + status = XMC_USIC_CH_SetBaudrateEx(channel, rate, XMC_SPI_CH_OVERSAMPLING); + } + else + { + /* Fractional divider mode */ + status = XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING); + } + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return (XMC_SPI_CH_STATUS_t)status; +} + /* Enable the selected slave signal by setting (SELO) bits in PCR register. */ void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave) { @@ -145,7 +165,7 @@ void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel) { XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_MSLS); - + /* Configuration of Protocol Control Register */ channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk; } @@ -161,12 +181,12 @@ void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, cons /* Check FIFO size */ if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U) { - while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { } - + XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); - + channel->TBUF[mode] = data; } else @@ -194,7 +214,7 @@ uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel) } /* Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields. */ -void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_us) +void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel, uint32_t tinterword_delay_us) { uint32_t peripheral_clock; uint32_t pdiv; @@ -205,45 +225,45 @@ void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterwo uint32_t divider_factor2 = 32U; uint32_t divider_factor1_int = 0U; uint32_t divider_factor1_int_min = 4U; - uint32_t divider_factor1_frac_min =100U; + uint32_t divider_factor1_frac_min = 100U; uint32_t divider_factor1_frac = 0U; uint32_t divider_factor2_temp = 0U; peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); pdiv = (uint32_t)(channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos; step = (uint32_t)(channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos; fFD = (uint32_t)((peripheral_clock >> 10U) * step); - fpdiv= fFD/(1U+pdiv); + fpdiv = fFD / (1U + pdiv); - if(tinterword_delay_us < (128000000/fpdiv)) + if (tinterword_delay_us < (128000000 / fpdiv)) { - for(divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp) + for (divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp) { - divider_factor1 = (tinterword_delay_us*fpdiv)/(divider_factor2_temp*10000); - divider_factor1_frac = divider_factor1%100U; + divider_factor1 = (tinterword_delay_us * fpdiv) / (divider_factor2_temp * 10000); + divider_factor1_frac = divider_factor1 % 100U; - if(divider_factor1_frac > 50) + if (divider_factor1_frac > 50) { - divider_factor1_int = (divider_factor1/100U)+1; - divider_factor1_frac = (divider_factor1_int*100)-divider_factor1; + divider_factor1_int = (divider_factor1 / 100U) + 1; + divider_factor1_frac = (divider_factor1_int * 100) - divider_factor1; } else { - divider_factor1_int = (divider_factor1/100U); + divider_factor1_int = (divider_factor1 / 100U); } if ((divider_factor1_int < 5U) && (divider_factor1_int > 0) && (divider_factor1_frac < divider_factor1_frac_min)) { divider_factor1_frac_min = divider_factor1_frac; divider_factor1_int_min = divider_factor1_int; - divider_factor2= divider_factor2_temp; + divider_factor2 = divider_factor2_temp; } } } channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk | - USIC_CH_PCR_SSCMode_PCTQ1_Msk | - USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | + USIC_CH_PCR_SSCMode_PCTQ1_Msk | + USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) | (((divider_factor1_int_min - 1) << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_PCTQ1_Msk) | (((divider_factor2 - 1 ) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_DCTQ1_Msk); } @@ -252,7 +272,7 @@ XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel) { XMC_SPI_CH_STATUS_t status = XMC_SPI_CH_STATUS_OK; - if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) + if (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { status = XMC_SPI_CH_STATUS_BUSY; } @@ -268,12 +288,12 @@ XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel) void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR |= (event&0x1fc00U); + channel->CCR |= (event & 0x1fc00U); channel->PCR_SSCMode |= ((event << 13U) & 0xe000U); } void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR &= (uint32_t)~(event&0x1fc00U); + channel->CCR &= (uint32_t)~(event & 0x1fc00U); channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_uart.c b/cores/xmc_lib/XMCLib/src/xmc_uart.c index a4cefa0d..db5577d2 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_uart.c +++ b/cores/xmc_lib/XMCLib/src/xmc_uart.c @@ -1,59 +1,43 @@ /** * @file xmc_uart.c - * @date 2016-07-22 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    - * - * 2015-05-20: - * - xmc_uart_ch_stop API implementation corrected. - * - Modified XMC_UART_CH_Stop() API for not setting to IDLE the channel if it is busy
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-09-01: - * - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration
    - * - * 2016-07-22: - * - Modified XMC_UART_CH_Init() to enable transfer status BUSY - * - Modified XMC_UART_CH_Stop() to check for transfer status + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * @endcond + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -61,13 +45,13 @@ * HEADER FILES *********************************************************************************************************************/ -#include -#include +#include "xmc_scu.h" +#include "xmc_uart.h" /********************************************************************************************************************* * MACROS *********************************************************************************************************************/ - + #define XMC_UART_CH_OVERSAMPLING (16UL) #define XMC_UART_CH_OVERSAMPLING_MIN_VAL (4UL) @@ -75,27 +59,39 @@ * API IMPLEMENTATION *********************************************************************************************************************/ -void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config) +void XMC_UART_CH_InitEx(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config, bool init_brg) { uint32_t oversampling = XMC_UART_CH_OVERSAMPLING; /* USIC channel switched on*/ XMC_USIC_CH_Enable(channel); - - if(config->oversampling != 0U) + + if (config->oversampling != 0U) { oversampling = (uint32_t)config->oversampling; } - - /* Configure baud rate */ - (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling); - + + if (init_brg) + { + /* Configure baud rate */ + if (config->normal_divider_mode) + { + /* Normal divider mode */ + (void)XMC_USIC_CH_SetBaudrateEx(channel, config->baudrate, oversampling); + } + else + { + /* Fractional divider mode */ + (void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling); + } + } + /* Configure frame format * Configure the number of stop bits - * Pulse length is set to 0 to have standard UART signaling, + * Pulse length is set to 0 to have standard UART signaling, * i.e. the 0 level is signaled during the complete bit time * Sampling point set equal to the half of the oversampling period - * Enable Sample Majority Decision + * Enable Sample Majority Decision * Enable Transfer Status BUSY */ channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) | @@ -131,23 +127,46 @@ void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const channel->CCR = (uint32_t)config->parity_mode; } - XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling) { XMC_UART_CH_STATUS_t status; - + status = XMC_UART_CH_STATUS_ERROR; - + if ((rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 2U)) && (oversampling >= XMC_UART_CH_OVERSAMPLING_MIN_VAL)) { if (XMC_USIC_CH_SetBaudrate(channel, rate, oversampling) == XMC_USIC_CH_STATUS_OK) { status = XMC_UART_CH_STATUS_OK; } - } + } return status; } +XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling, bool normal_divider_mode) +{ + XMC_USIC_CH_STATUS_t status; + + if ((rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 2U)) && (oversampling >= XMC_UART_CH_OVERSAMPLING_MIN_VAL)) + { + if (normal_divider_mode) + { + /* Normal divider mode */ + status = XMC_USIC_CH_SetBaudrateEx(channel, rate, oversampling); + } + else + { + /* Fractional divider mode */ + status = XMC_USIC_CH_SetBaudrate(channel, rate, oversampling); + } + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return (XMC_UART_CH_STATUS_t)status; +} void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data) { @@ -155,13 +174,13 @@ void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data) if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0UL) { /* Wait till the Transmit Buffer is free for transmission */ - while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) + while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY) { } - + /* Clear the Transmit Buffer indication flag */ XMC_UART_CH_ClearStatusFlag(channel, (uint32_t)XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION); - + /*Transmit data */ channel->TBUF[0U] = data; } @@ -188,7 +207,6 @@ uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel) return retval; } - XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel) { XMC_UART_CH_STATUS_t status = XMC_UART_CH_STATUS_OK; @@ -206,16 +224,14 @@ XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel) return status; } - void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR |= (event&0x1fc00U); - channel->PCR_ASCMode |= (event&0xf8U); + channel->CCR |= (event & 0x1fc00U); + channel->PCR_ASCMode |= (event & 0xf8U); } - void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event) { - channel->CCR &= (uint32_t)~(event&0x1fc00U); - channel->PCR_ASCMode &= (uint32_t)~(event&0xf8U); + channel->CCR &= (uint32_t)~(event & 0x1fc00U); + channel->PCR_ASCMode &= (uint32_t)~(event & 0xf8U); } diff --git a/cores/xmc_lib/XMCLib/src/xmc_usbd.c b/cores/xmc_lib/XMCLib/src/xmc_usbd.c index 88b436c0..f643e652 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_usbd.c +++ b/cores/xmc_lib/XMCLib/src/xmc_usbd.c @@ -1,61 +1,43 @@ /** * @file xmc_usbd.c - * @date 2015-06-20 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification,are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share - * modifications, enhancements or bug fixes with Infineon Technologies AG - * dave@infineon.com). - ********************************************************************************** + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-16: - * - Initial Version.
    - * 2015-03-18: - * - Updated the XMC_USBD_EndpointStall() to fix issue on USB clear stall.
    - * - Updated the XMC_USBD_EndpointConfigure() to fix issue in EP0 configuration.
    - * - Updated the XMC_USBD_IRQHandler()(Removed the DAVE_CE check on SOF event).
    - * 2015-06-20: - * - Removed GetDriverVersion API.
    - * - Updated the XMC_USBD_IsEnumDone() API.
    - * - Updated the copy right in the file header.
    - * - Updated the XMC_USBD_Disable() API to gate the clock after programming the SCU registers.
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ @@ -63,10 +45,10 @@ /******************************************************************************* * HEADER FILES *******************************************************************************/ -#include +#include "xmc_usbd.h" #if defined(USB0) - + /**< macro to check the maximum number of endpoints used*/ #define XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(usbd_max_num_eps) \ ((usbd_max_num_eps == XMC_USBD_MAX_NUM_EPS_1 ) || \ @@ -83,15 +65,15 @@ /* * Endpoint Out Fifo Size */ -uint32_t XMC_USBD_EP_OUT_BUFFERSIZE[7] = {0U,0U,0U,0U,0U,0U,0U}; +static uint32_t XMC_USBD_EP_OUT_BUFFERSIZE[7] = {0U, 0U, 0U, 0U, 0U, 0U, 0U}; /* * Endpoint In Fifo Size */ -uint32_t XMC_USBD_EP_IN_BUFFERSIZE[7] = {0U,0U,0U,0U,0U,0U,0U}; +static uint32_t XMC_USBD_EP_IN_BUFFERSIZE[7] = {0U, 0U, 0U, 0U, 0U, 0U, 0U}; /* * Device definition */ - XMC_USBD_DEVICE_t xmc_device; +XMC_USBD_DEVICE_t xmc_device; #ifdef __GNUC__ /*GCC*/ /* * Endpoint Out Fifo @@ -124,14 +106,14 @@ static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_OUT_BUFFER[7][256] __attr */ static __attribute__((aligned(4))) uint8_t XMC_USBD_EP_IN_BUFFER[7][256] __attribute__((section ("RW_IRAM1"))); #endif -XMC_USBD_t *usbd_init; +static XMC_USBD_t *usbd_init; /******************************************************************************* *LOCAL ROUTINES *******************************************************************************/ /*Local routines prototypes*/ -uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj); -static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count); +static uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj); +static void XMC_USBD_lReadFifo(const uint32_t ep_num, const uint32_t byte_count); static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *ep); static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num); static void XMC_USBD_lFlushRXFifo(void); @@ -177,7 +159,7 @@ const XMC_USBD_DRIVER_t Driver_USBD0 = * else 0 is returned. * @return 1 if an endpoint is active else 0 */ -uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj) +uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj) { uint8_t i; uint8_t result = 0U; @@ -202,9 +184,9 @@ uint8_t XMC_USBD_lDeviceActive(const XMC_USBD_t *const obj) * @arg ep_num the endpoint to read for * @arg byte_count the byte count to read */ -static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count) +static void XMC_USBD_lReadFifo(const uint32_t ep_num, const uint32_t byte_count) { - XMC_USBD_EP_t * ep = &xmc_device.ep[ep_num]; + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_num]; uint32_t word_count; uint32_t temp_data; uint32_t temp_word_count; @@ -221,22 +203,22 @@ static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count) } else if (ep->xferBuffer == NULL) { - /*Do Nothing*/ + /*Do Nothing*/ } else { /* store the data */ - for (i = 0U;i < word_count; i++) + for (i = 0U; i < word_count; i++) { - *(((uint32_t*)ep->xferBuffer)+i) = *fifo; + *(((uint32_t *)ep->xferBuffer) + i) = *fifo; } /* space is not devidable by 4 */ - if (byte_count!=temp_word_count) + if (byte_count != temp_word_count) { temp_data = *fifo; - for (i = 0U;(temp_word_count + i) < byte_count;i++) + for (i = 0U; (temp_word_count + i) < byte_count; i++) { - ep->xferBuffer[(word_count << 2)+i] = (uint8_t)((temp_data & ((uint32_t)0xFFU << (i * 8U))) >> (i * 8U)); + ep->xferBuffer[(word_count << 2) + i] = (uint8_t)((temp_data & ((uint32_t)0xFFU << (i * 8U))) >> (i * 8U)); } } @@ -255,9 +237,9 @@ static void XMC_USBD_lReadFifo(const uint32_t ep_num,const uint32_t byte_count) * @arg[in] ep the endpoint to use * @return the number of bytes written to the fifo */ -static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *const ep) +static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *const ep) { - dtxfsts_data_t freeSpace; + dtxfsts_data_t freeSpace; volatile uint32_t *fifo; uint32_t byte_count; uint32_t word_count; @@ -282,12 +264,12 @@ static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *const ep) } /* copy data dword wise */ - for (i = 0U; i < word_count;ep->xferBuffer+= 4U) + for (i = 0U; i < word_count; ep->xferBuffer += 4U) { - *fifo = *(uint32_t*)ep->xferBuffer; + *fifo = *(uint32_t *)ep->xferBuffer; i++; } - result=byte_count; + result = byte_count; } return result; } @@ -299,21 +281,22 @@ static uint32_t XMC_USBD_lWriteFifo(XMC_USBD_EP_t *const ep) * * @note Use 0x10 as parameter to flush all tx fifos. */ -static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num) +static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num) { - volatile grstctl_t data; + volatile grstctl_t data; uint32_t count; data.d32 = 0U; /*flush fifo */ data.b.txfflsh = 1U; data.b.txfnum = fifo_num; xmc_device.global_register->grstctl = data.d32; - for (count = 0U;count < 1000U; count++){} + for (count = 0U; count < 1000U; count++) {} do { - data.d32 = xmc_device.global_register->grstctl; - } while (data.b.txfflsh); - count = 0U; + data.d32 = xmc_device.global_register->grstctl; + } + while (data.b.txfflsh); + count = 0U; while (count++ < 1000U) { /* wait 3 phy clocks */ @@ -323,20 +306,21 @@ static void XMC_USBD_lFlushTXFifo(const uint8_t fifo_num) /** * @brief Flush the rx fifo */ -static void XMC_USBD_lFlushRXFifo(void) +static void XMC_USBD_lFlushRXFifo(void) { - volatile grstctl_t data; + volatile grstctl_t data; uint32_t count; - - data.d32 = 0U; + + data.d32 = 0U; data.b.rxfflsh = 1U; /* flush FIFO */ xmc_device.global_register->grstctl = data.d32; do { - for (count = 0U; count < 1000U; count++){} + for (count = 0U; count < 1000U; count++) {} data.d32 = xmc_device.global_register->grstctl; - } while (data.b.rxfflsh); + } + while (data.b.rxfflsh); count = 0U; while (count++ < 1000U) { @@ -355,12 +339,12 @@ static void XMC_USBD_lFlushRXFifo(void) * * @return Fifo number for a free fifo */ -static uint8_t XMC_USBD_lAssignTXFifo(void) +static uint8_t XMC_USBD_lAssignTXFifo(void) { uint16_t mask = 1U; uint8_t i = 0U; uint8_t result = 0U; - while( (i < (uint8_t)XMC_USBD_NUM_TX_FIFOS)&&((xmc_device.txfifomsk & mask) != 0U)) + while ( (i < (uint8_t)XMC_USBD_NUM_TX_FIFOS) && ((xmc_device.txfifomsk & mask) != 0U)) { mask = (uint16_t)(mask << 1U); i++; @@ -368,7 +352,7 @@ static uint8_t XMC_USBD_lAssignTXFifo(void) if ((xmc_device.txfifomsk & mask) == 0U) { xmc_device.txfifomsk |= mask; - result=i; + result = i; } return result; } @@ -379,7 +363,7 @@ static uint8_t XMC_USBD_lAssignTXFifo(void) * Mark an used tx fifo as free. * @param[in] fifo_nr Fifo number to free */ -static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr) +static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr) { xmc_device.txfifomsk = (uint16_t)((uint32_t)xmc_device.txfifomsk & (uint32_t)(~((uint32_t)((uint32_t)1U << fifo_nr)))); } @@ -395,11 +379,11 @@ static void XMC_USBD_lUnassignFifo(const uint8_t fifo_nr) * * @param[in] ep Endpoint to start the transfer */ -static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) +static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) { deptsiz_data_t data; depctl_data_t epctl; - + data.d32 = 0U; if ((ep->xferTotal - ep->xferLength) > ep->maxTransferSize) { @@ -411,9 +395,9 @@ static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) } if (ep->address_u.address_st.number == 0U) { - /* Setup the endpoint to receive 3 setup packages and one normal package.*/ - /* Cast the data pointer to use only one variable */ - deptsiz0_data_t *ep0_data = (deptsiz0_data_t*)&data; + /* Setup the endpoint to receive 3 setup packages and one normal package.*/ + /* Cast the data pointer to use only one variable */ + deptsiz0_data_t *ep0_data = (deptsiz0_data_t *)&data; ep0_data->b.pktcnt = 0x1U; ep0_data->b.supcnt = 0x3U; ep0_data->b.xfersize = (uint8_t)ep->xferTotal; @@ -429,18 +413,18 @@ static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) else { /* setup endpoint to recive a amount of packages by given size */ - data.b.pktcnt = (uint16_t)(((ep->xferLength - ep->xferCount) + (ep->maxPacketSize -(uint32_t)1U))/ep->maxPacketSize); - data.b.xfersize =(uint32_t)(ep->xferLength - ep->xferCount); + data.b.pktcnt = (uint16_t)(((ep->xferLength - ep->xferCount) + (ep->maxPacketSize - (uint32_t)1U)) / ep->maxPacketSize); + data.b.xfersize = (uint32_t)(ep->xferLength - ep->xferCount); } } - if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) { /* Programm dma address if needed */ xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepdma = (uint32_t)(ep->xferBuffer); } /* setup endpoint size and enable endpoint */ xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doeptsiz = data.d32; - + epctl.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; epctl.b.cnak = 1U; epctl.b.epena = 1U; @@ -455,12 +439,12 @@ static void XMC_USBD_lStartReadXfer(XMC_USBD_EP_t *const ep) * * @param[in] ep Endpoint to start the transfer */ -static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep) +static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep) { deptsiz_data_t size; depctl_data_t ctl; - - size.d32 = 0U; + + size.d32 = 0U; ctl.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; if ((ep->xferTotal - ep->xferLength) < ep->maxTransferSize) @@ -486,19 +470,19 @@ static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep) } else { - size.b.xfersize =(uint32_t)(ep->xferLength - ep->xferCount); - size.b.pktcnt = (uint16_t)(((uint16_t)(ep->xferLength - ep->xferCount) + (uint16_t)((uint16_t)ep->maxPacketSize - 1U))/ - ep->maxPacketSize); + size.b.xfersize = (uint32_t)(ep->xferLength - ep->xferCount); + size.b.pktcnt = (uint16_t)(((uint16_t)(ep->xferLength - ep->xferCount) + (uint16_t)((uint16_t)ep->maxPacketSize - 1U)) / + ep->maxPacketSize); } - if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (usbd_init->usbd_transfer_mode == XMC_USBD_USE_DMA) { /* Program dma*/ xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepdma = (uint32_t)ep->xferBuffer; } - if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) { /* enable fifo empty interrupt */ - xmc_device.device_register->dtknqr4_fifoemptymsk |= (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); + xmc_device.device_register->dtknqr4_fifoemptymsk |= (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); } } @@ -517,7 +501,7 @@ static void XMC_USBD_lStartWriteXfer(XMC_USBD_EP_t *const ep) * an interrupt, which is handled by this function. It resets the complete otg_core * into the default state. */ -static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) +static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) { uint32_t i; depctl_data_t epctl; @@ -525,33 +509,33 @@ static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) fifosize_data_t gnptxfsiz; daint_data_t daint; dcfg_data_t dcfg; - + /* Clear the Remote Wakeup Signaling */ dctl.d32 = xmc_device.device_register->dctl; dctl.b.rmtwkupsig = 1U; xmc_device.device_register->dctl = dctl.d32; /* enable naks for all eps */ - for (i = 0U;i < (uint8_t)XMC_USBD_NUM_EPS;i++) + for (i = 0U; i < (uint8_t)XMC_USBD_NUM_EPS; i++) { epctl.d32 = xmc_device.endpoint_out_register[i]->doepctl; - epctl.b.snak = 1U; - epctl.b.stall = 0U; - xmc_device.endpoint_out_register[i]->doepctl = epctl.d32; + epctl.b.snak = 1U; + epctl.b.stall = 0U; + xmc_device.endpoint_out_register[i]->doepctl = epctl.d32; } /* Configure fifos */ /* Calculate the size of the rx fifo */ xmc_device.global_register->grxfsiz = 64U; - /* Calculate the size of the tx fifo for ep 0 */ + /* Calculate the size of the tx fifo for ep 0 */ gnptxfsiz.d32 = 0U; gnptxfsiz.b.depth = 16U; gnptxfsiz.b.startaddr = 64U; xmc_device.global_register->gnptxfsiz = gnptxfsiz.d32; /* calculate the size for the rest */ - for (i = 1U;i < (uint8_t)XMC_USBD_NUM_TX_FIFOS;i++) + for (i = 1U; i < (uint8_t)XMC_USBD_NUM_TX_FIFOS; i++) { - xmc_device.global_register->dtxfsiz[i- 1U] = (uint32_t)(((256U + (i*(64U)))/4U) | ((uint32_t)16U << 16U)); + xmc_device.global_register->dtxfsiz[i - 1U] = (uint32_t)(((256U + (i * (64U))) / 4U) | ((uint32_t)16U << 16U)); } /* flush the fifos for proper operation */ @@ -559,7 +543,7 @@ static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) XMC_USBD_lFlushTXFifo(0x0U); XMC_USBD_lFlushRXFifo(); /* Flush learning queue not needed due to fifo config */ - /* enable ep0 interrupts */ + /* enable ep0 interrupts */ daint.d32 = 0U; daint.b.inep0 = 1U; daint.b.outep0 = 1U; @@ -568,19 +552,19 @@ static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) /* enable endpoint interrupts */ /* out ep interrupts */ XMC_USBD_EnableEventOUTEP(((uint32_t)XMC_USBD_EVENT_OUT_EP_TX_COMPLET | (uint32_t)XMC_USBD_EVENT_OUT_EP_DISABLED | - (uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP | (uint32_t)XMC_USBD_EVENT_OUT_EP_AHB_ERROR)); + (uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP | (uint32_t)XMC_USBD_EVENT_OUT_EP_AHB_ERROR)); /*in ep interrupts */ XMC_USBD_EnableEventINEP(((uint32_t)XMC_USBD_EVENT_IN_EP_TX_COMPLET | (uint32_t)XMC_USBD_EVENT_IN_EP_DISABLED | - (uint32_t)XMC_USBD_EVENT_IN_EP_AHB_ERROR | (uint32_t)XMC_USBD_EVENT_IN_EP_TIMEOUT)); + (uint32_t)XMC_USBD_EVENT_IN_EP_AHB_ERROR | (uint32_t)XMC_USBD_EVENT_IN_EP_TIMEOUT)); - /* Clear device Address */ + /* Clear device Address */ dcfg.d32 = xmc_device.device_register->dcfg; dcfg.b.devaddr = 0U; xmc_device.device_register->dcfg = dcfg.d32; - if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) { /* Clear Empty interrupt */ xmc_device.device_register->dtknqr4_fifoemptymsk = 0U; @@ -600,14 +584,14 @@ static void XMC_USBD_lHandleUSBReset(const XMC_USBD_t *const obj) * * It detects especially connect and disconnect events. */ -static void XMC_USBD_lHandleOTGInt(void) +static void XMC_USBD_lHandleOTGInt(void) { gotgint_data_t data; data.d32 = xmc_device.global_register->gotgint; if (data.b.sesenddet) { - xmc_device.IsPowered = 0U; - xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_POWER_OFF); + xmc_device.IsPowered = 0U; + xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_POWER_OFF); } XMC_USBD_lClearEventOTG(data.d32); @@ -618,14 +602,14 @@ static void XMC_USBD_lHandleOTGInt(void) * * Handles the enumeration done from dwc_otg, when the host has enumerated the device. */ -static void XMC_USBD_lHandleEnumDone(void) +static void XMC_USBD_lHandleEnumDone(void) { /* Normaly we need to check dctl * We are always fullspeed, so max it up. */ depctl_data_t epctl; gusbcfg_data_t gusbcfg; - - epctl.d32=xmc_device.endpoint_in_register[0U]->diepctl; + + epctl.d32 = xmc_device.endpoint_in_register[0U]->diepctl; epctl.b.mps = 0x00U; /* 64 Byte, this is also automatically set for out ep */ xmc_device.endpoint_in_register[0U]->diepctl = epctl.d32; @@ -635,7 +619,7 @@ static void XMC_USBD_lHandleEnumDone(void) xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_CONNECT); - /* Set Trim */ + /* Set Trim */ gusbcfg.d32 = xmc_device.global_register->gusbcfg; gusbcfg.b.usbtrdtim = 9U; /* default value for LS/FS */ xmc_device.global_register->gusbcfg = gusbcfg.d32; @@ -651,7 +635,7 @@ static void XMC_USBD_lHandleEnumDone(void) * The interrupt handler first checks, which endpoint has caused the interrupt and then * determines, which interrupt should be handled. */ -static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) +static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) { daint_data_t daint; daint_data_t daintmsk; @@ -663,17 +647,17 @@ static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) uint16_t temp1; uint16_t mask; uint8_t ep_num; - + daint.d32 = xmc_device.device_register->daint; - + daintmsk.d32 = xmc_device.device_register->daintmsk; - - doepmsk.d32 = xmc_device.device_register->doepmsk; - + + doepmsk.d32 = xmc_device.device_register->doepmsk; + mask = daint.ep.out & daintmsk.ep.out; ep_num = 0U; doeptsiz.d32 = 0U; - + while ((uint16_t)mask >> ep_num) { temp1 = (mask >> (uint16_t)ep_num); @@ -683,43 +667,43 @@ static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) /* load register data for endpoint */ ep = &xmc_device.ep[ep_num]; doepint.d32 = xmc_device.endpoint_out_register[ep_num]->doepint & doepmsk.d32; - if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (obj->usbd_transfer_mode == XMC_USBD_USE_DMA) { doeptsiz.d32 = xmc_device.endpoint_out_register[ep_num]->doeptsiz; } - /* Setup Phase Complete */ + /* Setup Phase Complete */ if (doepint.b.setup) { /* ep0 not stalled any more */ ep->isStalled = 0U; - if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (obj->usbd_transfer_mode == XMC_USBD_USE_DMA) { /* calculate size for setup packet */ - ep->outBytesAvailable = (uint32_t)(((uint32_t)XMC_USBD_SETUP_COUNT - - (uint32_t)((deptsiz0_data_t*)&doeptsiz)->b.supcnt)*(uint32_t)XMC_USBD_SETUP_SIZE); + ep->outBytesAvailable = (uint32_t)(((uint32_t)XMC_USBD_SETUP_COUNT - + (uint32_t)((deptsiz0_data_t *)&doeptsiz)->b.supcnt) * (uint32_t)XMC_USBD_SETUP_SIZE); } - if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) - { - ep->outBytesAvailable += ep->xferCount; - } - ep->outInUse = 0U; - xmc_device.EndpointEvent_cb(0U,XMC_USBD_EP_EVENT_SETUP); /* signal endpoint event */ - /* clear the interrupt */ - XMC_USBD_ClearEventOUTEP((uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP,ep_num); + if (obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + { + ep->outBytesAvailable += ep->xferCount; + } + ep->outInUse = 0U; + xmc_device.EndpointEvent_cb(0U, XMC_USBD_EP_EVENT_SETUP); /* signal endpoint event */ + /* clear the interrupt */ + XMC_USBD_ClearEventOUTEP((uint32_t)XMC_USBD_EVENT_OUT_EP_SETUP, ep_num); } if (doepint.b.xfercompl) { - if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (obj->usbd_transfer_mode == XMC_USBD_USE_DMA) { uint32_t bytes = (ep->xferLength - ep->xferCount) - doeptsiz.b.xfersize; ep->xferCount += bytes; ep->xferBuffer += bytes; - } + } if (ep->xferTotal == ep->xferLength) { ep->outBytesAvailable = ep->xferCount; ep->outInUse = 0U; - xmc_device.EndpointEvent_cb(ep_num,XMC_USBD_EP_EVENT_OUT); + xmc_device.EndpointEvent_cb(ep_num, XMC_USBD_EP_EVENT_OUT); } else { @@ -728,7 +712,7 @@ static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) } - XMC_USBD_ClearEventOUTEP(doepint.d32,ep_num); + XMC_USBD_ClearEventOUTEP(doepint.d32, ep_num); } ep_num++; } @@ -743,7 +727,7 @@ static void XMC_USBD_lHandleOEPInt(const XMC_USBD_t *const obj) * The interrupt handler first checks, which endpoint has caused the interrupt and then * determines, which interrupt should be handled. */ -static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) +static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) { XMC_USBD_EP_t *ep; daint_data_t daint; @@ -755,15 +739,15 @@ static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) uint16_t mask; uint8_t ep_num; uint32_t inepint; - + daint.d32 = xmc_device.device_register->daint; - + diepmsk.d32 = xmc_device.device_register->diepmsk; - + dieptsiz.d32 = 0U; mask = daint.ep.in; ep_num = 0U; - + while ((uint16_t)mask >> ep_num) { temp1 = ((uint16_t)mask >> (uint16_t)ep_num); @@ -771,15 +755,15 @@ static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) if ((uint16_t)temp) { ep = &xmc_device.ep[ep_num]; - inepint = (uint32_t)xmc_device.endpoint_in_register[ep_num]->diepint; + inepint = (uint32_t)xmc_device.endpoint_in_register[ep_num]->diepint; diepint.d32 = inepint & - ((((uint32_t)((uint32_t)xmc_device.device_register->dtknqr4_fifoemptymsk >> ep->address_u.address_st.number) & - 0x1U) << 7U) | (uint32_t)diepmsk.d32); - if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + ((((uint32_t)((uint32_t)xmc_device.device_register->dtknqr4_fifoemptymsk >> ep->address_u.address_st.number) & + 0x1U) << 7U) | (uint32_t)diepmsk.d32); + if (obj->usbd_transfer_mode == XMC_USBD_USE_DMA) { dieptsiz.d32 = xmc_device.endpoint_in_register[ep_num]->dieptsiz; } - if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) { if (diepint.b.emptyintr) { @@ -791,7 +775,7 @@ static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) } if (diepint.b.xfercompl) { - if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (obj->usbd_transfer_mode == XMC_USBD_USE_DMA) { /* update xfer values */ if ((dieptsiz.b.pktcnt == 0U) && (dieptsiz.b.xfersize == 0U)) @@ -801,16 +785,16 @@ static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) ep->xferBuffer += Bytes; } } - if (ep->xferTotal==ep->xferLength) + if (ep->xferTotal == ep->xferLength) { ep->inInUse = 0U; - if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) { /* mask fifo empty interrupt */ xmc_device.device_register->dtknqr4_fifoemptymsk = - (uint32_t)(xmc_device.device_register->dtknqr4_fifoemptymsk & ~(((uint32_t)1U << ep_num))); + (uint32_t)(xmc_device.device_register->dtknqr4_fifoemptymsk & ~(((uint32_t)1U << ep_num))); } - xmc_device.EndpointEvent_cb(0x80U | ep_num,XMC_USBD_EP_EVENT_IN); + xmc_device.EndpointEvent_cb(0x80U | ep_num, XMC_USBD_EP_EVENT_IN); } else { @@ -820,7 +804,7 @@ static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) } - XMC_USBD_ClearEventINEP((uint32_t)diepint.d32,ep_num); + XMC_USBD_ClearEventINEP((uint32_t)diepint.d32, ep_num); } ep_num++; } @@ -832,28 +816,28 @@ static void XMC_USBD_lHandleIEPInt(const XMC_USBD_t *const obj) * * This function handles the interrupt, when the rx fifo is not empty anymore. */ -static void XMC_USBD_lHandleRxFLvl(void) +static void XMC_USBD_lHandleRxFLvl(void) { - device_grxsts_data_t data; + device_grxsts_data_t data; data.d32 = xmc_device.global_register->grxstsp; switch (data.b.pktsts) - { + { case XMC_USBD_GRXSTS_PKTSTS_GOUTNAK: break; case XMC_USBD_GRXSTS_PKTSTS_OUTCMPL: break; case XMC_USBD_GRXSTS_PKTSTS_OUTDATA: - XMC_USBD_lReadFifo((uint32_t)data.b.epnum,(uint32_t)data.b.bcnt); + XMC_USBD_lReadFifo((uint32_t)data.b.epnum, (uint32_t)data.b.bcnt); break; case XMC_USBD_GRXSTS_PKTSTS_SETUP: - XMC_USBD_lReadFifo((uint32_t)data.b.epnum,(uint32_t)data.b.bcnt); + XMC_USBD_lReadFifo((uint32_t)data.b.epnum, (uint32_t)data.b.bcnt); break; case XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL: break; default: break; - } + } /* no need to clear */ } @@ -863,20 +847,20 @@ static void XMC_USBD_lHandleRxFLvl(void) * The handler first checks, which global interrupt has caused the interrupt * and then dispatches interrupt to the corresponding sub-handler. */ -void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj) +void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj) { gintmsk_data_t gintmsk; gintsts_data_t data; - + gintmsk.d32 = xmc_device.global_register->gintmsk; data.d32 = xmc_device.global_register->gintsts & gintmsk.d32; - + if (data.b.sofintr) { xmc_device.DeviceEvent_cb(XMC_USBD_EVENT_SOF); XMC_USBD_ClearEvent(XMC_USBD_EVENT_SOF); } - if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) { if (data.b.rxstsqlvl) { @@ -922,11 +906,11 @@ void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj) } if (data.b.outepintr) { - XMC_USBD_lHandleOEPInt(obj); + XMC_USBD_lHandleOEPInt(obj); } - if (data.b.otgintr) + if (data.b.otgintr) { - XMC_USBD_lHandleOTGInt(); + XMC_USBD_lHandleOTGInt(); } } @@ -938,7 +922,7 @@ void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj) /** * Enables the USB0 module **/ -void XMC_USBD_Enable(void) +void XMC_USBD_Enable(void) { #if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); @@ -951,7 +935,7 @@ void XMC_USBD_Enable(void) /** * Disables the USB0 module **/ -void XMC_USBD_Disable(void) +void XMC_USBD_Disable(void) { /* Clear Reset and power up */ XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); @@ -964,43 +948,43 @@ void XMC_USBD_Disable(void) /** * Clear the USB device event **/ -void XMC_USBD_ClearEvent(const XMC_USBD_EVENT_t event) +void XMC_USBD_ClearEvent(const XMC_USBD_EVENT_t event) { gintsts_data_t clear; clear.d32 = 0U; - switch(event) + switch (event) { case (XMC_USBD_EVENT_POWER_ON): - clear.b.sessreqintr = 1U; - break; + clear.b.sessreqintr = 1U; + break; case (XMC_USBD_EVENT_RESET): - clear.b.usbreset = 1U; - break; + clear.b.usbreset = 1U; + break; case (XMC_USBD_EVENT_SUSPEND): - clear.b.usbsuspend = 1U; - break; + clear.b.usbsuspend = 1U; + break; case (XMC_USBD_EVENT_RESUME): - clear.b.wkupintr = 1U; - break; + clear.b.wkupintr = 1U; + break; case (XMC_USBD_EVENT_REMOTE_WAKEUP): - clear.b.wkupintr = 1U; - break; + clear.b.wkupintr = 1U; + break; case (XMC_USBD_EVENT_SOF): - clear.b.sofintr = 1U; - break; + clear.b.sofintr = 1U; + break; case (XMC_USBD_EVENT_EARLYSUSPEND): - clear.b.erlysuspend = 1U; - break; + clear.b.erlysuspend = 1U; + break; case (XMC_USBD_EVENT_ENUMDONE): - clear.b.enumdone = 1U; - break; + clear.b.enumdone = 1U; + break; case (XMC_USBD_EVENT_OUTEP): - clear.b.outepintr = 1U; - break; - default: - break; - } - xmc_device.global_register->gintsts = clear.d32; + clear.b.outepintr = 1U; + break; + default: + break; + } + xmc_device.global_register->gintsts = clear.d32; } /** @@ -1016,7 +1000,7 @@ static void XMC_USBD_lClearEventOTG(uint32_t event) /** * Clear the USB IN EP events **/ -void XMC_USBD_ClearEventINEP(uint32_t event,const uint8_t ep_num) +void XMC_USBD_ClearEventINEP(uint32_t event, const uint8_t ep_num) { diepint_data_t clear; clear.d32 = event; @@ -1026,7 +1010,7 @@ void XMC_USBD_ClearEventINEP(uint32_t event,const uint8_t ep_num) /** * Clear the USB OUT EP events **/ -void XMC_USBD_ClearEventOUTEP(uint32_t event,const uint8_t ep_num) +void XMC_USBD_ClearEventOUTEP(uint32_t event, const uint8_t ep_num) { doepint_data_t clear; clear.d32 = event; @@ -1038,9 +1022,9 @@ void XMC_USBD_ClearEventOUTEP(uint32_t event,const uint8_t ep_num) **/ void XMC_USBD_EnableEventOUTEP(uint32_t event) { - doepint_data_t doepint; - doepint.d32 = event; - xmc_device.device_register->doepmsk |= doepint.d32; + doepint_data_t doepint; + doepint.d32 = event; + xmc_device.device_register->doepmsk |= doepint.d32; } /** @@ -1048,9 +1032,9 @@ void XMC_USBD_EnableEventOUTEP(uint32_t event) **/ void XMC_USBD_EnableEventINEP(uint32_t event) { - diepint_data_t diepint; - diepint.d32 = event; - xmc_device.device_register->diepmsk |= diepint.d32; + diepint_data_t diepint; + diepint.d32 = event; + xmc_device.device_register->diepmsk |= diepint.d32; } /** @@ -1058,7 +1042,7 @@ void XMC_USBD_EnableEventINEP(uint32_t event) **/ XMC_USBD_CAPABILITIES_t XMC_USBD_GetCapabilities() { - XMC_USBD_CAPABILITIES_t cap={0U}; + XMC_USBD_CAPABILITIES_t cap = {0U}; cap.event_connect = 1U; cap.event_disconnect = 1U; #if UC_SERIES == 45 @@ -1091,53 +1075,53 @@ XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) gintmsk_data_t gintmsk; XMC_ASSERT("XMC_USBD_Init: obj.usbd_max_num_eps not of type XMC_USBD_MAX_NUM_EPS_t", - XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(obj->usbd_max_num_eps)) - + XMC_USBD_CHECK_INPUT_MAX_NUM_EPS(obj->usbd_max_num_eps)) + XMC_USBD_Enable(); - + usbd_init = obj; /* Filling out buffer size */ - for(i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + for (i = 0U; i < (uint32_t)XMC_USBD_NUM_EPS; i++) { - XMC_USBD_EP_OUT_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; - XMC_USBD_EP_IN_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; + XMC_USBD_EP_OUT_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; + XMC_USBD_EP_IN_BUFFERSIZE[i] = XMC_USBD_EP0_BUFFER_SIZE; } /* clear device status */ - memset((void*)&xmc_device,0x0U,sizeof(XMC_USBD_DEVICE_t)); + memset((void *)&xmc_device, 0x0U, sizeof(XMC_USBD_DEVICE_t)); /* assign callbacks */ xmc_device.DeviceEvent_cb = obj->cb_xmc_device_event; xmc_device.EndpointEvent_cb = obj->cb_endpoint_event; XMC_USBD_BASE_ADDRESS = (uint8_t *)(obj->usbd); /* assign register address */ - xmc_device.global_register = (dwc_otg_core_global_regs_t*)(obj->usbd); - xmc_device.device_register = ((dwc_otg_device_global_regs_t*)(XMC_USBD_BASE_ADDRESS + DWC_DEV_GLOBAL_REG_OFFSET)); - for (i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + xmc_device.global_register = (dwc_otg_core_global_regs_t *)(obj->usbd); + xmc_device.device_register = ((dwc_otg_device_global_regs_t *)(XMC_USBD_BASE_ADDRESS + DWC_DEV_GLOBAL_REG_OFFSET)); + for (i = 0U; i < (uint32_t)XMC_USBD_NUM_EPS; i++) { - xmc_device.endpoint_in_register[i] = (dwc_otg_dev_in_ep_regs_t*)(XMC_USBD_BASE_ADDRESS + DWC_DEV_IN_EP_REG_OFFSET + - ((uint32_t)DWC_EP_REG_OFFSET*i)); + xmc_device.endpoint_in_register[i] = (dwc_otg_dev_in_ep_regs_t *)(XMC_USBD_BASE_ADDRESS + DWC_DEV_IN_EP_REG_OFFSET + + ((uint32_t)DWC_EP_REG_OFFSET * i)); } - for (i = 0U;i < (uint32_t)XMC_USBD_NUM_EPS;i++) + for (i = 0U; i < (uint32_t)XMC_USBD_NUM_EPS; i++) { - xmc_device.endpoint_out_register[i] = (dwc_otg_dev_out_ep_regs_t*)(XMC_USBD_BASE_ADDRESS + - DWC_DEV_OUT_EP_REG_OFFSET + - ((uint32_t)DWC_EP_REG_OFFSET*i)); + xmc_device.endpoint_out_register[i] = (dwc_otg_dev_out_ep_regs_t *)(XMC_USBD_BASE_ADDRESS + + DWC_DEV_OUT_EP_REG_OFFSET + + ((uint32_t)DWC_EP_REG_OFFSET * i)); } - for (i = 0U;i < (uint32_t)XMC_USBD_NUM_TX_FIFOS;i++) + for (i = 0U; i < (uint32_t)XMC_USBD_NUM_TX_FIFOS; i++) { - xmc_device.fifo[i] = (uint32_t*)(XMC_USBD_BASE_ADDRESS + - XMC_USBD_TX_FIFO_REG_OFFSET + - (i * XMC_USBD_TX_FIFO_OFFSET)); + xmc_device.fifo[i] = (uint32_t *)(XMC_USBD_BASE_ADDRESS + + XMC_USBD_TX_FIFO_REG_OFFSET + + (i * XMC_USBD_TX_FIFO_OFFSET)); } /* obj data structure for endpoint 0 */ /* Done by driver core */ - /* configure ahb details */ + /* configure ahb details */ gahbcfg.d32 = xmc_device.global_register->gahbcfg; gahbcfg.b.glblintrmsk = 1U; /* enable interrupts ( global mask ) */ gahbcfg.b.nptxfemplvl_txfemplvl = 1U; - if(obj->usbd_transfer_mode == XMC_USBD_USE_DMA) + if (obj->usbd_transfer_mode == XMC_USBD_USE_DMA) { /* Enable dma if needed */ gahbcfg.b.dmaenable = 1U; /* enable dma if needed */ @@ -1147,19 +1131,19 @@ XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) gahbcfg.b.dmaenable = 0U; } xmc_device.global_register->gahbcfg = gahbcfg.d32; - /* configure usb details */ - gusbcfg.d32= xmc_device.global_register->gusbcfg; + /* configure usb details */ + gusbcfg.d32 = xmc_device.global_register->gusbcfg; gusbcfg.b.force_dev_mode = 1U; /* force us into device mode */ gusbcfg.b.srpcap = 1U; /* enable session request protocoll */ xmc_device.global_register->gusbcfg = gusbcfg.d32; /* Device init */ - /* configure device speed */ + /* configure device speed */ dcfg.d32 = xmc_device.device_register->dcfg; dcfg.b.devspd = XMC_USBD_DCFG_DEVSPD_FS; dcfg.b.descdma = 0U; xmc_device.device_register->dcfg = dcfg.d32; - /* configure device functions */ + /* configure device functions */ dctl.d32 = xmc_device.device_register->dctl; dctl.b.sftdiscon = 1U; /* disconnect the device until its connected by the user */ /* all other config is done by default register value */ @@ -1171,7 +1155,7 @@ XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) /* clear interrupt status bits prior to unmasking */ xmc_device.global_register->gintmsk = 0U; /* disable all interrupts */ xmc_device.global_register->gintsts = 0xFFFFFFFFU; /* clear all interrupts */ - + gintmsk.d32 = 0U; /* enable common interrupts */ gintmsk.b.modemismatch = 1U; @@ -1184,7 +1168,7 @@ XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) gintmsk.b.usbsuspend = 1U; gintmsk.b.wkupintr = 1U; gintmsk.b.sofintr = 1U; - if(obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (obj->usbd_transfer_mode == XMC_USBD_USE_FIFO) { gintmsk.b.rxstsqlvl = 1U; } @@ -1197,26 +1181,26 @@ XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj) /** * Uninitializes the USB device **/ -XMC_USBD_STATUS_t XMC_USBD_Uninitialize() +XMC_USBD_STATUS_t XMC_USBD_Uninitialize() { /* Disconnect the device */ dctl_data_t dctl; - dctl.d32 = xmc_device.device_register->dctl; + dctl.d32 = xmc_device.device_register->dctl; dctl.b.sftdiscon = 1U; xmc_device.device_register->dctl = dctl.d32; /* clean up */ - memset((void*)&xmc_device,0U,sizeof(xmc_device)); + memset((void *)&xmc_device, 0U, sizeof(xmc_device)); return XMC_USBD_STATUS_OK; } /** * Connects the USB device to host **/ -XMC_USBD_STATUS_t XMC_USBD_DeviceConnect() +XMC_USBD_STATUS_t XMC_USBD_DeviceConnect() { /* Just disable softdisconnect */ dctl_data_t dctl; - dctl.d32 = xmc_device.device_register->dctl; + dctl.d32 = xmc_device.device_register->dctl; dctl.b.sftdiscon = 0U; xmc_device.device_register->dctl = dctl.d32; return XMC_USBD_STATUS_OK; @@ -1225,10 +1209,10 @@ XMC_USBD_STATUS_t XMC_USBD_DeviceConnect() /** * Disconnects the USB device from host **/ -XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect() +XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect() { dctl_data_t dctl; - dctl.d32 = xmc_device.device_register->dctl; + dctl.d32 = xmc_device.device_register->dctl; dctl.b.sftdiscon = 1U; xmc_device.device_register->dctl = dctl.d32; return XMC_USBD_STATUS_OK; @@ -1237,9 +1221,9 @@ XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect() /** * Gets the USB device state. **/ -XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj) +XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj) { - XMC_USBD_STATE_t state={0U}; + XMC_USBD_STATE_t state = {0U}; state.speed = XMC_USBD_SPEED_FULL; state.connected = xmc_device.IsConnected; state.active = XMC_USBD_lDeviceActive(obj); @@ -1250,11 +1234,11 @@ XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj) /** * Prepares the endpoint to read next OUT packet **/ -XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size) +XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size) { XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_EP_NUM_MASK]; XMC_USBD_STATUS_t result; - + if (ep->outInUse || !ep->isConfigured) { result = XMC_USBD_STATUS_ERROR; @@ -1273,7 +1257,7 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t siz ep->xferBuffer = ep->outBuffer; ep->outBytesAvailable = 0U; XMC_USBD_lStartReadXfer(ep); - result= XMC_USBD_STATUS_OK; + result = XMC_USBD_STATUS_OK; } return result; } @@ -1281,14 +1265,14 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t siz /** * Reads the number of bytes from the USB OUT endpoint **/ -int32_t XMC_USBD_EndpointRead(const uint8_t ep_num,uint8_t * buffer,uint32_t length) +int32_t XMC_USBD_EndpointRead(const uint8_t ep_num, uint8_t *buffer, uint32_t length) { XMC_USBD_EP_t *ep = &xmc_device.ep[ep_num]; if (length > ep->outBytesAvailable) { length = ep->outBytesAvailable; } - memcpy(buffer,&ep->outBuffer[ep->outOffset],length); + memcpy(buffer, &ep->outBuffer[ep->outOffset], length); ep->outBytesAvailable -= length; if (ep->outBytesAvailable) { @@ -1304,9 +1288,9 @@ int32_t XMC_USBD_EndpointRead(const uint8_t ep_num,uint8_t * buffer,uint32_t len /** * Writes number of bytes in to the USB IN endpoint. **/ -int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint32_t length) +int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num, const uint8_t *buffer, uint32_t length) { - XMC_USBD_EP_t * ep = &xmc_device.ep[ep_num & (uint8_t)XMC_USBD_EP_NUM_MASK]; + XMC_USBD_EP_t *ep = &xmc_device.ep[ep_num & (uint8_t)XMC_USBD_EP_NUM_MASK]; int32_t result; if (!ep->isConfigured) { @@ -1314,7 +1298,7 @@ int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint3 } else if (ep->inInUse == 1U) { - result=(int32_t)0; + result = (int32_t)0; } else { @@ -1323,8 +1307,8 @@ int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint3 length = ep->inBufferSize; } /* copy data into input buffer for DMA and FIFO mode */ - memcpy(ep->inBuffer,(const void *)buffer,length); - ep->xferBuffer = ep->inBuffer; + memcpy(ep->inBuffer, (const void *)buffer, length); + ep->xferBuffer = ep->inBuffer; ep->xferTotal = length; /* set transfer values */ ep->xferLength = 0U; @@ -1332,7 +1316,7 @@ int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint3 ep->inInUse = 1U; /* start the transfer */ XMC_USBD_lStartWriteXfer(ep); - result=(int32_t)ep->xferTotal; + result = (int32_t)ep->xferTotal; } return result; } @@ -1340,7 +1324,7 @@ int32_t XMC_USBD_EndpointWrite(const uint8_t ep_num,const uint8_t * buffer,uint3 /** * Sets the USB device address. **/ -XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(const uint8_t address,const XMC_USBD_SET_ADDRESS_STAGE_t stage) +XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(const uint8_t address, const XMC_USBD_SET_ADDRESS_STAGE_t stage) { dcfg_data_t data; data.d32 = xmc_device.device_register->dcfg; @@ -1349,13 +1333,13 @@ XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(const uint8_t address,const XMC_USBD data.b.devaddr = address; xmc_device.device_register->dcfg = data.d32; } - return XMC_USBD_STATUS_OK; + return XMC_USBD_STATUS_OK; } /** * Set/clear stall on the selected endpoint. **/ -XMC_USBD_STATUS_t XMC_USBD_EndpointStall(const uint8_t ep_addr, const bool stall) +XMC_USBD_STATUS_t XMC_USBD_EndpointStall(const uint8_t ep_addr, const bool stall) { depctl_data_t data; XMC_USBD_EP_t *ep = &xmc_device.ep[(ep_addr & (uint8_t)XMC_USBD_EP_NUM_MASK)]; @@ -1380,29 +1364,30 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointStall(const uint8_t ep_addr, const bool stall else { /* just clear stall bit */ - if (ep_addr & (uint8_t)XMC_USBD_ENDPOINT_DIRECTION_MASK) - { - data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; - data.b.stall = 0U; - data.b.setd0pid = 1U; /* reset pid to 0 */ - xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; - } - else - { - data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; - data.b.stall = 0U; - data.b.setd0pid = 1U; /* reset pid to 0 */ - xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; - } - ep->isStalled = 0U; - } - return XMC_USBD_STATUS_OK; + if (ep_addr & (uint8_t)XMC_USBD_ENDPOINT_DIRECTION_MASK) + { + data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; + data.b.stall = 0U; + data.b.setd0pid = 1U; /* reset pid to 0 */ + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; + } + else + { + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + data.b.stall = 0U; + data.b.setd0pid = 1U; /* reset pid to 0 */ + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; + } + ep->isStalled = 0U; + } + return XMC_USBD_STATUS_OK; } /** * Aborts the data transfer on the selected endpoint **/ -XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(const uint8_t ep_addr) { +XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(const uint8_t ep_addr) +{ XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; if (ep->address_u.address_st.direction) { @@ -1426,14 +1411,14 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(const uint8_t ep_addr) { * Configures the given endpoint **/ XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(const uint8_t ep_addr, - const XMC_USBD_ENDPOINT_TYPE_t ep_type, - const uint16_t ep_max_packet_size) + const XMC_USBD_ENDPOINT_TYPE_t ep_type, + const uint16_t ep_max_packet_size) { daint_data_t daintmsk; XMC_USBD_EP_t *ep; - daintmsk.d32 = xmc_device.device_register->daintmsk; - ep =&xmc_device.ep[ep_addr & (uint32_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; - memset((void*)ep,0x0U,sizeof(XMC_USBD_EP_t)); /* clear endpoint structure */ + daintmsk.d32 = xmc_device.device_register->daintmsk; + ep = &xmc_device.ep[ep_addr & (uint32_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; + memset((void *)ep, 0x0U, sizeof(XMC_USBD_EP_t)); /* clear endpoint structure */ /* do ep configuration */ ep->address_u.address = ep_addr; ep->isConfigured = 1U; @@ -1457,85 +1442,85 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(const uint8_t ep_addr, { depctl_data_t data; data.d32 = xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl; - /*enable endpoint */ - data.b.usbactep = 1U; - /* set ep type */ - data.b.eptype = (uint8_t)ep_type; - /* set mps */ + /*enable endpoint */ + data.b.usbactep = 1U; + /* set ep type */ + data.b.eptype = (uint8_t)ep_type; + /* set mps */ if (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL) { - switch(ep_max_packet_size) - { - case (64U): - data.b.mps = 0x0U; - break; - case (32U): - data.b.mps = 0x1U; - break; - case (16U): - data.b.mps = 0x2U; - break; - case (8U): - data.b.mps = 0x3U; - break; - default: - break; - } - } - else - { - data.b.mps = ep_max_packet_size; - } - /* set first data0 pid */ - data.b.setd0pid = 1U; - /* clear stall */ - data.b.stall = 0U; - /* set tx fifo */ - ep->txFifoNum = XMC_USBD_lAssignTXFifo(); /* get tx fifo */ - data.b.txfnum = ep->txFifoNum; - xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; /* configure endpoint */ - daintmsk.ep.in |= (uint16_t)((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts for endpoint */ + switch (ep_max_packet_size) + { + case (64U): + data.b.mps = 0x0U; + break; + case (32U): + data.b.mps = 0x1U; + break; + case (16U): + data.b.mps = 0x2U; + break; + case (8U): + data.b.mps = 0x3U; + break; + default: + break; + } + } + else + { + data.b.mps = ep_max_packet_size; + } + /* set first data0 pid */ + data.b.setd0pid = 1U; + /* clear stall */ + data.b.stall = 0U; + /* set tx fifo */ + ep->txFifoNum = XMC_USBD_lAssignTXFifo(); /* get tx fifo */ + data.b.txfnum = ep->txFifoNum; + xmc_device.endpoint_in_register[ep->address_u.address_st.number]->diepctl = data.d32; /* configure endpoint */ + daintmsk.ep.in |= (uint16_t)((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts for endpoint */ } if ((ep->address_u.address_st.direction == 0U) || (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL)) { /* is out */ - depctl_data_t data; - data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; - /*enable endpoint */ - data.b.usbactep = 1U; - /* set ep type */ - data.b.eptype = (uint8_t)ep_type; + depctl_data_t data; + data.d32 = xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl; + /*enable endpoint */ + data.b.usbactep = 1U; + /* set ep type */ + data.b.eptype = (uint8_t)ep_type; /* set mps */ if (ep_type == XMC_USBD_ENDPOINT_TYPE_CONTROL) - { - switch(ep_max_packet_size) - { - case (64U): - data.b.mps = 0x0U; - break; - case (32U): - data.b.mps = 0x1U; - break; - case (16U): - data.b.mps = 0x2U; - break; - case (8U): - data.b.mps = 0x3U; - break; - default: - break; - } - } - else - { - data.b.mps = ep_max_packet_size; - } - /* set first data0 pid */ - data.b.setd0pid = 1U; - /* clear stall */ - data.b.stall =(uint8_t) 0U; - xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; /* configure endpoint */ - daintmsk.ep.out |=(uint16_t) ((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts */ + { + switch (ep_max_packet_size) + { + case (64U): + data.b.mps = 0x0U; + break; + case (32U): + data.b.mps = 0x1U; + break; + case (16U): + data.b.mps = 0x2U; + break; + case (8U): + data.b.mps = 0x3U; + break; + default: + break; + } + } + else + { + data.b.mps = ep_max_packet_size; + } + /* set first data0 pid */ + data.b.setd0pid = 1U; + /* clear stall */ + data.b.stall = (uint8_t) 0U; + xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; /* configure endpoint */ + daintmsk.ep.out |= (uint16_t) ((uint16_t)1U << (uint8_t)ep->address_u.address_st.number); /* enable interrupts */ } xmc_device.device_register->daintmsk = daintmsk.d32; return XMC_USBD_STATUS_OK; @@ -1544,20 +1529,20 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(const uint8_t ep_addr, /** * Unconfigure the selected endpoint. **/ -XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(const uint8_t ep_addr) +XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(const uint8_t ep_addr) { XMC_USBD_EP_t *ep = &xmc_device.ep[ep_addr & (uint8_t)XMC_USBD_ENDPOINT_NUMBER_MASK]; depctl_data_t data; - daint_data_t daintmsk; - XMC_USBD_STATUS_t result; - uint32_t number_temp; - data.d32 = 0U; - daintmsk.d32 = xmc_device.device_register->daintmsk; + daint_data_t daintmsk; + XMC_USBD_STATUS_t result; + uint32_t number_temp; + data.d32 = 0U; + daintmsk.d32 = xmc_device.device_register->daintmsk; number_temp = (uint32_t)((uint32_t)1U << (uint8_t)ep->address_u.address_st.number); /* if not configured return an error */ if (!ep->isConfigured) { - result = XMC_USBD_STATUS_ERROR; + result = XMC_USBD_STATUS_ERROR; } else { @@ -1582,7 +1567,7 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(const uint8_t ep_addr) { xmc_device.endpoint_out_register[ep->address_u.address_st.number]->doepctl = data.d32; daintmsk.ep.out = (uint16_t)((uint32_t)daintmsk.ep.out & (~(uint32_t)number_temp)); - if(usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) + if (usbd_init->usbd_transfer_mode == XMC_USBD_USE_FIFO) { xmc_device.device_register->dtknqr4_fifoemptymsk &= ~number_temp; } @@ -1597,7 +1582,7 @@ XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(const uint8_t ep_addr) /** * Gets the current USB frame number **/ -uint16_t XMC_USBD_GetFrameNumber(void) +uint16_t XMC_USBD_GetFrameNumber(void) { uint16_t result; dsts_data_t dsts; @@ -1618,10 +1603,10 @@ uint32_t XMC_USBD_IsEnumDone(void) /*** * MISRA C 2004 Deviations - * + * * 1. cast from pointer to pointer [MISRA 2004 Rule 11.4] * 2. cast from pointer to unsigned int [Encompasses MISRA 2004 Rule 11.1], [MISRA 2004 Rule 11.3] * 3. call to function 'memset()' not made in the presence of a prototype [MISRA 2004 Rule 8.1] - * 4. No explicit type for symbol '_Bool', int assumed + * 4. No explicit type for symbol '_Bool', int assumed */ #endif /* defined(USB0) */ diff --git a/cores/xmc_lib/XMCLib/src/xmc_usbh.c b/cores/xmc_lib/XMCLib/src/xmc_usbh.c index 8b100139..86aadce8 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_usbh.c +++ b/cores/xmc_lib/XMCLib/src/xmc_usbh.c @@ -1,57 +1,49 @@ /** * @file xmc_usbh.c - * @date 2016-06-30 * * @cond - ********************************************************************************** - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * (To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - ********************************************************************************************************************* + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Change History - * -------------- + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2016-06-30: - * - Initial
    - * 2016-09-01: - * - Removed Keil specific exclusion
    - * - * @endcond + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** + * + * @endcond * */ -#include -#include - #include "xmc_usbh.h" -#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48)) +#if defined(USB0) && ((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48)) /*Function provides transfer result*/ static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl); @@ -71,14 +63,15 @@ static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state); static const XMC_USBH_DRIVER_VERSION_t xmc_usbh_driver_version = { XMC_USBH_API_VERSION, XMC_USBH_DRV_VERSION }; /*Variables to hold selected VBUS port pin*/ -XMC_GPIO_PORT_t * VBUS_port = XMC_GPIO_PORT3; -uint32_t VBUS_pin = 2U; +static XMC_GPIO_PORT_t *VBUS_port = XMC_GPIO_PORT3; +static uint32_t VBUS_pin = 2U; /*Array to track nack events on each pipe*/ -bool is_nack[USBH0_MAX_PIPE_NUM]; +static bool is_nack[USBH0_MAX_PIPE_NUM]; /* Driver Capabilities */ -static const XMC_USBH_CAPABILITIES_t xmc_usbh_driver_capabilities = { +static const XMC_USBH_CAPABILITIES_t xmc_usbh_driver_capabilities = +{ 0x0001U, /* Root HUB available Ports Mask */ 0U, /* Automatic SPLIT packet handling */ 1U, /* Signal Connect event */ @@ -86,20 +79,21 @@ static const XMC_USBH_CAPABILITIES_t xmc_usbh_driver_capabilities = { 0U /* Signal Overcurrent event */ }; /* Driver state and registers */ -static XMC_USBH0_DEVICE_t XMC_USBH0_device/* __attribute__((section ("RW_IRAM1")))*/ = { - (USB0_GLOBAL_TypeDef *)(USB0_BASE), /** Global register interface */ - ((USB0_CH_TypeDef *)(USB0_CH0_BASE)), /** Host channel interface */ - 0, /** Port event callback; set during init */ - 0, /** Pipe event callback; set during init */ - false, /** init status */ - XMC_USBH_POWER_OFF, /** USB Power status */ - false /** Port reset state */ +static XMC_USBH0_DEVICE_t XMC_USBH0_device/* __attribute__((section ("RW_IRAM1")))*/ = +{ + (USB0_GLOBAL_TypeDef *)(USB0_BASE), /** Global register interface */ + ((USB0_CH_TypeDef *)(USB0_CH0_BASE)), /** Host channel interface */ + 0, /** Port event callback; set during init */ + 0, /** Pipe event callback; set during init */ + false, /** init status */ + XMC_USBH_POWER_OFF, /** USB Power status */ + false /** Port reset state */ }; /*USB host pipe information. The array stores information related to packet id, data toggle, * pending data transfer information, periodic transfer interval, received data size etc for each * pipe.*/ -volatile XMC_USBH0_pipe_t pipe[USBH0_MAX_PIPE_NUM]; +static volatile XMC_USBH0_pipe_t pipe[USBH0_MAX_PIPE_NUM]; /* FIFO sizes in bytes (total available memory for FIFOs is 1.25 kB) */ #define RX_FIFO_SIZE (1128U) /* RxFIFO size */ @@ -119,11 +113,18 @@ static uint32_t *XMC_USBH0_dfifo_ptr[USBH0_MAX_PIPE_NUM]; __INLINE static void XMC_lClockGating(uint8_t enable) { #if defined(CLOCK_GATING_SUPPORTED) -if (enable == XMC_USBH_CLOCK_GATING_ENABLE) + if (enable == XMC_USBH_CLOCK_GATING_ENABLE) + { XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); - if (enable == XMC_USBH_CLOCK_GATING_DISABLE) + } + if (enable == XMC_USBH_CLOCK_GATING_DISABLE) + { XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0); + } +#else + XMC_UNUSED_ARG(enable); #endif + return; } @@ -150,7 +151,8 @@ __INLINE static void XMC_lTriggerHaltChannel(USB0_CH_TypeDef *ptr_ch) * Start transfer on Pipe. The function uses transfer complete interrupts to transfer data more than maximum * packet size. It takes care of updating data toggle information in subsequent packets related to the same data transfer. */ -static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr_ch) { +static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr_ch) +{ uint32_t hcchar; uint32_t hctsiz; uint32_t hcintmsk; @@ -193,15 +195,16 @@ static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr hctsiz &= (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; /* Packet specific setup */ - switch (ptr_pipe->packet & XMC_USBH_PACKET_TOKEN_Msk) { + switch (ptr_pipe->packet & XMC_USBH_PACKET_TOKEN_Msk) + { case XMC_USBH_PACKET_IN: /* set transfer direction to input */ hcchar |= (uint32_t)USB_CH_HCCHAR_EPDir_Msk; /* Enable IN transfer specific interrupts */ hcintmsk |= (uint32_t)( USB_CH_HCINTMSK_DataTglErrMsk_Msk | - USB_CH_HCINTMSK_BblErrMsk_Msk | - USB_CH_HCINTMSK_AckMsk_Msk | - USB_CH_HCINTMSK_NakMsk_Msk ) ; + USB_CH_HCINTMSK_BblErrMsk_Msk | + USB_CH_HCINTMSK_AckMsk_Msk | + USB_CH_HCINTMSK_NakMsk_Msk ) ; break; case XMC_USBH_PACKET_OUT: break; @@ -213,7 +216,8 @@ static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr break; } /* Prepare PID */ - switch (ptr_pipe->packet & XMC_USBH_PACKET_DATA_Msk) { + switch (ptr_pipe->packet & XMC_USBH_PACKET_DATA_Msk) + { case XMC_USBH_PACKET_DATA0: hctsiz &= (uint32_t)~USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk; hctsiz |= (uint32_t)USB_CH_HCTSIZx_DPID_DATA0; @@ -227,45 +231,55 @@ static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr } /* Prepare odd/even frame */ - if ((XMC_USBH0_device.global_register->HFNUM & 1U) != 0U) { + if ((XMC_USBH0_device.global_register->HFNUM & 1U) != 0U) + { hcchar &= (uint32_t)~USB_CH_HCCHAR_OddFrm_Msk; - } else { + } + else + { hcchar |= (uint32_t)USB_CH_HCCHAR_OddFrm_Msk; } - + /* Get transfer type specific status */ - switch (ptr_pipe->ep_type) { + switch (ptr_pipe->ep_type) + { case XMC_USBH_ENDPOINT_CONTROL: case XMC_USBH_ENDPOINT_BULK: - if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) { + if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) + { txsts = XMC_USBH0_device.global_register->GNPTXSTS; } break; case XMC_USBH_ENDPOINT_ISOCHRONOUS: case XMC_USBH_ENDPOINT_INTERRUPT: - if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) { + if (!(hcchar & USB_CH_HCCHAR_EPDir_Msk)) + { txsts = XMC_USBH0_device.global_register->HPTXSTS; } break; default: break; } - + /* Calculate remaining transfer size */ num_remaining_transfer = ptr_pipe->num - ptr_pipe->num_transferred_total; /* Limit transfer to available space inside fifo/queue if OUT transaction */ - if ((uint32_t)(hcchar & USB_CH_HCCHAR_EPDir_Msk) == 0U) { + if ((uint32_t)(hcchar & USB_CH_HCCHAR_EPDir_Msk) == 0U) + { max_pckt_size = ptr_pipe->ep_max_packet_size; num_remaining_fifo = (uint32_t)((uint32_t)(txsts & 0x0000FFFFU) << 2); num_remaining_queue = (uint32_t)((uint32_t)(txsts & 0x00FF0000U) >> 16); - if (num_remaining_transfer > num_remaining_fifo) { + if (num_remaining_transfer > num_remaining_fifo) + { num_remaining_transfer = num_remaining_fifo; } pckt_num = (uint32_t)((num_remaining_transfer + (max_pckt_size - 1U)) / max_pckt_size); - if (pckt_num > num_remaining_queue) { + if (pckt_num > num_remaining_queue) + { pckt_num = num_remaining_queue; } - if (num_remaining_transfer > (pckt_num * max_pckt_size)) { + if (num_remaining_transfer > (pckt_num * max_pckt_size)) + { num_remaining_transfer = pckt_num * max_pckt_size; } cnt = (uint16_t)((num_remaining_transfer + 3U) / 4U); @@ -275,15 +289,19 @@ static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr /* For OUT/SETUP transfer num_transferring represents num of bytes to be sent */ ptr_pipe->num_transferring = num_remaining_transfer; } - else { + else + { /* For IN transfer num_transferring is zero */ ptr_pipe->num_transferring = 0U; } /* Set packet count and transfer size */ - if (num_remaining_transfer != 0U) { + if (num_remaining_transfer != 0U) + { hctsiz |= (((num_remaining_transfer + ptr_pipe->ep_max_packet_size) - 1U) / ptr_pipe->ep_max_packet_size) << 19U; hctsiz |= num_remaining_transfer; - } else { /* Zero length packet */ + } + else /* Zero length packet */ + { hctsiz |= ((uint32_t)1U << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); /* Packet count = 1 */ hctsiz |= 0U; /* Transfer size = 0 */ } @@ -291,11 +309,12 @@ static bool XMC_lStartTransfer (XMC_USBH0_pipe_t *ptr_pipe, USB0_CH_TypeDef *ptr ptr_ch->HCINTMSK = hcintmsk; /* Enable channel interrupts */ ptr_ch->HCTSIZ_BUFFERMODE = hctsiz; /* Write ch transfer size */ ptr_ch->HCCHAR = hcchar; /* Write ch characteristics */ - while (cnt != 0U) { /* Load data */ + while (cnt != 0U) /* Load data */ + { #if defined __TASKING__/*tasking*/ *ptr_dest = *((__unaligned uint32_t *)ptr_src); #else/* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ - *ptr_dest = *((__packed uint32_t *)ptr_src); + *ptr_dest = *((uint32_t *)ptr_src); #endif ptr_src += 4U; cnt--; @@ -334,7 +353,8 @@ static XMC_USBH_CAPABILITIES_t XMC_USBH_GetCapabilities (void) { return xmc_usbh * XMC_USBH_Select_VBUS(), XMC_USBH_Uninitialize() \n */ static int32_t XMC_USBH_Initialize (XMC_USBH_SignalPortEvent_t cb_port_event, - XMC_USBH_SignalPipeEvent_t cb_pipe_event) { + XMC_USBH_SignalPipeEvent_t cb_pipe_event) +{ uint32_t channel; int32_t status = XMC_USBH_DRIVER_OK; @@ -349,12 +369,13 @@ static int32_t XMC_USBH_Initialize (XMC_USBH_SignalPortEvent_t cb_port_event, XMC_USBH0_device.SignalPipeEvent_cb = cb_pipe_event; /* assign fifo start addresses */ - for (channel = 0U; channel < USBH0_MAX_PIPE_NUM; channel++) { + for (channel = 0U; channel < USBH0_MAX_PIPE_NUM; channel++) + { XMC_USBH0_dfifo_ptr[channel] = (uint32_t *)((uint32_t)USB0_BASE + ((channel + 1U) * 0x01000U)); } XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); - + XMC_USBH0_device.init_done = true; } return status; @@ -368,7 +389,8 @@ static int32_t XMC_USBH_Initialize (XMC_USBH_SignalPortEvent_t cb_port_event, * \parRelated APIs:
    * XMC_USBH_Select_VBUS(), XMC_USBH_Initialize(), XMC_USBH_PortVbusOnOff() \n */ -static int32_t XMC_USBH_Uninitialize (void) { +static int32_t XMC_USBH_Uninitialize (void) +{ XMC_USBH0_device.init_done = false; (void)XMC_USBH_PowerControl(XMC_USBH_POWER_OFF); return XMC_USBH_DRIVER_OK; @@ -385,10 +407,12 @@ static int32_t XMC_USBH_Uninitialize (void) { * \parRelated APIs:
    * XMC_USBH_Select_VBUS(), XMC_USBH_Initialize(), XMC_USBH_PortVbusOnOff(), XMC_USBH_Uninitialize() \n */ -static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) { +static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) +{ int32_t status = XMC_USBH_DRIVER_OK; uint32_t loc_value; - switch (state) { + switch (state) + { case XMC_USBH_POWER_LOW: status = XMC_USBH_DRIVER_ERROR_UNSUPPORTED; break; @@ -456,22 +480,22 @@ static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) { XMC_USBH0_device.global_register->HCFG |= (uint32_t)(0x200U | USB_CH_HCFG_FSLSSUP(1)); /* Rx FIFO setting */ - XMC_USBH0_device.global_register->GRXFSIZ = (RX_FIFO_SIZE/4U); + XMC_USBH0_device.global_register->GRXFSIZ = (RX_FIFO_SIZE / 4U); /* Non-periodic Tx FIFO setting */ - XMC_USBH0_device.global_register->GNPTXFSIZ_HOSTMODE = (((uint32_t)(TX_FIFO_SIZE_NON_PERI/4U) << 16) | (RX_FIFO_SIZE / 4U)); + XMC_USBH0_device.global_register->GNPTXFSIZ_HOSTMODE = (((uint32_t)(TX_FIFO_SIZE_NON_PERI / 4U) << 16) | (RX_FIFO_SIZE / 4U)); /* Periodic Tx FIFO setting */ XMC_USBH0_device.global_register->HPTXFSIZ = ((uint32_t)(TX_FIFO_SIZE_PERI / 4U) << 16U) | ((RX_FIFO_SIZE + TX_FIFO_SIZE_NON_PERI) / 4U); /* Enable channel interrupts */ XMC_USBH0_device.global_register->HAINTMSK = ((uint32_t)1U << USBH0_MAX_PIPE_NUM) - 1U; /* Unmask interrupts */ XMC_USBH0_device.global_register->GINTMSK_HOSTMODE = ( - USB_GINTSTS_HOSTMODE_DisconnInt_Msk | - USB_GINTMSK_HOSTMODE_HChIntMsk_Msk | - USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk | - USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk | - USB_GINTMSK_HOSTMODE_SofMsk_Msk | - USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk - ) ; + USB_GINTSTS_HOSTMODE_DisconnInt_Msk | + USB_GINTMSK_HOSTMODE_HChIntMsk_Msk | + USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk | + USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk | + USB_GINTMSK_HOSTMODE_SofMsk_Msk | + USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk + ) ; /* Set powered state */ XMC_USBH0_device.power_state = state; /* Enable interrupts */ @@ -480,8 +504,6 @@ static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) { NVIC_SetPriority (USB0_0_IRQn, 0U); NVIC_EnableIRQ (USB0_0_IRQn); break; - default: - status = XMC_USBH_DRIVER_ERROR_UNSUPPORTED; } return status; } @@ -496,7 +518,8 @@ static int32_t XMC_USBH_PowerControl (XMC_USBH_POWER_STATE_t state) { * \parDescription:
    * Set USB port VBUS on/off. */ -static int32_t XMC_USBH_PortVbusOnOff (uint8_t port, bool vbus) { +static int32_t XMC_USBH_PortVbusOnOff (uint8_t port, bool vbus) +{ int32_t status = XMC_USBH_DRIVER_OK; if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) { @@ -510,11 +533,14 @@ static int32_t XMC_USBH_PortVbusOnOff (uint8_t port, bool vbus) { } else { - if (vbus != 0U) { + if (vbus != 0U) + { /* Port power on */ XMC_USBH0_device.global_register->HPRT |= (uint32_t)USB_HPRT_PrtPwr_Msk; XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1); - } else { + } + else + { /* Port power off */ XMC_USBH0_device.global_register->HPRT &= (uint32_t)~USB_HPRT_PrtPwr_Msk; XMC_GPIO_SetMode(VBUS_port, (uint8_t)VBUS_pin, XMC_GPIO_MODE_INPUT_TRISTATE); @@ -532,7 +558,8 @@ static int32_t XMC_USBH_PortVbusOnOff (uint8_t port, bool vbus) { * The function depends on implementation of XMC_USBH_osDelay() for 1ms delay to achieve required delay. * */ -static int32_t XMC_USBH_PortReset (uint8_t port) { +static int32_t XMC_USBH_PortReset (uint8_t port) +{ uint32_t hprt; int32_t status = XMC_USBH_DRIVER_OK; if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) @@ -650,7 +677,7 @@ static int32_t XMC_USBH_PortResume (uint8_t port) XMC_USBH0_device.global_register->HPRT = hprt; } } - + return status; } @@ -666,7 +693,7 @@ static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) { XMC_USBH_PORT_STATE_t port_state = { 0U, 0U, 0U }; uint32_t hprt; - + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) { /*Do not update the port state*/ @@ -680,7 +707,7 @@ static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) else { hprt = XMC_USBH0_device.global_register->HPRT; - if(((hprt & USB_HPRT_PrtConnSts_Msk) != 0U)) + if (((hprt & USB_HPRT_PrtConnSts_Msk) != 0U)) { port_state.connected = 1U; } @@ -690,12 +717,13 @@ static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) } port_state.overcurrent = 0U; - switch ((uint32_t)((uint32_t)(hprt & USB_HPRT_PrtSpd_Msk) >> USB_HPRT_PrtSpd_Pos)) { + switch ((uint32_t)((uint32_t)(hprt & USB_HPRT_PrtSpd_Msk) >> USB_HPRT_PrtSpd_Pos)) + { case 1U: /* Full speed */ - port_state.speed = XMC_USBH_SPEED_FULL; - break; + port_state.speed = XMC_USBH_SPEED_FULL; + break; default: - break; + break; } } } @@ -704,6 +732,9 @@ static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) /** * @param dev_addr Device address + * @param dev_speed Device speed + * @param hub_addr Hub address. This value should be 0 since hub is not supported. + * @param hub_port USB port number. Only one port(0) is supported. * @param ep_addr Device endpoint address \n * - ep_addr.0..3: Address \n * - ep_addr.7: Direction\n @@ -718,33 +749,38 @@ static XMC_USBH_PORT_STATE_t XMC_USBH_PortGetState (uint8_t port) * \parRelated APIs:
    * XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n */ -static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval) +static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval) { XMC_USBH0_pipe_t *ptr_pipe; USB0_CH_TypeDef *ptr_ch; uint32_t i; uint32_t loc_val; - + + XMC_UNUSED_ARG(hub_addr); + XMC_UNUSED_ARG(hub_port); + XMC_UNUSED_ARG(dev_speed); + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) { ptr_ch = (USB0_CH_TypeDef *)NULL; } else { - /* get first free pipe available */ + /* get first free pipe available */ ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers); - for (i = 0U; i < USBH0_MAX_PIPE_NUM; i++) { + for (i = 0U; i < USBH0_MAX_PIPE_NUM; i++) + { if ((ptr_ch->HCCHAR & 0x3FFFFFFFU) == 0U) { break; } ptr_ch++; } - + /* free pipe found? */ if (i == USBH0_MAX_PIPE_NUM) - { + { ptr_ch = (USB0_CH_TypeDef *)NULL; } else @@ -760,21 +796,23 @@ static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t ep_a { loc_val = 1U; } - ptr_ch->HCCHAR = ((uint32_t)(USB_CH_HCCHARx_MPS(ep_max_packet_size))| - USB_CH_HCCHARx_EPNUM(ep_addr)) | + ptr_ch->HCCHAR = ((uint32_t)(USB_CH_HCCHARx_MPS(ep_max_packet_size)) | + USB_CH_HCCHARx_EPNUM(ep_addr)) | (uint32_t)(USB_CH_HCCHAR_EPDir_Msk * loc_val) | (USB_CH_HCCHARx_EPTYPE (ep_type) ) | (USB_CH_HCCHARx_DEVADDR (dev_addr) ) ; /* Store Pipe settings */ ptr_pipe->ep_max_packet_size = ep_max_packet_size; ptr_pipe->ep_type = ep_type; - switch (ep_type) { + switch (ep_type) + { case XMC_USBH_ENDPOINT_CONTROL: case XMC_USBH_ENDPOINT_BULK: break; case XMC_USBH_ENDPOINT_ISOCHRONOUS: case XMC_USBH_ENDPOINT_INTERRUPT: - if (ep_interval > 0U) { + if (ep_interval > 0U) + { ptr_pipe->interval_reload = ep_interval; } ptr_pipe->interval = ptr_pipe->interval_reload; @@ -792,6 +830,9 @@ static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t ep_a /** * @param pipe_hndl Pointer returned by the pipe create function. It is the hardware based address of a USB channel. * @param dev_addr Device address to be configured for the pipe. + * @param dev_speed Device speed class. + * @param hub_addr Hub address. It should be 0 since hub is not supported. + * @param hub_port USB port number. Only one port(0) is supported. * @param ep_max_packet_size Endpoint maximum packet size * @return Execution_status * @@ -801,14 +842,17 @@ static XMC_USBH_PIPE_HANDLE XMC_USBH_PipeCreate (uint8_t dev_addr, uint8_t ep_a * \parRelated APIs:
    * XMC_USBH_PipeCreate(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n */ -static int32_t XMC_USBH_PipeModify (XMC_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_addr, uint16_t ep_max_packet_size) +static int32_t XMC_USBH_PipeModify (XMC_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint16_t ep_max_packet_size) { - XMC_USBH0_pipe_t *ptr_pipe; USB0_CH_TypeDef *ptr_ch; uint32_t hcchar; int32_t status = XMC_USBH_DRIVER_OK; + XMC_UNUSED_ARG(hub_addr); + XMC_UNUSED_ARG(hub_port); + XMC_UNUSED_ARG(dev_speed); + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) { status = XMC_USBH_DRIVER_ERROR; @@ -841,7 +885,7 @@ static int32_t XMC_USBH_PipeModify (XMC_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_ } } } - + return status; } @@ -855,7 +899,8 @@ static int32_t XMC_USBH_PipeModify (XMC_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_ * \parRelated APIs:
    * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeReset(), XMC_USBH_PipeTransfer() \n */ -static int32_t XMC_USBH_PipeDelete (XMC_USBH_PIPE_HANDLE pipe_hndl) { +static int32_t XMC_USBH_PipeDelete (XMC_USBH_PIPE_HANDLE pipe_hndl) +{ XMC_USBH0_pipe_t *ptr_pipe; USB0_CH_TypeDef *ptr_ch; int32_t status = XMC_USBH_DRIVER_OK; @@ -873,7 +918,7 @@ static int32_t XMC_USBH_PipeDelete (XMC_USBH_PIPE_HANDLE pipe_hndl) { else { ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); - ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); if (ptr_pipe->in_use != 0U) { status = XMC_USBH_DRIVER_ERROR_BUSY; @@ -902,7 +947,8 @@ static int32_t XMC_USBH_PipeDelete (XMC_USBH_PIPE_HANDLE pipe_hndl) { * \parRelated APIs:
    * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n */ -static int32_t XMC_USBH_PipeReset (XMC_USBH_PIPE_HANDLE pipe_hndl) { +static int32_t XMC_USBH_PipeReset (XMC_USBH_PIPE_HANDLE pipe_hndl) +{ XMC_USBH0_pipe_t *ptr_pipe; USB0_CH_TypeDef *ptr_ch; int32_t status = XMC_USBH_DRIVER_OK; @@ -920,7 +966,7 @@ static int32_t XMC_USBH_PipeReset (XMC_USBH_PIPE_HANDLE pipe_hndl) { else { ptr_ch = (USB0_CH_TypeDef *)(pipe_hndl); - ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); if (ptr_pipe->in_use != 0U) { status = XMC_USBH_DRIVER_ERROR_BUSY; @@ -952,20 +998,21 @@ static int32_t XMC_USBH_PipeReset (XMC_USBH_PIPE_HANDLE pipe_hndl) { * \parRelated APIs:
    * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeReset() \n */ -static int32_t XMC_USBH_PipeTransfer (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t packet, uint8_t *data, uint32_t num) { +static int32_t XMC_USBH_PipeTransfer (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t packet, uint8_t *data, uint32_t num) +{ XMC_USBH0_pipe_t *ptr_pipe; int32_t status = XMC_USBH_DRIVER_OK; if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) - { + { status = XMC_USBH_DRIVER_ERROR; } else { - if(!(((((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_OUT) || - ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_IN))) || - ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_SETUP ))) + if (!(((((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_OUT) || + ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_IN))) || + ((packet & XMC_USBH_PACKET_TOKEN_Msk) == XMC_USBH_PACKET_SETUP ))) { status = XMC_USBH_DRIVER_ERROR_PARAMETER; } @@ -1001,12 +1048,15 @@ static int32_t XMC_USBH_PipeTransfer (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t p ptr_pipe->interrupt_triggered = 0U; ptr_pipe->event = 0U; - if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->interval != 0U)) { + if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->interval != 0U)) + { ptr_pipe->in_use = 1U; /* transfer will be started inside interrupt (SOF) */ - } else { + } + else + { ptr_pipe->transfer_active = 1U; ptr_pipe->in_use = 1U; - if(XMC_lStartTransfer (ptr_pipe, (USB0_CH_TypeDef *)pipe_hndl) == false) + if (XMC_lStartTransfer (ptr_pipe, (USB0_CH_TypeDef *)pipe_hndl) == false) { status = XMC_USBH_DRIVER_ERROR; } @@ -1029,7 +1079,8 @@ static int32_t XMC_USBH_PipeTransfer (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t p * \parRelated APIs:
    * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n */ -static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl) { +static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl) +{ uint32_t status; if (pipe_hndl == 0U) { @@ -1052,14 +1103,15 @@ static uint32_t XMC_USBH_PipeTransferGetResult (XMC_USBH_PIPE_HANDLE pipe_hndl) * \parRelated APIs:
    * XMC_USBH_PipeCreate(), XMC_USBH_PipeModify(), XMC_USBH_PipeDelete(), XMC_USBH_PipeTransfer() \n */ -static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { +static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) +{ XMC_USBH0_pipe_t *ptr_pipe; USB0_CH_TypeDef *ptr_ch; uint32_t timeout; int32_t status = XMC_USBH_DRIVER_ERROR; - + ptr_ch = (USB0_CH_TypeDef *) pipe_hndl; - + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) { /*Error in power state*/ @@ -1074,7 +1126,8 @@ static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { { ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[(ptr_ch - (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers))]); - if (ptr_pipe->in_use != 0U) { + if (ptr_pipe->in_use != 0U) + { ptr_pipe->in_use = 0U; /* Disable channel if not yet halted */ if ((ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) == 0U) @@ -1083,7 +1136,8 @@ static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { { ptr_ch->HCINTMSK = 0U; (void)XMC_USBH_osDelay(1U); - if (ptr_ch->HCINT & USB_CH_HCINT_NAK_Msk) { + if (ptr_ch->HCINT & USB_CH_HCINT_NAK_Msk) + { ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ status = XMC_USBH_DRIVER_OK; } @@ -1093,8 +1147,10 @@ static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { ptr_ch->HCCHAR = (uint32_t)(ptr_ch->HCCHAR | USB_CH_HCCHAR_ChEna_Msk | USB_CH_HCCHAR_ChDis_Msk); /* wait until channel is halted */ - for (timeout = 0U; timeout < 5000U; timeout++) { - if (ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) { + for (timeout = 0U; timeout < 5000U; timeout++) + { + if (ptr_ch->HCINT & USB_CH_HCINT_ChHltd_Msk) + { ptr_ch->HCINT = USB_CH_HCINTx_ALL; status = XMC_USBH_DRIVER_OK; } @@ -1118,7 +1174,7 @@ static int32_t XMC_USBH_PipeTransferAbort (XMC_USBH_PIPE_HANDLE pipe_hndl) { static uint16_t XMC_USBH_GetFrameNumber (void) { uint16_t status; - + if (XMC_USBH0_device.power_state == XMC_USBH_POWER_OFF) { status = 0U; @@ -1142,7 +1198,8 @@ static uint16_t XMC_USBH_GetFrameNumber (void) * is transmitted for an OUT transaction. * */ -void XMC_USBH_HandleIrq (uint32_t gintsts) { +void XMC_USBH_HandleIrq (uint32_t gintsts) +{ XMC_USBH0_pipe_t *ptr_pipe; USB0_CH_TypeDef *ptr_ch; uint32_t hprt, haint, hcint, pktcnt, mpsiz; @@ -1150,39 +1207,49 @@ void XMC_USBH_HandleIrq (uint32_t gintsts) { uint8_t *ptr_data; uint32_t *dfifo; uint32_t grxsts, bcnt, dat, len, len_rest; - + /* Host port interrupt */ - if ((gintsts & USB_GINTSTS_HOSTMODE_PrtInt_Msk) != 0U) { + if ((gintsts & USB_GINTSTS_HOSTMODE_PrtInt_Msk) != 0U) + { hprt = XMC_USBH0_device.global_register->HPRT; /* Clear port enable */ XMC_USBH0_device.global_register->HPRT = hprt & (uint32_t)(~USB_HPRT_PrtEna_Msk); - if ((hprt & USB_HPRT_PrtConnDet_Msk) != 0U) { + if ((hprt & USB_HPRT_PrtConnDet_Msk) != 0U) + { XMC_USBH0_device.global_register->HCFG = (0x200U | (USB_CH_HCFG_FSLSPCS(1) | - USB_CH_HCFG_FSLSSUP(1))); + USB_CH_HCFG_FSLSSUP(1))); /* Ignore connect under reset */ - if (XMC_USBH0_device.port_reset_active == false) { + if (XMC_USBH0_device.port_reset_active == false) + { XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_CONNECT); } } - if ((hprt & USB_HPRT_PrtEnChng_Msk) != 0U) { /* If port enable changed */ - if ((hprt & USB_HPRT_PrtEna_Msk) != 0U) { /* If device connected */ - if (XMC_USBH0_device.port_reset_active == true) { + if ((hprt & USB_HPRT_PrtEnChng_Msk) != 0U) /* If port enable changed */ + { + if ((hprt & USB_HPRT_PrtEna_Msk) != 0U) /* If device connected */ + { + if (XMC_USBH0_device.port_reset_active == true) + { XMC_USBH0_device.port_reset_active = false; XMC_USBH0_device.SignalPortEvent_cb(0U, XMC_USBH_EVENT_RESET); } } } } - + /* Disconnect interrupt */ - if ((gintsts & USB_GINTSTS_HOSTMODE_DisconnInt_Msk) != 0U) { + if ((gintsts & USB_GINTSTS_HOSTMODE_DisconnInt_Msk) != 0U) + { XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_DisconnInt_Msk; /* Clear disconnect interrupt */ /* Ignore disconnect under reset */ - if ( XMC_USBH0_device.port_reset_active == false) { + if ( XMC_USBH0_device.port_reset_active == false) + { ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers); - ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); - for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { - if (ptr_pipe->in_use != 0U) { + ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) + { + if (ptr_pipe->in_use != 0U) + { ptr_pipe->in_use = 0U; ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* Clear all interrupts */ ptr_ch->HCINTMSK = USB_CH_HCINT_ChHltd_Msk; /* Enable halt interrupt */ @@ -1196,37 +1263,43 @@ void XMC_USBH_HandleIrq (uint32_t gintsts) { } } /* Handle receive fifo not-empty interrupt */ - if ((gintsts & USB_GINTSTS_HOSTMODE_RxFLvl_Msk) != 0U) { + if ((gintsts & USB_GINTSTS_HOSTMODE_RxFLvl_Msk) != 0U) + { XMC_USBH0_device.global_register->GINTMSK_HOSTMODE &= (uint32_t)~USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk; - grxsts = (XMC_USBH0_device.global_register->GRXSTSP_HOSTMODE); + grxsts = (XMC_USBH0_device.global_register->GRXSTSP_HOSTMODE); /* IN Data Packet received ? */ - if ((uint32_t)((grxsts >> 17U) & 0x0FU) == (uint32_t)USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT) { + if ((uint32_t)((grxsts >> 17U) & 0x0FU) == (uint32_t)USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT) + { ch = (uint32_t)(grxsts & USB_GRXSTSR_DEVICEMODE_EPNum_Msk); bcnt = ((uint32_t)(grxsts & USB_GRXSTSR_DEVICEMODE_BCnt_Msk) >> USB_GRXSTSR_DEVICEMODE_BCnt_Pos); dfifo = (uint32_t *)XMC_USBH0_dfifo_ptr[ch]; - ptr_data = pipe[ch].data + pipe[ch].num_transferred_total; + ptr_data = pipe[ch].data; + ptr_data += pipe[ch].num_transferred_total; len = bcnt / 4U; /* Received number of 32-bit data */ len_rest = bcnt & 3U; /* Number of bytes left */ /* Read data from fifo */ /* Read 32 bit sized data */ - while (len != 0U) { + while (len != 0U) + { #if defined __TASKING__/*tasking*/ *((__unaligned uint32_t *)ptr_data) = *dfifo; #else /* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ - *((__packed uint32_t *)ptr_data) = *dfifo; + *((uint32_t *)ptr_data) = *dfifo; #endif ptr_data += 4U; len--; } /* Read 8 bit sized data */ - if (len_rest != 0U) { + if (len_rest != 0U) + { #if defined __TASKING__/*tasking*/ dat = *((__unaligned uint32_t *)dfifo); #else /* defined (__GNUC__) || defined (__CC_ARM) || defined (__ICCARM__)*/ - dat = *((__packed uint32_t *)dfifo); + dat = *((uint32_t *)dfifo); #endif - while (len_rest != 0U) { + while (len_rest != 0U) + { *ptr_data = (uint8_t)dat; ptr_data++; dat >>= 8; @@ -1240,12 +1313,15 @@ void XMC_USBH_HandleIrq (uint32_t gintsts) { } /* Handle sof interrupt */ - if ((gintsts & USB_GINTSTS_HOSTMODE_Sof_Msk) != 0U) { /* If start of frame interrupt */ + if ((gintsts & USB_GINTSTS_HOSTMODE_Sof_Msk) != 0U) /* If start of frame interrupt */ + { XMC_USBH0_device.global_register->GINTSTS_HOSTMODE = USB_GINTSTS_HOSTMODE_Sof_Msk; /* Clear SOF interrupt */ ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); - for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) + { /* If interrupt transfer is active handle period (interval) */ - if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->in_use == 1U)) { + if ((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->in_use == 1U)) + { if (ptr_pipe->interval != 0U) { ptr_pipe->interval--; @@ -1259,109 +1335,135 @@ void XMC_USBH_HandleIrq (uint32_t gintsts) { ptr_pipe++; } } - + /* Handle host ctrl interrupt */ - if ((gintsts & USB_GINTSTS_HOSTMODE_HChInt_Msk) != 0U) { + if ((gintsts & USB_GINTSTS_HOSTMODE_HChInt_Msk) != 0U) + { haint = XMC_USBH0_device.global_register->HAINT; - for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) + { /* Check for interrupt of all channels */ - if ((haint & (uint32_t)((uint32_t)1U << ch)) != 0U) { + if ((haint & (uint32_t)((uint32_t)1U << ch)) != 0U) + { haint &= (uint32_t)~((uint32_t)1U << ch); ptr_ch = (USB0_CH_TypeDef *)(XMC_USBH0_device.host_channel_registers) + ch; - ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[ch]); + ptr_pipe = (XMC_USBH0_pipe_t *)(&pipe[ch]); /*Local variable for HCINT*/ dat = ptr_ch->HCINT; hcint = (uint32_t)(dat & ptr_ch->HCINTMSK); - if ((hcint & USB_CH_HCINT_ChHltd_Msk) != 0U) { /* channel halted ? */ + if ((hcint & USB_CH_HCINT_ChHltd_Msk) != 0U) /* channel halted ? */ + { ptr_ch->HCINTMSK = 0U; /* disable all channel interrupts */ ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* clear all interrupts */ ptr_pipe->transfer_active = 0U; /* set status transfer not active */ hcint = 0U; } - if ((hcint & USB_CH_HCINT_XferCompl_Msk) != 0U) { /* data transfer finished ? */ + if ((hcint & USB_CH_HCINT_XferCompl_Msk) != 0U) /* data transfer finished ? */ + { ptr_ch->HCINT = USB_CH_HCINTx_ALL; /* clear all interrupts */ - if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) == 0U) { /* endpoint OUT ? */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) == 0U) /* endpoint OUT ? */ + { ptr_ch->HCINTMSK = 0U; /* disable all channel interrupts */ ptr_pipe->transfer_active = 0U; /* transfer not in progress */ ptr_pipe->num_transferred_total += ptr_pipe->num_transferring; /* admin OUT transfer status */ ptr_pipe->num_transferring = 0U; /* admin OUT transfer status */ - if (ptr_pipe->num_transferred_total == ptr_pipe->num) { /* all bytes transferred ? */ + if (ptr_pipe->num_transferred_total == ptr_pipe->num) /* all bytes transferred ? */ + { ptr_pipe->in_use = 0U; /* release pipe */ ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_TRANSFER_COMPLETE; /* prepare event notification */ - } - hcint = 0U; - } - if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + } + hcint = 0U; + } + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) /* endpoint IN ? */ + { ptr_pipe->in_use = 0U; /* release pipe */ ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_TRANSFER_COMPLETE; /* prepare event notification */ XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ } } - if ((hcint & USB_CH_HCINTMSK_AckMsk_Msk) != 0U) { /* ACK received ? */ + if ((hcint & USB_CH_HCINTMSK_AckMsk_Msk) != 0U) /* ACK received ? */ + { ptr_ch->HCINT = USB_CH_HCINTMSK_AckMsk_Msk; /* clear ACK interrupt */ is_nack[ch] = false; - if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) /* endpoint IN ? */ + { if ((ptr_pipe->num != ptr_pipe->num_transferred_total) && /* if all data was not transferred */ (ptr_pipe->num_transferring != 0U) && /* if zero-length packet was not received */ - ((ptr_pipe->num_transferred_total%ptr_pipe->ep_max_packet_size) == 0U)){ /* if short packet was not received */ - ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ + ((ptr_pipe->num_transferred_total % ptr_pipe->ep_max_packet_size) == 0U)) /* if short packet was not received */ + { + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ } - } else { /* endpoint OUT */ + } + else /* endpoint OUT */ + { XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ - } + } hcint = 0U; } /*local variable for HCCHAR*/ dat = ptr_ch->HCCHAR; if (((hcint & (USB_CH_HCINTMSK_StallMsk_Msk | /* STALL */ - USB_CH_HCINTMSK_NakMsk_Msk | /* or NAK */ - USB_CH_HCINTx_ERRORS )) != 0U) && /* or transaction error */ + USB_CH_HCINTMSK_NakMsk_Msk | /* or NAK */ + USB_CH_HCINTx_ERRORS )) != 0U) && /* or transaction error */ ((dat & USB_CH_HCCHAR_EPDir_Msk) == 0U)) - { /* and endpoint OUT */ + { + /* and endpoint OUT */ - pktcnt = (uint32_t)((ptr_ch->HCTSIZ_BUFFERMODE & USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk) /* administrate OUT transfer status */ - >> USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); - mpsiz = (ptr_ch->HCCHAR ) & 0x000007FFU; - if ((ptr_pipe->num_transferring >= mpsiz) && (pktcnt > 0U)) { - ptr_pipe->num_transferred_total += (uint32_t)(ptr_pipe->num_transferring - (mpsiz * pktcnt)); - } - ptr_pipe->num_transferring = 0U; + pktcnt = (uint32_t)((ptr_ch->HCTSIZ_BUFFERMODE & USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk) /* administrate OUT transfer status */ + >> USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos); + mpsiz = (ptr_ch->HCCHAR ) & 0x000007FFU; + if ((ptr_pipe->num_transferring >= mpsiz) && (pktcnt > 0U)) + { + ptr_pipe->num_transferred_total += (uint32_t)(ptr_pipe->num_transferring - (mpsiz * pktcnt)); + } + ptr_pipe->num_transferring = 0U; } - if ((hcint & USB_CH_HCINTMSK_NakMsk_Msk)!=0U) { /* if NAK */ - is_nack[ch] = true; - ptr_pipe->event |= (uint8_t)XMC_USBH_EVENT_HANDSHAKE_NAK; - ptr_ch->HCINT = USB_CH_HCINTMSK_NakMsk_Msk; /* clear NAK interrupt */ - if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) { /* endpoint IN ? */ - if (ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) { /* is endpoint of type interrupt ? */ - XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt (after halted will be restarted in next sof) */ - } else { /* is endpoint not of type interrupt ?*/ - ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ - } - } else { /* If endpoint OUT */ /* endpoint OUT ? */ - XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + if ((hcint & USB_CH_HCINTMSK_NakMsk_Msk) != 0U) /* if NAK */ + { + is_nack[ch] = true; + ptr_pipe->event |= (uint8_t)XMC_USBH_EVENT_HANDSHAKE_NAK; + ptr_ch->HCINT = USB_CH_HCINTMSK_NakMsk_Msk; /* clear NAK interrupt */ + if ((ptr_ch->HCCHAR & USB_CH_HCCHAR_EPDir_Msk) != 0U) /* endpoint IN ? */ + { + if (ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) /* is endpoint of type interrupt ? */ + { + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt (after halted will be restarted in next sof) */ } - hcint = 0U; + else /* is endpoint not of type interrupt ?*/ + { + ptr_ch->HCCHAR |= (uint32_t)USB_CH_HCCHAR_ChEna_Msk; /* trigger next transfer */ + } + } + else + { + /* If endpoint OUT */ /* endpoint OUT ? */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + } + hcint = 0U; } - if ((hcint & USB_CH_HCINTMSK_StallMsk_Msk) != 0U) { /* if STALL */ - /*Reset the packet data toggle*/ - ptr_ch->HCINT = USB_CH_HCINTMSK_StallMsk_Msk; /* clear STALL interrupt */ - ptr_pipe->in_use = 0U; /* release pipe */ - ptr_pipe->packet &= (uint32_t)(~XMC_USBH_PACKET_DATA_Msk); - ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; - ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_HANDSHAKE_STALL; /* prepare event notification */ - XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ - hcint = 0U; - } - if ((hcint & USB_CH_HCINTx_ERRORS) != 0U) { /* if transaction error */ - ptr_ch->HCINT = USB_CH_HCINTx_ERRORS; /* clear all error interrupt */ - ptr_pipe->in_use = 0U; /* release pipe */ - ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_BUS_ERROR; /* prepare event notification */ - XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ - hcint = 0U; + if ((hcint & USB_CH_HCINTMSK_StallMsk_Msk) != 0U) /* if STALL */ + { + /*Reset the packet data toggle*/ + ptr_ch->HCINT = USB_CH_HCINTMSK_StallMsk_Msk; /* clear STALL interrupt */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->packet &= (uint32_t)(~XMC_USBH_PACKET_DATA_Msk); + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_HANDSHAKE_STALL; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + hcint = 0U; + } + if ((hcint & USB_CH_HCINTx_ERRORS) != 0U) /* if transaction error */ + { + ptr_ch->HCINT = USB_CH_HCINTx_ERRORS; /* clear all error interrupt */ + ptr_pipe->in_use = 0U; /* release pipe */ + ptr_pipe->event = (uint8_t)XMC_USBH_EVENT_BUS_ERROR; /* prepare event notification */ + XMC_lTriggerHaltChannel(ptr_ch); /* trigger channel halt */ + hcint = 0U; } - if ((ptr_pipe->transfer_active == 0U) && (ptr_pipe->in_use == 0U) && (ptr_pipe->event != 0U)) { + if ((ptr_pipe->transfer_active == 0U) && (ptr_pipe->in_use == 0U) && (ptr_pipe->event != 0U)) + { XMC_USBH0_device.SignalPipeEvent_cb((XMC_USBH_EP_HANDLE)ptr_ch, (uint32_t)ptr_pipe->event); ptr_pipe->event = 0U; } @@ -1380,35 +1482,37 @@ void XMC_USBH_HandleIrq (uint32_t gintsts) { /* Handle restarts of unfinished transfers (due to NAK or ACK) */ ptr_pipe = (XMC_USBH0_pipe_t *)(pipe); - for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) { - if ((ptr_pipe->in_use == 1U) && (ptr_pipe->transfer_active == 0U)) { + for (ch = 0U; ch < USBH0_MAX_PIPE_NUM; ch++) + { + if ((ptr_pipe->in_use == 1U) && (ptr_pipe->transfer_active == 0U)) + { /* Restart periodic transfer if not in progress and interval expired */ - if (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) + if (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) { - /*Data toggle if NACK not received*/ - if (!is_nack[ch]) - { - switch (ptr_pipe->packet & (uint32_t)XMC_USBH_PACKET_DATA_Msk) - { - case XMC_USBH_PACKET_DATA0: - ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; - ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA1; - break; - case XMC_USBH_PACKET_DATA1: - ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; - ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; - break; - default: - break; - } - } - else - { - is_nack[ch] = false; - } + /*Data toggle if NACK not received*/ + if (!is_nack[ch]) + { + switch (ptr_pipe->packet & (uint32_t)XMC_USBH_PACKET_DATA_Msk) + { + case XMC_USBH_PACKET_DATA0: + ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA1; + break; + case XMC_USBH_PACKET_DATA1: + ptr_pipe->packet &= (uint32_t)~XMC_USBH_PACKET_DATA_Msk; + ptr_pipe->packet |= (uint32_t)XMC_USBH_PACKET_DATA0; + break; + default: + break; + } + } + else + { + is_nack[ch] = false; + } } - if (((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)&&(ptr_pipe->interrupt_triggered == 1U))|| - (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)) + if (((ptr_pipe->ep_type == (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT) && (ptr_pipe->interrupt_triggered == 1U)) || + (ptr_pipe->ep_type != (uint8_t)XMC_USBH_ENDPOINT_INTERRUPT)) { ptr_pipe->interrupt_triggered = 0U; ptr_pipe->transfer_active = 1U; @@ -1426,7 +1530,7 @@ uint32_t XMC_USBH_GetInterruptStatus(void) } /*Function selects the port pin used as DRIVEVBUS*/ -void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin) +void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t *port, uint32_t pin) { VBUS_port = port; VBUS_pin = pin; @@ -1449,7 +1553,8 @@ void XMC_USBH_TurnOffResumeBit(void) /*USB host driver assembling all the implementation into a single CMSIS compliant structure type*/ -XMC_USBH_DRIVER_t Driver_USBH0 = { +const XMC_USBH_DRIVER_t Driver_USBH0 = +{ XMC_USBH_GetVersion, XMC_USBH_GetCapabilities, XMC_USBH_Initialize, @@ -1472,8 +1577,9 @@ XMC_USBH_DRIVER_t Driver_USBH0 = { /*Weak definition of delay function*/ -__WEAK uint8_t XMC_USBH_osDelay( ) +__WEAK uint8_t XMC_USBH_osDelay(uint32_t MS) { + (void)MS; /*A precise time delay implementation for this function has to be provided*/ while (1) { diff --git a/cores/xmc_lib/XMCLib/src/xmc_usic.c b/cores/xmc_lib/XMCLib/src/xmc_usic.c index b849c63f..3ec7747e 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_usic.c +++ b/cores/xmc_lib/XMCLib/src/xmc_usic.c @@ -1,59 +1,41 @@ /** * @file xmc_usic.c - * @date 2015-09-01 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial draft
    - * - Documentation improved
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-05-08: - * - Clearing bit fields PDIV, PCTQ, PPPEN in XMC_USIC_CH_SetBaudrate() API
    - * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-08-27: - * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG()
    + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-08-28: - * - Added asserts to XMC_USIC_CH_ConfigExternalInputSignalToBRG()
    - * - * 2015-09-01: - * - Fixed warning in the asserts
    + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond * @@ -66,6 +48,8 @@ #include "xmc_usic.h" #include "xmc_scu.h" +#include /* abs */ + /******************************************************************************* * MACROS *******************************************************************************/ @@ -85,13 +69,13 @@ void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel) XMC_USIC_Enable(XMC_USIC0); } #if defined(USIC1) - else if((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)) + else if ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1)) { XMC_USIC_Enable(XMC_USIC1); } #endif #if defined(USIC2) - else if((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)) + else if ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1)) { XMC_USIC_Enable(XMC_USIC2); } @@ -112,26 +96,24 @@ void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel) channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk; } - void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel) { channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) | USIC_CH_KSCFG_BPMODEN_Msk); } - XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling) { XMC_USIC_CH_STATUS_t status; - + uint32_t peripheral_clock; - + uint32_t clock_divider; uint32_t clock_divider_min; uint32_t pdiv; uint32_t pdiv_int; uint32_t pdiv_int_min; - + uint32_t pdiv_frac; uint32_t pdiv_frac_min; @@ -140,17 +122,18 @@ XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint3 { peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / 100U; rate = rate / 100U; - clock_divider_min = 1U; + + clock_divider_min = 1024U; pdiv_int_min = 1U; pdiv_frac_min = 0x3ffU; - for(clock_divider = 1023U; clock_divider > 0U; --clock_divider) + for (clock_divider = 1024U; clock_divider > 0U; --clock_divider) { pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling)); pdiv_int = pdiv >> 10U; pdiv_frac = pdiv & 0x3ffU; - if ((pdiv_int < 1024U) && (pdiv_frac < pdiv_frac_min)) + if ((pdiv_int <= 1024U) && (pdiv_frac < pdiv_frac_min)) { pdiv_frac_min = pdiv_frac; pdiv_int_min = pdiv_int; @@ -159,7 +142,7 @@ XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint3 } channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL | - (clock_divider_min << USIC_CH_FDR_STEP_Pos); + ((clock_divider_min - 1) << USIC_CH_FDR_STEP_Pos); channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | USIC_CH_BRG_PDIV_Msk | @@ -167,22 +150,178 @@ XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint3 USIC_CH_BRG_PPPEN_Msk)) | ((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) | ((pdiv_int_min - 1U) << USIC_CH_BRG_PDIV_Pos); - + status = XMC_USIC_CH_STATUS_OK; } - else + else { status = XMC_USIC_CH_STATUS_ERROR; } - + return status; } +XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, int32_t rate, int32_t oversampling) +{ + int32_t peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + int32_t brg_clock = rate * oversampling; + int32_t actual_rate_upper; + int32_t actual_rate_lower; + uint32_t pdiv = 1; + uint32_t divider_step; + XMC_USIC_CH_STATUS_t status; + + if (peripheral_clock > brg_clock) + { + divider_step = peripheral_clock / brg_clock; // integer division gets truncated + while (divider_step >= 1023) + { + pdiv++; + brg_clock = rate * oversampling * pdiv; + divider_step = peripheral_clock / brg_clock; // integer division gets truncated + } + actual_rate_upper = peripheral_clock / (divider_step * oversampling * pdiv); + actual_rate_lower = peripheral_clock / ((divider_step + 1) * oversampling * pdiv); + + // choose better approximation if the peripheral frequency is not a multiple of the baudrate + if (abs(rate - actual_rate_lower) < abs(rate - actual_rate_upper)) + { + divider_step += 1; + } + + divider_step = 1024 - divider_step; + + + channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL | + (divider_step << USIC_CH_FDR_STEP_Pos); + + channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | + USIC_CH_BRG_PDIV_Msk | + USIC_CH_BRG_PCTQ_Msk | + USIC_CH_BRG_PPPEN_Msk)) | + ((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) | + ((pdiv - 1) << USIC_CH_BRG_PDIV_Pos); + + status = XMC_USIC_CH_STATUS_OK; + } + else + { + status = XMC_USIC_CH_STATUS_ERROR; + } + + return status; +} + +void XMC_USIC_CH_SetBaudrateDivider(XMC_USIC_CH_t *const channel, + XMC_USIC_CH_BRG_CLOCK_SOURCE_t clksel, + bool pppen, + uint32_t pdiv, + XMC_USIC_CH_BRG_CTQSEL_t ctqsel, + uint32_t pctq, + uint32_t dctq) +{ + uint32_t regval = channel->BRG; + regval &= (uint32_t)~(USIC_CH_BRG_CLKSEL_Msk | USIC_CH_BRG_PPPEN_Msk | USIC_CH_BRG_PDIV_Msk | USIC_CH_BRG_CTQSEL_Msk | USIC_CH_BRG_PCTQ_Msk | USIC_CH_BRG_DCTQ_Msk); + regval |= clksel | (pppen ? USIC_CH_BRG_PPPEN_Msk : 0) | (pdiv << USIC_CH_BRG_PDIV_Pos) | ctqsel | (pctq << USIC_CH_BRG_PCTQ_Pos) | (dctq << USIC_CH_BRG_DCTQ_Pos); + channel->BRG = regval; +} + +uint32_t XMC_USIC_CH_GetBaudrate(XMC_USIC_CH_t *const channel) +{ + uint32_t divider; + if ((channel->BRG & USIC_CH_BRG_CTQSEL_Msk) == USIC_CH_BRG_CTQSEL_Msk) + { + // CTQSEL = 3 + divider = 2; + } + else + { + // CTQSEL = 0, 1, or 2 + divider = (channel->BRG & USIC_CH_BRG_PPPEN_Msk) ? 2 : 1; + + if ((((channel->BRG & USIC_CH_BRG_CTQSEL_Msk) >> USIC_CH_BRG_CTQSEL_Pos) & 0x1) == 0) + { + // CTQSEL = 0 or 2 + divider *= ((channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos) + 1; + if ((((channel->BRG & USIC_CH_BRG_CTQSEL_Msk) >> USIC_CH_BRG_CTQSEL_Pos) & 0x2) != 0) + { + // CTQSEL = 2 + divider *= 2; + } + } + } + + divider *= ((channel->BRG & USIC_CH_BRG_PCTQ_Msk) >> USIC_CH_BRG_PCTQ_Pos) + 1; + divider *= ((channel->BRG & USIC_CH_BRG_DCTQ_Msk) >> USIC_CH_BRG_DCTQ_Pos) + 1; + + uint32_t fperi = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + float baudrate; + if ((channel->FDR & USIC_CH_FDR_DM_Msk) == XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL) + { + baudrate = fperi * (((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos) / 1024.0F); + } + else + { + /* Normal divider mode */ + baudrate = fperi * (1.0F / (1024 - ((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos))); + } + + baudrate /= divider; + + return (uint32_t)baudrate; +} + +uint32_t XMC_USIC_CH_GetSCLKFrequency(XMC_USIC_CH_t *const channel) +{ + uint32_t divider; + divider = (channel->BRG & USIC_CH_BRG_PPPEN_Msk) ? 2 : 1; + divider *= ((channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos) + 1; + divider *= 2; + + uint32_t fperi = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + float baudrate; + if ((channel->FDR & USIC_CH_FDR_DM_Msk) == XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL) + { + /* Fractional divider mode */ + baudrate = fperi * (((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos) / 1024.0F); + } + else + { + /* Normal divider mode */ + baudrate = fperi * (1.0F / (1024 - ((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos))); + } + + baudrate /= divider; + + return (uint32_t)baudrate; +} + +uint32_t XMC_USIC_CH_GetMCLKFrequency(XMC_USIC_CH_t *const channel) +{ + uint32_t fperi = XMC_SCU_CLOCK_GetPeripheralClockFrequency(); + + float baudrate; + if ((channel->FDR & USIC_CH_FDR_DM_Msk) == XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL) + { + /* Fractional divider mode */ + baudrate = fperi * (1.0F / (1024 - ((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos))); + } + else + { + /* Normal divider mode */ + baudrate = fperi / (((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos) / 1024.0F); + } + + baudrate /= 2; + + return (uint32_t)baudrate; +} + void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, - const uint16_t pdiv, - const uint32_t oversampling, - const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) + const uint16_t pdiv, + const uint32_t oversampling, + const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode) { XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Divider out of range", ((1U < pdiv) || (pdiv < 1024U))); XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Oversampling out of range", ((1U < oversampling) || (oversampling < 32U))); @@ -191,18 +330,17 @@ void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel, XMC_USIC_CH_SetBRGInputClockSource(channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T); /* Setting the trigger combination mode */ - XMC_USIC_CH_SetInputTriggerCombinationMode(channel,XMC_USIC_CH_INPUT_DX1,combination_mode); + XMC_USIC_CH_SetInputTriggerCombinationMode(channel, XMC_USIC_CH_INPUT_DX1, combination_mode); /* Configuring the dividers and oversampling */ channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk | USIC_CH_BRG_PDIV_Msk | USIC_CH_BRG_PCTQ_Msk | USIC_CH_BRG_PPPEN_Msk)) | - (((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) | - (((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos); + (((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) | + (((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos); } - void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, const uint32_t data_pointer, const XMC_USIC_CH_FIFO_SIZE_t size, @@ -211,18 +349,17 @@ void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel, /* Disable FIFO */ channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk; - /* LOF = 0, A standard transmit buffer event occurs when the filling level - * equals the limit value and gets lower due to transmission of a data word - * STBTEN = 0, the trigger of the standard transmit buffer event is based on - * the transition of the fill level from equal to below the limit, not the - * fact being below + /* LOF = 0, A standard transmit buffer event occurs when the filling level equals the limit value and gets + * lower due to transmission of a data word + * STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level + * from equal to below the limit, not the fact being below */ channel->TBCTR = (uint32_t)(channel->TBCTR & (uint32_t)~(USIC_CH_TBCTR_LIMIT_Msk | - USIC_CH_TBCTR_DPTR_Msk | - USIC_CH_TBCTR_SIZE_Msk)) | + USIC_CH_TBCTR_DPTR_Msk | + USIC_CH_TBCTR_SIZE_Msk)) | (uint32_t)((limit << USIC_CH_TBCTR_LIMIT_Pos) | - (data_pointer << USIC_CH_TBCTR_DPTR_Pos) | - ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); + (data_pointer << USIC_CH_TBCTR_DPTR_Pos) | + ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); } @@ -234,150 +371,146 @@ void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel, /* Disable FIFO */ channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk; - /* LOF = 1, A standard receive buffer event occurs when the filling level - * equals the limit value and gets bigger due to the reception of a new data word + /* LOF = 1, A standard receive buffer event occurs when the filling level equals the limit value and gets bigger + * due to the reception of a new data word */ channel->RBCTR = (uint32_t)((channel->RBCTR & (uint32_t)~(USIC_CH_RBCTR_LIMIT_Msk | - USIC_CH_RBCTR_DPTR_Msk | - USIC_CH_RBCTR_LOF_Msk)) | - ((limit << USIC_CH_RBCTR_LIMIT_Pos) | - (data_pointer << USIC_CH_RBCTR_DPTR_Pos) | - ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) | - (uint32_t)USIC_CH_RBCTR_LOF_Msk)); + USIC_CH_RBCTR_DPTR_Msk | + USIC_CH_RBCTR_LOF_Msk)) | + ((limit << USIC_CH_RBCTR_LIMIT_Pos) | + (data_pointer << USIC_CH_RBCTR_DPTR_Pos) | + ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) | + (uint32_t)USIC_CH_RBCTR_LOF_Msk)); } - void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_FIFO_SIZE_t size, - const uint32_t limit) + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) { - /* Disable FIFO */ - channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk; + XMC_UNUSED_ARG(size); - /* STBTEN = 0, the trigger of the standard transmit buffer event is based on - * the transition of the fill level + /* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level * from equal to below the limit, not the fact being below */ channel->TBCTR = (uint32_t)((uint32_t)(channel->TBCTR & (uint32_t)~USIC_CH_TBCTR_LIMIT_Msk) | - (limit << USIC_CH_TBCTR_LIMIT_Pos) | - ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos)); + (limit << USIC_CH_TBCTR_LIMIT_Pos)); } - void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_FIFO_SIZE_t size, - const uint32_t limit) + const XMC_USIC_CH_FIFO_SIZE_t size, + const uint32_t limit) { - /* Disable FIFO */ - channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk; + XMC_UNUSED_ARG(size); channel->RBCTR = (uint32_t)((uint32_t)(channel->RBCTR & (uint32_t)~USIC_CH_RBCTR_LIMIT_Msk) | - (limit << USIC_CH_RBCTR_LIMIT_Pos) | - ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos)); + (limit << USIC_CH_RBCTR_LIMIT_Pos)); } - void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { channel->INPR = (uint32_t)((channel->INPR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | - (service_request << (uint32_t)interrupt_node)); + (service_request << (uint32_t)interrupt_node)); } - void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { channel->TBCTR = (uint32_t)((channel->TBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | - (service_request << (uint32_t)interrupt_node)); + (service_request << (uint32_t)interrupt_node)); } void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel, - const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, - const uint32_t service_request) + const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node, + const uint32_t service_request) { channel->RBCTR = (uint32_t)((channel->RBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) | - (service_request << (uint32_t)interrupt_node)); + (service_request << (uint32_t)interrupt_node)); } - void XMC_USIC_Enable(XMC_USIC_t *const usic) { if (usic == USIC0) { #if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0); + while (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_USIC0)); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0); -#endif + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_USIC0)); +#endif } -#if defined(USIC1) +#if defined(USIC1) else if (usic == USIC1) { #if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1); -#endif + while (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_USIC1)); +#endif #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1); -#endif + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_USIC1)); +#endif } -#endif -#if defined(USIC2) +#endif +#if defined(USIC2) else if (usic == USIC2) { -#if defined(CLOCK_GATING_SUPPORTED) +#if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2); + while (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_USIC2)); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2); -#endif + while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_USIC2)); +#endif } -#endif +#endif else { XMC_ASSERT("USIC module not available", 0/*Always*/); } } - void XMC_USIC_Disable(XMC_USIC_t *const usic) { if (usic == (XMC_USIC_t *)USIC0) { -#if defined(PERIPHERAL_RESET_SUPPORTED) +#if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0); -#endif -#if defined(CLOCK_GATING_SUPPORTED) +#endif +#if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0); #endif } -#if defined(USIC1) +#if defined(USIC1) else if (usic == (XMC_USIC_t *)USIC1) { -#if defined(PERIPHERAL_RESET_SUPPORTED) +#if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1); -#endif -#if defined(CLOCK_GATING_SUPPORTED) +#endif +#if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1); #endif } -#endif -#if defined(USIC2) +#endif +#if defined(USIC2) else if (usic == (XMC_USIC_t *)USIC2) { -#if defined(PERIPHERAL_RESET_SUPPORTED) +#if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2); -#endif -#if defined(CLOCK_GATING_SUPPORTED) +#endif +#if defined(CLOCK_GATING_SUPPORTED) XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2); #endif } -#endif +#endif else { - XMC_ASSERT("USIC module not available", 0/*Always*/); + XMC_ASSERT("USIC module not available", 0/*Always*/); } + } diff --git a/cores/xmc_lib/XMCLib/src/xmc_vadc.c b/cores/xmc_lib/XMCLib/src/xmc_vadc.c index b47dd134..7a0a8287 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_vadc.c +++ b/cores/xmc_lib/XMCLib/src/xmc_vadc.c @@ -1,102 +1,50 @@ /** * @file xmc_vadc.c - * @date 2016-06-17 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-15: - * - Initial
    - * - * 2015-02-20: - * - Revised for XMC1201 device.
    - * - * 2015-04-27: - * - Added new APIs for SHS.
    - * - Added New APIs for trigger edge selection.
    - * - Added new APIs for Queue flush entries, boundary selection, Boundary node pointer.
    - * - Revised GatingMode APIs and EMUX Control Init API.
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed version macros and declaration of GetDriverVersion API + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. * - * 2015-06-25: - * - BFL configuration in channel initialization fixed. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * 2015-07-28: - * - CLOCK_GATING_SUPPORTED and PERIPHERAL_RESET_SUPPORTED macros used - * - Clubbed the macro definitions for XMC13 XMC12 and XMC14 - * - Clubbed the macro definitions for XMC44 XMC47 and XMC48 - * - New APIs Created. - * - XMC_VADC_GLOBAL_SetIndividualBoundary - * - XMC_VADC_GROUP_SetIndividualBoundary - * - XMC_VADC_GROUP_GetAlias - * - XMC_VADC_GROUP_GetInputClass - * - XMC_VADC_GROUP_ChannelSetIclass - * - XMC_VADC_GROUP_ChannelGetResultAlignment - * - XMC_VADC_GROUP_ChannelGetInputClass - * - XMC_VADC_GROUP_SetResultSubtractionValue + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * - * 2015-12-01: - * - Fixed the analog calibration voltage for XMC1100 to external reference upper supply range. - * - Fixed the XMC_VADC_GLOBAL_StartupCalibration() for XMC1100. - * - * 2016-06-17: - * - New macros added XMC_VADC_SHS_FULL_SET_REG, XMC_VADC_RESULT_PRIORITY_AVAILABLE - * and XMC_VADC_SYNCTR_START_LOCATION - * - New Enum added XMC_VADC_SHS_GAIN_LEVEL_t and XMC_VADC_SYNCTR_EVAL_t - * - Fixed the EVAL configuration in API XMC_VADC_GROUP_CheckSlaveReadiness and XMC_VADC_GROUP_IgnoreSlaveReadiness - * - New APIs added are: - * - XMC_VADC_GROUP_SetSyncSlaveReadySignal - * - XMC_VADC_GROUP_ChannelGetAssertedEvents - * - XMC_VADC_GROUP_GetAssertedResultEvents - * - XMC_VADC_GROUP_SetResultRegPriority - * - XMC_VADC_GROUP_SetSyncReadySignal - * - XMC_VADC_GROUP_GetSyncReadySignal - * - XMC_VADC_GROUP_GetResultRegPriority - * - * 2017-01-11: - * - Fix assertion in XMC_VADC_GROUP_CheckSlaveReadiness() and XMC_VADC_GROUP_IgnoreSlaveReadiness() checking the slave_group parameter - * - * @endcond + * @endcond * */ /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ -#include +#include "xmc_vadc.h" /********************************************************************************************************************* * MACROS @@ -122,17 +70,19 @@ #if (XMC_VADC_GROUP_AVAILABLE == 1U) -#if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) -static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef*)(void*)VADC_G0, - (VADC_G_TypeDef*)(void*)VADC_G1, - (VADC_G_TypeDef*)(void*)VADC_G2, - (VADC_G_TypeDef*)(void*)VADC_G3 }; +#if (XMC_VADC_MAXIMUM_NUM_GROUPS == 4U) +static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef *)(void *)VADC_G0, + (VADC_G_TypeDef *)(void *)VADC_G1, + (VADC_G_TypeDef *)(void *)VADC_G2, + (VADC_G_TypeDef *)(void *)VADC_G3 + }; #else -static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef* )(void *) VADC_G0, - (VADC_G_TypeDef* )(void *)VADC_G1 }; +static VADC_G_TypeDef *const g_xmc_vadc_group_array[XMC_VADC_MAXIMUM_NUM_GROUPS] = {(VADC_G_TypeDef * )(void *) VADC_G0, + (VADC_G_TypeDef * )(void *)VADC_G1 + }; #endif -#endif +#endif /********************************************************************************************************************* * LOCAL ROUTINES @@ -158,7 +108,7 @@ void XMC_VADC_GLOBAL_EnableModule(void) #endif #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC); + XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC); #endif #if defined(PERIPHERAL_RESET_SUPPORTED) @@ -190,6 +140,10 @@ void XMC_VADC_GLOBAL_Init(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GL #endif XMC_ASSERT("XMC_VADC_GLOBAL_Init:Wrong Module Pointer", (global_ptr == VADC)) +#if (UC_SERIES == XMC14) + XMC_SCU_CLOCK_SetAdcClockSrc(XMC_SCU_CLOCK_ADCCLKSRC_48MHZ); +#endif + /* Enable the VADC module*/ XMC_VADC_GLOBAL_EnableModule(); @@ -232,10 +186,9 @@ void XMC_VADC_GLOBAL_Init(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GL } -#if( UC_SERIES != XMC11 ) /* API to Set the Global IClass registers*/ void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_GLOBAL_CLASS_t config, - const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) { XMC_ASSERT("XMC_VADC_GLOBAL_InputClassInit:Wrong Module Pointer", (global_ptr == VADC)) @@ -246,6 +199,7 @@ void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const X if (conv_type == XMC_VADC_GROUP_CONV_STD ) { #endif + XMC_UNUSED_ARG(conv_type); global_ptr->GLOBICLASS[set_num] = config.globiclass & (uint32_t)(VADC_GLOBICLASS_CMS_Msk | VADC_GLOBICLASS_STCS_Msk); #if(XMC_VADC_EMUX_AVAILABLE == 1U) @@ -256,7 +210,6 @@ void XMC_VADC_GLOBAL_InputClassInit(XMC_VADC_GLOBAL_t *const global_ptr, const X } #endif } -#endif /* API to enable startup calibration feature */ void XMC_VADC_GLOBAL_StartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr) @@ -265,36 +218,49 @@ void XMC_VADC_GLOBAL_StartupCalibration(XMC_VADC_GLOBAL_t *const global_ptr) uint8_t i; VADC_G_TypeDef *group_ptr; #endif - + XMC_ASSERT("XMC_VADC_GLOBAL_StartupCalibration:Wrong Module Pointer", (global_ptr == VADC)) global_ptr->GLOBCFG |= (uint32_t)VADC_GLOBCFG_SUCAL_Msk; #if (XMC_VADC_GROUP_AVAILABLE == 1U) /* Loop until all active groups finish calibration */ - for(i=0U; iARBCFG) & (uint32_t)VADC_G_ARBCFG_ANONS_Msk) { /* This group is active. Loop until it finishes calibration */ - while((group_ptr->ARBCFG) & (uint32_t)VADC_G_ARBCFG_CAL_Msk) +#if UC_FAMILY == XMC1 + // wait until calibration is started + while ((group_ptr->ARBCFG & (uint32_t)VADC_G_ARBCFG_CALS_Msk) == 0) + { + __NOP(); + } +#endif + while ((group_ptr->ARBCFG) & (uint32_t)VADC_G_ARBCFG_CAL_Msk) { - /* NOP */ + __NOP(); } } } #else + + /* Loop until calibration is started */ + while ((((SHS0->SHSCFG) & (uint32_t)SHS_SHSCFG_STATE_Msk) >> (uint32_t)SHS_SHSCFG_STATE_Pos) != + XMC_VADC_SHS_START_UP_CAL_ACTIVE ) + { + __NOP(); + } /* Loop until it finishes calibration */ while ((((SHS0->SHSCFG) & (uint32_t)SHS_SHSCFG_STATE_Msk) >> (uint32_t)SHS_SHSCFG_STATE_Pos) == XMC_VADC_SHS_START_UP_CAL_ACTIVE ) { - /* NOP */ + __NOP(); } #endif } - /* API to set boudaries for result of conversion. Should the boundaries be violated, interrupts are generated */ #if (XMC_VADC_BOUNDARY_AVAILABLE == 1U) void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, @@ -314,8 +280,8 @@ void XMC_VADC_GLOBAL_SetBoundaries(XMC_VADC_GLOBAL_t *const global_ptr, /* API to set an individual boundary for conversion results */ void XMC_VADC_GLOBAL_SetIndividualBoundary(XMC_VADC_GLOBAL_t *const global_ptr, - const XMC_VADC_CHANNEL_BOUNDARY_t selection, - const uint16_t boundary_value) + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value) { uint32_t globbound; @@ -405,13 +371,13 @@ void XMC_VADC_GLOBAL_BindGroupToEMux(XMC_VADC_GLOBAL_t *const global_ptr, const global_ptr->EMUXSEL |= (uint32_t) (group << pos); } -#endif +#endif /* API to bind result event with a service request line */ void XMC_VADC_GLOBAL_SetResultEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr) { uint32_t node; - + XMC_ASSERT("XMC_VADC_GLOBAL_SetResultEventInterruptNode:Wrong Module Pointer", (global_ptr == VADC)) XMC_ASSERT("XMC_VADC_GLOBAL_SetResultEventInterruptNode:Wrong SR Number", (sr <= XMC_VADC_SR_SHARED_SR3)) @@ -432,7 +398,7 @@ void XMC_VADC_GLOBAL_SetResultEventInterruptNode(XMC_VADC_GLOBAL_t *const global void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *const global_ptr, XMC_VADC_SR_t sr) { uint32_t node; - + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode:Wrong Module Pointer", (global_ptr == VADC)) if (sr >= XMC_VADC_SR_SHARED_SR0) @@ -449,7 +415,7 @@ void XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode(XMC_VADC_GLOBAL_t *co } /* API to initialize an instance of group of VADC hardware */ -#if (XMC_VADC_GROUP_AVAILABLE == 1U) +#if (XMC_VADC_GROUP_AVAILABLE == 1U) void XMC_VADC_GROUP_Init( XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CONFIG_t *config) { XMC_ASSERT("XMC_VADC_GROUP_Init:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) @@ -465,13 +431,13 @@ void XMC_VADC_GROUP_Init( XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROU group_ptr->BOUND = config->g_bound; /* External mux configuration */ - XMC_VADC_GROUP_ExternalMuxControlInit(group_ptr,config->emux_config); + XMC_VADC_GROUP_ExternalMuxControlInit(group_ptr, config->emux_config); } /* API to program conversion characteristics */ void XMC_VADC_GROUP_InputClassInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_GROUP_CLASS_t config, - const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) + const XMC_VADC_GROUP_CONV_t conv_type, const uint32_t set_num) { uint32_t conv_class; uint32_t conv_mode_pos; @@ -485,7 +451,7 @@ void XMC_VADC_GROUP_InputClassInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_ XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong Conversion Type", ((conv_type) <= XMC_VADC_GROUP_CONV_EMUX)) XMC_ASSERT("XMC_VADC_GROUP_InputClassInit:Wrong ICLASS set number", (set_num < XMC_VADC_MAX_ICLASS_SET)) - /* + /* * Obtain the mask and position macros of the parameters based on what is being requested - Standard channels vs * external mux channels. */ @@ -539,19 +505,19 @@ void XMC_VADC_GROUP_SetPowerMode(XMC_VADC_GROUP_t *const group_ptr, const XMC_VA void XMC_VADC_GROUP_SetSyncSlave(XMC_VADC_GROUP_t *const group_ptr, uint32_t master_grp, uint32_t slave_grp) { uint32_t synctr; - #if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) - #endif +#if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) +#endif XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlave:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - - #if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) + +#if (XMC_VADC_MULTIPLE_SLAVEGROUPS == 1U ) /* Determine the coding of SYNCTR */ if (slave_grp > master_grp) { master_grp = master_grp + 1U; } - #endif - +#endif + /* Program SYNCTR */ synctr = group_ptr->SYNCTR; synctr &= ~((uint32_t)VADC_G_SYNCTR_STSEL_Msk); @@ -574,21 +540,21 @@ void XMC_VADC_GROUP_SetSyncMaster(XMC_VADC_GROUP_t *const group_ptr) /* API to enable checking of readiness of slaves before a synchronous conversion request is issued */ void XMC_VADC_GROUP_CheckSlaveReadiness(XMC_VADC_GROUP_t *const group_ptr, uint32_t slave_group) { - uint32_t i,master_grp_num; + uint32_t i, master_grp_num; XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Slave group", ((slave_group >= 0) && (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1)))) + XMC_ASSERT("XMC_VADC_GROUP_CheckSlaveReadiness:Wrong Slave group", (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1))) - master_grp_num =0; - for(i=0; i= 0) && (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1)))) + XMC_ASSERT("XMC_VADC_GROUP_IgnoreSlaveReadiness:Wrong Slave group", (slave_group <= (XMC_VADC_MAXIMUM_NUM_GROUPS - 1))) - master_grp_num =0; - for(i=0; iSYNCTR &= ~(1U << (slave_group + XMC_VADC_SYNCTR_START_LOCATION)); } /* API to configure EVAL bit in the slave groups*/ void XMC_VADC_GROUP_SetSyncSlaveReadySignal(XMC_VADC_GROUP_t *const group_ptr, - uint32_t eval_waiting_group, - uint32_t eval_origin_group) + uint32_t eval_waiting_group, + uint32_t eval_origin_group) { XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group numbers", (eval_waiting_group == eval_origin_group )) + XMC_ASSERT("XMC_VADC_GROUP_SetSyncSlaveReadySignal:Wrong Group numbers", (eval_waiting_group != eval_origin_group )) - if(eval_origin_group < eval_waiting_group) + if (eval_origin_group < eval_waiting_group) { - eval_origin_group++; + eval_origin_group++; } group_ptr->SYNCTR |= (1U << (eval_origin_group + XMC_VADC_SYNCTR_START_LOCATION)); } @@ -668,7 +634,7 @@ void XMC_VADC_GROUP_DisableChannelSyncRequest(XMC_VADC_GROUP_t *const group_ptr, } } -/* API to retrieve the converter state - Idle vs Busy */ +/* API to retrieve the converter state - Idle vs Busy */ XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const group_ptr) { uint32_t arbcfg; @@ -679,7 +645,7 @@ XMC_VADC_GROUP_STATE_t XMC_VADC_GROUP_IsConverterBusy(XMC_VADC_GROUP_t *const gr arbcfg &= (uint32_t)VADC_G_ARBCFG_BUSY_Msk; arbcfg = arbcfg >> VADC_G_ARBCFG_BUSY_Pos; - return( (XMC_VADC_GROUP_STATE_t)arbcfg); + return ( (XMC_VADC_GROUP_STATE_t)arbcfg); } /* API to set boundaries for conversion results */ @@ -700,16 +666,16 @@ void XMC_VADC_GROUP_SetBoundaries(XMC_VADC_GROUP_t *const group_ptr, const uint3 /* API to set an individual boundary for conversion results */ void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, - const XMC_VADC_CHANNEL_BOUNDARY_t selection, - const uint16_t boundary_value) + const XMC_VADC_CHANNEL_BOUNDARY_t selection, + const uint16_t boundary_value) { uint32_t bound; XMC_ASSERT("XMC_VADC_GROUP_SetIndividualBoundary:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_SetIndividualBoundary:Wrong Boundary Selection", - ((XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 == selection) || - (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1 == selection))) + ((XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0 == selection) || + (XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1 == selection))) /* Program the Boundary registers */ bound = group_ptr->BOUND; @@ -733,14 +699,14 @@ void XMC_VADC_GROUP_SetIndividualBoundary(XMC_VADC_GROUP_t *const group_ptr, /* Manually assert service request (Interrupt) to NVIC */ void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t sr_num, - const XMC_VADC_GROUP_IRQ_t type) + const uint32_t sr_num, + const XMC_VADC_GROUP_IRQ_t type) { uint32_t sract; XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR number", (sr_num <= XMC_VADC_SR_SHARED_SR3)) - XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR type", ((type)<= XMC_VADC_GROUP_IRQ_SHARED)) + XMC_ASSERT("XMC_VADC_GROUP_TriggerServiceRequest:Wrong SR type", ((type) <= XMC_VADC_GROUP_IRQ_SHARED)) sract = group_ptr->SRACT; @@ -760,8 +726,8 @@ void XMC_VADC_GROUP_TriggerServiceRequest(XMC_VADC_GROUP_t *const group_ptr, /* API to set the SR line for the Boundary flag node pointer*/ void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, - const uint8_t boundary_flag_num, - const XMC_VADC_BOUNDARY_NODE_t sr) + const uint8_t boundary_flag_num, + const XMC_VADC_BOUNDARY_NODE_t sr) { uint32_t flag_pos; XMC_ASSERT("XMC_VADC_GROUP_SetBoundaryEventInterruptNode:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) @@ -781,8 +747,8 @@ void XMC_VADC_GROUP_SetBoundaryEventInterruptNode(XMC_VADC_GROUP_t *const group_ /* API to Initialize the Sample and hold features*/ void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VADC_GLOBAL_SHS_CONFIG_t *config) { - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong Index number",(config == (XMC_VADC_GLOBAL_SHS_CONFIG_t*)NULL)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_Init:Wrong Index number", (config == (XMC_VADC_GLOBAL_SHS_CONFIG_t *)NULL)) /* Initialize the SHS Configuration register*/ shs_ptr->SHSCFG = (uint32_t)((uint32_t)config->shscfg | (uint32_t)SHS_SHSCFG_SCWC_Msk); @@ -799,8 +765,8 @@ void XMC_VADC_GLOBAL_SHS_Init(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, const XMC_VA void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode:Wrong Index number", (group_num <= XMC_VADC_GROUP_INDEX_1)) /* Set the converted to Accelerated mode from compatible mode*/ if (group_num == XMC_VADC_GROUP_INDEX_0 ) @@ -821,8 +787,8 @@ void XMC_VADC_GLOBAL_SHS_EnableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, XMC_VADC_GROUP_INDEX_t group_num) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode:Wrong Index number", (group_num <= XMC_VADC_GROUP_INDEX_1)) /* Set the converted to Accelerated mode from compatible mode*/ if (group_num == XMC_VADC_GROUP_INDEX_0 ) @@ -841,13 +807,13 @@ void XMC_VADC_GLOBAL_SHS_DisableAcceleratedMode(XMC_VADC_GLOBAL_SHS_t *const shs /* API to set the Short sample time of the Sample and hold module*/ void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - uint8_t sst_value) + XMC_VADC_GROUP_INDEX_t group_num, + uint8_t sst_value) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SST value",(sst_value < 64U)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong Index number", (group_num <= XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetShortSampleTime:Wrong SST value", (sst_value < 64U)) /* Set the short sample time for the Accelerated mode of operation*/ if (group_num == XMC_VADC_GROUP_INDEX_0 ) @@ -862,7 +828,7 @@ void XMC_VADC_GLOBAL_SHS_SetShortSampleTime(XMC_VADC_GLOBAL_SHS_t *const shs_ptr } else { - /* for MISRA*/ + /* for MISRA*/ } } #endif @@ -875,8 +841,8 @@ void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, { uint32_t ch_mask; - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) - XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong Index number",(group_num <= XMC_VADC_GROUP_INDEX_1)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong SHS Pointer", (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) + XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetGainFactor:Wrong Index number", (group_num <= XMC_VADC_GROUP_INDEX_1)) /*Calculate location of channel bit-field*/ ch_mask = ((uint32_t)ch_num << (uint32_t)2); @@ -899,10 +865,10 @@ void XMC_VADC_GLOBAL_SHS_SetGainFactor(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, #if(XMC_VADC_SHS_FULL_SET_REG == 1U) /* API to enable the gain and offset calibration of the Sample and hold module*/ void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num) + XMC_VADC_GROUP_INDEX_t group_num) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations:Wrong group selected", (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) @@ -923,12 +889,12 @@ void XMC_VADC_GLOBAL_SHS_EnableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t * /* API to enable the gain and offset calibration of the Sample and hold module*/ void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num) + XMC_VADC_GROUP_INDEX_t group_num) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations:Wrong group selected", - (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) + (group_num <= (uint32_t)XMC_VADC_GROUP_INDEX_1)) if ( XMC_VADC_GROUP_INDEX_0 == group_num) { @@ -946,17 +912,17 @@ void XMC_VADC_GLOBAL_SHS_DisableGainAndOffsetCalibrations(XMC_VADC_GLOBAL_SHS_t /* API to get the offset calibration value of the Sample and hold module*/ uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - XMC_VADC_SHS_GAIN_LEVEL_t gain_level) + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level) { uint32_t calibration_value; XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong Group number selected", - (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + (group_num == XMC_VADC_GROUP_INDEX_0) || (group_num == XMC_VADC_GROUP_INDEX_1)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue:Wrong gain level selected", - (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_1)|| - (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0) || (gain_level == XMC_VADC_SHS_GAIN_LEVEL_1) || + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2) || (gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) calibration_value = 0U; if ( XMC_VADC_GROUP_INDEX_0 == group_num) @@ -976,17 +942,17 @@ uint8_t XMC_VADC_GLOBAL_SHS_GetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *con /* API to set the offset calibration value of the Sample and hold module*/ void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - XMC_VADC_SHS_GAIN_LEVEL_t gain_level, - uint8_t offset_calibration_value) + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_GAIN_LEVEL_t gain_level, + uint8_t offset_calibration_value) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong Group number selected", - (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + (group_num == XMC_VADC_GROUP_INDEX_0) || (group_num == XMC_VADC_GROUP_INDEX_1)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue:Wrong gain level selected", - (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_1)|| - (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2)||(gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_0) || (gain_level == XMC_VADC_SHS_GAIN_LEVEL_1) || + (gain_level == XMC_VADC_SHS_GAIN_LEVEL_2) || (gain_level == XMC_VADC_SHS_GAIN_LEVEL_3)) if ( XMC_VADC_GROUP_INDEX_0 == group_num) { @@ -1009,16 +975,16 @@ void XMC_VADC_GLOBAL_SHS_SetOffsetCalibrationValue(XMC_VADC_GLOBAL_SHS_t *const /* API to set the values of sigma delta loop of the Sample and hold module*/ void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, - XMC_VADC_GROUP_INDEX_t group_num, - XMC_VADC_SHS_LOOP_CH_t loop_select, - uint8_t ch_num) + XMC_VADC_GROUP_INDEX_t group_num, + XMC_VADC_SHS_LOOP_CH_t loop_select, + uint8_t ch_num) { XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong SHS Pointer", - (shs_ptr == (XMC_VADC_GLOBAL_SHS_t*)(void*)SHS0)) + (shs_ptr == (XMC_VADC_GLOBAL_SHS_t *)(void *)SHS0)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Group number selected", - (group_num == XMC_VADC_GROUP_INDEX_0)||(group_num == XMC_VADC_GROUP_INDEX_1)) + (group_num == XMC_VADC_GROUP_INDEX_0) || (group_num == XMC_VADC_GROUP_INDEX_1)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Delta sigma loop selected", - (loop_select == XMC_VADC_SHS_LOOP_CH_0)||(loop_select == XMC_VADC_SHS_LOOP_CH_1)) + (loop_select == XMC_VADC_SHS_LOOP_CH_0) || (loop_select == XMC_VADC_SHS_LOOP_CH_1)) XMC_ASSERT("XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) @@ -1030,7 +996,7 @@ void XMC_VADC_GLOBAL_SHS_SetSigmaDeltaLoop(XMC_VADC_GLOBAL_SHS_t *const shs_ptr, #endif -#if (XMC_VADC_GSCAN_AVAILABLE == 1U) +#if (XMC_VADC_GSCAN_AVAILABLE == 1U) /* API to initialize the group scan hardware of a kernel */ void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_SCAN_CONFIG_t *config) { @@ -1040,14 +1006,14 @@ void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_S /* All configurations have to be performed with the arbitration slot disabled */ XMC_VADC_GROUP_ScanDisableArbitrationSlot(group_ptr); - + /* Read in the existing contents of arbitration priority register */ reg = group_ptr->ARBPR; /* Program the priority of the request source */ reg &= ~(uint32_t)VADC_G_ARBPR_PRIO1_Msk; reg |= (uint32_t)((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO1_Pos); - + /* Program the start mode */ if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) { @@ -1056,19 +1022,19 @@ void XMC_VADC_GROUP_ScanInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_S group_ptr->ARBPR = reg; - group_ptr->ASCTRL = (uint32_t)(config->asctrl |(VADC_G_ASCTRL_XTWC_Msk) |(VADC_G_ASCTRL_GTWC_Msk) | - (VADC_G_ASCTRL_TMWC_Msk)); + group_ptr->ASCTRL = (uint32_t)(config->asctrl | (VADC_G_ASCTRL_XTWC_Msk) | (VADC_G_ASCTRL_GTWC_Msk) | + (VADC_G_ASCTRL_TMWC_Msk)); + + group_ptr->ASMR = (uint32_t)((config->asmr) | (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_ASMR_ENGT_Pos)); - group_ptr->ASMR = (uint32_t)((config->asmr)| (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_ASMR_ENGT_Pos)); - if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) { group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_RPTDIS_Msk; } - + /* Enable arbitration slot now */ XMC_VADC_GROUP_ScanEnableArbitrationSlot(group_ptr); - + } /* API to select one of the 16 inputs as a trigger input for Group Scan request source */ @@ -1077,7 +1043,7 @@ void XMC_VADC_GROUP_ScanSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, XMC_VAD uint32_t scanctrl; XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Trigger Port", ((trigger_input)< XMC_VADC_NUM_PORTS)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTrigger:Wrong Trigger Port", ((trigger_input) < XMC_VADC_NUM_PORTS)) scanctrl = group_ptr->ASCTRL; scanctrl |= (uint32_t) VADC_G_ASCTRL_XTWC_Msk; @@ -1092,7 +1058,7 @@ void XMC_VADC_GROUP_ScanSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, con uint32_t scanctrl; XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Trigger Port", ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectTriggerEdge:Wrong Trigger Port", ((trigger_edge) <= XMC_VADC_TRIGGER_EDGE_ANY)) scanctrl = group_ptr->ASCTRL; scanctrl |= (uint32_t) VADC_G_ASCTRL_XTWC_Msk; @@ -1107,7 +1073,7 @@ void XMC_VADC_GROUP_ScanSelectGating(XMC_VADC_GROUP_t *const group_ptr, XMC_VADC uint32_t scanctrl; XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Gating Port", ((gating_input)< XMC_VADC_NUM_PORTS)) + XMC_ASSERT("XMC_VADC_GROUP_ScanSelectGating:Wrong Gating Port", ((gating_input) < XMC_VADC_NUM_PORTS)) scanctrl = group_ptr->ASCTRL; scanctrl |= (uint32_t)VADC_G_ASCTRL_GTWC_Msk; @@ -1127,8 +1093,8 @@ void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr) /* To disable trigger and gating before abort*/ asctrl = group_ptr->ASCTRL; - group_ptr->ASCTRL =(0U | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | - (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); + group_ptr->ASCTRL = (0U | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | + (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); /* To disable Arbitration before abort*/ arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN1_Pos) & 1U); @@ -1137,12 +1103,12 @@ void XMC_VADC_GROUP_ScanSequenceAbort(XMC_VADC_GROUP_t *const group_ptr) group_ptr->ASMR &= ~((uint32_t)VADC_G_ASMR_ENGT_Msk); group_ptr->ASMR |= (uint32_t)VADC_G_ASMR_CLRPND_Msk; - /* Enable the arbitration slot 1*/ + /* Enable the arbitration slot 1*/ group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN1_Pos); /* Enable any disabled gating*/ - group_ptr->ASCTRL =(asctrl | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | - (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); + group_ptr->ASCTRL = (asctrl | (uint32_t)VADC_G_ASCTRL_XTWC_Msk | + (uint32_t)VADC_G_ASCTRL_GTWC_Msk | (uint32_t)VADC_G_ASCTRL_TMWC_Msk ); } /* API to find out number of channels awaiting conversion */ @@ -1161,7 +1127,7 @@ uint32_t XMC_VADC_GROUP_ScanGetNumChannelsPending(XMC_VADC_GROUP_t *const group_ { reg = group_ptr->ASPND; - for(i=0U;iASSEL; + assel = group_ptr->ASSEL; assel &= (~( 1 << channel_num)); group_ptr->ASSEL = assel; } @@ -1206,27 +1172,27 @@ void XMC_VADC_GROUP_ScanRemoveChannel(XMC_VADC_GROUP_t *const group_ptr, const u /* API to initialize background scan request source hardware */ void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const XMC_VADC_BACKGROUND_CONFIG_t *config) { - #if (XMC_VADC_GROUP_AVAILABLE ==1U) +#if (XMC_VADC_GROUP_AVAILABLE ==1U) uint8_t i; uint32_t reg; uint32_t conv_start_mask; - #endif - +#endif + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundInit:Wrong Module Pointer", (global_ptr == VADC)) - #if (XMC_VADC_GROUP_AVAILABLE ==1U) - for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + for (i = (uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) { XMC_VADC_GROUP_BackgroundDisableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); } - + conv_start_mask = (uint32_t) 0; if (XMC_VADC_STARTMODE_WFS != (XMC_VADC_STARTMODE_t)config->conv_start_mode) { conv_start_mask = (uint32_t)VADC_G_ARBPR_CSM2_Msk; } - - for(i=0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + + for (i = 0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) { reg = g_xmc_vadc_group_array[i]->ARBPR; @@ -1234,35 +1200,35 @@ void XMC_VADC_GLOBAL_BackgroundInit(XMC_VADC_GLOBAL_t *const global_ptr, const X /* Program the priority of the request source */ reg |= (uint32_t)((uint32_t)config->req_src_priority << VADC_G_ARBPR_PRIO2_Pos); - + /* Program the start mode */ reg |= conv_start_mask; g_xmc_vadc_group_array[i]->ARBPR = reg; - + } - #endif +#endif /* program BRSCTRL register */ global_ptr->BRSCTRL = (uint32_t)(config->asctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); /* program BRSMR register */ - global_ptr->BRSMR = (uint32_t)((config->asmr)| (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_BRSMR_ENGT_Pos)); - + global_ptr->BRSMR = (uint32_t)((config->asmr) | (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_BRSMR_ENGT_Pos)); + #if (XMC_VADC_GROUP_AVAILABLE ==1U) if (XMC_VADC_STARTMODE_CNR == (XMC_VADC_STARTMODE_t)(config->conv_start_mode)) { global_ptr->BRSMR |= (uint32_t)VADC_BRSMR_RPTDIS_Msk; } #endif - - #if (XMC_VADC_GROUP_AVAILABLE ==1U) - for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + +#if (XMC_VADC_GROUP_AVAILABLE ==1U) + for (i = (uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) { XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); } - #endif - +#endif + } /* API to select one of the 16 inputs as a trigger for background scan request source */ @@ -1271,9 +1237,9 @@ void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr uint32_t scanctrl; XMC_ASSERT("VADC_BCKGND_SelectTriggerInput:Wrong Module Pointer", (global_ptr == VADC)) - XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTrigger:Wrong Trigger Port", ((input_num)< XMC_VADC_NUM_PORTS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTrigger:Wrong Trigger Port", ((input_num) < XMC_VADC_NUM_PORTS)) + - scanctrl = global_ptr->BRSCTRL; scanctrl |= (uint32_t)VADC_BRSCTRL_XTWC_Msk; scanctrl &= ~((uint32_t)VADC_BRSCTRL_XTSEL_Msk); @@ -1283,13 +1249,13 @@ void XMC_VADC_GLOBAL_BackgroundSelectTrigger(XMC_VADC_GLOBAL_t *const global_ptr /* Select a trigger edge*/ void XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge(XMC_VADC_GLOBAL_t *const global_ptr, - const XMC_VADC_TRIGGER_EDGE_t trigger_edge) + const XMC_VADC_TRIGGER_EDGE_t trigger_edge) { uint32_t scanctrl; XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge:Wrong Global Pointer", (global_ptr == VADC)) XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge:Wrong Trigger Port", - ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + ((trigger_edge) <= XMC_VADC_TRIGGER_EDGE_ANY)) scanctrl = global_ptr->BRSCTRL; scanctrl |= (uint32_t) VADC_BRSCTRL_XTWC_Msk; @@ -1305,7 +1271,7 @@ void XMC_VADC_GLOBAL_BackgroundSelectGating(XMC_VADC_GLOBAL_t *const global_ptr, uint32_t scanctrl; XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Module Pointer", (global_ptr == VADC)) - XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Gating Port", ((input_num)< XMC_VADC_NUM_PORTS)) + XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundSelectGating:Wrong Gating Port", ((input_num) < XMC_VADC_NUM_PORTS)) scanctrl = global_ptr->BRSCTRL; scanctrl |= (uint32_t)VADC_BRSCTRL_GTWC_Msk; @@ -1327,12 +1293,12 @@ void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr /* To disable trigger and gating before abort*/ brsctrl = global_ptr->BRSCTRL; - global_ptr->BRSCTRL =(0U | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); + global_ptr->BRSCTRL = (0U | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); /* Disable Background Request source */ #if (XMC_VADC_GROUP_AVAILABLE ==1U) - for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + for (i = (uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) { grp_asen2_flag[i] = (uint8_t)(g_xmc_vadc_group_array[i]->ARBPR >> VADC_G_ARBPR_ASEN2_Pos); XMC_VADC_GROUP_BackgroundDisableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); @@ -1344,17 +1310,17 @@ void XMC_VADC_GLOBAL_BackgroundAbortSequence(XMC_VADC_GLOBAL_t *const global_ptr #if (XMC_VADC_GROUP_AVAILABLE ==1U) /* Enable Background Request source */ - for(i=(uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + for (i = (uint8_t)0; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) { if ((uint8_t)1 == grp_asen2_flag[i]) { - XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t*)g_xmc_vadc_group_array[i]); + XMC_VADC_GROUP_BackgroundEnableArbitrationSlot((XMC_VADC_GROUP_t *)g_xmc_vadc_group_array[i]); } } #endif /* Re-enable any disabled trigger and gating*/ - global_ptr->BRSCTRL =(brsctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); + global_ptr->BRSCTRL = (brsctrl | (uint32_t)VADC_BRSCTRL_XTWC_Msk | (uint32_t)VADC_BRSCTRL_GTWC_Msk); } /* API to determine how many channels are awaiting conversion */ @@ -1368,15 +1334,15 @@ uint32_t XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending(XMC_VADC_GLOBAL_t *cons XMC_ASSERT("XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending:Wrong Module Pointer", (global_ptr == VADC)) count = 0U; - + /* Loop through all groups and find out who is awaiting conversion */ - for(i = 0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) + for (i = 0U; i < XMC_VADC_MAXIMUM_NUM_GROUPS; i++) { if (global_ptr->BRSSEL[i]) { reg = global_ptr->BRSPND[i]; - for(j=0U;jARBPR; /* Request Source priority */ @@ -1417,9 +1383,9 @@ void XMC_VADC_GROUP_QueueInit(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_ group_ptr->ARBPR = reg; - group_ptr->QCTRL0 = (uint32_t)((config->qctrl0)|(uint32_t)(VADC_G_QCTRL0_XTWC_Msk)| - (uint32_t)(VADC_G_QCTRL0_TMWC_Msk)| - (uint32_t)(VADC_G_QCTRL0_GTWC_Msk)); + group_ptr->QCTRL0 = (uint32_t)((config->qctrl0) | (uint32_t)(VADC_G_QCTRL0_XTWC_Msk) | + (uint32_t)(VADC_G_QCTRL0_TMWC_Msk) | + (uint32_t)(VADC_G_QCTRL0_GTWC_Msk)); /* Gating mode */ group_ptr->QMR0 = ((uint32_t)(config->qmr0) | (uint32_t)((uint32_t)XMC_VADC_GATEMODE_IGNORE << VADC_G_QMR0_ENGT_Pos)); @@ -1438,11 +1404,11 @@ void XMC_VADC_GROUP_QueueSelectTrigger(XMC_VADC_GROUP_t *const group_ptr, const XMC_VADC_TRIGGER_INPUT_SELECT_t input_num) { uint32_t qctrl; - + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Trigger Port", ((input_num)< XMC_VADC_NUM_PORTS)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTrigger:Wrong Trigger Port", ((input_num) < XMC_VADC_NUM_PORTS)) + - /* Now select the conversion trigger */ qctrl = group_ptr->QCTRL0; qctrl |= (uint32_t)VADC_G_QCTRL0_XTWC_Msk; @@ -1457,7 +1423,7 @@ void XMC_VADC_GROUP_QueueSelectTriggerEdge(XMC_VADC_GROUP_t *const group_ptr, co uint32_t qctrl; XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Gating Port", ((trigger_edge)<= XMC_VADC_TRIGGER_EDGE_ANY)) + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectTriggerEdge:Wrong Gating Port", ((trigger_edge) <= XMC_VADC_TRIGGER_EDGE_ANY)) /* Now select the gating input */ qctrl = group_ptr->QCTRL0; @@ -1473,8 +1439,8 @@ void XMC_VADC_GROUP_QueueSelectGating(XMC_VADC_GROUP_t *const group_ptr, const X uint32_t qctrl; XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Gating Port", ((input_num)< XMC_VADC_NUM_PORTS)) - + XMC_ASSERT("XMC_VADC_GROUP_QueueSelectGating:Wrong Gating Port", ((input_num) < XMC_VADC_NUM_PORTS)) + /* Now select the gating input */ qctrl = group_ptr->QCTRL0; qctrl |= (uint32_t)VADC_G_QCTRL0_GTWC_Msk; @@ -1503,7 +1469,7 @@ uint32_t XMC_VADC_GROUP_QueueGetLength(XMC_VADC_GROUP_t *const group_ptr) { length = (qsr & (uint32_t)VADC_G_QSR0_FILL_Msk) + 1U; } - + if (qbur0 & (uint32_t)VADC_G_QBUR0_V_Msk ) { length++; @@ -1523,22 +1489,22 @@ void XMC_VADC_GROUP_QueueAbortSequence(XMC_VADC_GROUP_t *const group_ptr) /* Disable any gating if present*/ qctrl0 = group_ptr->QCTRL0; - group_ptr->QCTRL0 =(0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | - (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); - + group_ptr->QCTRL0 = (0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + /* Disable the Arbitration 0 in the group before abort*/ arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN0_Pos) & 1U); XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); - + /* Flush the Entries from queue*/ XMC_VADC_GROUP_QueueFlushEntries(group_ptr); - + /* Enable the arbitration slot 0*/ group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN0_Pos); - + /* Enable any disabled gating*/ group_ptr->QCTRL0 = (qctrl0 | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | - (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); } /* API to abort conversion of the channel queued up next */ @@ -1550,13 +1516,13 @@ void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr) bool arbitration_status; XMC_ASSERT("XMC_VADC_GROUP_QueueRemoveChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - + /* Disable any gating if present*/ - qctrl0= group_ptr->QCTRL0; + qctrl0 = group_ptr->QCTRL0; + + group_ptr->QCTRL0 = (0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); - group_ptr->QCTRL0 =(0U | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | - (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); - /* Disable the Arbitration 0 in the group before abort*/ arbitration_status = (bool)((uint32_t)(group_ptr->ARBPR >> VADC_G_ARBPR_ASEN0_Pos) & 1U); XMC_VADC_GROUP_QueueDisableArbitrationSlot(group_ptr); @@ -1571,17 +1537,17 @@ void XMC_VADC_GROUP_QueueRemoveChannel(XMC_VADC_GROUP_t *const group_ptr) length_after_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); /* Loop until a reduction in queue length is assessed */ - while(length_after_abort == length_before_abort) + while (length_after_abort == length_before_abort) { length_after_abort = XMC_VADC_GROUP_QueueGetLength(group_ptr); } } /* Enable the arbitration slot 0*/ group_ptr->ARBPR |= (uint32_t)((uint32_t)arbitration_status << VADC_G_ARBPR_ASEN0_Pos); - + /* Enable any disabled gating*/ group_ptr->QCTRL0 = (qctrl0 | (uint32_t)VADC_G_QCTRL0_XTWC_Msk | - (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); + (uint32_t)VADC_G_QCTRL0_GTWC_Msk | (uint32_t)VADC_G_QCTRL0_TMWC_Msk ); } /* Get details of channel meant to be converted right after the ongoing conversion */ @@ -1590,7 +1556,7 @@ int32_t XMC_VADC_GROUP_QueueGetNextChannel(XMC_VADC_GROUP_t *const group_ptr) int32_t ch_num; XMC_ASSERT("XMC_VADC_GROUP_QueueGetNextChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - + /* * Check if there is something in the backup stage. If not, read queue-0 * entry. @@ -1618,7 +1584,7 @@ int32_t XMC_VADC_GROUP_QueueGetInterruptedChannel(XMC_VADC_GROUP_t *const group_ int32_t ch_num; XMC_ASSERT("XMC_VADC_GROUP_QueueGetInterruptedChannel:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - + if ((group_ptr->QBUR0) & (uint32_t)VADC_G_QBUR0_V_Msk) { ch_num = (int32_t)(group_ptr->QBUR0 & (uint32_t)VADC_G_QBUR0_REQCHNR_Msk); @@ -1653,7 +1619,7 @@ void XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(XMC_VADC_GROUP_t *const gro #if (XMC_VADC_GROUP_AVAILABLE ==1U) /* API to initialize a channel unit */ void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num, - const XMC_VADC_CHANNEL_CONFIG_t *config) + const XMC_VADC_CHANNEL_CONFIG_t *config) { uint32_t prio; uint32_t ch_assign; @@ -1662,7 +1628,7 @@ void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_ XMC_ASSERT("XMC_VADC_GROUP_ChannelInit:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_ChannelInit:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) - + prio = (uint32_t)config->channel_priority; /* Priority channel */ @@ -1699,37 +1665,6 @@ void XMC_VADC_GROUP_ChannelInit(XMC_VADC_GROUP_t *const group_ptr, const uint32_ } -/* API to set an alias channel for channels numbered 2 through 7 */ -void XMC_VADC_GROUP_SetChannelAlias(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t src_ch_num, - const uint32_t alias_ch_num) -{ - uint32_t alias; - uint32_t mask; - uint32_t pos; - - XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) - XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Alias Channel", ((alias_ch_num == 0)|| (alias_ch_num == 1U))) - XMC_ASSERT("XMC_VADC_GROUP_SetChannelAlias:Wrong Aliased Channel", ((src_ch_num < 8U))) - - alias = group_ptr->ALIAS; - - if (0U == alias_ch_num) - { - mask = (uint32_t) VADC_G_ALIAS_ALIAS0_Msk; - pos = (uint32_t) VADC_G_ALIAS_ALIAS0_Pos; - } - else - { - mask = (uint32_t) VADC_G_ALIAS_ALIAS1_Msk; - pos = (uint32_t) VADC_G_ALIAS_ALIAS1_Pos; - } - alias &= ~mask; - alias |= (uint32_t)(src_ch_num << pos); - - group_ptr->ALIAS = alias; -} - /* API to determine whether input to a channel has violated boundary conditions */ bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr, const uint32_t ch_num) { @@ -1748,7 +1683,7 @@ bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr */ /* Extract CHEVMODE for requested channel */ chctr = group_ptr->CHCTR[ch_num]; - chctr = (uint32_t)(chctr >> (uint32_t)VADC_G_CHCTR_CHEVMODE_Pos)& (uint32_t)0x3; + chctr = (uint32_t)(chctr >> (uint32_t)VADC_G_CHCTR_CHEVMODE_Pos) & (uint32_t)0x3; /* Extract CEFLAG for the requested channel */ ceflag = group_ptr->CEFLAG; @@ -1756,7 +1691,7 @@ bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr /* Check what was the channel event generation criteria */ if ( (( (uint32_t)XMC_VADC_CHANNEL_EVGEN_INBOUND == chctr) \ - || ((uint32_t) XMC_VADC_CHANNEL_EVGEN_OUTBOUND == chctr)) && (ceflag) ) + || ((uint32_t) XMC_VADC_CHANNEL_EVGEN_OUTBOUND == chctr)) && (ceflag) ) { retval = (bool)true; } @@ -1766,13 +1701,13 @@ bool XMC_VADC_GROUP_ChannelIsResultOutOfBounds(XMC_VADC_GROUP_t *const group_ptr /* Set a reference voltage for conversion */ void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const XMC_VADC_CHANNEL_REF_t ref) + const uint32_t ch_num, + const XMC_VADC_CHANNEL_REF_t ref) { uint32_t chctr; XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Channel Number", ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) - XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Voltage Reference", ((ref)<= XMC_VADC_CHANNEL_REF_ALT_CH0)) + XMC_ASSERT("XMC_VADC_GROUP_ChannelSetInputReference:Wrong Voltage Reference", ((ref) <= XMC_VADC_CHANNEL_REF_ALT_CH0)) chctr = group_ptr->CHCTR[ch_num]; chctr &= ~((uint32_t)VADC_G_CHCTR_REFSEL_Msk); @@ -1783,8 +1718,8 @@ void XMC_VADC_GROUP_ChannelSetInputReference(XMC_VADC_GROUP_t *const group_ptr, /* API to select one of the available 16 registers for storing the channel result */ void XMC_VADC_GROUP_ChannelSetResultRegister(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const uint32_t result_reg_num) + const uint32_t ch_num, + const uint32_t result_reg_num) { uint32_t chctr; @@ -1852,8 +1787,8 @@ void XMC_VADC_GROUP_ChannelTriggerEvent(XMC_VADC_GROUP_t *const group_ptr, const /* API to bind channel event with a service request (NVIC Node) */ void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const XMC_VADC_SR_t sr) + const uint32_t ch_num, + const XMC_VADC_SR_t sr) { uint32_t route_mask; @@ -1870,8 +1805,8 @@ void XMC_VADC_GROUP_ChannelSetEventInterruptNode(XMC_VADC_GROUP_t *const group_p /* API to configure conditions for generation of channel event */ void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria( XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - const XMC_VADC_CHANNEL_EVGEN_t criteria) + const uint32_t ch_num, + const XMC_VADC_CHANNEL_EVGEN_t criteria) { uint32_t chctr; @@ -1889,19 +1824,19 @@ void XMC_VADC_GROUP_ChannelTriggerEventGenCriteria( XMC_VADC_GROUP_t *const grou /* API to configure the boundary selection */ void XMC_VADC_GROUP_ChannelSetBoundarySelection(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t ch_num, - XMC_VADC_BOUNDARY_SELECT_t boundary_sel, - XMC_VADC_CHANNEL_BOUNDARY_t selection) + const uint32_t ch_num, + XMC_VADC_BOUNDARY_SELECT_t boundary_sel, + XMC_VADC_CHANNEL_BOUNDARY_t selection) { XMC_ASSERT("XMC_VADC_GROUP_ChannelSetBoundarySelection:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_ChannelSetBoundarySelection:Wrong Channel Number", - ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) + ((ch_num) < XMC_VADC_NUM_CHANNELS_PER_GROUP)) group_ptr->CHCTR[ch_num] &= ~((uint32_t)VADC_G_CHCTR_BNDSELL_Msk << boundary_sel); - group_ptr->CHCTR[ch_num] |= (selection<< ((uint32_t)VADC_G_CHCTR_BNDSELL_Pos + (uint32_t)boundary_sel)); + group_ptr->CHCTR[ch_num] |= (selection << ((uint32_t)VADC_G_CHCTR_BNDSELL_Pos + (uint32_t)boundary_sel)); } -/* Make the specified result register part of Result FIFO */ +/* Make the specified result register part of Result FIFO */ void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uint32_t res_reg) { uint32_t fen; @@ -1920,14 +1855,14 @@ void XMC_VADC_GROUP_AddResultToFifo(XMC_VADC_GROUP_t *const group_ptr, const uin /* Applicable to fast compare mode, this API sets up the value which is to be compared against conversion result */ void XMC_VADC_GROUP_SetResultFastCompareValue(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg, - const XMC_VADC_RESULT_SIZE_t compare_val) + const uint32_t res_reg, + const XMC_VADC_RESULT_SIZE_t compare_val) { uint32_t res = group_ptr->RES[res_reg]; XMC_ASSERT("XMC_VADC_GROUP_SetResultFastCompareValue:Wrong Group Pointer", XMC_VADC_CHECK_GROUP_PTR(group_ptr)) XMC_ASSERT("XMC_VADC_GROUP_SetResultFastCompareValue:Wrong Result Register", - ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) + ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) res &= ~((uint32_t)VADC_G_RES_RESULT_Msk); res |= (uint32_t)((uint32_t)compare_val << XMC_VADC_RESULT_LEFT_ALIGN_10BIT); @@ -1959,7 +1894,7 @@ XMC_VADC_FAST_COMPARE_t XMC_VADC_GROUP_GetFastCompareResult(XMC_VADC_GROUP_t *co /* Applicable to fast compare mode, this API sets up the value which is to be compared against conversion result */ void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, - const uint16_t subtraction_val) + const uint16_t subtraction_val) { uint32_t res; @@ -1974,8 +1909,8 @@ void XMC_VADC_GROUP_SetResultSubtractionValue(XMC_VADC_GROUP_t *const group_ptr, /* API to select a service request line (NVIC Node) for result event of specified unit of result hardware */ void XMC_VADC_GROUP_SetResultInterruptNode(XMC_VADC_GROUP_t *const group_ptr, - const uint32_t res_reg, - const XMC_VADC_SR_t sr) + const uint32_t res_reg, + const XMC_VADC_SR_t sr) { uint32_t route_mask; @@ -2011,7 +1946,7 @@ uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uin XMC_ASSERT("XMC_VADC_GROUP_GetResultFifoTail:Wrong Result Register", ((res_reg) < XMC_VADC_NUM_RESULT_REGISTERS)) tail = 0U; - exit_flag= (bool)false; + exit_flag = (bool)false; if ((bool)true == XMC_VADC_GROUP_IsResultRegisterFifoHead(group_ptr, res_reg)) { @@ -2026,30 +1961,30 @@ uint32_t XMC_VADC_GROUP_GetResultFifoTail(XMC_VADC_GROUP_t *const group_ptr, uin else { /* Stop either at a node that does not have FEN set or at Node-0 */ - for(i = (int32_t)res_reg; i >= (int32_t)0; i--) + for (i = (int32_t)res_reg; i >= (int32_t)0; i--) { - rcr = group_ptr->RCR[i]; - rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; + rcr = group_ptr->RCR[i]; + rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; - if (rcr) - { - if ((int32_t)0 == i) - { + if (rcr) + { + if ((int32_t)0 == i) + { /* No more nodes. Stop here */ tail = (uint32_t)0; exit_flag = (bool)true; - } - } - else - { - /* The preceding register forms the tail of the FIFO */ - tail = (uint32_t)i + (uint32_t)1; - exit_flag = (bool)true; - } - if (exit_flag) - { - break; - } + } + } + else + { + /* The preceding register forms the tail of the FIFO */ + tail = (uint32_t)i + (uint32_t)1; + exit_flag = (bool)true; + } + if (exit_flag) + { + break; + } } } return tail; @@ -2067,13 +2002,13 @@ uint32_t XMC_VADC_GROUP_GetResultFifoHead(XMC_VADC_GROUP_t *const group_ptr, con if ((bool)true == XMC_VADC_GROUP_IsResultRegisterFifoHead(group_ptr, res_reg)) { - head = res_reg; + head = res_reg; } else { head = XMC_VADC_NUM_RESULT_REGISTERS - (uint32_t)1; - for(i = res_reg; i < XMC_VADC_NUM_RESULT_REGISTERS ; i++) + for (i = res_reg; i < XMC_VADC_NUM_RESULT_REGISTERS ; i++) { rcr = group_ptr->RCR[i]; rcr &= (uint32_t)VADC_G_RCR_FEN_Msk; diff --git a/cores/xmc_lib/XMCLib/src/xmc_wdt.c b/cores/xmc_lib/XMCLib/src/xmc_wdt.c index 11c72370..4bfa31c9 100644 --- a/cores/xmc_lib/XMCLib/src/xmc_wdt.c +++ b/cores/xmc_lib/XMCLib/src/xmc_wdt.c @@ -1,50 +1,45 @@ /** * @file xmc_wdt.c - * @date 2015-06-20 * * @cond - ********************************************************************************************************************* - * XMClib v2.1.16 - XMC Peripheral Driver Library + ***************************************************************************** + * XMClib - XMC Peripheral Driver Library * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). - ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. * - * Change History - * -------------- + * Boost Software License - Version 1.0 - August 17th, 2003 * - * 2015-02-20: - * - Initial
    + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * 2015-06-20: - * - Removed definition of GetDriverVersion API
    + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ***************************************************************************** * * @endcond */ - + /********************************************************************************************************************* * HEADER FILES ********************************************************************************************************************/ @@ -67,7 +62,7 @@ void XMC_WDT_Enable(void) #endif #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT); -#endif +#endif } /* Disables watchdog clock and resets watchdog. */ @@ -75,9 +70,9 @@ void XMC_WDT_Disable(void) { #if defined(PERIPHERAL_RESET_SUPPORTED) XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT); -#endif +#endif #if defined(CLOCK_GATING_SUPPORTED) - XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT); + XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT); #endif #if UC_FAMILY == XMC4 diff --git a/docs/Built-in-Libraries.md b/docs/Built-in-Libraries.md index 6bcb9940..5c98b796 100644 --- a/docs/Built-in-Libraries.md +++ b/docs/Built-in-Libraries.md @@ -1,7 +1,7 @@ ## Documentation Documentation of the Built-in libraries is to be found on [this page](https://github.com/Infineon/InfineonDoxyGenerator). -## DeviceControlXMC +## DeviceControl XMC ### Examples Supported @@ -52,3 +52,10 @@ With XMC 2Go (possibly also with other XMC1000 family devices), you might easily ## OneWire Library Library for One wire protocol. It could be used to access 1-wire temperature sensors, memory and other chips. +## CAN Library +This library provides support for the CAN protocol. For further details, please refer to the [README.md](https://github.com/Infineon/XMC-for-Arduino/blob/master/libraries/CAN/README.md) file in the CAN library. +|Example|Boards|Description| +|:---|:---:|:---| +|CANSender|
    • XMC1400 2GO
    | This example demonstrates how to send a CAN message. It supports two different message/frame formats: standard and extended. The CAN standard frame uses an 11-bit identifier, while the CAN extended frame uses a 29-bit identifier.| +|CANReceiver/CANReceiverCallback |
    • XMC1400 2GO
    | This example demonstrates how to receive a CAN message. There are two methods for receiving messages: the default method runs a loop that continuously polls for new messages, while the callback method registers a callback function that triggers an interrupt when data is received on the CAN bus. In both examples, messages with any ID transmitted on the CAN bus can be received. Additionally, messages can be filtered for specific IDs using the `filter()` function. | +|CANLoopBack |
    • XMC1400 2GO
    | This example demonstrates the loopback mode of CAN. In this mode, the CAN transmitter is internally connected to its receiver, allowing the message to be sent and received internally without transmission onto the actual CAN bus. | \ No newline at end of file diff --git a/docs/Contributing-and-Third-Party-Libraries.md b/docs/Contributing-and-Third-Party-Libraries.md index e8c8fc19..5cd2df0a 100644 --- a/docs/Contributing-and-Third-Party-Libraries.md +++ b/docs/Contributing-and-Third-Party-Libraries.md @@ -34,6 +34,14 @@ To merge your PR, please try to add a git tag in the format `VX.Y.Z` (e.g. V3.3. ### WIKI Because of the limitations of the github wiki, it is difficult to create PR for changes of wiki. Please refer to the answer under: https://stackoverflow.com/questions/10642928/how-can-i-make-a-pull-request-for-a-wiki-page-on-github and create a ticket for your modifications. +### Debugging +The new Arduino IDE (v2.x) supports debugging. Please refer to https://docs.arduino.cc/software/ide-v2/tutorials/ide-v2-debugger for more details. + +No additional hardware setup is required since the XMC evaluation board includes a J-Link on-board debugger. You can proceed directly to: +https://docs.arduino.cc/software/ide-v2/tutorials/ide-v2-debugger/#getting-to-know-the-debugger + +If you encounter any unusual behavior with the Arduino IDE, try clearing the cache. + ## Creating and Maintaining Third Party Libraries ### Background The Arduino IDE allows for external libraries to be added to support devices and functions diff --git a/docs/Contributors.md b/docs/Contributors.md deleted file mode 100644 index 3c675653..00000000 --- a/docs/Contributors.md +++ /dev/null @@ -1,32 +0,0 @@ -# XMC-for-Arduino -## Contributing to XMC-for-Arduino Project -First important point **All Contributions** are welcomed. - -Please contribute and raise issues via the [github repository](https://github.com/Infineon/XMC-for-Arduino/tree/develop) - -Check the **develop** branch for any Beta releases fixes for any issues you may find. - -## Developer notes - -General points on repository branches and flow - -1. _master_ branch is intended to be copy of release version -2. Please make Pull Requests to _develop_ branch for review, inclusion and availability for others -3. At next release _develop_ is merged into _master_ for release -4. Other branches are for other tests and not to be treated as anything but work in progress for now -5. Check [XMC-for-Arduino Wiki](https://github.com/Infineon/XMC-for-Arduino/wiki) for any additional information - -### Local Running using Arduino IDE (**ON WINDOWS**): -Clone the repository in arduino folder: -- Open Arduino and install any Infineon XMC library (e.g. 2.2.0) -- Open the library location in Arduino program folder -`C:\Users\"USERNAME"\AppData\Local\Arduino15\packages\Infineon\hardware\xmc` -- Open git bash, type command: -`git clone "HTTP_SSH_REPOSITORY" "LIBRARY_VERSION (e.g. 2.2.0)"` - -This is a workaround for current local compilation/testing. - -### CICD - -Currently github workflow is used for automaticaly build test and release. Workflows are defined by YAML file in the `.github/workflows` directory. -To merge your PR, please try to add a git tag in the format `VX.Y.Z` (e.g. V3.3.0) to trigger the release process in your fork and pass the compilation tests. \ No newline at end of file diff --git a/docs/Home.md b/docs/Home.md index 5526010c..4cd9586e 100644 --- a/docs/Home.md +++ b/docs/Home.md @@ -1,5 +1,5 @@ # Welcome -Welcome to the XMC-for-Arduino wiki! You'll find information about the boards ([XMC1100 2Go](XMC1100-2Go), [XMC1100 H-Bridge 2Go](XMC1100-H-Bridge-2Go), [XMC1100 Boot Kit](XMC1100-Boot-Kit), [XMC1400 2Go](XMC1400-2Go), [XMC1400 Kit for Arduino](Board/XMC1400-Kit-for-Arduino), [XMC1300 Boot Kit](XMC1300-Boot-Kit), [XMC1300 Sense2GoL](XMC1300-Sense2GoL.md), [XMC4400 Platform2Go](XMC4400-Platform2Go.md), [XMC4700 Relax Kit](XMC4700-Relax-Kit.md), and [DEMO Radar BB XMC4700](DEMO-Radar-BB-XMC4700.md) as well as additional information. +Welcome to the XMC-for-Arduino wiki! Here you'll find information about the boards ([XMC1100 2Go](XMC1100-2Go), [XMC1100 H-Bridge 2Go](XMC1100-H-Bridge-2Go), [XMC1100 Boot Kit](XMC1100-Boot-Kit), [XMC1400 2Go](XMC1400-2Go), [XMC1400 Kit for Arduino](XMC1400-Kit-for-Arduino), [XMC1300 Boot Kit](XMC1300-Boot-Kit), [XMC1300 Sense2GoL](XMC1300-Sense2GoL), [XMC4400 Platform2Go](XMC4400-Platform2Go), [XMC4700 Relax Kit](XMC4700-Relax-Kit), and [DEMO Radar BB XMC4700](DEMO-Radar-BB-XMC4700) as well as additional information. Please have a look on the sidebar to find the related information and visit our site for makers [here](www.infineon.com/4makers) with additional information about other boards. Please note that from release **version 2.0.0** onwards, only the following boards are supported: @@ -7,7 +7,7 @@ Please note that from release **version 2.0.0** onwards, only the following boar * [XMC1100 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_2go_xmc1100_v1/) * [XMC1100 Boot Kit](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc11_boot_001/) * [XMC1300 Boot Kit](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc13_boot_001/) -* [XMC1400 2Go (placeholder)]() +* [XMC1400 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc14_2go/) * [XMC1400 Kit for Arduino](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc1400_arduino/) * [XMC4200 Platform 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_plt2go_xmc4200/) * [XMC4400 Platform 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_plt2go_xmc4400//) diff --git a/docs/XMC1400-2Go.md b/docs/XMC1400-2Go.md index e9529e0e..832cad36 100644 --- a/docs/XMC1400-2Go.md +++ b/docs/XMC1400-2Go.md @@ -1,28 +1,13 @@ # Overview -This pages summarizes information about the XMC1400 2Go evaluation board and its implementation for the Arduino IDE. The XMC 2Go board consists of a XMC1400 microcontroller with a debugger implemented by a XMC4200 microcontroller. The Infineon homepage of the board can be found soon in [placeholder]. +This page summarizes information about the KIT_XMC14_2GO evaluation board and its implementation with the Arduino IDE. The board consists of a XMC1400 microcontroller with a debugger implemented by an XMC4200 microcontroller. More information about the board, including datasheets, user manuals, and schematics, can be found [here](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc14_2go/). # Arduino Pin Out -The pin layout of the XMC1400 2Go for the Arduino IDE is as follows (the original file can be found [here](https://github.com/Infineon/Assets/blob/version-2.x/Pictures/XMC%202Go_PO_v2.png)): +The pin layout of the KIT_XMC14_2GO for the Arduino IDE is as follows: -![XMC1400 2Go Pin Out for Arduin (placeholder)] +![KIT_XMC14_2GO pinout for Arduino](image/XMC1400_Kit2Go_Pinout.png) -# Key Features - - * XMC1400 microcontroller (ARM® Cortexâ„¢-M0 based) - * Power supply from USB via Debug probe (J-Link) or up to 12V external power on Vin or 5V and 3V3 pins - * Onboard J-Link debugger - * ESD and reverse current protection - * *CAN enablement (software in development)* - * Reset button - * 2 User LEDs @ P0.6 and P0.7 - * Ultra-small evaluation board (51.8 mm x 13.8 mm) - -# PCB Design Data -In case you want to change the design or reuse it for your own projects, please find the XMC1400 2Go board design under the following link: - -[XMC1400 2Go PCB Design Data (placeholder)](t) - -# Board Information, Datasheet and Additional Information -A PDF summarizing the features and layout of the XMC 14002Go board is stored on the Infineon homepage [here(placeholder)](). -The datasheet for the XMC1100 can be found here [XMC1400 Datasheet](https://www.infineon.com/dgdl/Infineon-XMC1400-DataSheet-v01_04-EN.pdf?fileId=5546d46250cc1fdf015110a2596343b2) while the respective reference manual is located here [XMC1100 Reference Manual](https://www.infineon.com/dgdl/Infineon-XMC1400-AA_ReferenceManual-UM-v01_01-EN.pdf?fileId=5546d46250cc1fdf0150f6ebc29a7109). +# :warning: Important Note +## CAN Terminal Resistor +The resistor R3 needs to be removed if the board is neither a start nor an end node of a CAN network. +For more information on CAN, please refer to [Built-in Libraries: CAN](Built-in-Libraries#can-library) \ No newline at end of file diff --git a/docs/XMC4400-Platform2Go.md b/docs/XMC4400-Platform2Go.md index f230407c..65b972d7 100644 --- a/docs/XMC4400-Platform2Go.md +++ b/docs/XMC4400-Platform2Go.md @@ -9,8 +9,7 @@ The pin layout of the XMC4400 Platform 2Go evaluation board (for 5V Shields) for ![XMC4400 Platform 2Go evaluation board (for 5V Shields) Pin Out for Arduino](https://github.com/Infineon/Assets/blob/version-2.x/Pictures/xmc4400_platform2go_PO_v2.png) -## Important Note - +## Connected I2S and Analog pin Please note that **Arduino pin number 15 & 21 (SCL & A5)** and **Arduino pin number 14 & 20 (SDA & A4)** are **connected** with each other on the board itself. Although they are different physical pins of the microcontroller, they are connected with each other on the board to comply with the original Arduino UNO Rev3 pin connections. This influences analog measurements on A4 and A5 if you are using I2C simultaneously. Details of the connection can also be found in the schematics in the user manual of the board [here](https://www.infineon.com/dgdl/Infineon-XMC4400_Platform2Go-UserManual-v01_00-EN.pdf?fileId=5546d4626f229553016f8fc159482c94). @@ -27,6 +26,9 @@ You can also cut the connection to the pins physically by cutting the marked blu ![XMC4400 Cut Lines Board](https://user-images.githubusercontent.com/26908977/96910232-7332d980-149f-11eb-81ec-2b5c23b01372.png) +## CAN Terminal Resistor +R2 needs to be removed if the board is neither start nor end node. + # Key Features * XMCâ„¢4400 (ARM® Cortexâ„¢-M4) * ARDUINO Uno compatibility diff --git a/docs/image/XMC1400_Kit2Go_Pinout.png b/docs/image/XMC1400_Kit2Go_Pinout.png new file mode 100644 index 00000000..78d7044f Binary files /dev/null and b/docs/image/XMC1400_Kit2Go_Pinout.png differ diff --git a/libraries/CAN/LICENSE b/libraries/CAN/LICENSE new file mode 100644 index 00000000..bdb03fb9 --- /dev/null +++ b/libraries/CAN/LICENSE @@ -0,0 +1,22 @@ +MIT License + +Copyright (c) 2024 Infineon Technologies AG +Copyright (c) 2017 Sandeep Mistry + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/libraries/CAN/Makefile b/libraries/CAN/Makefile new file mode 100644 index 00000000..87f800fa --- /dev/null +++ b/libraries/CAN/Makefile @@ -0,0 +1,106 @@ +FQBN ?= +PORT ?= +TESTS ?= + +$(info FQBN : $(FQBN)) +$(info PORT : $(PORT)) + + +TESTS_CONNECTED=-DTEST_CAN_CONNECTED + +TESTS_NOT_CONNECTED=-DTEST_CAN + + +CAN_connected: TESTS=-DTEST_CAN -DTEST_CAN_CONNECTED +CAN: TESTS=-DTEST_CAN + +CAN_connected CAN: unity flash + +test_all: TESTS=$(TESTS_CONNECTED) $(TESTS_NOT_CONNECTED) +test_connected: TESTS=$(TESTS_CONNECTED) +test: TESTS=$(TESTS_NOT_CONNECTED) + +test_all \ +test_connected \ +test: unity flash + + +EXAMPLES = CANReceiver CANReceiverCallback CANSender + + +clean: + -rm -rf build/* + + +arduino: clean + mkdir -p build +# copy library file +# cp -r libraries/CAN/* build +# find src -name '*.[hc]*' -a \( \! -name 'main*' \) -print -exec cp {} build \; + + +CANReceiver: arduino + cp examples/CANReceiver/CANReceiver.ino build/build.ino + +CANReceiverCallback: arduino + cp examples/CANReceiverCallback/CANReceiverCallback.ino build/build.ino + +CANSender: arduino + cp examples/CANSender/CANSender.ino build/build.ino + +# master1: +# ... + +# slave1: +# ... + + +# old unity setup part. +# TODO: Add unit test +#unity: arduino +# cp -r test/unit/Unity/*.[hc] build +# cp test/unit/src/framework/arduino/Test_*.[hc]* build +# cp test/unit/src/framework/arduino/unity_ifx.cpp build +# cp test/unit/src/framework/arduino/Test_main.ino build/build.ino + + +# For WSL and Windows : +# download arduino-cli.exe from : https://downloads.arduino.cc/arduino-cli/arduino-cli_latest_Windows_64bit.zip +compile: +ifeq ($(FQBN),) + $(error "Must set variable FQBN in order to be able to compile Arduino sketches !") +else +# CAUTION : only use '=' when assigning values to vars, not '+=' + arduino-cli.exe compile --clean --log --warnings all --fqbn $(FQBN) --build-property "compiler.c.extra_flags=\"-DUNITY_INCLUDE_CONFIG_H=1\"" \ + --build-property compiler.cpp.extra_flags="$(TESTS)" \ + --build-property compiler.ar.cmd=arm-none-eabi-gcc-ar \ + --build-property compiler.libraries.ldflags=-lstdc++ \ + --build-property compiler.arm.cmsis.path="-isystem{compiler.xmclib_include.path}/XMCLib_CAN_v4_3_0/inc -isystem{compiler.xmclib_include.path}/XMCLib/inc -isystem{compiler.dsp_include.path} -isystem{compiler.nn_include.path} -isystem{compiler.cmsis_include.path} -isystem{compiler.xmclib_include.path}/LIBS -isystem{build.variant.path} -isystem{build.variant.config_path}" \ + --build-property compiler.usb.path="-isystem{runtime.platform.path}/cores/usblib -isystem{runtime.platform.path}/cores/usblib/Common -isystem{runtime.platform.path}/cores/usblib/Class -isystem{runtime.platform.path}/cores/usblib/Class/Common -isystem{runtime.platform.path}/cores/usblib/Class/Device -isystem{runtime.platform.path}/cores/usblib/Core -isystem{runtime.platform.path}/cores/usblib/Core/XMC4000" \ + build +endif + + +upload: +ifeq ($(PORT),) + $(error "Must set variable PORT (Windows port naming convention, ie COM16) in order to be able to flash Arduino sketches !") +endif +ifeq ($(FQBN),) + $(error "Must set variable FQBN in order to be able to flash Arduino sketches !") +else + arduino-cli.exe upload -p $(PORT) --fqbn $(FQBN) build +endif + + +flash: compile upload + + +monitor: +ifeq ($(PORT),) + $(error "Must set variable PORT (Windows port naming convention, ie COM16) in order to be able to flash Arduino sketches !") +endif +ifeq ($(FQBN),) + $(error "Must set variable FQBN in order to be able to flash Arduino sketches !") +else + arduino-cli.exe monitor -c baudrate=9600 -p $(PORT) --fqbn $(FQBN) +endif diff --git a/libraries/CAN/Makefile.test b/libraries/CAN/Makefile.test new file mode 100644 index 00000000..44e22ff2 --- /dev/null +++ b/libraries/CAN/Makefile.test @@ -0,0 +1,27 @@ +### Build commands + + +### Example program +## XMC4700_Relax_Kit +make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM20 CANReceiver flash monitor + +make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM20 CANReceiverCallback flash monitor + +make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM24 CANSender flash monitor + +make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM24 CANLoopBack flash monitor + +## XMC1400_XMC2GO +make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM41 CANReceiver flash monitor + +make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM41 CANReceiverCallback flash monitor + +make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM42 CANSender flash monitor + +make FQBN=Infineon:xmc:XMC1400_XMC2GO PORT=COM42 CANLoopBack flash monitor + + +### Unit tests +make FQBN=Infineon:xmc:XMC4700_Relax_Kit PORT=COM20 CAN monitor + +make FQBN=Infineon:xmc:XMC1100_XMC2GO PORT=COM21 CAN_connected monitor diff --git a/libraries/CAN/README.md b/libraries/CAN/README.md new file mode 100644 index 00000000..a77d8d53 --- /dev/null +++ b/libraries/CAN/README.md @@ -0,0 +1,289 @@ +This is an Arduino library for XMC boards using CAN bus to send and receive data. + +Based on [Arduino CAN library](https://www.arduino.cc/reference/en/libraries/can/)/ [Github Repo](https://github.com/sandeepmistry/arduino-CAN) + +# Hardware Setup + +XMC boards with CAN support (CAN transceiver on board and CAN controller module): XMC4200 Platform2GO, XMC4400 Platform2GO, XMC4700 Relax Kit and XMC1400 XMC2GO. + +:warning: There is a 120 ohm terminal resistor on the XMC4200 Platform2GO and XMC1400 XMC2Go boards, not on the XMC4400 Platform2GO and XMC4700 Relax Kit. Please remove or add resistors as needed. + +All CAN nodes should be connected using the (twisted) pair cable for the CAN_H and CAN_L + +# Software Usage + +There are [examples](libraries/CAN/examples). See the API definition below for more details. + +# CAN API + +Here the API definition is based on: + +- [:warning: XMC specification](#warning-xmc-specification) + * [Set device id](#set-device-id) +- [Include Library](#include-library) +- [Setup](#setup) + * [Begin](#begin) + * [Set pins](#set-pins) + * [End](#end) +- [Sending data](#sending-data) + * [Begin packet](#begin-packet) + * [Writing](#writing) + * [End packet](#end-packet) +- [Receiving data](#receiving-data) + * [Parsing packet](#parsing-packet) + * [Register callback](#register-callback) + * [Packet ID](#packet-id) + * [Packet Extended](#packet-extended) + * [Packet RTR](#packet-rtr) + * [Packet DLC](#packet-dlc) + * [Available](#available) + * [Peeking](#peeking) + * [Reading](#reading) + * [Filtering](#filtering) +- [Other modes](#other-modes) + * [Loopback mode](#loopback-mode) + * [Sleep mode](#sleep-mode) + +## :warning: XMC specification + +Due to the different behavior of xmc4 series and xmc1 series, the library and provided examples was tested primarily on **xmc1400 2go**. + +The known difference is that the XMC4 is unable to receive CAN messages for all IDs. Therefore, it is necessary to define the device ID using the following function: + +### Set device id + +```arduino + CAN.setDeviceId(id); +``` + * `id` - 11 bits standard id of the device. (default: `0xFF`) + + + + +## Include Library +```arduino +#include +``` + +## Setup + +### Begin + +Initialize the library with the specified bit rate. + +```arduino +CAN.begin(bitrate); +``` + * `bitrate` - bit rate in bits per seconds (bps) (`1000E3`, `500E3`(default), `250E3`, `200E3`, `125E3`, `100E3`, `80E3`, `50E3`, `40E3`, `20E3`, `10E3`, `5E3`) + +Returns `1` on success, `0` on failure. + +### Set pins + +The RX and TX pins are determined. + + +### End + +Stop the library + +```arduino +CAN.end() +``` + + +## Sending data + +### Begin packet + +Start the sequence of sending a packet. + +```arduino +CAN.beginPacket(id); +CAN.beginPacket(id, dlc); +CAN.beginPacket(id, dlc, rtr); + +CAN.beginExtendedPacket(id); +CAN.beginExtendedPacket(id, dlc); +CAN.beginExtendedPacket(id, dlc, rtr); +``` + + * `id` - 11-bit id (standard packet) or 29-bit packet id (extended packet) + * `dlc` - (optional) value of Data Length Code (DLC) field of packet, default is size of data written in packet + * `rtr` - (optional) value of Remote Transmission Request (RTR) field of packet (`false` or `true`), defaults to `false`. RTR packets contain no data, the DLC field of the packet represents the requested length. + +Returns `1` on success, `0` on failure. + +### Writing + +Write data to the packet. Each packet can contain up to 8 bytes. + +```arduino +CAN.write(byte); + +CAN.write(buffer, length); +``` +* `byte` - single byte to write to packet + +or + +* `buffer` - data to write to packet +* `length` - size of data to write + +Returns the number of bytes written. + +**Note:** Other Arduino `Print` API's can also be used to write data into the packet + +### End packet + +End the sequence of sending a packet. + +```arduino +CAN.endPacket() +``` + +Returns `1` on success, `0` on failure. + +## Receiving data + +### Parsing packet + +Check if a packet has been received. + +```arduino +int packetSize = CAN.parsePacket(id); +``` + * `id` - 11-bit id (standard packet) or 29-bit packet id (extended packet) + +Returns the packet size in bytes or `0` if no packet was received. For RTR packets the size reflects the DLC field of the packet. + +### Register callback + +Register a callback function for when a packet is received. + +```arduino +CAN.onReceive(onReceive); + +void onReceive(int packetSize) { + // ... +} +``` + + * `onReceive` - function to call when a packet is received. + +### Packet ID + +```arduino +long id = CAN.packetId(); +``` + +Returns the id (11-bit or 29 bit) of the received packet. Standard packets have an 11-bit id, extended packets have an 29-bit id. + + +### Packet Extended + +```arduino +bool extended = CAN.packetExtended(); +``` + +Returns `true` if the received packet is extended, `false` otherwise. + +### Packet RTR + +```arduino +bool rtr = CAN.packetRtr(); +``` + +Returns the value of the Remote Transmission Request (RTR) field of the packet `true`/`false`. RTR packets contain no data, the DLC field is the requested data length. + +### Packet DLC + +```arduino +int DLC = CAN.packetDlc(); +``` + +Returns the value of the Data Length Code (DLC) field of the packet. + + +### Available + +```arduino +int availableBytes = CAN.available() +``` + +Returns number of bytes available for reading. + +### Peeking + +Peek at the next byte in the packet. + +```arduino +int b = CAN.peek(); +``` + +Returns the next byte in the packet or `-1` if no bytes are available. + +### Reading + +Read the next byte from the packet. + +```arduino +int b = CAN.read(); +``` + +Returns the next byte in the packet or `-1` if no bytes are available. + +**Note:** Other Arduino [`Stream` API's](https://www.arduino.cc/en/Reference/Stream) can also be used to read data from the packet + + +### Filtering + +Filter packets that meet the desired criteria. + +``` +CAN.filter(id); +CAN.filter(id, mask); + +CAN.filterExtended(id); +CAN.filterExtended(id, mask); +``` + + * `id` - 11-bit id (standard packet) or 29-bit packet id (extended packet) + * `mask` - (optional) 11-bit mask (standard packet) or 29-bit mask (extended packet), defaults to `0x7ff` or `0x1fffffff` (extended) + +Only packets that meet the following criteria are acknowleged and received, other packets are ignored: + +``` +if ((packetId & mask) == id) { + // acknowleged and received +} else { + // ignored +} +``` + +Returns `1` on success, `0` on failure. + + +## Other modes + +### Loopback mode + +Put the CAN controller in loopback mode, any outgoing packets will also be received. + +```arduino +CAN.loopback(); +``` + +### Sleep mode + +Put the CAN contoller in sleep mode. + +```arduino +CAN.sleep(); +``` + +Wake up the CAN contoller if it was previously in sleep mode. + +```arduino +CAN.wakeup(); +``` diff --git a/libraries/CAN/examples/CANLoopBack/CANLoopBack.ino b/libraries/CAN/examples/CANLoopBack/CANLoopBack.ino new file mode 100644 index 00000000..fd5c6275 --- /dev/null +++ b/libraries/CAN/examples/CANLoopBack/CANLoopBack.ino @@ -0,0 +1,60 @@ +// Copyright (c) 2024 Infineon Technologies AG. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include + +void setup() { + // put your setup code here, to run once: + Serial.begin(9600); + while (!Serial) + ; + + Serial.println("CAN Loopback"); + + // start the CAN bus at 500 kbps + if (!CAN.begin(500E3)) { + Serial.println("Starting CAN failed!"); + while (1) + ; + } + + // set the can in loopback mode + CAN.loopback(); +} + +void loop() { + + // + Serial.print("Sending packet"); + CAN.beginPacket(0x12); + CAN.write('L'); + CAN.write('O'); + CAN.write('O'); + CAN.write('P'); + CAN.endPacket(); + + + int packetSize = CAN.parsePacket(); + + if (packetSize) { + // received a packet + Serial.print("Received "); + + if (CAN.packetExtended()) { + Serial.print("extended "); + } + + Serial.print("packet with id 0x"); + Serial.print(CAN.packetId(), HEX); + + Serial.print(" and length "); + Serial.println(packetSize); + + while (CAN.available()) { + Serial.print((char)CAN.read()); + } + Serial.println(); + } + + delay(1000); +} diff --git a/libraries/CAN/examples/CANReceiver/CANReceiver.ino b/libraries/CAN/examples/CANReceiver/CANReceiver.ino new file mode 100644 index 00000000..a42a6de6 --- /dev/null +++ b/libraries/CAN/examples/CANReceiver/CANReceiver.ino @@ -0,0 +1,58 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include + +void setup() { + Serial.begin(9600); + while (!Serial); + delay(1000); + Serial.println("CAN Receiver"); + + // start the CAN bus at 500 kbps + if (!CAN.begin(500000)) { + Serial.println("Starting CAN failed!"); + while (1); + } +} + +void loop() { + // try to parse packet + + int packetSize = CAN.parsePacket(); + + if (packetSize) { + // received a packet + Serial.print("Received "); + + + if (CAN.packetExtended()) { + Serial.print("extended "); + } + + if (CAN.packetRtr()) { + // Remote transmission request, packet contains no data + Serial.print("RTR "); + } + + Serial.print("packet with id 0x"); + Serial.print(CAN.packetId(), HEX); + + if (CAN.packetRtr()) { + Serial.print(" and requested length "); + Serial.println(CAN.packetDlc()); + } else { + Serial.print(" and length "); + Serial.println(packetSize); + + // only print packet data for non-RTR packets + while (CAN.available()) { + Serial.print((char)CAN.read()); + } + Serial.println(); + } + + Serial.println(); + } +} + diff --git a/libraries/CAN/examples/CANReceiverCallback/CANReceiverCallback.ino b/libraries/CAN/examples/CANReceiverCallback/CANReceiverCallback.ino new file mode 100644 index 00000000..9446d12a --- /dev/null +++ b/libraries/CAN/examples/CANReceiverCallback/CANReceiverCallback.ino @@ -0,0 +1,59 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include + +void setup() { + Serial.begin(9600); + while (!Serial); + delay(1000); + Serial.println("CAN Receiver Callback"); + + // start the CAN bus at 500 kbps + if (!CAN.begin(500E3)) { + Serial.println("Starting CAN failed!"); + while (1); + } + + // register the receive callback + CAN.onReceive(onReceive); +} + +void loop() { + // do nothing +} + +void onReceive(int packetSize) { + // received a packet + Serial.print("Received "); + + if (CAN.packetExtended()) { + Serial.print("extended "); + } + + if (CAN.packetRtr()) { + // Remote transmission request, packet contains no data + Serial.print("RTR "); + } + + Serial.print("packet with id 0x"); + Serial.print(CAN.packetId(), HEX); + + if (CAN.packetRtr()) { + Serial.print(" and requested length "); + Serial.println(CAN.packetDlc()); + } else { + Serial.print(" and length "); + Serial.println(packetSize); + + // only print packet data for non-RTR packets + while (CAN.available()) { + Serial.print((char)CAN.read()); + } + Serial.println(); + } + + Serial.println(); +} + + diff --git a/libraries/CAN/examples/CANSender/CANSender.ino b/libraries/CAN/examples/CANSender/CANSender.ino new file mode 100644 index 00000000..714a0954 --- /dev/null +++ b/libraries/CAN/examples/CANSender/CANSender.ino @@ -0,0 +1,47 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include + +void setup() { + Serial.begin(9600); + while (!Serial); + + Serial.println("CAN Sender"); + + // start the CAN bus at 500 kbps + if (!CAN.begin(500E3)) { + Serial.println("Starting CAN failed!"); + while (1); + } +} + +void loop() { + // send packet: id is 11 bits, packet can contain up to 8 bytes of data + Serial.print("Sending packet ... "); + + CAN.beginPacket(0x12); + CAN.write('h'); + CAN.write('e'); + CAN.write('l'); + CAN.write('l'); + CAN.write('o'); + CAN.endPacket(); + + Serial.println("done"); + + delay(1000); + + CAN.beginExtendedPacket(0xFFF); + CAN.write('w'); + CAN.write('o'); + CAN.write('r'); + CAN.write('l'); + CAN.write('d'); + CAN.endPacket(); + + Serial.println("done"); + + delay(1000); +} + diff --git a/libraries/CAN/keywords.txt b/libraries/CAN/keywords.txt new file mode 100644 index 00000000..d0595c19 --- /dev/null +++ b/libraries/CAN/keywords.txt @@ -0,0 +1,44 @@ +####################################### +# Syntax Coloring Map For CAN +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +CAN KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 + +beginPacket KEYWORD2 +beginExtendedPacket KEYWORD2 +endPacket KEYWORD2 + +parsePacket KEYWORD2 +packetId KEYWORD2 +packetExtended KEYWORD2 +packetRtr KEYWORD2 +packetDlc KEYWORD2 + +write KEYWORD2 + +available KEYWORD2 +read KEYWORD2 +peek KEYWORD2 +flush KEYWORD2 + +onReceive KEYWORD2 +filter KEYWORD2 +filterExtended KEYWORD2 +loopback KEYWORD2 +sleep KEYWORD2 +wakeup KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/libraries/CAN/library.properties b/libraries/CAN/library.properties new file mode 100644 index 00000000..364c4c00 --- /dev/null +++ b/libraries/CAN/library.properties @@ -0,0 +1,10 @@ +name=CAN +version=1.0.0 +author=Infineon Technologies AG +maintainer=Infineon Technologies AG +sentence=This library allows the XMC µC to use the CAN for sending and receiving data. +paragraph= CAN (Controller Area Network) is a serial communication protocol that was originally developed for the automotive industry. This library allows the XMC microcontroller to send and receive data using the CAN protocol. +category=Communication +url= https://github.com/Infineon/XMC-for-Arduino/tree/master/arm/libraries/CAN +architectures=xmc + diff --git a/libraries/CAN/src/CAN.h b/libraries/CAN/src/CAN.h new file mode 100644 index 00000000..edc6ad59 --- /dev/null +++ b/libraries/CAN/src/CAN.h @@ -0,0 +1,8 @@ +#ifndef CAN_H +#define CAN_H + +#if defined(CAN_xmc) + #include "CANXMC.h" +#endif + +#endif \ No newline at end of file diff --git a/libraries/CAN/src/CANController.cpp b/libraries/CAN/src/CANController.cpp new file mode 100644 index 00000000..df4bb3f9 --- /dev/null +++ b/libraries/CAN/src/CANController.cpp @@ -0,0 +1,160 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license +// information. +#include "CANController.h" + +CANControllerClass::CANControllerClass() + : _onReceive(NULL), + + _packetBegun(false), + _txId(-1), + _txExtended(-1), + _txRtr(false), + _txDlc(0), + _txLength(0), + + _rxId(-1), + _rxExtended(false), + _rxRtr(false), + _rxDlc(0), + _rxLength(0), + _rxIndex(0) { + // overide Stream timeout value + setTimeout(0); +} + +CANControllerClass::~CANControllerClass() {} + +int CANControllerClass::begin(long /*baudRate*/) { + _packetBegun = false; + _txId = -1; + _txRtr = false; + _txDlc = 0; + _txLength = 0; + + _rxId = -1; + _rxRtr = false; + _rxDlc = 0; + _rxLength = 0; + _rxIndex = 0; + + return 1; +} + +void CANControllerClass::end() {} + +int CANControllerClass::beginPacket(int id, int dlc, bool rtr) { + if (id < 0 || id > 0x7FF) { + return 0; + } + + if (dlc > 8) { + return 0; + } + + _packetBegun = true; + _txId = id; + _txExtended = false; + _txRtr = rtr; + _txDlc = dlc; + _txLength = 0; + + memset(_txData, 0x00, sizeof(_txData)); + + return 1; +} + +int CANControllerClass::beginExtendedPacket(long id, int dlc, bool rtr) { + if (id < 0 || id > 0x1FFFFFFF) { + return 0; + } + + if (dlc > 8) { + return 0; + } + + _packetBegun = true; + _txId = id; + _txExtended = true; + _txRtr = rtr; + _txDlc = dlc; + _txLength = 0; + + memset(_txData, 0x00, sizeof(_txData)); + + return 1; +} + +int CANControllerClass::endPacket() { + if (!_packetBegun) { + return 0; + } + _packetBegun = false; + + if (_txDlc >= 0) { + _txLength = _txDlc; + } + + return 1; +} + +int CANControllerClass::parsePacket() { return 0; } + +long CANControllerClass::packetId() { return _rxId; } + +bool CANControllerClass::packetExtended() { return _rxExtended; } + +bool CANControllerClass::packetRtr() { return _rxRtr; } + +int CANControllerClass::packetDlc() { return _rxDlc; } + +size_t CANControllerClass::write(uint8_t byte) { return write(&byte, sizeof(byte)); } + +size_t CANControllerClass::write(const uint8_t *buffer, size_t size) { + if (!_packetBegun) { + return 0; + } + + if (size > (sizeof(_txData) - _txLength)) { + size = sizeof(_txData) - _txLength; + } + + memcpy(&_txData[_txLength], buffer, size); + _txLength += size; + + return size; +} + +int CANControllerClass::available() { return (_rxLength - _rxIndex); } + +int CANControllerClass::read() { + if (!available()) { + return -1; + } + + return _rxData[_rxIndex++]; +} + +int CANControllerClass::peek() { + if (!available()) { + return -1; + } + + return _rxData[_rxIndex]; +} + +void CANControllerClass::flush() {} + +void CANControllerClass::onReceive(void (*callback)(int)) { _onReceive = callback; } + +int CANControllerClass::filter(int /*id*/, int /*mask*/) { return 0; } + +int CANControllerClass::filterExtended(long /*id*/, long /*mask*/) { return 0; } + +int CANControllerClass::observe() { return 0; } + +int CANControllerClass::loopback() { return 0; } + +int CANControllerClass::sleep() { return 0; } + +int CANControllerClass::wakeup() { return 0; } diff --git a/libraries/CAN/src/CANController.h b/libraries/CAN/src/CANController.h new file mode 100644 index 00000000..6d914279 --- /dev/null +++ b/libraries/CAN/src/CANController.h @@ -0,0 +1,73 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license +// information. +#include +#ifndef CAN_CONTROLLER_H + #define CAN_CONTROLLER_H + +class CANControllerClass : public Stream { + +public: + virtual int begin(long baudRate); + virtual void end(); + + int beginPacket(int id, int dlc = -1, bool rtr = false); + int beginExtendedPacket(long id, int dlc = -1, bool rtr = false); + virtual int endPacket(); + + virtual int parsePacket(); + long packetId(); + bool packetExtended(); + bool packetRtr(); + int packetDlc(); + + // from Print + virtual size_t write(uint8_t byte); + virtual size_t write(const uint8_t *buffer, size_t size); + + // from Stream + virtual int available(); + virtual int read(); + virtual int peek(); + virtual void flush(); + + virtual void onReceive(void (*callback)(int)); + + virtual int filter(int id) { return filter(id, 0x7ff); } + + virtual int filter(int id, int mask); + + virtual int filterExtended(long id) { return filterExtended(id, 0x1fffffff); } + + virtual int filterExtended(long id, long mask); + + virtual int observe(); + virtual int loopback(); + virtual int sleep(); + virtual int wakeup(); + +protected: + CANControllerClass(); + virtual ~CANControllerClass(); + +protected: + void (*_onReceive)(int); + + bool _packetBegun; + long _txId; + bool _txExtended; + bool _txRtr; + int _txDlc; + int _txLength; + uint8_t _txData[8]; + + long _rxId; + bool _rxExtended; + bool _rxRtr; + int _rxDlc; + int _rxLength; + int _rxIndex; + uint8_t _rxData[8]; +}; + +#endif diff --git a/libraries/CAN/src/CANXMC.cpp b/libraries/CAN/src/CANXMC.cpp new file mode 100644 index 00000000..69ef539f --- /dev/null +++ b/libraries/CAN/src/CANXMC.cpp @@ -0,0 +1,393 @@ +#include "CANXMC.h" +#include + +/* CAN Receive Message Object definition, can also be used for transmit remote + * frame*/ +XMC_CAN_MO_t CAN_msg_rx = { + .can_mo_ptr = (CAN_MO_TypeDef *)CAN_MO0, + {0xFF, XMC_CAN_FRAME_TYPE_STANDARD_11BITS, // {can_identifier, can_id_mode + XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1}, // can_priority} + {0x000, 1U}, // {can_id_mask, can_ide_mask} + .can_data_length = 0U, + .can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ, +}; + +/* CAN Transmit Message Object definition */ +XMC_CAN_MO_t CAN_msg_tx = { + .can_mo_ptr = (CAN_MO_TypeDef *)CAN_MO1, + {0xFF, XMC_CAN_FRAME_TYPE_STANDARD_11BITS, // {can_identifier, can_id_mode + XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1}, // can_priority} + {0x7FFU, 1U}, // {can_id_mask, can_ide_mask} + .can_data_length = 0U, + .can_mo_type = XMC_CAN_MO_TYPE_TRANSMSGOBJ, +}; + +/* Flag for receive interrupt*/ +static volatile bool can_frame_received = false; + +/* construct with configuration of different target */ +CANXMC::CANXMC(XMC_ARD_CAN_t *conf) { _XMC_CAN_config = conf; } + +CANXMC::~CANXMC() {} + +int CANXMC::setIdentifier(long id) { // TODO: delete in the future! + // figure out filtering problem for xmc4700 + XMC_CAN_MO_SetIdentifier(&CAN_msg_rx, id); + return 0; +}; + +/** + * @brief Initializes the CAN interface with the specified baudrate. + * + * This function configures the CAN bit time, enables the CAN node, and sets up the necessary pin + * configurations. + * + * @param baudrate The desired baudrate for the CAN interface. The default value is 500,000 bps. + * @return Returns 1 if the initialization is successful, 0 otherwise. + */ +int CANXMC::begin(long baudrate /*= 500e3*/) { + /* CAN bit time configuration*/ + XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t CAN_NODE_bit_time_config = { + .can_frequency = _XMC_CAN_config->can_frequency, + .baudrate = (uint32_t)baudrate, + .sample_point = (uint16_t)(80 * 100), + .sjw = (uint16_t)1, + }; + + XMC_CAN_Enable(CAN_xmc); + + /* Configuration of CAN Node and enable the clock */ + XMC_CAN_InitEx(CAN_xmc, _XMC_CAN_config->can_clock, _XMC_CAN_config->can_frequency); + if (XMC_CAN_STATUS_SUCCESS == XMC_CAN_NODE_NominalBitTimeConfigureEx( + _XMC_CAN_config->can_node, &CAN_NODE_bit_time_config)) { + XMC_CAN_NODE_EnableConfigurationChange(_XMC_CAN_config->can_node); + XMC_CAN_NODE_SetInitBit(_XMC_CAN_config->can_node); + XMC_CAN_NODE_ReSetAnalyzerMode(_XMC_CAN_config->can_node); + + /* Configure CAN NODE input pin */ + XMC_GPIO_Init(_XMC_CAN_config->tx.port, _XMC_CAN_config->tx.pin, + &(_XMC_CAN_config->tx_config)); + XMC_GPIO_SetHardwareControl(_XMC_CAN_config->tx.port, _XMC_CAN_config->tx.pin, + XMC_GPIO_HWCTRL_DISABLED); + XMC_GPIO_Init(_XMC_CAN_config->rx.port, _XMC_CAN_config->rx.pin, + &(_XMC_CAN_config->rx_config)); + XMC_GPIO_SetHardwareControl(_XMC_CAN_config->rx.port, _XMC_CAN_config->rx.pin, + XMC_GPIO_HWCTRL_DISABLED); + XMC_CAN_NODE_SetReceiveInput(_XMC_CAN_config->can_node, _XMC_CAN_config->node_input); + + /* Allocate the rx and tx message object*/ + XMC_CAN_MO_Config(&CAN_msg_rx); + XMC_CAN_AllocateMOtoNodeList(CAN_xmc, _XMC_CAN_config->can_node_num, 0); + XMC_CAN_MO_Config(&CAN_msg_tx); + XMC_CAN_AllocateMOtoNodeList(CAN_xmc, _XMC_CAN_config->can_node_num, 1); + + /* Message object accepts the reception of both, standard and extended + * frames */ + XMC_CAN_MO_AcceptStandardAndExtendedID(&CAN_msg_rx); + +#if (UC_SERIES == XMC14) + // select interrupt source (A,B,C etc) input to NVIC node (only for XMC1400 + // devices) + XMC_SCU_SetInterruptControl(_XMC_CAN_config->irq_num, _XMC_CAN_config->irq_source); +#endif + + XMC_CAN_MO_SetEventNodePointer(&CAN_msg_rx, XMC_CAN_MO_POINTER_EVENT_RECEIVE, + _XMC_CAN_config->irq_service_request); + XMC_CAN_MO_EnableEvent(&CAN_msg_rx, XMC_CAN_MO_EVENT_RECEIVE); + XMC_CAN_NODE_DisableConfigurationChange(_XMC_CAN_config->can_node); + XMC_CAN_NODE_ResetInitBit(_XMC_CAN_config->can_node); + + return 1; + } else { + return 0; + } +}; + +/** + * @brief Disables the CAN module and ends the CANXMC object. + * + * This function disables the CAN module and ends the CANXMC object. It disables the receive event + * for the CAN message object and disables the CAN module using the XMC_CAN_Disable function. + */ +void CANXMC::end() { + XMC_CAN_MO_DisableEvent(&CAN_msg_rx, XMC_CAN_MO_EVENT_RECEIVE); + XMC_CAN_Disable(CAN_xmc); + CANControllerClass::end(); +}; + +/** + * Ends the packet transmission on the CAN bus. + * + * @return 1 if the packet was successfully transmitted, 0 otherwise. + */ +int CANXMC::endPacket() { + if (!CANControllerClass::endPacket()) { + return 0; + } + + if (_txRtr) { + // TODO: LJ: how to receive remote frame? and response... + + /* Configure remote frame to be transmitted and data length code */ + if (_txExtended) { + XMC_CAN_MO_SetExtendedID(&CAN_msg_rx); + } else { + XMC_CAN_MO_SetStandardID(&CAN_msg_rx); + } + XMC_CAN_MO_SetIdentifier(&CAN_msg_rx, _txId); + XMC_CAN_MO_SetDataLengthCode(&CAN_msg_rx, _txLength); + XMC_CAN_MO_UpdateData(&CAN_msg_rx); + + /* Send remote frame */ + XMC_CAN_STATUS_t send_status = XMC_CAN_MO_Transmit(&CAN_msg_rx); + + if (send_status == XMC_CAN_STATUS_SUCCESS) { + return 1; + } else { + return 0; + } + + } else { + /* Configure data frame to be transmitted and data length code */ + if (_txExtended) { + XMC_CAN_MO_SetExtendedID(&CAN_msg_tx); + } else { + XMC_CAN_MO_SetStandardID(&CAN_msg_tx); + } + XMC_CAN_MO_SetIdentifier(&CAN_msg_tx, _txId); + memcpy(CAN_msg_tx.can_data_byte, _txData, _txLength); + XMC_CAN_MO_SetDataLengthCode(&CAN_msg_tx, _txLength); + + XMC_CAN_MO_UpdateData(&CAN_msg_tx); + + /* Send data frame */ + XMC_CAN_STATUS_t send_status = XMC_CAN_MO_Transmit(&CAN_msg_tx); + + if (send_status == XMC_CAN_STATUS_SUCCESS) { + return 1; + } else { + return 0; + } + } +}; + +/** + * @brief Parses a CAN packet received by the XMC_CAN module. + * + * This function waits until a new CAN packet is available in the receive buffer, + * then retrieves the packet information such as the identifier, frame type, remote + * transmission request (RTR), data length code (DLC), and data payload. If the packet + * is an extended frame, the `_rxExtended` flag is set to true. If the packet is an RTR + * frame, the `_rxRtr` flag is set to true and the `_rxLength` is set to 0. Otherwise, + * the `_rxLength` is set to the DLC and the data payload is copied to the `_rxData` + * buffer. Finally, the function resets the receive flag and returns the length of the + * received packet. + * + * @return The length of the received packet. + */ +int CANXMC::parsePacket() { + while ((XMC_CAN_MO_GetStatus(&CAN_msg_rx) & CAN_MO_MOSTAT_NEWDAT_Msk) >> + CAN_MO_MOSTAT_NEWDAT_Pos != + 1) + ; + XMC_CAN_MO_Receive(&CAN_msg_rx); + + /* check CAN frame type */ + _rxId = XMC_CAN_MO_GetIdentifier(&CAN_msg_rx); + + if (CAN_msg_rx.can_id_mode == XMC_CAN_FRAME_TYPE_EXTENDED_29BITS) { + _rxExtended = true; + } else { + _rxExtended = false; + }; + + _rxRtr = CAN_msg_rx.can_mo_ptr->MOFCR & (uint32_t)CAN_MO_MOFCR_RMM_Msk; + _rxDlc = CAN_msg_rx.can_data_length; + if (_rxRtr) { + _rxLength = 0; + } else { + _rxLength = _rxDlc; + memcpy(_rxData, CAN_msg_rx.can_data_byte, _rxLength); + } + /* set the flag back and wait for next receive */ + can_frame_received = false; + + _rxIndex = 0; + + return _rxLength; +}; + +/** + * Sets the callback function to be called when a CAN message is received. + * + * @param callback A pointer to the function to be called when a CAN message is received. + * The function should take an integer parameter. + * Pass nullptr to disable the callback. + */ +void CANXMC::onReceive(void (*callback)(int)) { + CANControllerClass::onReceive(callback); + if (callback) { + NVIC_EnableIRQ(_XMC_CAN_config->irq_num); + } else { + NVIC_DisableIRQ(_XMC_CAN_config->irq_num); + } +}; + +/** + * Sets the filter for the CAN message object. + * + * @param id The identifier to match against incoming messages. + * @param mask The mask to apply to the identifier for filtering. + * @return 1 if the filter was set successfully, 0 otherwise. + */ +int CANXMC::filter(int id, int mask) { + XMC_CAN_MO_SetStandardID(&CAN_msg_rx); + XMC_CAN_MO_SetIdentifier(&CAN_msg_rx, id); + XMC_CAN_MO_AcceptOnlyMatchingIDE(&CAN_msg_rx); + XMC_CAN_MO_SetAcceptanceMask(&CAN_msg_rx, mask); + + return 1; +}; + +/** + * Sets the filter for extended CAN messages. + * + * @param id The identifier to match against the received message. + * @param mask The mask to apply to the identifier for filtering. + * @return 1 if the filter was set successfully, 0 otherwise. + */ +int CANXMC::filterExtended(long id, long mask) { + XMC_CAN_MO_SetExtendedID(&CAN_msg_rx); + XMC_CAN_MO_SetIdentifier(&CAN_msg_rx, id); + XMC_CAN_MO_AcceptOnlyMatchingIDE(&CAN_msg_rx); + XMC_CAN_MO_SetAcceptanceMask(&CAN_msg_rx, mask); + return 1; +}; + +int CANXMC::observe() { + // TODO: LJ: no idea what this is + return 0; +}; + +int CANXMC::loopback() { + // TODO: LJ: It is actually only some application level... it is not + // library... + + /* reset CAN nodes*/ + XMC_CAN_Disable(CAN_xmc); + /* CAN bit time configuration*/ + XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t CAN_NODE_bit_time_config = { + .can_frequency = _XMC_CAN_config->can_frequency, + .baudrate = (uint32_t)50000, // TODO: LJ: need to be changed + .sample_point = (uint16_t)(80 * 100), + .sjw = (uint16_t)1, + }; + + XMC_CAN_Enable(CAN_xmc); + /* Configuration of CAN Node and enable the clock */ + XMC_CAN_InitEx(CAN_xmc, _XMC_CAN_config->can_clock, _XMC_CAN_config->can_frequency); + if (XMC_CAN_STATUS_SUCCESS == + XMC_CAN_NODE_NominalBitTimeConfigureEx(CAN_NODE1, &CAN_NODE_bit_time_config)) { + + /* Enable CAN node 1 for Loop-back mode */ + XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE1); + XMC_CAN_NODE_EnableLoopBack(CAN_NODE1); + XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE1); + XMC_CAN_NODE_ResetInitBit(CAN_NODE1); + + /* Initializes CAN tx Message Object for loopback */ + XMC_CAN_MO_Config(&CAN_msg_tx); + /* Allocate tx Message object to Node 1 */ + XMC_CAN_AllocateMOtoNodeList(CAN_xmc, 1, 1); + } else { + return 0; + } + + if (XMC_CAN_STATUS_SUCCESS == + XMC_CAN_NODE_NominalBitTimeConfigureEx(CAN_NODE0, &CAN_NODE_bit_time_config)) { + /* Enable CAN node 0 for Loop-back mode */ + XMC_CAN_NODE_EnableConfigurationChange(CAN_NODE0); + XMC_CAN_NODE_EnableLoopBack(CAN_NODE0); + XMC_CAN_NODE_DisableConfigurationChange(CAN_NODE0); + XMC_CAN_NODE_ResetInitBit(CAN_NODE0); + + /* Initializes CAN rx Message Object for loopback */ + XMC_CAN_MO_Config(&CAN_msg_rx); + /*Allocate rx Message object to Node 0 */ + XMC_CAN_AllocateMOtoNodeList(CAN_xmc, 0, 0); + XMC_CAN_MO_AcceptStandardAndExtendedID(&CAN_msg_rx); + /* Enable receive event */ + XMC_CAN_MO_SetEventNodePointer(&CAN_msg_rx, XMC_CAN_MO_POINTER_EVENT_RECEIVE, + _XMC_CAN_config->irq_service_request); + XMC_CAN_MO_EnableEvent(&CAN_msg_rx, XMC_CAN_MO_EVENT_RECEIVE); + + return 1; + } else { + return 0; + } +}; + + +/** + * Puts the CAN module into sleep mode. + * This function disables the CAN module by setting the EDIS bit in the CLC register. + * @return true if the CAN module is successfully put into sleep mode, false otherwise. + */ +int CANXMC::sleep() { + CAN_xmc -> CLC |= CAN_CLC_EDIS_Msk; + return CAN_xmc -> CLC & CAN_CLC_EDIS_Msk != 0; +}; + +/** + * @brief Wakes up the CAN module. + * This function is used to wake up the CAN module by clearing the EDIS bit in the CLC register. + * @return true if the CAN module is successfully woken up, false otherwise. + */ +int CANXMC::wakeup() { + CAN_xmc -> CLC &= CAN_CLC_EDIS_Msk; + return CAN_xmc -> CLC & CAN_CLC_EDIS_Msk == 0; +}; + +/** + * @brief This function is called when an interrupt is triggered for the CANXMC module. + * It checks if a CAN frame has been received and if so, it parses the packet and + * calls the _onReceive() function with the number of available frames. + */ +void CANXMC::onInterrupt() { + if (can_frame_received == true) { + CAN.parsePacket(); + CAN._onReceive(CAN.available()); + } +}; + +/* Interrupt Handler */ +/** + * @brief Interrupt handler for CAN0_7_IRQHandler (XMC4 series) or CAN0_3_IRQHandler (XMC1 series). + * + * This function is called when a CAN frame is received. It sets the can_frame_received flag to true + * and calls the onInterrupt() function of the CAN object. + * + * @note This function is intended to be used as an interrupt handler and should not be called + * directly. + */ +extern "C" { +#if (UC_FAMILY == XMC4) +void CAN0_7_IRQHandler() { + /* Set the frame received flag to true */ + can_frame_received = true; + + CAN.onInterrupt(); +} +#endif + +#if (UC_SERIES == XMC14) +void CAN0_3_IRQHandler() { + /* Set the frame received flag to true */ + can_frame_received = true; + + CAN.onInterrupt(); +} +#endif +} + +CANXMC CAN(&XMC_CAN_0); diff --git a/libraries/CAN/src/CANXMC.h b/libraries/CAN/src/CANXMC.h new file mode 100644 index 00000000..9e63e43c --- /dev/null +++ b/libraries/CAN/src/CANXMC.h @@ -0,0 +1,35 @@ +#include "CANController.h" +#include "xmc_can.h" + +class CANXMC : public CANControllerClass { + +public: + CANXMC(XMC_ARD_CAN_t *conf); + ~CANXMC() final; + + int begin(long baudRate = 500E3) final; + void end() final; + + int endPacket() final; + + int parsePacket() final; + + void onReceive(void (*callback)(int)) final; + + using CANControllerClass::filter; + int filter(int id, int mask) final; + using CANControllerClass::filterExtended; + int filterExtended(long id, long mask) final; + + int observe() final; + int loopback() final; + int sleep() final; + int wakeup() final; + int setIdentifier(long); + static void onInterrupt(); + +private: + XMC_ARD_CAN_t *_XMC_CAN_config; +}; + +extern CANXMC CAN; \ No newline at end of file diff --git a/libraries/DeviceControlXMC/src/DeviceControlXMC.cpp b/libraries/DeviceControlXMC/src/DeviceControlXMC.cpp index ffebd590..d17dd94b 100644 --- a/libraries/DeviceControlXMC/src/DeviceControlXMC.cpp +++ b/libraries/DeviceControlXMC/src/DeviceControlXMC.cpp @@ -239,7 +239,7 @@ void XMCClass::configureSleepMode( sleepMode_t type, usic_t usic, ledt_t ledt, ccu_t ccu, wdt_t wdt, flash_t flash ) { sleep_config |= usic; -#if (defined (LEDTS0) || ( LEDTS1 )|| ( LEDTS2)) +#if (defined(LEDTS0) || defined(LEDTS1) || defined(LEDTS2)) sleep_config |= ledt; #else XMC_UNUSED_ARG( ledt ); diff --git a/libraries/DeviceControlXMC/src/DeviceControlXMC.h b/libraries/DeviceControlXMC/src/DeviceControlXMC.h index 35351681..475c7e3c 100644 --- a/libraries/DeviceControlXMC/src/DeviceControlXMC.h +++ b/libraries/DeviceControlXMC/src/DeviceControlXMC.h @@ -111,7 +111,8 @@ enum sleepMode_t { USIC_OFF = 0x00, }; enum ledt_t { - #if (defined (LEDTS0) || ( LEDTS1 )|| ( LEDTS2)) + #if (defined(LEDTS0) || defined(LEDTS1) || defined(LEDTS2)) + LEDT_ON = XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 | XMC_SCU_PERIPHERAL_CLOCK_LEDTS1, #endif LEDT_OFF = 0x00, diff --git a/tests/testdefines/testdefines.ino b/tests/testdefines/testdefines.ino index 28a9ca3a..df1b7166 100644 --- a/tests/testdefines/testdefines.ino +++ b/tests/testdefines/testdefines.ino @@ -6,7 +6,7 @@ extern char VeneerStart, VeneerEnd, eROData; #endif extern char __ram_code_start, __ram_code_end, __bss_end, __bss_start; extern char Heap_Bank1_Start, Heap_Bank1_End; -extern char sText, __initial_sp, __stack_start, __data_start, __data_end; +extern char sText, __initial_sp, __data_start, __data_end; #define str(x) Serial.println( #x ) #define str1(x) str(x) @@ -16,7 +16,7 @@ uint32_t temp, code_size; void setup() { -delay( 60 ); +delay( 2000 ); Serial.begin( 115200, SERIAL_8N1 ); Serial.println( "PC Services - XMC-for-Arduino useful defines example" ); Serial.print( "Built on: " ); @@ -90,7 +90,7 @@ code_size += temp; Serial.println( temp ); #endif Serial.print( "Stack\t\t" ); -temp = &__initial_sp - &__stack_start; +temp = &__initial_sp ; Serial.println( temp ); Serial.print( "Data\t\t" ); temp = &__data_end - &__data_start; @@ -132,7 +132,9 @@ Serial.println( NUM_ANALOG_INPUTS ); Serial.print( "DAC\t\t" ); Serial.println( NUM_ANALOG_OUTPUTS ); #endif - +#ifdef CAN +Serial.print( "CAN enabled" ); +#endif str2( NUM_LEDS ); Serial.write( '\t' ); str1( NUM_LEDS ); diff --git a/tools/xmc_data.py b/tools/xmc_data.py index 4320b12e..e93b9644 100644 --- a/tools/xmc_data.py +++ b/tools/xmc_data.py @@ -57,6 +57,20 @@ "bitposition_LSB":"12" } }, + "XMC1404-0200":{ + "IDCHIP":{ + "addr":"40010004", + "size":"4", + "value":"00014000", + "mask":"FFFFF000" + }, + "FLSIZE":{ + "addr":"40000404", + "size": "4", + "bitposition_MSB":"17", + "bitposition_LSB":"12" + } + }, "XMC4200-256":{ "IDCHIP":{ "addr":"50004004", diff --git a/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h b/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h index e8eb4787..9a9b6852 100644 --- a/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h +++ b/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h @@ -244,8 +244,8 @@ XMC_UART_t XMC_UART_0 = #endif }, .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH }, .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, #ifdef SERIAL_DEBUG @@ -255,8 +255,8 @@ XMC_UART_t XMC_UART_0 = #endif }, .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH }, #ifdef SERIAL_DEBUG .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C1_DX0_P1_3, @@ -288,8 +288,9 @@ XMC_SPI_t XMC_SPI_0 = }, .mosi_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .miso = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, @@ -306,8 +307,9 @@ XMC_SPI_t XMC_SPI_0 = }, .sclkout_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + } }; @@ -325,8 +327,9 @@ XMC_I2C_t XMC_I2C_0 = }, .sda_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .scl = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, @@ -334,8 +337,9 @@ XMC_I2C_t XMC_I2C_0 = }, .scl_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = XMC_INPUT_F, .input_source_dx1 = XMC_INPUT_E, @@ -350,18 +354,21 @@ XMC_I2S_t i2s_config = { .input_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .sclk_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .wa_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .protocol_irq_num = (IRQn_Type) USIC0_2_IRQn, .protocol_irq_service_request = 2 diff --git a/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h b/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h index 8afaa445..757088fb 100644 --- a/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h +++ b/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h @@ -190,8 +190,9 @@ XMC_UART_t XMC_UART_0 = #endif }, .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .tx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, #ifdef SERIAL_DEBUG @@ -201,8 +202,9 @@ XMC_UART_t XMC_UART_0 = #endif }, .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C0_DX0_DX3INS, .input_source_dx1 = XMC_INPUT_INVALID, @@ -234,8 +236,9 @@ XMC_SPI_t XMC_SPI_0 = }, .mosi_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .miso = { .port = (XMC_GPIO_PORT_t*)PORT0_BASE, @@ -252,8 +255,9 @@ XMC_SPI_t XMC_SPI_0 = }, .sclkout_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + } }; @@ -271,8 +275,9 @@ XMC_I2C_t XMC_I2C_0 = }, .sda_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .scl = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, @@ -280,8 +285,9 @@ XMC_I2C_t XMC_I2C_0 = }, .scl_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = XMC_INPUT_F, .input_source_dx1 = XMC_INPUT_E, @@ -304,8 +310,9 @@ XMC_I2C_t XMC_I2C_1 = }, .sda_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .scl = { .port = (XMC_GPIO_PORT_t*)PORT0_BASE, @@ -313,8 +320,9 @@ XMC_I2C_t XMC_I2C_1 = }, .scl_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = XMC_INPUT_B, .input_source_dx1 = XMC_INPUT_A, @@ -329,18 +337,21 @@ XMC_I2S_t i2s_config = { .input_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .sclk_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .wa_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .protocol_irq_num = (IRQn_Type) USIC0_2_IRQn, .protocol_irq_service_request = 2 diff --git a/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h b/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h index 85b17a49..b9cad522 100755 --- a/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h +++ b/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h @@ -243,8 +243,9 @@ XMC_UART_t XMC_UART_0 = #endif }, .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, #ifdef SERIAL_DEBUG @@ -254,8 +255,8 @@ XMC_UART_t XMC_UART_0 = #endif }, .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH }, #ifdef SERIAL_DEBUG .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C1_DX0_P1_3, @@ -287,8 +288,9 @@ XMC_SPI_t XMC_SPI_0 = }, .mosi_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .miso = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, @@ -305,8 +307,9 @@ XMC_SPI_t XMC_SPI_0 = }, .sclkout_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + } }; @@ -324,8 +327,9 @@ XMC_I2C_t XMC_I2C_0 = }, .sda_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .scl = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, @@ -333,8 +337,9 @@ XMC_I2C_t XMC_I2C_0 = }, .scl_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = XMC_INPUT_F, .input_source_dx1 = XMC_INPUT_E, diff --git a/variants/XMC1400/XMC1000_RomFunctionTable.h b/variants/XMC1400/XMC1000_RomFunctionTable.h index d4df47a3..aaf80ff3 100644 --- a/variants/XMC1400/XMC1000_RomFunctionTable.h +++ b/variants/XMC1400/XMC1000_RomFunctionTable.h @@ -1,41 +1,41 @@ /********************************************************************************************************************* * @file XMC1000_RomFunctionTable.h - * @brief ROM functions prototypes for the XMC1400-Series - * @version V1.0 - * @date 03 Sep 2015 + * @brief ROM functions prototypes for the XMC1000-Series * * @cond ********************************************************************************************************************* - * Copyright (c) 2015-2016, Infineon Technologies AG + * Copyright (c) 2013-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. ********************************************************************************************************************* * - **************************** Change history ********************************* - * V1.0, 03 Sep 2015, JFT : Initial version - ***************************************************************************** * @endcond */ @@ -61,6 +61,17 @@ extern "C" { /* Pointer to Request BMI installation routine */ #define _BmiInstallationReq (ROM_FUNCTION_TABLE_START + 0x08U) +/* Pointer to Calculate chip temperature routine */ +#define _CalcTemperature (ROM_FUNCTION_TABLE_START + 0x0CU) + +/* Pointer to Erase Flash Sector routine */ +#define _NvmEraseSector (ROM_FUNCTION_TABLE_START + 0x10U) + +/* Pointer to Program & Verify Flash Block routine */ +#define _NvmProgVerifyBlock (ROM_FUNCTION_TABLE_START + 0x14U) + +/* Pointer to Calculate target level for temperature comparison routine */ +#define _CalcTSEVAR (ROM_FUNCTION_TABLE_START + 0x20U) /* *************************************************************************** ******************************** Enumerations ******************************** @@ -95,79 +106,140 @@ typedef enum TagNVMStatus } NVM_STATUS; -/* *************************************************************************** +/**************************************************************************** *********************************** Macros *********************************** *************************************************************************** */ -/* *************************************************************************** +/**************************************************************************** Description: Erase granularity = 1 Page of 16 blocks of 16 Bytes = Equivalent to 256 Bytes using this routine. Input parameters: -– Logical address of the Flash Page to be erased which must be page aligned +- Logical address of the Flash Page to be erased which must be page aligned and in NVM address range Return status: -– OK (NVM_PASS) -– Invalid address (NVM_E_DST_ALIGNMENT or NVM_E_DST_AREA_EXCEED) -– Operation failed (Error during low level NVM programming driver): - NVM_E_FAIL - NVM_E_VERIFY - NVM_E_NVM_FAIL +- OK (NVM_PASS) +- Invalid address (NVM_E_DST_ALIGNMENT or NVM_E_DST_AREA_EXCEED) Prototype: - NVM_STATUS XMC1000_NvmErasePage(uint32_t *pageAddr) -*************************************************************************** */ -#define XMC1000_NvmErasePage (*((NVM_STATUS (**) (uint32_t * )) \ - _NvmErase)) + int32_t XMC1000_NvmErasePage(uint32_t *pageAddr) +****************************************************************************/ +#define XMC1000_NvmErasePage (*((int32_t (**) (uint32_t * )) _NvmErase)) -/* *************************************************************************** +/**************************************************************************** Description: This procedure performs erase (skipped if not necessary), program and verify of selected Flash page. Input parameter: -– Logical address of the target Flash Page, must be page aligned and in NVM +- Logical address of the target Flash Page, must be page aligned and in NVM address range -– Address in SRAM where the data starts, must be 4-byte aligned +- Address in SRAM where the data starts, must be 4-byte aligned Return status: -– OK (NVM_PASS) -– Invalid addresses +- OK (NVM_PASS) +- Invalid addresses NVM_E_DST_ALIGNMENT NVM_E_SRC_ALIGNMENT NVM_E_DST_AREA_EXCEED NVM_E_SRC_AREA_EXCCEED -– Operation failed (Error during low level NVM programming driver): - NVM_E_FAIL +- Operation failed (Error during low level NVM programming driver): NVM_E_VERIFY NVM_E_NVM_FAIL Prototype: - NVM_STATUS XMC1000_NvmProgVerify(const uint32_t *srcAddr, uint32_t *dstAddr) -*************************************************************************** */ -#define XMC1000_NvmProgVerify (*((NVM_STATUS (**) (const uint32_t * ,\ - uint32_t * ))\ - _NvmProgVerify)) + int32_t XMC1000_NvmProgVerify(const uint32_t *srcAddr, uint32_t *dstAddr) +****************************************************************************/ +#define XMC1000_NvmProgVerify (*((int32_t (**) (const uint32_t * ,uint32_t * )) _NvmProgVerify)) -/* *************************************************************************** +/**************************************************************************** Description: This procedure initiates installation of a new BMI value. In particular, it can be used as well as to restore the state upon delivery for a device already in User Productive mode. Input parameter: -– BMI value to be installed +- BMI value to be installed Return status: -– wrong input BMI value (0x01) - only upon error, if OK the procedure triggers +- wrong input BMI value (0x01) - only upon error, if OK the procedure triggers a reset respectively does not return to calling routine ! Prototype: unsigned long XMC1000_BmiInstallationReq(unsigned short requestedBmiValue) -**************************************************************************** */ -#define XMC1000_BmiInstallationReq (*((uint32_t (**) (uint16_t)) \ - _BmiInstallationReq)) +*****************************************************************************/ +#define XMC1000_BmiInstallationReq (*((uint32_t (**) (uint16_t)) _BmiInstallationReq)) + +/**************************************************************************** +Description: This procedure calculates the current chip temperature as +measured by the XMC1000 built-in sensor, based on data from Flash including +trimming values and pre-calculated constants and data from the actual +measurement (read from Temperature Sensor Counter2 Monitor Register ANATSEMON). + +Input parameter: +- None + +Return status: +- chip temperature in degree Kelvin + +Prototype: + uint32_t XMC1000_CalcTemperature(void) +*****************************************************************************/ +#define XMC1000_CalcTemperature (*((uint32_t (**) (void )) _CalcTemperature)) + +/**************************************************************************** +Description: XMC1000 Flash can be erased with granularity of one sector, i.e. + 16 pages of (16 blocks of 16 Bytes) = 4K Bytes using this routine. + +Input parameter: +– sectorAddr: logical address of the Flash Sector to be erased, must be in NVM address range + +Return status: +– OK (NVM_PASS) +– invalid address (NVM_E_DST_AREA_EXCEEDED, NVM_E_DST_ALIGNMENT) + +Prototype: + int32_t XMC1000_NvmEraseSector(uint32_t *sectorAddr) +*****************************************************************************/ +#define XMC1000_NvmEraseSector (*((int32_t (**) (uint32_t * )) _NvmEraseSector)) + +/**************************************************************************** +Description: XMC1100 Flash can be programmed and verified with granularity of +one block (4 words of 4 Bytes) = 16 Bytes using this routine. + +Input parameter: +– dstAddr: logical address of the Flash Sector to be erased, must be in NVM address range +- srcAddr: address in SRAM where the data starts + +Return status: +– OK (NVM_PASS) +– invalid addresses (NVM_E_SRC_AREA_EXCEEDED, NVM_E_SRC_ALIGNMENT, + NVM_E_DST_AREA_EXCEEDED, NVM_E_DST_ALIGNMENT) +– operation failed (NVM_E_NVM_FAIL, NVM_E_VERIFY) + +Prototype: + int32_t XMC1000_NvmProgVerifyBlock(const uint32_t *srcAddr, uint32_t *dstAddr) +*****************************************************************************/ +#define XMC1000_NvmProgVerifyBlock (*((int32_t (**) (const uint32_t * , uint32_t * )) _NvmProgVerifyBlock)) + +/**************************************************************************** +Description: This procedure, a kind of reverse of Calculate chip temperature, +calculates the value which must be installed in SCU_ANALOG->ANATSEIH.TSE_IH or +SCU_ANALOG->ANATSEIL.TSE_IL register to get indication in +SCU_INTERRUPT->SRRAW.TSE_LOW or SCU_INTERRUPT->SRRAW.TSE_HIGH +when the chip temperature is above/below some target/threshold. + +Input parameter: +– temperature: threshold temperature in degree Kelvin - allowed range 223...423 + +Return status: +– equivalent sensor threshold value for the temperature provided as input parameter + +Prototype: + uint32_t XMC1000_CalcTSEVAR(uint32_t temperature) +*****************************************************************************/ +#define XMC1000_CalcTSEVAR (*((uint32_t (**) (uint32_t * )) _CalcTSEVAR)) #ifdef __cplusplus } diff --git a/variants/XMC1400/XMC1400.h b/variants/XMC1400/XMC1400.h index 3d4439b7..dd40ad38 100644 --- a/variants/XMC1400/XMC1400.h +++ b/variants/XMC1400/XMC1400.h @@ -1,39 +1,41 @@ /********************************************************************************************************************* - * Copyright (c) 2015-2017, Infineon Technologies AG + * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. *********************************************************************************************************************/ /****************************************************************************************************//** - * @file XMC1400.h + * @file XMC1404.h * * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for - * XMC1400 from Infineon. - * - * @version V1.1.1 (Reference Manual v1.1) - * @date 19. June 2017 + * XMC1404 from Infineon. * * @note Generated with SVDConv V2.87l * from CMSIS SVD File 'XMC1400_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1), @@ -46,7 +48,7 @@ * @{ */ -/** @addtogroup XMC1400 +/** @addtogroup XMC1404 * @{ */ @@ -68,7 +70,7 @@ typedef enum { SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* --------------------- XMC1400 Specific Interrupt Numbers --------------------- */ +/* --------------------- XMC1404 Specific Interrupt Numbers --------------------- */ IRQ0_IRQn = 0, IRQ1_IRQn = 1, IRQ2_IRQn = 2, @@ -8809,7 +8811,7 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #define PPB ((PPB_Type *) PPB_BASE) #define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE) #define ERU1 ((ERU_GLOBAL_TypeDef *) ERU1_BASE) -#if (UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404) +#if defined(UC_DEVICE) && ((UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404)) #define MATH ((MATH_Type *) MATH_BASE) #endif #define PAU ((PAU_Type *) PAU_BASE) @@ -8817,7 +8819,7 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE) #define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE) #define PRNG ((PRNG_Type *) PRNG_BASE) -#if UC_DEVICE == XMC1404 +#if defined(UC_DEVICE) && (UC_DEVICE == XMC1404) #define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE) #define LEDTS1 ((LEDTS0_GLOBAL_TypeDef *) LEDTS1_BASE) #define LEDTS2 ((LEDTS0_GLOBAL_TypeDef *) LEDTS2_BASE) @@ -8828,8 +8830,8 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE) #define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE) #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) -#if (UC_DEVICE == XMC1403) || (UC_DEVICE == XMC1404) -#define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) +#if defined(UC_DEVICE) && ((UC_DEVICE == XMC1403) || (UC_DEVICE == XMC1404)) +#define CAN_xmc ((CAN_GLOBAL_TypeDef *) CAN_BASE) #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) #define CAN_MO ((CAN_MO_CLUSTER_Type *) CAN_MO_BASE) @@ -8839,7 +8841,7 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #define SCU_POWER ((SCU_POWER_Type *) SCU_POWER_BASE) #define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE) #define SCU_RESET ((SCU_RESET_Type *) SCU_RESET_BASE) -#if (UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404) +#if defined(UC_DEVICE) && ((UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404)) #define COMPARATOR ((COMPARATOR_Type *) COMPARATOR_BASE) #endif #define SCU_ANALOG ((SCU_ANALOG_Type *) SCU_ANALOG_BASE) @@ -8853,7 +8855,7 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #define CCU41_CC41 ((CCU4_CC4_TypeDef *) CCU41_CC41_BASE) #define CCU41_CC42 ((CCU4_CC4_TypeDef *) CCU41_CC42_BASE) #define CCU41_CC43 ((CCU4_CC4_TypeDef *) CCU41_CC43_BASE) -#if (UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404) +#if defined(UC_DEVICE) && ((UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404)) #define CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE) #define CCU81 ((CCU8_GLOBAL_TypeDef *) CCU81_BASE) #define CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE) @@ -8871,7 +8873,7 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE) #define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE) #define SHS0 ((SHS_Type *) SHS0_BASE) -#if (UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404) +#if defined(UC_DEVICE) && ((UC_DEVICE == XMC1402) || (UC_DEVICE == XMC1404)) #define BCCU0 ((BCCU_Type *) BCCU0_BASE) #define BCCU0_CH0 ((BCCU_CH_Type *) BCCU0_CH0_BASE) #define BCCU0_CH1 ((BCCU_CH_Type *) BCCU0_CH1_BASE) @@ -8894,7 +8896,7 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St /** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group XMC1400 */ +/** @} */ /* End of group XMC1404 */ /** @} */ /* End of group Infineon */ #ifdef __cplusplus @@ -8902,5 +8904,5 @@ typedef struct { /*!< (@ 0x40040400) PORT4 St #endif -#endif /* XMC1400_H */ +#endif /* XMC1404_H */ diff --git a/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h b/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h index 77b110c4..014c921b 100644 --- a/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h +++ b/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h @@ -244,8 +244,8 @@ XMC_UART_t XMC_UART_0 = #endif }, .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH }, .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, #ifdef SERIAL_DEBUG @@ -255,8 +255,8 @@ XMC_UART_t XMC_UART_0 = #endif }, .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH }, #ifdef SERIAL_DEBUG .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C1_DX0_P1_3, @@ -288,8 +288,9 @@ XMC_SPI_t XMC_SPI_0 = }, .mosi_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .miso = { .port = (XMC_GPIO_PORT_t*)PORT0_BASE, @@ -306,8 +307,9 @@ XMC_SPI_t XMC_SPI_0 = }, .sclkout_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + } }; @@ -325,8 +327,9 @@ XMC_I2C_t XMC_I2C_0 = }, .sda_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .scl = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, @@ -334,8 +337,9 @@ XMC_I2C_t XMC_I2C_0 = }, .scl_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = XMC_INPUT_F, .input_source_dx1 = XMC_INPUT_E, diff --git a/variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h b/variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h index cf343003..b0c8b7f6 100644 --- a/variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h +++ b/variants/XMC1400/config/XMC1400_XMC2GO/pins_arduino.h @@ -127,6 +127,7 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define USIC0_5_IRQHandler IRQ14_Handler // I2C #define USIC0_5_IRQn IRQ14_IRQn +/* I2S interrupt source B */ #define USIC1_2_IRQHandler IRQ11_Handler // I2S #define USIC1_2_IRQn IRQ11_IRQn @@ -136,6 +137,11 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define ERU0_0_IRQHandler IRQ3_Handler // RESET #define ERU0_0_IRQn IRQ3_IRQn +/* CAN interrupt source B */ +#define CAN0_3_IRQHandler IRQ7_Handler // CAN +#define CAN0_3_IRQn IRQ7_IRQn + + #define digitalPinToInterrupt(p) (((p) == 9) ? 0 : NOT_AN_INTERRUPT) #ifdef ARDUINO_MAIN @@ -159,7 +165,10 @@ const XMC_PORT_PIN_t mapping_port_pin[] = /* 14 */ {XMC_GPIO_PORT0, 7}, // LED 1 output P0.7 /* 15 */ {XMC_GPIO_PORT0, 6}, // LED 2 output P0.6 /* 16 */ {XMC_GPIO_PORT2, 1}, // DEBUG_TX P2.1 - /* 17 */ {XMC_GPIO_PORT2, 2} // DEBUG_RX P2.2 (INPUT ONLY) + /* 17 */ {XMC_GPIO_PORT2, 2}, // DEBUG_RX P2.2 (INPUT ONLY) + + /* 18 */ {XMC_GPIO_PORT1, 0}, // CAN_TX P1.0 (connected with CAN Transceiver) + /* 19 */ {XMC_GPIO_PORT1, 1} // CAN_RX P1.1 (connected with CAN Transceiver) }; const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); @@ -191,7 +200,7 @@ XMC_PWM4_t mapping_pwm4[] = {CCU40, CCU40_CC43, 3, mapping_port_pin[2], P0_3_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 2 P0.3 {CCU40, CCU40_CC41, 1, mapping_port_pin[3], P0_4_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P0.4 {CCU40, CCU40_CC40, 0, mapping_port_pin[8], P0_5_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 8 P0.5 - {CCU41, CCU41_CC40, 3, mapping_port_pin[9], P1_4_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 9 P1.4 + {CCU41, CCU41_CC40, 0, mapping_port_pin[9], P1_4_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 9 P1.4 }; const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); const uint8_t NUM_PWM4 = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); @@ -233,8 +242,9 @@ XMC_UART_t XMC_UART_0 = #endif }, .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .tx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, // TX P2.0 #ifdef SERIAL_DEBUG @@ -244,8 +254,9 @@ XMC_UART_t XMC_UART_0 = #endif }, .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C0_DX0_DX3INS, .input_source_dx1 = XMC_INPUT_INVALID, @@ -277,8 +288,9 @@ XMC_SPI_t XMC_SPI_0 = }, .mosi_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .miso = { .port = (XMC_GPIO_PORT_t*)PORT0_BASE, @@ -295,8 +307,9 @@ XMC_SPI_t XMC_SPI_0 = }, .sclkout_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + } }; @@ -313,8 +326,9 @@ XMC_I2C_t XMC_I2C_0 = }, .sda_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .scl = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, @@ -322,8 +336,9 @@ XMC_I2C_t XMC_I2C_0 = }, .scl_config = { .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .input_source_dx0 = XMC_INPUT_F, .input_source_dx1 = XMC_INPUT_E, @@ -337,24 +352,50 @@ XMC_I2S_t i2s_config = { .input_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .sclk_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .wa_config = { .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, .protocol_irq_num = (IRQn_Type) USIC1_2_IRQn, .protocol_irq_service_request = 2, .protocol_irq_source = XMC_SCU_IRQCTRL_USIC1_SR2_IRQ11 }; +// XMC CAN instance +#ifdef CAN_xmc +XMC_ARD_CAN_t XMC_CAN_0 = { + .can_node = CAN_NODE0, + .can_node_num = XMC_NODE_NUM_0, + .can_clock = XMC_CAN_CANCLKSRC_MCLK, + .can_frequency = (uint32_t)48000000, + .rx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)1}, + .rx_config = + { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + }, + .tx = {.port = (XMC_GPIO_PORT_t *)PORT1_BASE, .pin = (uint8_t)0}, + .tx_config = + { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9, + }, + .node_input = CAN_NODE0_RXD_P1_1, + .irq_num = CAN0_3_IRQn, + .irq_service_request = 3, + .irq_source = XMC_SCU_IRQCTRL_CAN0_SR3_IRQ7}; +#endif + // Serial Interrupt and event handling #ifdef __cplusplus extern "C" { diff --git a/variants/XMC1400/linker_script_200k.ld b/variants/XMC1400/linker_script_200k.ld index 29fdf06d..f1018ded 100644 --- a/variants/XMC1400/linker_script_200k.ld +++ b/variants/XMC1400/linker_script_200k.ld @@ -1,74 +1,59 @@ /** * @file XMC1400x0200.ld - * @date 2017-04-20 * * @cond ********************************************************************************************************************* * Linker file for the GNU C Compiler v1.6 - * Supported devices: XMC1402- ANY Package 200kB Flash 16kB RAM + * Supported devices: XMC1402-Q064X0200 + * XMC1402-T038X0200 + * XMC1402-Q040X0200 + * XMC1402-Q048X0200 + * XMC1403-Q040X0200 + * XMC1403-Q048X0200 + * XMC1403-Q064X0200 + * XMC1404-Q048X0200 + * XMC1404-Q064X0200 + * XMC1404-F064X0200 * - * - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * Copyright (c) 2015-2021, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. ********************************************************************************************************************* * - * Change History - * -------------- - * - * 2015-07-07: - * - Product splitting - * - Copyright notice update - * - * 2015-11-24: - * - Compatibility with GCC 4.9 2015q2 - * - * 2016-03-15: - * - Add assertion to check that region SRAM_combined does not overflowed no_init section - * - * 2016-06-07: - * - Add XMC1403-Q040X0200 - * - * 2016-07-20: - * - Add XMC1402-T038X0200, XMC1402-Q040X0200, XMC1402-Q048X0200 - * - * 2016-10-28: - * - Fix linker not complaining if sum of data + text sections is bigger that physical FLASH size - * - * 2017-04-07: - * - Added new symbols __text_size and eText - * - * 2017-04-20: - * - Change vtable location to flash area to save ram - * - * @endcond + * @endcond * */ OUTPUT_FORMAT("elf32-littlearm") OUTPUT_ARCH(arm) +GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) MEMORY @@ -84,7 +69,7 @@ SECTIONS { /* TEXT section */ - .text : + .text : { sText = .; KEEP(*(.reset)); @@ -111,7 +96,7 @@ SECTIONS *(.rodata .rodata.*) *(.gnu.linkonce.r*) - *(vtable) + *(vtable) . = ALIGN(4); } > FLASH @@ -172,7 +157,7 @@ SECTIONS * (.data*); *(*.data); *(.gnu.linkonce.d*) - + . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); @@ -205,13 +190,13 @@ SECTIONS . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ __ram_code_start = .; /* functions with __attribute__ ((section (".ram_code")))*/ - *(.ram_code) + *(.ram_code) . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ __ram_code_end = .; } > SRAM AT > FLASH __ram_code_load = LOADADDR (.ram_code); __ram_code_size = __ram_code_end - __ram_code_start; - + __text_size = (__exidx_end - sText) + VeneerSize + __data_size + __ram_code_size; eText = sText + __text_size; @@ -230,14 +215,14 @@ SECTIONS Heap_Bank1_Start = .; } > SRAM __bss_size = __bss_end - __bss_start; - + /* .no_init section contains SystemCoreClock. See system.c file */ - .no_init ORIGIN(SRAM) + LENGTH(SRAM) - no_init_size (NOLOAD) : + .no_init ORIGIN(SRAM) + LENGTH(SRAM) - no_init_size (NOLOAD) : { Heap_Bank1_End = .; * (.no_init); } > SRAM - + /* Heap - Bank1*/ Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start; diff --git a/variants/XMC1400/startup_XMC1400.S b/variants/XMC1400/startup_XMC1400.S index 0e689990..c99e42c8 100644 --- a/variants/XMC1400/startup_XMC1400.S +++ b/variants/XMC1400/startup_XMC1400.S @@ -1,43 +1,41 @@ /********************************************************************************************************************* * @file startup_XMC1400.S * @brief CMSIS Core Device Startup File for Infineon XMC1400 Device Series - * @version V1.1 - * @date 05 Jan 2016 * * @cond ********************************************************************************************************************* - * Copyright (c) 2015-2016, Infineon Technologies AG + * Copyright (c) 2015-2021, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. ********************************************************************************************************************* * - **************************** Change history ******************************** - * V1.0, Sep, 03, 2015 JFT:Initial version - * MCLK=8MHz, PCLK=16MHz - * V1.1, Jan, 05, 2016 JFT:Fix .reset section attributes - * * @endcond */ @@ -91,10 +89,26 @@ *****************************************************************************/ #define CLKVAL2_SSW 0x00000100 +/***************************************************************************** + * WAIT_ASCBSL_ENTRY Configuration + * Wait time before ASC BSL channel selection (number of MCLK clock cycles) + * Disable wait time before ASC BSL channel selection + * + *****************************************************************************/ +#define WAIT_ASCBSL_ENTRY_SSW 0x80000000 + /* A couple of macros to ease definition of the various handlers */ .macro Insert_InterruptHandler Interrupt .weak \Interrupt\()_Handler +#if defined(ENABLE_OWN_HANDLER) + .thumb_func + .type \Interrupt\()_Handler, %function +\Interrupt\()_Handler: + b . + .size \Interrupt\()_Handler, . - \Interrupt\()_Handler +#else .thumb_set \Interrupt\()_Handler, Default_Handler +#endif .endm .macro Insert_InterruptVeener Interrupt @@ -126,12 +140,12 @@ __Vectors: .long HardFault_Handler /* Hard Fault Handler */ .long CLKVAL1_SSW /* Reserved */ .long CLKVAL2_SSW /* Reserved */ + .long WAIT_ASCBSL_ENTRY_SSW /* Reserved */ #ifdef RETAIN_VECTOR_TABLE .long 0 /* Reserved */ .long 0 /* Reserved */ .long 0 /* Reserved */ .long 0 /* Reserved */ - .long 0 /* Reserved */ .long SVC_Handler /* SVCall Handler */ .long 0 /* Reserved */ .long 0 /* Reserved */ @@ -230,6 +244,10 @@ Reset_Handler: .L_loop3_done: #endif /* __SKIP_BSS_CLEAR */ + /* OS-specific low-level initialization */ + ldr r0, =cy_toolchain_init + blx r0 + #ifndef __SKIP_LIBC_INIT_ARRAY ldr r0, =__libc_init_array blx r0 @@ -263,6 +281,17 @@ __copy_data: .pool .size Reset_Handler,.-Reset_Handler + +/* OS-specific low-level initialization */ + .thumb_func + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + /* ======================================================================== */ /* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ diff --git a/variants/XMC1400/system_XMC1400.c b/variants/XMC1400/system_XMC1400.c index 5bf9f60e..dce9d13d 100644 --- a/variants/XMC1400/system_XMC1400.c +++ b/variants/XMC1400/system_XMC1400.c @@ -1,45 +1,41 @@ /********************************************************************************************************************* * @file system_XMC1400.c * @brief Device specific initialization for the XMC1400-Series according to CMSIS - * @version V1.2 - * @date 19 Jun 2017 * * @cond ********************************************************************************************************************* - * Copyright (c) 2015-2017, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. ********************************************************************************************************************* * - * *************************** Change history ******************************** - * V1.0, 03 Sep 2015, JFT : Initial version - * MCLK = 48MHz, PCLK = 96MHz - * V1.1, 09 Dec 2015, JFT : Enable prefetch unit - * V1.2, 19 Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK - * Added support for ARM Compiler 6 (armclang) - * * @endcond */ @@ -47,7 +43,7 @@ * HEADER FILES *******************************************************************************/ -#include +#include "XMC1400.h" #include "system_XMC1400.h" /******************************************************************************* @@ -88,11 +84,23 @@ // OSCHP external oscillator mode // <0=> Crystal mode // <1=> External clock direct input mode -// Default: Crystal mode +// <2=> Power down +// Default: Power down */ -#define OSCHP_MODE 0 +#define OSCHP_MODE 2 #define OSCHP_MODE_XTAL 0 #define OSCHP_MODE_DIRECT 1 +#define OSCHP_MODE_POWER_DOWN 2 + +/* +// OSCLP external oscillator mode +// <0=> Oscillator mode +// <2=> Power down +// Default: Power down +*/ +#define OSCLP_MODE 2 +#define OSCLP_MODE_XTAL 0 +#define OSCLP_MODE_POWER_DOWN 2 /* // RTC clock source selection @@ -113,6 +121,15 @@ #define PCLK_CLOCK_SRC_MCLK 0 #define PCLK_CLOCK_SRC_2XMCLK 1 + +#if (DCLK_CLOCK_SRC == DCLK_CLOCK_SRC_EXT_XTAL) && (OSCHP_MODE == OSCHP_MODE_POWER_DOWN) +#error Selected OSC_HP as DCLK clock source but OSC_HP is disabled +#endif + +#if (RTC_CLOCK_SRC == RTC_CLOCK_SRC_EXT_XTAL) && (OSCLP_MODE == OSCLP_MODE_POWER_DOWN) +#error Selected OSC_LP as RTC clock source but OSC_LP is disabled +#endif + /* //-------- <<< end of configuration section >>> ------------------ */ @@ -124,7 +141,7 @@ #if defined ( __CC_ARM ) uint32_t SystemCoreClock __attribute__((at(0x20003FFC))); #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -uint32_t SystemCoreClock __attribute__((section(".ARM.__at_0x20003FFC"))); +uint32_t SystemCoreClock __attribute__((section(".bss.ARM.__at_0x20003FFC"))); #elif defined ( __ICCARM__ ) __no_init uint32_t SystemCoreClock; #elif defined ( __GNUC__ ) @@ -136,13 +153,12 @@ uint32_t SystemCoreClock __at( 0x20003FFC ); /******************************************************************************* * LOCAL FUNCTIONS *******************************************************************************/ -#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1 -static inline void delay(uint32_t cycles) +#if (OSCHP_MODE != OSCHP_MODE_POWER_DOWN) || ((OSCLP_MODE != OSCLP_MODE_POWER_DOWN) && (!defined(DISABLE_WAIT_RTC_XTAL_OSC_STARTUP))) +__STATIC_FORCEINLINE void delay(uint32_t cycles) { - while(cycles > 0) + while(--cycles > 0) { __NOP(); - cycles--; } } #endif @@ -170,9 +186,10 @@ __WEAK void SystemCoreClockSetup(void) /* disable bit protection */ SCU_GENERAL->PASSWD = 0x000000C0UL; -#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1 +#if OSCHP_MODE != OSCHP_MODE_POWER_DOWN - if (OSCHP_GetFrequency() > 20000000U) + /* OSC_CM.D001 Additions and corrections related to ANAOSCHPCTRL register */ + if (OSCHP_GetFrequency() <= 20000000U) { SCU_ANALOG->ANAOSCHPCTRL |= SCU_ANALOG_ANAOSCHPCTRL_HYSCTRL_Msk; } @@ -181,35 +198,56 @@ __WEAK void SystemCoreClockSetup(void) SCU_ANALOG->ANAOSCHPCTRL = (SCU_ANALOG->ANAOSCHPCTRL & ~SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk) | (OSCHP_MODE << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos); - /* Enable OSC_HP oscillator watchdog*/ - SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk; - - do + do { - /* Restart OSC_HP oscillator watchdog */ + /* clear the status bit before restarting the detection. */ SCU_INTERRUPT->SRCLR1 = SCU_INTERRUPT_SRCLR1_LOECI_Msk; - SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDRES_Msk; - /* Wait a few DCO2 cycles for the update of the clock detection result */ - delay(2500); + /* According to errata SCU_CM.023, to reset the XOWD it is needed to disable/enable the watchdog, + keeping in between at least one DCO2 cycle */ + + /* Disable XOWD */ + SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_XOWDEN_Msk; + + /* Clock domains synchronization, at least 1 DCO2 cycle */ + /* delay value calculation assuming worst case DCO1=48Mhz and 3cycles per delay iteration */ + delay(538); + + /* Enable XOWD */ + SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_XOWDEN_Msk | SCU_CLK_OSCCSR_XOWDRES_Msk; - /* check clock is ok */ - } - while(SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk); + /* OSCCSR.XOWDRES bit will be automatically reset to 0 after XOWD is reset */ + while (SCU_CLK->OSCCSR & SCU_CLK_OSCCSR_XOWDRES_Msk); + + /* Wait a at least 5 DCO2 cycles for the update of the XTAL OWD result */ + /* delay value calculation assuming worst case DCO1=48Mhz and 3cycles per delay iteration */ + delay(2685); + + } while (SCU_INTERRUPT->SRRAW1 & SCU_INTERRUPT_SRRAW1_LOECI_Msk); - /* DCLK source using OSC_HP */ - SCU_CLK->CLKCR1 |= SCU_CLK_CLKCR1_DCLKSEL_Msk; - #else - + /* Disable OSC_HP */ + SCU_ANALOG->ANAOSCHPCTRL |= SCU_ANALOG_ANAOSCHPCTRL_MODE_Msk; +#endif + +#if DCLK_CLOCK_SRC != DCLK_CLOCK_SRC_DCO1 + /* DCLK source using OSC_HP */ + SCU_CLK->CLKCR1 |= SCU_CLK_CLKCR1_DCLKSEL_Msk; +#else /* DCLK source using DCO1 */ SCU_CLK->CLKCR1 &= ~SCU_CLK_CLKCR1_DCLKSEL_Msk; - -#endif +#endif -#if RTC_CLOCK_SRC == RTC_CLOCK_SRC_EXT_XTAL +#if OSCLP_MODE == OSCLP_MODE_XTAL /* Enable OSC_LP */ SCU_ANALOG->ANAOSCLPCTRL &= ~SCU_ANALOG_ANAOSCLPCTRL_MODE_Msk; +#ifndef DISABLE_WAIT_RTC_XTAL_OSC_STARTUP + /* Wait oscillator startup time ~5s */ + delay(6500000); +#endif +#else + /* Disable OSC_LP */ + SCU_ANALOG->ANAOSCLPCTRL |= SCU_ANALOG_ANAOSCLPCTRL_MODE_Msk; #endif /* Update PCLK selection mux. */ diff --git a/variants/XMC1400/system_XMC1400.h b/variants/XMC1400/system_XMC1400.h index 44371213..7326fb9a 100644 --- a/variants/XMC1400/system_XMC1400.h +++ b/variants/XMC1400/system_XMC1400.h @@ -1,41 +1,41 @@ /********************************************************************************************************************* * @file system_XMC1400.h * @brief Device specific initialization for the XMC1400-Series according to CMSIS - * @version V1.0 - * @date 03 Sep 2015 * * @cond ********************************************************************************************************************* - * Copyright (c) 2015-2016, Infineon Technologies AG + * Copyright (c) 2015-2020, Infineon Technologies AG * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. + * Boost Software License - Version 1.0 - August 17th, 2003 * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided with the distribution. + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * - * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with - * Infineon Technologies AG dave@infineon.com). + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. ********************************************************************************************************************* * - **************************** Change history ********************************* - * V1.0, 03 Sep 2015, JFT : Initial version - ***************************************************************************** * @endcond */ diff --git a/variants/XMC4200/XMC4200.h b/variants/XMC4200/XMC4200.h index 427a7ce7..8dbcc54c 100644 --- a/variants/XMC4200/XMC4200.h +++ b/variants/XMC4200/XMC4200.h @@ -13123,7 +13123,7 @@ typedef struct { /*!< (@ 0x48028E00) PORT14 S #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE) #define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE) #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) -#define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) +#define CAN_xmc ((CAN_GLOBAL_TypeDef *) CAN_BASE) #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) #define CAN_MO0 ((CAN_MO_TypeDef *) CAN_MO0_BASE) diff --git a/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h b/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h index 074bb9aa..768a276f 100644 --- a/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h +++ b/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h @@ -375,6 +375,32 @@ XMC_I2C_t XMC_I2C_0 = .protocol_irq_service_request = 2 }; +// XMC CAN instance +#ifdef CAN_xmc +XMC_ARD_CAN_t XMC_CAN_0 = +{ + .can_node = CAN_NODE0, + .can_node_num = XMC_NODE_NUM_0, + .can_clock = XMC_CAN_CANCLKSRC_FPERI, + .can_frequency = (uint32_t)144000000, + .rx = { .port = (XMC_GPIO_PORT_t*)PORT14_BASE, + .pin = (uint8_t)3 + }, + .rx_config = { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE + }, + .tx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)0 + }, + .tx_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 + }, + .node_input = CAN_NODE0_RXD_P14_3, + .irq_num = CAN0_7_IRQn, + .irq_service_request = 7u +}; +#endif + // Serial Interrupt and event handling #ifdef __cplusplus extern "C" { diff --git a/variants/XMC4400/XMC4400.h b/variants/XMC4400/XMC4400.h index 60e427e3..8e37ef56 100644 --- a/variants/XMC4400/XMC4400.h +++ b/variants/XMC4400/XMC4400.h @@ -16559,7 +16559,7 @@ typedef struct { /*!< (@ 0x48028F00) PORT15 S #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE) #define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE) #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) -#define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) +#define CAN_xmc ((CAN_GLOBAL_TypeDef *) CAN_BASE) #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) #define CAN_MO0 ((CAN_MO_TypeDef *) CAN_MO0_BASE) diff --git a/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h b/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h index f75c2c95..734ca39c 100644 --- a/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h +++ b/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h @@ -427,6 +427,31 @@ XMC_I2C_t XMC_I2C_0 = .protocol_irq_service_request = 2 }; +// XMC CAN instance +#ifdef CAN_xmc +XMC_ARD_CAN_t XMC_CAN_0 = +{ + .can_node = CAN_NODE1, + .can_node_num = XMC_NODE_NUM_1, + .can_clock = XMC_CAN_CANCLKSRC_FPERI, + .can_frequency = (uint32_t)144000000, + .rx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)13 + }, + .rx_config = { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE + }, + .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)12 + }, + .tx_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 + }, + .node_input = CAN_NODE1_RXD_P1_13, + .irq_num = CAN0_7_IRQn, + .irq_service_request = 7u +}; +#endif // Serial Interrupt and event handling #ifdef __cplusplus diff --git a/variants/XMC4700/XMC4700.h b/variants/XMC4700/XMC4700.h index c833ca04..92431beb 100644 --- a/variants/XMC4700/XMC4700.h +++ b/variants/XMC4700/XMC4700.h @@ -17617,7 +17617,7 @@ typedef struct { /*!< (@ 0x48028F00) PORT15 S #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) #define USIC2_CH0 ((USIC_CH_TypeDef *) USIC2_CH0_BASE) #define USIC2_CH1 ((USIC_CH_TypeDef *) USIC2_CH1_BASE) -#define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) +#define CAN_xmc ((CAN_GLOBAL_TypeDef *) CAN_BASE) #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) #define CAN_NODE2 ((CAN_NODE_TypeDef *) CAN_NODE2_BASE) diff --git a/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h b/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h index f35cac49..9105d732 100644 --- a/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h +++ b/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h @@ -251,7 +251,10 @@ const XMC_PORT_PIN_t mapping_port_pin[] = /* 92 */ {XMC_GPIO_PORT3, 3}, // P3.3 X2-8 /* 93 */ {XMC_GPIO_PORT0, 15}, // PWM40-0 / PWM20 P0.15 X2-6 /* 94 */ {XMC_GPIO_PORT0, 12}, // PWM40-3 / PWM22 P0.12 X2-4 - /* 95 */ {XMC_GPIO_PORT3, 12} // ECAT0.P1_LINK_ACT P3.12 X2-2 + /* 95 */ {XMC_GPIO_PORT3, 12}, // ECAT0.P1_LINK_ACT P3.12 X2-2 + + /* 96 */ {XMC_GPIO_PORT1, 12}, // CAN_TX + /* 97 */ {XMC_GPIO_PORT1, 13} // CAN_RX }; const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) );; @@ -704,6 +707,33 @@ XMC_I2S_t i2s_config = .protocol_irq_service_request = 2 }; + +// XMC CAN instance +#ifdef CAN_xmc +XMC_ARD_CAN_t XMC_CAN_0 = +{ + .can_node = CAN_NODE1, + .can_node_num = XMC_NODE_NUM_1, + .can_clock = XMC_CAN_CANCLKSRC_FPERI, + .can_frequency = (uint32_t)144000000, + .rx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)13 + }, + .rx_config = { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE + }, + .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)12 + }, + .tx_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 + }, + .node_input = CAN_NODE1_RXD_P1_13, + .irq_num = CAN0_7_IRQn, + .irq_service_request = 7u +}; +#endif + // Serial Interrupt and event handling #ifdef __cplusplus extern "C" {