From 6a4f9fd98b557f07d3a9bcce93b98c8fc76d5fd4 Mon Sep 17 00:00:00 2001 From: gitlab-runner Date: Tue, 23 Feb 2021 10:36:45 -0600 Subject: [PATCH] Upload mtb-example-psoc6-smartio-ramping-led 2.2.0.108 --- .../cyreservedresources.list | 71 +++ .../TARGET_CYSBSYSKIT-01/design.cyqspi | 63 +++ .../TARGET_CYSBSYSKIT-01/design.modus | 432 +++++++++++++++ .../cyreservedresources.list | 20 + .../TARGET_CYSBSYSKIT-DEV-01/design.cyqspi | 63 +++ .../TARGET_CYSBSYSKIT-DEV-01/design.modus | 503 ++++++++++++++++++ LICENSE | 2 +- README.md | 33 +- 8 files changed, 1174 insertions(+), 13 deletions(-) create mode 100644 COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/cyreservedresources.list create mode 100644 COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.cyqspi create mode 100644 COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.modus create mode 100644 COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/cyreservedresources.list create mode 100644 COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.cyqspi create mode 100644 COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.modus diff --git a/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/cyreservedresources.list b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/cyreservedresources.list new file mode 100644 index 0000000..96ca199 --- /dev/null +++ b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/cyreservedresources.list @@ -0,0 +1,71 @@ +[Device=CY8C624AFNI-S2D43] + +[Blocks] +# WIFI +# CYBSP_WIFI_SDIO +sdhc[0] +# CYBSP_WIFI_SDIO_D0 +ioss[0].port[2].pin[0] +# CYBSP_WIFI_SDIO_D1 +ioss[0].port[2].pin[1] +# CYBSP_WIFI_SDIO_D2 +ioss[0].port[2].pin[2] +# CYBSP_WIFI_SDIO_D3 +ioss[0].port[2].pin[3] +# CYBSP_WIFI_SDIO_CMD +ioss[0].port[2].pin[4] +# CYBSP_WIFI_SDIO_CLK +ioss[0].port[2].pin[5] +# CYBSP_WIFI_WL_REG_ON +ioss[0].port[2].pin[6] +# CYBSP_WIFI_DEVICE_WAKE +ioss[0].port[2].pin[7] +# CYBSP_WIFI_HOST_WAKE +ioss[0].port[1].pin[4] + +# BT UART +# CYBSP_BT_UART +scb[12] +# CYBSP_BT_POWER +ioss[0].port[12].pin[0] +# CYBSP_BT_DEVICE_WAKE +ioss[0].port[12].pin[2] +# CYBSP_BT_HOST_WAKE +ioss[0].port[12].pin[3] +# CYBSP_BT_UART_RX +ioss[0].port[13].pin[4] +# CYBSP_BT_UART_TX +ioss[0].port[13].pin[5] +# CYBSP_BT_UART_RTS +ioss[0].port[13].pin[6] +# CYBSP_BT_UART_CTS +ioss[0].port[13].pin[7] +# CYBSP_BT_UART_CLK_DIV +peri[0].div_16[1] + +# UART +# CYBSP_DEBUG_UART +scb[10] +# CYBSP_DEBUG_UART_RX +ioss[0].port[5].pin[4] +# CYBSP_DEBUG_UART_TX +ioss[0].port[5].pin[5] +# CYBSP_DEBUG_UART_RTS +ioss[0].port[5].pin[6] +# CYBSP_DEBUG_UART_CTS +ioss[0].port[5].pin[7] + +# CYBSP_DEBUG_UART_CLK_DIV +peri[0].div_16[0] + +# POWER +srss[0].power[0] + +# RTC +srss[0].rtc[0] + +# CM0(NP) I2C +# CYBSP_I2C_SCL +ioss[0].port[8].pin[0] +# CYBSP_I2C_SDA +ioss[0].port[8].pin[1] diff --git a/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.cyqspi b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.cyqspi new file mode 100644 index 0000000..f0610e1 --- /dev/null +++ b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S + false + None + 0x18000000 + 0x10000 + 0x1800FFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.modus b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.modus new file mode 100644 index 0000000..1d33554 --- /dev/null +++ b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-01/design.modus @@ -0,0 +1,432 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/cyreservedresources.list b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/cyreservedresources.list new file mode 100644 index 0000000..28833f5 --- /dev/null +++ b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/cyreservedresources.list @@ -0,0 +1,20 @@ +[Device=CY8C624AFNI-S2D43] + +[Blocks] +# WIFI +# CYBSP_WIFI_SDIO +sdhc[0] +# CYBSP_WIFI_SDIO_D0 +ioss[0].port[2].pin[0] +# CYBSP_WIFI_SDIO_D1 +ioss[0].port[2].pin[1] +# CYBSP_WIFI_SDIO_D2 +ioss[0].port[2].pin[2] +# CYBSP_WIFI_SDIO_D3 +ioss[0].port[2].pin[3] +# CYBSP_WIFI_SDIO_CMD +ioss[0].port[2].pin[4] +# CYBSP_WIFI_SDIO_CLK +ioss[0].port[2].pin[5] +# CYBSP_WIFI_WL_REG_ON +ioss[0].port[2].pin[6] diff --git a/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.cyqspi b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.cyqspi new file mode 100644 index 0000000..13ee5dc --- /dev/null +++ b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S (4-byte Addressing Mode) + true + None + 0x18000000 + 0x4000000 + 0x1BFFFFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S (4-byte Addressing Mode) + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.modus b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.modus new file mode 100644 index 0000000..90b7709 --- /dev/null +++ b/COMPONENT_CUSTOM_DESIGN_MODUS/TARGET_CYSBSYSKIT-DEV-01/design.modus @@ -0,0 +1,503 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LICENSE b/LICENSE index 91c81ad..f7eec35 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -CYPRESS END USER LICENSE AGREEMENT +CYPRESS (AN INFINEON COMPANY) END USER LICENSE AGREEMENT PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING diff --git a/README.md b/README.md index 5d472ab..8d4dc92 100644 --- a/README.md +++ b/README.md @@ -2,6 +2,8 @@ This example uses a PWM resource and Smart I/O™ in PSoC 6 MCU to implement a ramping LED, where an LED gradually cycles through increasing and decreasing brightness levels. There is no CPU usage except for the initialization of PWM and Smart I/O. +[Provide feedback on this Code Example.](https://cypress.co1.qualtrics.com/jfe/form/SV_1NTns53sK2yiljn?Q_EED=eyJVbmlxdWUgRG9jIElkIjoiQ0UyMTk0OTAiLCJTcGVjIE51bWJlciI6IjAwMi0xOTQ5MCIsIkRvYyBUaXRsZSI6IlBTb0MgNiBNQ1U6IFJhbXBpbmcgTEVEIFVzaW5nIFNtYXJ0IEkvTyIsInJpZCI6InZrdmsiLCJEb2MgdmVyc2lvbiI6IjIuMi4wIiwiRG9jIExhbmd1YWdlIjoiRW5nbGlzaCIsIkRvYyBEaXZpc2lvbiI6Ik1DRCIsIkRvYyBCVSI6IklDVyIsIkRvYyBGYW1pbHkiOiJQU09DIn0=) + ## Requirements - [ModusToolbox® software](https://www.cypress.com/products/modustoolbox-software-environment) v2.2 @@ -28,6 +30,8 @@ This example uses a PWM resource and Smart I/O™ in PSoC 6 MCU to implement a r - [PSoC 62S1 Wi-Fi BT Pioneer Kit](https://www.cypress.com/CYW9P62S1-43012EVB-01) (CYW9P62S1-43012EVB-01) - [PSoC 62S3 Wi-Fi BT Prototyping Kit](https://www.cypress.com/CY8CPROTO-062S3-4343W) (CY8CPROTO-062S3-4343W) - [PSoC 64 Secure Boot Wi-Fi BT Pioneer Kit](http://www.cypress.com/CY8CKIT-064B0S2-4343W) (CY8CKIT-064B0S2-4343W) +- Rapid IoT Connect Platform RP01 Feather Kit (CYSBSYSKIT-01) +- Rapid IoT Connect Developer Kit (CYSBSYSKIT-DEV-01) ## Hardware Setup @@ -123,19 +127,22 @@ If using a PSoC 64 Secure MCU kit (like CY8CKIT-064B0S2-4343W), the PSoC 64 Secu **Table 1. LED Pin Connection** - | Board | Smart I/O Output Pin | LED Pin | - | -----------------------|-------------------------|-------------| - | CY8CKIT-062-BLE | P9[1] | P13[7] | - | CY8CKIT-062-WIFI-BT | P9[1] | P13[7] | - | CY8CPROTO-062-4343W | P9[1] | P13[7] | - | CY8CPROTO-063-BLE | P9[1] | P6[3] | - | CY8CPROTO-062S3-4343W | P9[1] | P11[1] | - | CY8CKIT-062S2-43012 | A9 | LED.R | - | CYW9P62S1-43438EVB-01 | A9 | LED.R | - | CYW9P62S1-43012EVB-01 | IO11**1** | LED.R | - | CY8CKIT-064B0S2-4343W | A9 | LED.R | + | Board | Smart I/O Output Pin | LED Pin | + | -----------------------|-------------------------|------------------------------| + | CY8CKIT-062-BLE | P9[1] | P13[7] | + | CY8CKIT-062-WIFI-BT | P9[1] | P13[7] | + | CY8CPROTO-062-4343W | P9[1] | P13[7] | + | CY8CPROTO-063-BLE | P9[1] | P6[3] | + | CY8CPROTO-062S3-4343W | P9[1] | P11[1] | + | CY8CKIT-062S2-43012 | A9 | LED.R | + | CYW9P62S1-43438EVB-01 | A9 | LED.R | + | CYW9P62S1-43012EVB-01 | IO11**1** | LED.R | + | CY8CKIT-064B0S2-4343W | A9 | LED.R | + | CYSBSYSKIT-01 | P9[1] | External LED**2** | + | CYSBSYSKIT-DEV-01 | P9[1] | External LED**2** | **Note:**
**1**. By default, IO11 of the CYW9P62S1-43012EVB-01 board is not connected to the MCU. Remove **R29** and populate **R152** with a 0-ohm resistor to connect to the MCU pin. See the board schematics for more details. + **Note:**
**2**. On CYSBSYSKIT-01 & CYSBSYSKIT-DEV-01, the USER LED is not available on the feather header, so the user has to connect the Smart I/O pin to an external LED pulled-up to 1.8v similar to USER LED on CYSBSYSKIT-01 & CYSBSYSKIT-DEV-01. See the board schematics for more details. ## Debugging @@ -232,7 +239,7 @@ Figure 6 and Figure 7 show the Peripheral Clock configuration for Smart I/O and | [CY8CPROTO-063-BLE](https://www.cypress.com/CY8CPROTO-063-BLE) PSoC 6 BLE Prototyping Kit | [CY8CPROTO-062-4343W](https://www.cypress.com/CY8CPROTO-062-4343W) PSoC 6 Wi-Fi BT Prototyping Kit | | [CY8CKIT-062S2-43012](https://www.cypress.com/CY8CKIT-062S2-43012) PSoC 62S2 Wi-Fi BT Pioneer Kit | [CY8CPROTO-062S3-4343W](https://www.cypress.com/CY8CPROTO-062S3-4343W) PSoC 62S3 Wi-Fi BT Prototyping Kit | | [CYW9P62S1-43438EVB-01](https://www.cypress.com/CYW9P62S1-43438EVB-01) PSoC 62S1 Wi-Fi BT Pioneer Kit | [CYW9P62S1-43012EVB-01](https://www.cypress.com/CYW9P62S1-43012EVB-01) PSoC 62S1 Wi-Fi BT Pioneer Kit | | -|[CY8CKIT-064B0S2-4343W](http://www.cypress.com/CY8CKIT-064B0S2-4343W) PSoC 64 Secure Boot Wi-Fi BT Pioneer Kit| | | +|[CY8CKIT-064B0S2-4343W](http://www.cypress.com/CY8CKIT-064B0S2-4343W) PSoC 64 Secure Boot Wi-Fi BT Pioneer Kit| [CYSBSYSKIT-01] Rapid IoT Connect Platform RP01 Feather Kit | [CYSBSYSKIT-DEV-01] Rapid IoT Connect Developer Kit | | **Libraries** | | | PSoC 6 Peripheral Driver Library (PDL) and docs | [mtb-pdl-cat1](https://github.com/cypresssemiconductorco/mtb-pdl-cat1) on GitHub | | Cypress Hardware Abstraction Layer (HAL) Library and docs | [mtb-hal-cat1](https://github.com/cypresssemiconductorco/mtb-hal-cat1) on GitHub | @@ -260,6 +267,8 @@ Document Title: CE219490 - PSoC 6 MCU: Ramping LED using Smart I/O | 1.1.0 | Modified project folder structure | | 1.2.0 | Updated to support ModusToolbox software v2.1, Added new kits | | 2.0.0 | Major update to support ModusToolbox software v2.2, added support for new kits
This version is not backward compatible with ModusToolbox software v2.1 | +| 2.1.0 | Added CUSTOM_DESIGN_MODUS for CYSBSYSKIT-01 Rapid IoT Connect Platform RP01 Feather Kit | +| 2.2.0 | Added CUSTOM_DESIGN_MODUS for CYSBSYSKIT-DEV-01 Rapid IoT Connect Developer Kit | ------ All other trademarks or registered trademarks referenced herein are the property of their respective owners.