@@ -2032,7 +2032,6 @@ static int do_attach(struct iommu_dev_data *dev_data,
20322032 struct protection_domain * domain )
20332033{
20342034 struct amd_iommu * iommu = get_amd_iommu_from_dev_data (dev_data );
2035- struct pci_dev * pdev ;
20362035 int ret = 0 ;
20372036
20382037 /* Update data structures */
@@ -2047,30 +2046,13 @@ static int do_attach(struct iommu_dev_data *dev_data,
20472046 domain -> dev_iommu [iommu -> index ] += 1 ;
20482047 domain -> dev_cnt += 1 ;
20492048
2050- pdev = dev_is_pci ( dev_data -> dev ) ? to_pci_dev ( dev_data -> dev ) : NULL ;
2049+ /* Setup GCR3 table */
20512050 if (pdom_is_sva_capable (domain )) {
20522051 ret = init_gcr3_table (dev_data , domain );
20532052 if (ret )
20542053 return ret ;
2055-
2056- if (pdev ) {
2057- pdev_enable_caps (pdev );
2058-
2059- /*
2060- * Device can continue to function even if IOPF
2061- * enablement failed. Hence in error path just
2062- * disable device PRI support.
2063- */
2064- if (amd_iommu_iopf_add_device (iommu , dev_data ))
2065- pdev_disable_cap_pri (pdev );
2066- }
2067- } else if (pdev ) {
2068- pdev_enable_cap_ats (pdev );
20692054 }
20702055
2071- /* Update device table */
2072- amd_iommu_dev_update_dte (dev_data , true);
2073-
20742056 return ret ;
20752057}
20762058
@@ -2163,17 +2145,18 @@ static void detach_device(struct device *dev)
21632145
21642146 do_detach (dev_data );
21652147
2148+ out :
2149+ spin_unlock (& dev_data -> lock );
2150+
2151+ spin_unlock_irqrestore (& domain -> lock , flags );
2152+
21662153 /* Remove IOPF handler */
21672154 if (ppr )
21682155 amd_iommu_iopf_remove_device (iommu , dev_data );
21692156
21702157 if (dev_is_pci (dev ))
21712158 pdev_disable_caps (to_pci_dev (dev ));
21722159
2173- out :
2174- spin_unlock (& dev_data -> lock );
2175-
2176- spin_unlock_irqrestore (& domain -> lock , flags );
21772160}
21782161
21792162static struct iommu_device * amd_iommu_probe_device (struct device * dev )
@@ -2485,6 +2468,7 @@ static int amd_iommu_attach_device(struct iommu_domain *dom,
24852468 struct iommu_dev_data * dev_data = dev_iommu_priv_get (dev );
24862469 struct protection_domain * domain = to_pdomain (dom );
24872470 struct amd_iommu * iommu = get_amd_iommu_from_dev (dev );
2471+ struct pci_dev * pdev ;
24882472 int ret ;
24892473
24902474 /*
@@ -2517,7 +2501,23 @@ static int amd_iommu_attach_device(struct iommu_domain *dom,
25172501 }
25182502#endif
25192503
2520- iommu_completion_wait (iommu );
2504+ pdev = dev_is_pci (dev_data -> dev ) ? to_pci_dev (dev_data -> dev ) : NULL ;
2505+ if (pdev && pdom_is_sva_capable (domain )) {
2506+ pdev_enable_caps (pdev );
2507+
2508+ /*
2509+ * Device can continue to function even if IOPF
2510+ * enablement failed. Hence in error path just
2511+ * disable device PRI support.
2512+ */
2513+ if (amd_iommu_iopf_add_device (iommu , dev_data ))
2514+ pdev_disable_cap_pri (pdev );
2515+ } else if (pdev ) {
2516+ pdev_enable_cap_ats (pdev );
2517+ }
2518+
2519+ /* Update device table */
2520+ amd_iommu_dev_update_dte (dev_data , true);
25212521
25222522 return ret ;
25232523}
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