RP2A03 clocked at 20mhz? #22
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The chip is clocked at 20 MHz, but that is divided by 12 internally to provide an internal clock of 1.66 MHz. In the NES it is clocked at 21.48 MHz, so it is actually a bit slower in the NESizer. |
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Okay awesome - makes total sense. I've added pin headers now (instead of an Atmega328AU on the underside) so I can jumper internal 20mhz or external clock .. in the event clock modulation isn't that exciting as I hope I can just solder the jumper closed. I verified my clock modulation on a scope, smooth and stable from 10mhz down to about 80khz. Also added an extra 10uf cap on the +ve side of the mixer bias and a separate 78L05 just for the opamp to help reduce any noise bleed. |
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Another annoying question (sorry) Have you considered replacing the RAM chips and battery with a SST25VF080B EEprom? |
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Sounds like some cool additions, especially the separate 7805. Good luck with the build! :) |
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Not annoying at all! The hardware design is a good mix of practical solutions and some solutions chosen purely for the fun or challenge of it at the time (10 years ago or so now, time flies!). Since the 2A03 required 8 GPIOs to feed it instructions anyway, I liked the idea of sharing those 8 GPIOs for interfacing the rest of the system (LEDs, buttons, memory) as well - especially since the 2A03 wouldn't actually be needing new instructions that often and the lines would just sit idle. It sort of became an obsession to not use unnecessarily many GPIOs in the Atmega. In hindsight, a more pragmatic solution would have been to just move to a larger Atmega package and use some more pins. Then a lot of those latches could probably be ditched. I did consider flash (although with a parallel interface) to avoid the battery backup, but I didn't like the lifetime aspect of it, although it would take a while to reach 100.000 writes on a flash cell... I also wanted to make an old school battery backed memory circuit (but it did end up being a huge hassle). It does end up quite expensive though, the RAMs and the DS1210 are super expensive. So I guess it is in the 'if it aint broke dont fix it' category, yes :P Using a SPI flash is a nice idea, I agree it should probably be fast enough - reading N bytes from the flash would take about 8 + 24 + 8*N cycles at 10 MHz (so something like 80 CPU cycles to read one byte), and when I look at the disassembly of memory.c I see that the number of instructions needed to perform a read today would be a bit less than that but not by too much. Some variants of reading, such as sequential reading (only updating latches as needed), might take less cycles compared to the SPI flash though. Most of the pins (MISO, MOSI, SCK) are available as well. The SS pin is in use, but it can probably be driven by one of the latches instead. Code wise it should also be pretty easy, all the memory related stuff is in io/memory.c, so any other modules accessing the memory don't really know anything about how the access happens. So if you want to try this out it should be pretty doable! Should be fairly easy to mod the board to test it out as well. |
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Am I missing something in the schematic - or is the 2A03 being clocked at 20mhz? I cant find an actual datasheet - wikipedia says max clock is 1.79mhz
Given the age I would expect 2A03 could probably handle 2-6mhz .. but 20 would be a stretch. Has anyone noticed 2A03's frying after a period in this?
Im about to build one - just wondering if I stick a 2mhz cmos clock on it before I order the PCBs
(Really my inner hacker wants to circuit bend this and put an adjustable clock on it :P)
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