From e6e7c7a1df8813c364bf79891838ec07304d6f67 Mon Sep 17 00:00:00 2001 From: Aba Date: Mon, 22 Jul 2024 23:49:39 -0700 Subject: [PATCH] Minor cleanup --- deepsocflow/c/runtime.h | 73 ++++++++++++++----------------- deepsocflow/test/sv/axi_sys_tb.sv | 8 ++-- 2 files changed, 36 insertions(+), 45 deletions(-) diff --git a/deepsocflow/c/runtime.h b/deepsocflow/c/runtime.h index 5a16d47..2130657 100644 --- a/deepsocflow/c/runtime.h +++ b/deepsocflow/c/runtime.h @@ -86,24 +86,21 @@ typedef struct { Memory_st mem; - static inline void flush_cache(void *addr, uint32_t bytes) { - // Do nothing - } - // Get and set config are done by sv extern EXT_C u32 get_config(u32); extern EXT_C void set_config(u32, u32); + static inline void flush_cache(void *addr, uint32_t bytes) {} // Do nothing #else #define sim_fprintf(...) #define mem (*(Memory_st* restrict)MEM_BASEADDR) inline volatile u32 get_config(u32 offset){ - return *(volatile u32 *)(CONFIG_BASEADDR + offset); + return *(volatile u32 *)(CONFIG_BASEADDR + offset*4); } inline void set_config(u32 offset, u32 data){ - volatile u32 *Addr = (volatile u32 *restrict)(CONFIG_BASEADDR + offset); + volatile u32 *Addr = (volatile u32 *restrict)(CONFIG_BASEADDR + offset*4); *Addr = data; } #endif @@ -285,7 +282,7 @@ extern EXT_C u8 model_run() { #endif debug_printf("Starting model_run()\n"); - set_config(4*A_START, 1); + set_config(A_START, 1); for (ib = 0; ib < N_BUNDLES; ib++) { @@ -307,7 +304,7 @@ extern EXT_C u8 model_run() { #ifdef SIM DMA_WAIT: // if sim return, so SV can pass time, and call again, which will jump to DMA_WAIT again - if (!get_config(4*(A_DONE_WRITE + ocm_bank))) + if (!get_config(A_DONE_WRITE + ocm_bank)) return 1; char f_path_raw [1000], f_path_sum [1000]; // make sure full f_path_raw is shorter than 1000 @@ -316,12 +313,12 @@ extern EXT_C u8 model_run() { FILE *fp_raw = fopen(f_path_raw, "a"); FILE *fp_sum = fopen(f_path_sum, "a"); #else - while (!get_config(4*(A_DONE_WRITE + ocm_bank))){ + while (!get_config(A_DONE_WRITE + ocm_bank)){ // in FPGA, wait for write done }; usleep(0); #endif - set_config(4*(A_DONE_WRITE + ocm_bank), 0); + set_config(A_DONE_WRITE + ocm_bank, 0); flush_cache(&ocm[ocm_bank], PE_ROWS*PE_COLS*sizeof(Y_TYPE)) ; w_last = iw_kw2 == pb->w_kw2-1 ? pb->kw/2+1 : 1; @@ -508,7 +505,7 @@ extern EXT_C u8 model_run() { fclose(fp_sum); fclose(fp_raw); #endif - set_config(4*(A_DONE_READ + ocm_bank), 1); + set_config(A_DONE_READ + ocm_bank, 1); debug_printf("-------- iw_kw2 0x%x done \n", iw_kw2); } // iw_kw2 iw_kw2 = 0; @@ -554,7 +551,7 @@ extern EXT_C u8 model_run() { fclose(fp_packed); } #endif - set_config(4*A_BUNDLE_DONE, 1); + set_config(A_BUNDLE_DONE, 1); } // ib ib = 0; debug_printf("done all bundles!!\n"); @@ -569,19 +566,6 @@ extern EXT_C u8 model_run() { // Rest of the helper functions used in simulation. #ifdef SIM -extern EXT_C void sim_fill_memory (){ - FILE *fp; - char f_path [1000]; - - sprintf(f_path, "%s/wbx.bin", DATA_DIR); - fp = fopen(f_path, "rb"); - debug_printf("DEBUG: Reading from file %s \n", f_path); - if(!fp) - debug_printf("ERROR! File not found: %s \n", f_path); - int bytes = fread(mem.w, 1, WB_BYTES+X_BYTES, fp); - fclose(fp); -} - extern EXT_C u32 addr_64to32(void* restrict addr){ u64 offset = (u64)addr - (u64)&mem; return (u32)offset + 0x20000000; @@ -613,24 +597,31 @@ u32 addr_64to32 (void* addr){ extern EXT_C void model_setup(){ #ifdef SIM - sim_fill_memory(); + FILE *fp; + char f_path [1000]; + sprintf(f_path, "%s/wbx.bin", DATA_DIR); + fp = fopen(f_path, "rb"); + debug_printf("DEBUG: Reading from file %s \n", f_path); + if(!fp) debug_printf("ERROR! File not found: %s \n", f_path); + int bytes = fread(mem.w, 1, WB_BYTES+X_BYTES, fp); + fclose(fp); #endif flush_cache(&mem.w, WB_BYTES+X_BYTES); // force transfer to DDR, starting addr & length // Write registers in controller - set_config(4*A_START, 0); // Start - set_config(4*(A_DONE_READ+0), 1); // Done read ocm bank 0 - set_config(4*(A_DONE_READ+1), 1); // Done read ocm bank 1 - set_config(4*(A_DONE_WRITE+0), 0); // Done write ocm bank 0 - set_config(4*(A_DONE_WRITE+1), 0); // Done write ocm bank 1 - set_config(4*(A_OCM_BASE+0), addr_64to32(ocm[0])); // Base addr ocm bank 0 - set_config(4*(A_OCM_BASE+1), addr_64to32(ocm[1])); // Base addr ocm bank 1 - set_config(4*A_WEIGHTS_BASE, addr_64to32(mem.w)); // Base adddr weights - set_config(4*A_BUNDLE_DONE, 1); // Bundle done (?) - set_config(4*A_N_BUNDLES_1, N_BUNDLES); // Number of bundles - set_config(4*A_W_DONE, 0); // Weigths done - set_config(4*A_X_DONE, 0); // Bundle done - set_config(4*A_O_DONE, 0); // Output done + set_config(A_START , 0); // Start + set_config(A_DONE_READ +0, 1); // Done read ocm bank 0 + set_config(A_DONE_READ +1, 1); // Done read ocm bank 1 + set_config(A_DONE_WRITE+0, 0); // Done write ocm bank 0 + set_config(A_DONE_WRITE+1, 0); // Done write ocm bank 1 + set_config(A_OCM_BASE +0, addr_64to32(ocm[0])); // Base addr ocm bank 0 + set_config(A_OCM_BASE +1, addr_64to32(ocm[1])); // Base addr ocm bank 1 + set_config(A_WEIGHTS_BASE, addr_64to32(mem.w)); // Base adddr weights + set_config(A_BUNDLE_DONE , 1); // Bundle done writing (pixel dma waits for this) + set_config(A_N_BUNDLES_1 , N_BUNDLES); // Number of bundles + set_config(A_W_DONE , 0); // Weigths done + set_config(A_X_DONE , 0); // Bundle done + set_config(A_O_DONE , 0); // Output done // Write into BRAM the config for controller i32 parameters[8*N_BUNDLES]; @@ -640,14 +631,14 @@ extern EXT_C void model_setup(){ parameters[8*var+2] = bundles[var].x_bpt; // x_bpt parameters[8*var+3] = bundles[var].w_bpt_p0; // w_bpt0 parameters[8*var+4] = bundles[var].w_bpt; // w_bpt + assert_printf(bundles[var].p, <, 1<<16, "", "P should be less than 2**16 for bundle:%x", var); assert_printf(bundles[var].t, <, 1<<16, "", "T should be less than 2**16 for bundle:%x", var); parameters[8*var+5] = (bundles[var].t << 16) + bundles[var].p; // max p - parameters[8*var+6] = ((u32*)&bundles[var].header)[0]; parameters[8*var+7] = ((u32*)&bundles[var].header)[1]; } for (int var = 0; var < 8*N_BUNDLES; var++){ - set_config(4*(16+var), parameters[var]); + set_config(16+var, parameters[var]); } } diff --git a/deepsocflow/test/sv/axi_sys_tb.sv b/deepsocflow/test/sv/axi_sys_tb.sv index 02026a3..1bdb6f2 100644 --- a/deepsocflow/test/sv/axi_sys_tb.sv +++ b/deepsocflow/test/sv/axi_sys_tb.sv @@ -60,14 +60,14 @@ module axi_sys_tb; function automatic int get_config(input int offset); - if (offset < 16*4) return dut.OC_TOP.CONTROLLER.cfg[offset/4]; - else return dut.OC_TOP.CONTROLLER.sdp_ram.RAM[offset/4-16]; + if (offset < 16) return dut.OC_TOP.CONTROLLER.cfg [offset ]; + else return dut.OC_TOP.CONTROLLER.sdp_ram.RAM[offset-16]; endfunction function automatic set_config(input int offset, input int data); - if (offset < 16*4) dut.OC_TOP.CONTROLLER.cfg[offset/4] <= data; - else dut.OC_TOP.CONTROLLER.sdp_ram.RAM[offset/4-16] <= data; + if (offset < 16) dut.OC_TOP.CONTROLLER.cfg [offset ] <= data; + else dut.OC_TOP.CONTROLLER.sdp_ram.RAM[offset-16] <= data; endfunction