From 8547d8ace154fd65c65cdfc951b09a6b6af2f262 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Tue, 4 Mar 2025 23:40:22 +0000 Subject: [PATCH 01/36] Start on an ECOND formatter --- include/pflib/ECOND_Formatter.h | 26 +++++++ src/pflib/ECOND_Formatter.cxx | 121 ++++++++++++++++++++++++++++++++ 2 files changed, 147 insertions(+) create mode 100644 include/pflib/ECOND_Formatter.h create mode 100644 src/pflib/ECOND_Formatter.cxx diff --git a/include/pflib/ECOND_Formatter.h b/include/pflib/ECOND_Formatter.h new file mode 100644 index 00000000..c54c56b7 --- /dev/null +++ b/include/pflib/ECOND_Formatter.h @@ -0,0 +1,26 @@ +#ifndef pflib_ECOND_Formatter_h_included +#define pflib_ECOND_Formatter_h_included + +#include +#include + +namespace pflib { + + class ECOND_Formatter { + public: + ECOND_Formatter(int subsystem_id, int conributor_id); + void test(); + + private: + std::vector format_elink(const std::vector& src); + int zs_process(int ic, uint32_t word); + + int burn_count_; + int subsystem_id_; + int contributor_id_; + int sentinel_; + }; + +} + +#endif // pflib_ECOND_Formatter_h_included diff --git a/src/pflib/ECOND_Formatter.cxx b/src/pflib/ECOND_Formatter.cxx new file mode 100644 index 00000000..f09b0f2b --- /dev/null +++ b/src/pflib/ECOND_Formatter.cxx @@ -0,0 +1,121 @@ +#include "pflib/ECOND_Formatter.h" +#include + +namespace pflib { + + ECOND_Formatter::ECOND_Formatter(int subsys, int contrib) : burn_count_{0}, subsystem_id_{subsys}, contributor_id_{contrib}, sentinel_{0xA5} { + } + + std::vector ECOND_Formatter::format_elink(const std::vector& src) { + std::vector dest; + int n_readout=0; + // check for right number of words, correct header, etc + if (src.size()!=40 || ((src[0]>>28)&0xF)!=0xF) { + // if (src.size()!=40 || ((src[0]>>28)&0xF)!=0xF || (((src[0]&0xF)!=0x5 && (src[0]&0xF)!=0x2))) { + printf("Invalid contents\n"); + return dest; + } + dest.push_back(0); + dest.push_back(0); + + // stat bits (assuming happy for now) + dest[0]|=(0x7u<<29); + // hamming bits + dest[0]|=(src[0]&0x70)<<(26-4); + // common mode + dest[0]|=(src[1]&0xFFFFF)<<5; + + uint32_t building_word=0; + int space_left=32; // bits in the word + + for (int iw=0; iw<37; iw++) { + uint32_t word=src[2+iw]; + int ic=iw; + if (ic==18) ic=-1; + else if (ic>18) ic-=1; + int code=zs_process(ic,word); + if (code>=0) { + // set the channel map bit + if (ic>=32) dest[0]|=(1<<(ic-32)); + else dest[1]|=(1<>10)&0xFFFFF); + insert_len=24; + } else if (code==1) { // ADC-1 and TOA ZS + insert_value=(0x1<<12)|((word>>8)&0xFFC); + insert_len=16; + } else if (code==2) { // TcTp=01, TOA ZS + insert_value=(0x2<<12)|((word>>10)&0xFFFFF); + insert_len=24; + } else if (code==3) { // ADC-1 ZS + insert_value=(0x3<<12)|(word&0xFFFFF); + insert_len=24; + } else if (code==4) { // readout all, ADC + insert_value=(0x1<<30)|(word&0x3FFFFFFF); + } else if (code==12) { // readout all, TOT + insert_value=word; + } else { // invalid code, readout all + insert_value=word; + } + // + while (insert_len>=space_left) { + building_word|=(insert_value>>(insert_len-space_left)); + if ((insert_len-space_left)==8) insert_value&=0xFF; + else if ((insert_len-space_left)==16) insert_value&=0xFFFF; + else if ((insert_len-space_left)==24) insert_value&=0xFFFFFF; + insert_len-=space_left; + dest.push_back(building_word); + building_word=0; + space_left=32; + } + if (insert_len>0) { + building_word|=insert_value<<(space_left-insert_len); + space_left-=insert_len; + } + } + } + if (space_left!=32) { + dest.push_back(building_word); + } + + return dest; + } + int ECOND_Formatter::zs_process(int ic, uint32_t word) { + // eventually, implement detailed code to carry out different classes of ZS with provided + // parameters. For now, we just look at the tc/tp code + int tctp=(word>>30)&0x3; + if (tctp==0x3) return 12; // is TOT + if (tctp==0x2) return 8; // is strange + if (tctp==0x1) return 2; // is invalid due to ongoing TOT + /// at this point, we have tctp=0, so we can apply zs algorithms + // TOA zs... + bool no_toa=((word&0x3FF)==0); + return 0; + return 4; // assume we just read out everything for now, but easy to add TOA zs logic + } + + static const uint32_t data[]={0xf00c9c86u,0x2012c02, + 0x0c601803,0x08f07d02,0x08509602,0x0840d702, + 0x0c705d03,0x0c303d03,0x08f0ff02, + 0x0c906d03,0x0c203d03,0x0c200c03,0x0ca06503, + 0x0c609a03,0x0ce02c03,0x0c304903,0x0c308e03, + 0x0c108e03,0x0c508e03,0x0ce03c03,0x0c705d03, + 0x0cf03c03,0x0c902403,0x0cf07d03,0x0cf03c03, + 0x0cf07d03,0x0c409603,0x0c50d303,0x0ca0aa03, + 0x0cd03403,0x0c701c03,0x0cd07503,0x0c305103, + 0x0c902803,0x0cb03403,0x0c906903,0x0c706503, + 0x0890eb02,0x08f0ff02,0x0}; + + void ECOND_Formatter::test() { + std::vector xd; + for (int i=0; i<40; i++) xd.push_back(data[i]); + std::vector ecd=format_elink(xd); + for (size_t j=0; j Date: Wed, 10 Sep 2025 20:21:04 +0000 Subject: [PATCH 02/36] Change CTL test to deal with very good mezzanines --- app/lpgbt/main.cxx | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/app/lpgbt/main.cxx b/app/lpgbt/main.cxx index 8af6864c..658df53c 100644 --- a/app/lpgbt/main.cxx +++ b/app/lpgbt/main.cxx @@ -430,7 +430,19 @@ bool test_ctl(ToolBox* target) { // ensure that the lpGBT is setup properly for transmitting the fast control for (int i = 0; i < 7; i++) target->lpgbt->setup_etx(i, true); // set all the CTL links to mode (4) (just 4 links in this counting...) - for (int i = 0; i < 4; i++) target->olink->set_elink_tx_mode(i, 4); + for (int i=0; i<4; i++) + target->olink->set_elink_tx_mode(i,4); + + bool ok=true; + for (int ilink=0; ilink<7; ilink++) { + std::vector words=mezz.capture(ilink,false); + if (words[0]==0) { + printf(" CTL Link %d is all zeros\n",ilink); + ok=false; + } + } + if (!ok) return false; + // set the prbs length mezz.set_prbs_len_ms(1000); // one second per point... for (int ph = 0; ph < 510; ph += 20) { @@ -446,14 +458,12 @@ bool test_ctl(ToolBox* target) { } printf("\n"); } - bool pass = true; - for (int i = 0; i < 7; i++) { - if (nbad[i] == 0) { - printf(" Suspiciously, never saw a failure on %d, was PRBS ok?\n", i); - pass = false; - } else if (nbad[i] > 4) { - printf(" High failure count (%d) on link %d\n", nbad[i], i); - pass = false; + + bool pass=true; + for (int i=0; i<7; i++) { + if (nbad[i]>4) { + printf(" High failure count (%d) on link %d\n",nbad[i],i); + pass=false; } } if (pass) From 70c3d4c51e367dde21bf86b2e2ecf29a116e33d7 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Tue, 16 Sep 2025 22:39:05 +0000 Subject: [PATCH 03/36] Working EC and handling of dual link firmware, pretty much done with lpGBT-only development --- CMakeLists.txt | 1 + app/lpgbt/lpgbt_mezz_tester.cc | 36 ---- app/lpgbt/lpgbt_mezz_tester.h | 1 - app/lpgbt/main.cxx | 192 +++++++++++++++---- app/lpgbt/zcu_optolink.cc | 99 +++++++++- app/lpgbt/zcu_optolink.h | 9 +- include/pflib/Hcal.h | 2 +- include/pflib/I2C.h | 2 +- include/pflib/Target.h | 1 + include/pflib/lpGBT.h | 33 ++++ include/pflib/lpgbt/lpGBT_standard_configs.h | 21 ++ include/pflib/zcu/lpGBT_ICEC_ZCU_Simple.h | 1 + src/pflib/lpGBT.cxx | 118 ++++++++++++ src/pflib/lpgbt/lpGBT_standard_configs.cxx | 48 +++++ src/pflib/zcu/UIO.cxx | 45 ++++- src/pflib/zcu/lpGBT_ICEC_ZCU_Simple.cxx | 25 ++- 16 files changed, 540 insertions(+), 94 deletions(-) create mode 100644 include/pflib/lpgbt/lpGBT_standard_configs.h create mode 100644 src/pflib/lpgbt/lpGBT_standard_configs.cxx diff --git a/CMakeLists.txt b/CMakeLists.txt index b8ca1a6a..2cd8593c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -158,6 +158,7 @@ add_library(pflib SHARED src/pflib/lpgbt/lpGBT_ConfigTransport_I2C.cxx src/pflib/lpgbt/lpGBT_Registers.cxx src/pflib/lpgbt/lpGBT_Utility.cxx + src/pflib/lpgbt/lpGBT_standard_configs.cxx src/pflib/TargetFiberless.cxx src/pflib/GPIO_HcalHGCROCZCU.cxx src/pflib/FastControlCMS_MMap.cxx diff --git a/app/lpgbt/lpgbt_mezz_tester.cc b/app/lpgbt/lpgbt_mezz_tester.cc index bd5d9d0d..6e444ec1 100644 --- a/app/lpgbt/lpgbt_mezz_tester.cc +++ b/app/lpgbt/lpgbt_mezz_tester.cc @@ -159,39 +159,3 @@ std::vector LPGBT_Mezz_Tester::capture(int ilink, bool is_rx) { } -void LPGBT_Mezz_Tester::capture_ec(int mode, std::vector& tx, std::vector& rx) { - static constexpr int REG_SPY_CTL = 67; - static constexpr int REG_READ = 69; - - uint32_t val=opto_.read(REG_SPY_CTL); - val=val&0x1FF; - val=val|((mode&0x3)<<10)|(1<<9); - opto_.write(REG_SPY_CTL,val); - - // now wait for it... - bool done=false; - do { - usleep(100); - done=(opto_.read(REG_READ)&0x400)!=0; - if (mode==0) done=true; - } while (!done); - val=val&0x1FF; - val=val|((mode&0x3)<<10); // disable the spy - opto_.write(REG_SPY_CTL,val); - - tx.clear(); - rx.clear(); - - val=val&0x1FF; - val=val|((mode&0x3)<<10); - for (int i=0; i<256; i++) { - val=val&0xFFF; - val=val|(i<<12); - opto_.write(REG_SPY_CTL,val); - usleep(1); - uint32_t k=opto_.read(REG_READ); - tx.push_back((k>>(2+11))&0x3); - rx.push_back((k>>11)&0x3); - } - -} diff --git a/app/lpgbt/lpgbt_mezz_tester.h b/app/lpgbt/lpgbt_mezz_tester.h index e0262949..29e4cd51 100644 --- a/app/lpgbt/lpgbt_mezz_tester.h +++ b/app/lpgbt/lpgbt_mezz_tester.h @@ -22,7 +22,6 @@ class LPGBT_Mezz_Tester { std::vector ber_tx(); std::vector capture(int ilink, bool is_rx = false); - void capture_ec(int mode, std::vector& tx, std::vector& rx); private: pflib::UIO& opto_; diff --git a/app/lpgbt/main.cxx b/app/lpgbt/main.cxx index 658df53c..7be64426 100644 --- a/app/lpgbt/main.cxx +++ b/app/lpgbt/main.cxx @@ -6,16 +6,18 @@ #include "lpgbt_mezz_tester.h" #include "pflib/lpgbt/lpGBT_ConfigTransport_I2C.h" #include "pflib/lpgbt/lpGBT_Utility.h" +#include "pflib/lpgbt/lpGBT_standard_configs.h" #include "pflib/menu/Menu.h" #include "pflib/zcu/lpGBT_ICEC_ZCU_Simple.h" #include "power_ctl_mezz.h" #include "zcu_optolink.h" struct ToolBox { - pflib::lpGBT* lpgbt; - pflib::lpGBT* lpgbt_i2c; - pflib::lpGBT* lpgbt_ic; - pflib::zcu::OptoLink* olink; + pflib::lpGBT* lpgbt{0}; + pflib::lpGBT* lpgbt_i2c{0}; + pflib::lpGBT* lpgbt_ic{0}; + pflib::lpGBT* lpgbt_ec{0}; + pflib::zcu::OptoLink* olink{0}; pflib::power_ctl_mezz* p_ctl{0}; }; @@ -42,8 +44,7 @@ void opto(const std::string& cmd, ToolBox* target) { i.second); } } - if (cmd == "RESET") { - olink.reset_link(); + if (cmd == "RESET") { olink.reset_link(); } if (cmd == "POLARITY") { bool change; @@ -61,24 +62,87 @@ void opto(const std::string& cmd, ToolBox* target) { } } +void i2c(const std::string& cmd, ToolBox* target) { + static int ibus=0; + ibus=tool::readline_int("Which I2C bus?",ibus); + target->lpgbt->setup_i2c(ibus,100); + if (cmd=="SCAN") { + for (int addr=0; addr<0x80; addr++) { + bool success=true; + char failchar; + target->lpgbt->start_i2c_read(ibus,addr); // try reading a byte + try { + target->lpgbt->i2c_transaction_check(ibus,true); + } catch (pflib::Exception& e) { + if (e.name()=="I2CErrorNoCLK") failchar='C'; + else if (e.name()=="I2CErrorNoACK") failchar='-'; + else if (e.name()=="I2CErrorSDALow") failchar='*'; + else failchar='?'; + // printf(e.what()); + success=false; + } + if ((addr%0x10)==0) printf("\n%02x ",addr); + if (success) printf("%02x ",addr); + else printf("%c%c ",failchar,failchar); + } + printf("\n"); + } + static int i2c_addr=0; + if (cmd=="WRITE") { + std::vector values; + i2c_addr=tool::readline_int("What I2C Address?",i2c_addr); + int nvalues=tool::readline_int("How many bytes?",1); + for (int i=0; ilpgbt->i2c_write(ibus,i2c_addr,values); + target->lpgbt->i2c_transaction_check(ibus,true); + } + if (cmd=="READ") { + std::vector values; + i2c_addr=tool::readline_int("What I2C Address?",i2c_addr); + int nvalues=tool::readline_int("How many bytes?",1); + target->lpgbt->start_i2c_read(ibus,i2c_addr,nvalues); + target->lpgbt->i2c_transaction_check(ibus,true); + values=target->lpgbt->i2c_read_data(ibus); + for (int i=0; ilpgbt == target->lpgbt_i2c); if (cmd == "STATUS") { if (comm_is_i2c) printf(" Communication by I2C\n"); - else + else if (target->lpgbt == target->lpgbt_ic) printf(" Communication by IC\n"); + else + printf(" Communication by EC\n"); int pusm = target->lpgbt->status(); printf(" PUSM %s (%d)\n", target->lpgbt->status_name(pusm).c_str(), pusm); } if (cmd == "RESET") { - LPGBT_Mezz_Tester tester(target->olink->coder()); - tester.reset_lpGBT(); + if (target->lpgbt_i2c!=0) { + LPGBT_Mezz_Tester tester(target->olink->coder()); + tester.reset_lpGBT(); + } else { // resets the TRIGGER lpGBT + target->lpgbt_ic->gpio_set(11,false); + target->lpgbt_ic->gpio_set(11,true); + } + } + if (cmd == "STANDARD_HCAL_DAQ") { + pflib::lpgbt::standard_config::setup_hcal_daq(*target->lpgbt); + printf("Applied standard HCAL DAQ configuration\n"); } if (cmd == "MODE") { LPGBT_Mezz_Tester tester(target->olink->coder()); - printf("MODE1 = 1 for Transceiver, MODE1=0 for Transmit-onlt\n"); + printf("MODE1 = 1 for Transceiver, MODE1=0 for Transmit-only\n"); bool wasMode, wasAddr; tester.get_mode(wasAddr, wasMode); bool newaddr = tool::readline_bool("ADDR bit", wasAddr); @@ -93,11 +157,20 @@ void general(const std::string& cmd, ToolBox* target) { } } if (cmd == "COMM") { - printf("Swapping communication paths\n"); - if (comm_is_i2c) - target->lpgbt = target->lpgbt_ic; - else + bool go_opto = tool::readline_bool("Use optical communication?",!comm_is_i2c); + if (go_opto) { + bool be_ic = tool::readline_bool("Talk to DAQ lpGBT?",target->lpgbt==target->lpgbt_ic); + if (!be_ic) { + printf(" Communication path is EC\n"); + target->lpgbt = target->lpgbt_ec; + } else { + printf(" Communication path is IC\n"); + target->lpgbt = target->lpgbt_ic; + } + } else { + printf(" Communication path is wired I2C (FMC)\n"); target->lpgbt = target->lpgbt_i2c; + } } } @@ -158,9 +231,9 @@ void adc(const std::string& cmd, ToolBox* target) { } void elink(const std::string& cmd, ToolBox* target) { - LPGBT_Mezz_Tester mezz(target->olink->coder()); if (cmd == "SPY") { + LPGBT_Mezz_Tester mezz(target->olink->coder()); bool isrx = tool::readline_bool("Spy on an RX? (false for TX) ", false); int ilink = tool::readline_int("Which elink to spy", 0); std::vector words = mezz.capture(ilink, isrx); @@ -180,7 +253,24 @@ void elink(const std::string& cmd, ToolBox* target) { } int imode = tool::readline_int("Which mode (zero for immediate)", 0); std::vector tx, rx; - mezz.capture_ec(imode, tx, rx); + target->olink->capture_ec(imode, tx, rx); + std::string stx, srx; + for (size_t i = 0; i < tx.size(); i++) { + stx += (tx[i] & 0x2) ? ("1") : ("0"); + stx += (tx[i] & 0x1) ? ("1") : ("0"); + srx += (rx[i] & 0x2) ? ("1") : ("0"); + srx += (rx[i] & 0x1) ? ("1") : ("0"); + if (((i + 1) % 32) == 0) { + printf("%3d %s %s\n", i - 31, stx.c_str(), srx.c_str()); + stx = ""; + srx = ""; + } + } + } + if (cmd == "ICSPY") { + int imode = tool::readline_int("Which mode (zero for immediate)", 0); + std::vector tx, rx; + target->olink->capture_ic(imode, tx, rx); std::string stx, srx; for (size_t i = 0; i < tx.size(); i++) { stx += (tx[i] & 0x2) ? ("1") : ("0"); @@ -496,7 +586,7 @@ bool test_ec(ToolBox* target) { uint32_t errors = 0; for (int cycle = 0; cycle < 100; cycle++) { - mezz.capture_ec(0, tx, rx); + target->olink->capture_ec(0, tx, rx); std::vector srx; for (size_t i = 0; i < tx.size(); i++) { @@ -630,6 +720,7 @@ namespace { auto gen = tool::menu("GENERAL", "GENERAL funcations") ->line("STATUS", "Status summary", general) ->line("MODE", "Setup the lpGBT ADDR and MODE1", general) + ->line("STANDARD_HCAL_DAQ", "Apply standard HCAL DAQ lpGBT setup", general) ->line("RESET", "Reset the lpGBT", general) ->line("COMM", "Communication mode", general); @@ -655,12 +746,19 @@ auto melink = tool::menu("ELINK", "Elink-related items") ->line("SETUP", "Setup a pin", elink) ->line("PATTERN", "Pattern selection for", elink) ->line("SPY", "Spy on one or more pins", elink) - ->line("ECSPY", "Spy on the EC link", elink); + ->line("ECSPY", "Spy on the EC link", elink) + ->line("ICSPY", "Spy on the IC link", elink); auto madc = tool::menu("ADC", "ADC and DAC-related actions") ->line("READ", "Read an ADC line", adc) ->line("ALL", "Read all ADC lines", adc); +auto mi2c = tool::menu("I2C", "I2C activities") + ->line("SCAN", "Scan an I2C bus", i2c) + ->line("READ", "Read from an I2C device", i2c) + ->line("WRITE", "Write to an I2C device", i2c); + + auto mtest = tool::menu("TEST", "Mezzanine testing functions") ->line("BASIC", "Test the power and communication functions", test) @@ -677,16 +775,34 @@ auto mtest = int main(int argc, char* argv[]) { if (argc == 2 and (!strcmp(argv[1], "-h") or !strcmp(argv[1], "--help"))) { printf("\nUSAGE: \n"); - printf(" %s -z OPTIONS\n\n", argv[0]); + printf(" %s OPTIONS\n\n", argv[0]); printf("OPTIONS:\n"); + printf(" --do [number] : Dual-optical configuration, implies no mezzanine\n"); + printf(" -o : Use optical communication by default\n"); + printf(" --nm : No mezzanine\n"); printf(" -s [file] : pass a script of commands to run through\n"); printf(" -h|--help : print this help and exit\n"); printf("\n"); return 1; } + bool wired=true; + bool nomezz=false; + std::string target_name("singleLPGBT"); + for (int i = 1; i < argc; i++) { std::string arg(argv[i]); + if (arg == "-o") wired=false; + if (arg == "--nm") nomezz=true; + if (arg == "--do") { + wired=false; + nomezz=true; + i++; + target_name="standardLpGBTpair-"; + target_name+=argv[i][0]; + printf("%s\n",target_name.c_str()); + } + if (arg == "-s") { if (i + 1 == argc or argv[i + 1][0] == '-') { std::cerr << "Argument " << arg << " requires a file after it." @@ -714,30 +830,38 @@ int main(int argc, char* argv[]) { tool::set_history_filepath("~/.pflpgbt-history"); - pflib::zcu::OptoLink olink; - LPGBT_Mezz_Tester tester(olink.coder()); - bool addr, mode1; - tester.get_mode(addr, mode1); // need to determine address + ToolBox t; + pflib::zcu::OptoLink olink(target_name.c_str()); int chipaddr = 0x78; - if (addr) chipaddr |= 0x1; - if (mode1) chipaddr |= 0x4; - printf(" ADDR = %d and MODE1=%d -> 0x%02x\n", addr, mode1, chipaddr); + if (wired) { + LPGBT_Mezz_Tester tester(olink.coder()); + bool addr, mode1; + tester.get_mode(addr, mode1); // need to determine address + if (addr) chipaddr |= 0x1; + if (mode1) chipaddr |= 0x4; + printf(" ADDR = %d and MODE1=%d -> 0x%02x\n", addr, mode1, chipaddr); + pflib::lpGBT_ConfigTransport_I2C* tport=new pflib::lpGBT_ConfigTransport_I2C(chipaddr, "/dev/i2c-23"); + t.lpgbt_i2c = new pflib::lpGBT(*tport); + } else { + chipaddr |= 0x4; + } - pflib::lpGBT_ConfigTransport_I2C tport(chipaddr, "/dev/i2c-23"); - pflib::lpGBT lpgbt_i2c(tport); - pflib::zcu::lpGBT_ICEC_Simple ic("singleLPGBT", false, chipaddr); + pflib::zcu::lpGBT_ICEC_Simple ic(target_name, false, chipaddr); pflib::lpGBT lpgbt_ic(ic); + pflib::zcu::lpGBT_ICEC_Simple ec(target_name, true, 0x78); // correct for HCAL + pflib::lpGBT lpgbt_ec(ec); tool::set_history_filepath("~/.pflpgbt-history"); - ToolBox t; - t.lpgbt_i2c = &lpgbt_i2c; t.lpgbt_ic = &lpgbt_ic; - t.lpgbt = t.lpgbt_i2c; + t.lpgbt_ec = &lpgbt_ec; + if (wired) t.lpgbt = t.lpgbt_i2c; + else t.lpgbt=t.lpgbt_ic; t.olink = &olink; /// need to make sure the voltage is at a safe level, will be done automatically here - pflib::power_ctl_mezz ctl("/dev/i2c-23"); - t.p_ctl = &ctl; + pflib::power_ctl_mezz* ctl(0); + if (!nomezz) ctl=new pflib::power_ctl_mezz("/dev/i2c-23"); + t.p_ctl = ctl; tool::run(&t); diff --git a/app/lpgbt/zcu_optolink.cc b/app/lpgbt/zcu_optolink.cc index 1b065d6a..e9f1fc12 100644 --- a/app/lpgbt/zcu_optolink.cc +++ b/app/lpgbt/zcu_optolink.cc @@ -3,7 +3,7 @@ namespace pflib { namespace zcu { -OptoLink::OptoLink() : transright_("transceiver_right"), coder_("singleLPGBT") { + OptoLink::OptoLink(const char* coder_name) : transright_("transceiver_right"), coder_(coder_name), coder_name_(coder_name) { // enable all SFPs, use internal clock transright_.write(0x2,0xF0000); @@ -37,7 +37,12 @@ void OptoLink::reset_link() { } coder_.write(0,1);// reset the DECODER - + usleep(1000); + coder_.write(65,0x40000000); //reset IC + coder_.write(67,0x40000000); //reset EC + usleep(1000); + coder_.write(65,0x00000000); //reset IC + coder_.write(67,0x00000000); //reset EC } static const uint32_t REG_POLARITY = 0x1; @@ -86,10 +91,17 @@ std::map OptoLink::opto_rates() { for (int i=0; tnames[i]!=0; i++) retval[tnames[i]]=transright_.read(TRIGHT_RATES_OFFSET+i); - const char* cnames[]={"LINK_WORD","LINK_ERROR","LINK_CLOCK","CLOCK_40",0}; - const int CRATES_OFFSET = 80; - for (int i=0; cnames[i]!=0; i++) - retval[cnames[i]]=coder_.read(CRATES_OFFSET+i); + if (coder_name_=="singleLPGBT") { + const char* cnames[]={"LINK_WORD","LINK_ERROR","LINK_CLOCK","CLOCK_40",0}; + const int CRATES_OFFSET = 80; + for (int i=0; cnames[i]!=0; i++) + retval[cnames[i]]=coder_.read(CRATES_OFFSET+i); + } else { + const char* cnames[]={"DAQ_LINK_WORD","TRIG_LINK_WORD", "DAQ_LINK_ERROR","TRIG_LINK_ERROR","DAQ_LINK_CLOCK","TRIG_LINK_CLOCK","CLOCK_40",0}; + const int CRATES_OFFSET = 80; + for (int i=0; cnames[i]!=0; i++) + retval[cnames[i]]=coder_.read(CRATES_OFFSET+i); + } @@ -107,6 +119,81 @@ std::map OptoLink::opto_rates() { coder_.write(REG_DOWNLINK_MODE0+i,mode&MASK_DOWNLINK_MODE); } + +void OptoLink::capture_ec(int mode, std::vector& tx, std::vector& rx) { + static constexpr int REG_SPY_CTL = 67; + static constexpr int REG_READ = 69; + + uint32_t val=coder_.read(REG_SPY_CTL); + val=val&0x1FF; + val=val|((mode&0x3)<<10)|(1<<9); + coder_.write(REG_SPY_CTL,val); + + // now wait for it... + bool done=false; + do { + usleep(100); + done=(coder_.read(REG_READ)&0x400)!=0; + if (mode==0) done=true; + } while (!done); + val=val&0x1FF; + val=val|((mode&0x3)<<10); // disable the spy + coder_.write(REG_SPY_CTL,val); + + tx.clear(); + rx.clear(); + + val=val&0x1FF; + val=val|((mode&0x3)<<10); + for (int i=0; i<256; i++) { + val=val&0xFFF; + val=val|(i<<12); + coder_.write(REG_SPY_CTL,val); + usleep(1); + uint32_t k=coder_.read(REG_READ); + tx.push_back((k>>(2+11))&0x3); + rx.push_back((k>>11)&0x3); + } + +} + +void OptoLink::capture_ic(int mode, std::vector& tx, std::vector& rx) { + static constexpr int REG_SPY_CTL = 65; + static constexpr int REG_READ = 68; + + uint32_t val=coder_.read(REG_SPY_CTL); + val=val&0x1FF; + val=val|((mode&0x3)<<10)|(1<<9); + coder_.write(REG_SPY_CTL,val); + + // now wait for it... + bool done=false; + do { + usleep(100); + done=(coder_.read(REG_READ)&0x400)!=0; + if (mode==0) done=true; + } while (!done); + val=val&0x1FF; + val=val|((mode&0x3)<<10); // disable the spy + coder_.write(REG_SPY_CTL,val); + + tx.clear(); + rx.clear(); + + val=val&0x1FF; + val=val|((mode&0x3)<<10); + for (int i=0; i<256; i++) { + val=val&0xFFF; + val=val|(i<<12); + coder_.write(REG_SPY_CTL,val); + usleep(1); + uint32_t k=coder_.read(REG_READ); + tx.push_back((k>>(2+11))&0x3); + rx.push_back((k>>11)&0x3); + } + +} + } } diff --git a/app/lpgbt/zcu_optolink.h b/app/lpgbt/zcu_optolink.h index 52ac01d6..f12b69bd 100644 --- a/app/lpgbt/zcu_optolink.h +++ b/app/lpgbt/zcu_optolink.h @@ -2,7 +2,7 @@ #define ZCU_OPTOLINK_INCLUDED 1 #include - +#include #include "pflib/zcu/UIO.h" namespace pflib { @@ -10,7 +10,7 @@ namespace zcu { class OptoLink { public: - OptoLink(); + OptoLink(const char* coder_name="singleLPGBT"); void reset_link(); @@ -27,9 +27,14 @@ class OptoLink { int get_elink_tx_mode(int ilink); void set_elink_tx_mode(int ilink, int mode); + void capture_ec(int mode, std::vector& tx, std::vector& rx); + void capture_ic(int mode, std::vector& tx, std::vector& rx); + + private: ::pflib::UIO transright_; ::pflib::UIO coder_; + std::string coder_name_; }; } // namespace zcu diff --git a/include/pflib/Hcal.h b/include/pflib/Hcal.h index 1d4e6986..9d611564 100644 --- a/include/pflib/Hcal.h +++ b/include/pflib/Hcal.h @@ -14,7 +14,7 @@ namespace pflib { /** - * representing a standard HCAL motherboard or a test system + * representing a standard HCAL backplane or a test system */ class Hcal { public: diff --git a/include/pflib/I2C.h b/include/pflib/I2C.h index 23f46b06..820bb51b 100644 --- a/include/pflib/I2C.h +++ b/include/pflib/I2C.h @@ -54,7 +54,7 @@ class I2C { int nread = 0) = 0; virtual std::vector general_write_read_ioctl( - int i2c_dev_addr, const std::vector& wdata, int nread = 0) = 0; + int i2c_dev_addr, const std::vector& wdata, int nread = 0) { return general_write_read(i2c_dev_addr, wdata, nread); } }; } // namespace pflib diff --git a/include/pflib/Target.h b/include/pflib/Target.h index 50ab38b4..763790b5 100644 --- a/include/pflib/Target.h +++ b/include/pflib/Target.h @@ -67,6 +67,7 @@ class Target { }; Target* makeTargetFiberless(); +Target* makeTargetHcalMB(); } // namespace pflib diff --git a/include/pflib/lpGBT.h b/include/pflib/lpGBT.h index 3c87e97f..f9bbbd33 100644 --- a/include/pflib/lpGBT.h +++ b/include/pflib/lpGBT.h @@ -54,6 +54,7 @@ class lpGBT { void write(uint16_t reg, uint8_t value) { tport_.write_reg(reg, value); } uint8_t read(uint16_t reg) { return tport_.read_reg(reg); } + std::vector read(uint16_t reg, int len) { return tport_.read_regs(reg,len); } typedef std::pair RegisterValue; typedef std::vector RegisterValueVector; @@ -157,8 +158,40 @@ class lpGBT { uint32_t read_efuse(uint16_t addr); + + /** Setup an I2C bus + \param ibus Which I2C bus (0-2) + \param speed_khz I2C speed (appropriate values are 100, 200, 400, 1000) + \param scl_drive Enable CMOS driver on SCL + \param strong_scl Enable higher-strength driver on SCL + \param strong_sda Enable higher-strength driver on SDA + \param pull_up_scl Enable internal pullup on SCL + \param pull_up_sda Enable internal pullup on SDA + */ + void setup_i2c(int ibus, int speed_khz, bool scl_drive=false, bool strong_scl=true, bool strong_sda=true, bool pull_up_scl=false, bool pull_up_sda=false); + + /** Start an I2C read */ + void start_i2c_read(int ibus, uint8_t i2c_addr, int len=1); + + /** Start an I2C write of a single byte */ + void i2c_write(int ibus, uint8_t i2c_addr, uint8_t value); + + /** Start an I2C write of multiple bytes */ + void i2c_write(int ibus, uint8_t i2c_addr, const std::vector& values); + + /** Check for transaction completion optionally waiting for completion, throws exception on failure */ + bool i2c_transaction_check(int ibus, bool wait=false); + + /** Get back the data from the read */ + std::vector i2c_read_data(int ibus); + private: lpGBT_ConfigTransport& tport_; + struct I2C { + uint8_t ctl_reg; + uint8_t read_len; + } i2c_[3]; + }; } // namespace pflib diff --git a/include/pflib/lpgbt/lpGBT_standard_configs.h b/include/pflib/lpgbt/lpGBT_standard_configs.h new file mode 100644 index 00000000..b468050f --- /dev/null +++ b/include/pflib/lpgbt/lpGBT_standard_configs.h @@ -0,0 +1,21 @@ +#ifndef lpgbt_standard_configs_h_included +#define lpgbt_standard_configs_h_included 1 + +#include "pflib/lpGBT.h" + +namespace pflib { + namespace lpgbt { + namespace standard_config { + + /** Setup the standard set of I/Os for the HCAL backplane DAQ lpGBT */ + void setup_hcal_daq(pflib::lpGBT&); + + /** Setup the standard set of I/Os for the HCAL backplane TRIG lpGBT */ + void setup_hcal_trig(pflib::lpGBT&); + + } + } +} + + +#endif // lpgbt_standard_configs_h_included diff --git a/include/pflib/zcu/lpGBT_ICEC_ZCU_Simple.h b/include/pflib/zcu/lpGBT_ICEC_ZCU_Simple.h index 628c503a..4d46ce72 100644 --- a/include/pflib/zcu/lpGBT_ICEC_ZCU_Simple.h +++ b/include/pflib/zcu/lpGBT_ICEC_ZCU_Simple.h @@ -26,6 +26,7 @@ class lpGBT_ICEC_Simple : public lpGBT_ConfigTransport { private: /// Offset depending on EC/IC int offset_; + int offset_status_; /// i2c address of the device uint8_t lpgbt_i2c_addr_; /// UIO block diff --git a/src/pflib/lpGBT.cxx b/src/pflib/lpGBT.cxx index c3893ae2..944451d2 100644 --- a/src/pflib/lpGBT.cxx +++ b/src/pflib/lpGBT.cxx @@ -123,6 +123,16 @@ static constexpr uint16_t REG_EPRX00CHNCNTR = 0x0d0; static constexpr uint16_t REG_ECLK_BASE = 0x06e; static constexpr uint16_t REG_POWERUP_STATUS = 0x1d9; +static constexpr uint16_t REG_I2CM0CONFIG = 0x100; +static constexpr uint16_t REG_I2CM0ADDRESS = 0x101; +static constexpr uint16_t REG_I2CM0DATA0 = 0x102; +static constexpr uint16_t REG_I2CM0CMD = 0x106; +static constexpr uint16_t REG_I2CM0STATUS = 0x171; +static constexpr uint16_t REG_I2CM0READBYTE = 0x173; +static constexpr uint16_t REG_I2CM0READ0 = 0x174; +static constexpr uint16_t REG_I2C_WSTRIDE = 7; +static constexpr uint16_t REG_I2C_RSTRIDE = 21; + static constexpr uint16_t REG_FUSECONTROL = 0x119; static constexpr uint16_t REG_FUSEADDRH = 0x11E; static constexpr uint16_t REG_FUSEADDRL = 0x11F; @@ -433,6 +443,114 @@ void lpGBT::setup_eclk(int ieclk, int rate, bool polarity, int strength) { // currently no ability to mess with pre-emphasis } + void lpGBT::setup_i2c(int ibus, int speed_khz, bool scl_drive, bool strong_scl, bool strong_sda, bool pull_up_scl, bool pull_up_sda) { + if (ibus<0 || ibus>2) return; + + uint8_t val; + val=0; + if (pull_up_scl) val|=0x40; + if (pull_up_sda) val|=0x10; + if (strong_scl) val|=0x20; + if (strong_sda) val|=0x08; + write(REG_I2CM0CONFIG+ibus*7,val); + + i2c_[ibus].ctl_reg=0; + if (scl_drive) i2c_[ibus].ctl_reg|=0x80; + if (speed_khz>125 && speed_khz<300) i2c_[ibus].ctl_reg|=0x01; + if (speed_khz>300 && speed_khz<500) i2c_[ibus].ctl_reg|=0x02; + if (speed_khz>500 && speed_khz<2000) i2c_[ibus].ctl_reg|=0x03; + + } + +static constexpr uint8_t CMD_I2C_WRITE_CR = 0; +static constexpr uint8_t CMD_I2C_1BYTE_WRITE = 2; +static constexpr uint8_t CMD_I2C_1BYTE_READ = 3; +static constexpr uint8_t CMD_I2C_W_MULTI_4BYTE0 = 8; +static constexpr uint8_t CMD_I2C_W_MULTI_4BYTE1 = 9; +static constexpr uint8_t CMD_I2C_W_MULTI_4BYTE2 = 10; +static constexpr uint8_t CMD_I2C_W_MULTI_4BYTE3 = 11; +static constexpr uint8_t CMD_I2C_WRITE_MULTI = 0xC; +static constexpr uint8_t CMD_I2C_READ_MULTI = 0xD; + + void lpGBT::start_i2c_read(int ibus, uint8_t i2c_addr, int len) { + if (ibus<0 || ibus>2 || len<0 || len>16) return; + i2c_[ibus].read_len=len; + write(REG_I2CM0ADDRESS+ibus*REG_I2C_WSTRIDE,i2c_addr); + if (len==1) { + write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,i2c_[ibus].ctl_reg); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_WRITE_CR); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_1BYTE_READ); + } else { + write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,i2c_[ibus].ctl_reg|(len<<2)); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_WRITE_CR); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_READ_MULTI); + } + } + + void lpGBT::i2c_write(int ibus, uint8_t i2c_addr, uint8_t value) { + if (ibus<0 || ibus>2) return; + write(REG_I2CM0ADDRESS+ibus*REG_I2C_WSTRIDE,i2c_addr); + write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,i2c_[ibus].ctl_reg); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_WRITE_CR); + write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,value); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_1BYTE_WRITE); + } + + void lpGBT::i2c_write(int ibus, uint8_t i2c_addr, const std::vector& values) { + if (ibus<0 || ibus>2 || values.size()>16) return; + write(REG_I2CM0ADDRESS+ibus*REG_I2C_WSTRIDE,i2c_addr); + write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,i2c_[ibus].ctl_reg|(values.size()<<2)); + write(REG_I2CM0CMD+ibus*REG_I2C_WSTRIDE,CMD_I2C_WRITE_CR); + // copying all the data into the core... + for (size_t i=0; i2) return false; + do { + uint8_t val=read(REG_I2CM0STATUS+ibus*REG_I2C_RSTRIDE); + if (val&NOCLK) { + PFEXCEPTION_RAISE("I2CErrorNoCLK", "No clock on I2C controller"); + } + if (val&NOACK) { + PFEXCEPTION_RAISE("I2CErrorNoACK", "No acknowledge from I2C target"); + } + if (val&LEVELE) { + PFEXCEPTION_RAISE("I2CErrorSDALow", "SDA Line Low on Start"); + } + if (val&SUCCESS) { + return true; + } + usleep(100); // + } while (wait); + return false; + } + + std::vector lpGBT::i2c_read_data(int ibus) { + std::vector retval; + if (ibus<0 || ibus>2) return retval; + if (i2c_[ibus].read_len==1) { + retval.push_back(read(REG_I2CM0READBYTE+ibus*REG_I2C_RSTRIDE)); + } else { + return read(REG_I2CM0READBYTE+ibus*REG_I2C_RSTRIDE,i2c_[ibus].read_len); + } + return retval; + } + + int lpGBT::status() { return read(REG_POWERUP_STATUS); } std::string lpGBT::status_name(int pusm) { static const char* states[] = {"ARESET", diff --git a/src/pflib/lpgbt/lpGBT_standard_configs.cxx b/src/pflib/lpgbt/lpGBT_standard_configs.cxx new file mode 100644 index 00000000..cc9ca79c --- /dev/null +++ b/src/pflib/lpgbt/lpGBT_standard_configs.cxx @@ -0,0 +1,48 @@ +#include "pflib/lpgbt/lpGBT_standard_configs.h" + +namespace pflib { + namespace lpgbt { + namespace standard_config { + + void setup_hcal_daq(pflib::lpGBT& lpgbt) { + + // setup the reset lines + lpgbt.gpio_cfg_set(0,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC2_HRST + lpgbt.gpio_set(0,true); + lpgbt.gpio_cfg_set(1,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC2_SRST + lpgbt.gpio_set(1,true); + lpgbt.gpio_cfg_set(2,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC1_HRST + lpgbt.gpio_set(2,true); + lpgbt.gpio_cfg_set(4,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC1_SRST + lpgbt.gpio_set(4,true); + lpgbt.gpio_cfg_set(8,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC_I2C_RST + lpgbt.gpio_set(8,true); + lpgbt.gpio_cfg_set(11,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // D2T_RSTB + lpgbt.gpio_set(11,true); + + // setup clocks + lpgbt.setup_eclk(0,320); // HGCROC3_CLK320 + lpgbt.setup_eclk(1,320); // HGCROC0_CLK320 + lpgbt.setup_eclk(2,320); // HGCROC2_CLK320 + lpgbt.setup_eclk(3,320); // HGCROC1_CLK320 + lpgbt.setup_eclk(4,320); // ECON-T0_CLK320 + lpgbt.setup_eclk(6,320); // ECON-T1_CLK320 + lpgbt.setup_eclk(5,320); // ECON-D_CLK320 + lpgbt.setup_eclk(7,40); // REFCLK_TO_TRIG + + // setup fast commands + lpgbt.setup_etx(0,true); // HGCROC2_FCMD + lpgbt.setup_etx(1,true); // HGCROC0_FCMD + lpgbt.setup_etx(2,true); // HGCROC3_FCMD + lpgbt.setup_etx(3,true); // ECON-T0_FCMF + lpgbt.setup_etx(4,true); // ECON-D_FCMD + lpgbt.setup_etx(5,true); // ECON-T1_FCMD + lpgbt.setup_etx(6,true); // HGCROC1_FCMD + + // setup the EC link + lpgbt.setup_ec(false,4,false,0,false,true,false,true); + } + + } + } +} diff --git a/src/pflib/zcu/UIO.cxx b/src/pflib/zcu/UIO.cxx index 3786f89f..9e0292d1 100644 --- a/src/pflib/zcu/UIO.cxx +++ b/src/pflib/zcu/UIO.cxx @@ -13,17 +13,54 @@ namespace pflib { UIO::UIO(const std::string& name, size_t length) : size_{length}, ptr_{0}, handle_{0} { + /** first, look for the DTSI map */ + FILE* fdtsi=fopen("/opt/ldmx-firmware/active/device-tree/pl-full.dtsi","r"); + uint32_t baseaddr=0; + if (fdtsi!=0) { + char buf[1024], *where; + uint32_t abaseaddr=0; + while (!feof(fdtsi)) { + buf[0]=0; + fgets(buf,1024,fdtsi); + + if ((where=strstr(buf,"@"))!=0) { + abaseaddr=strtoul(where+1,0,16); + } else if ((where=strstr(buf,"instance_id = "))!=0) { + std::string iname=strstr(where,"\"")+1; + iname.erase(iname.find('"')); + if (iname==name) { + baseaddr=abaseaddr; + break; + } + // printf("%08x %s\n",baseaddr,iname.c_str()); + } + } + fclose(fdtsi); + } for (int i = 0; i < 100; i++) { char namefile[200], buffer[100]; - snprintf(namefile, 200, "/sys/class/uio/uio%d/maps/map0/name", i); + if (baseaddr!=0) { + snprintf(namefile, 200, "/sys/class/uio/uio%d/maps/map0/addr", i); + } else { + snprintf(namefile, 200, "/sys/class/uio/uio%d/maps/map0/name", i); + } FILE* f = fopen(namefile, "r"); if (!f) continue; fgets(buffer, 100, f); fclose(f); + if (baseaddr!=0) { + if (strtoul(buffer,0,0)==baseaddr) { + snprintf(namefile, 200, "/dev/uio%d", i); + iopen(namefile, length); + break; + } + } else { // does it start with the same string? - if (strstr(buffer, name.c_str()) == buffer) { - snprintf(namefile, 200, "/dev/uio%d", i); - iopen(namefile, length); + if (strstr(buffer, name.c_str()) == buffer) { + snprintf(namefile, 200, "/dev/uio%d", i); + iopen(namefile, length); + break; + } } } if (ptr_ == 0) { diff --git a/src/pflib/zcu/lpGBT_ICEC_ZCU_Simple.cxx b/src/pflib/zcu/lpGBT_ICEC_ZCU_Simple.cxx index 5cfb4608..bcc65f87 100644 --- a/src/pflib/zcu/lpGBT_ICEC_ZCU_Simple.cxx +++ b/src/pflib/zcu/lpGBT_ICEC_ZCU_Simple.cxx @@ -28,6 +28,7 @@ static const uint32_t MASK_TX_EMPTY = 0x00000200; lpGBT_ICEC_Simple::lpGBT_ICEC_Simple(const std::string& target, bool isEC, uint8_t lpgbt_i2c_addr) : offset_{isEC ? (OFFSET_EC) : (OFFSET_IC)}, + offset_status_{isEC ? (OFFSET_EC-1) : (OFFSET_IC)}, lpgbt_i2c_addr_{lpgbt_i2c_addr}, transport_(target) { int reg = REG_CTL_RESET_N_READ + offset_; @@ -61,12 +62,14 @@ std::vector lpGBT_ICEC_Simple::read_regs(uint16_t reg, int n) { transport_.write(offset_ + REG_CTL_RESET_N_READ, val); // wait for done... int timeout = 1000; - for (val = transport_.read(offset_ + REG_STATUS_READ); (val & MASK_RX_EMPTY); - val = transport_.read(offset_ + REG_STATUS_READ)) { + for (val = transport_.read(offset_status_ + REG_STATUS_READ); (val & MASK_RX_EMPTY); + val = transport_.read(offset_status_ + REG_STATUS_READ)) { usleep(1); timeout--; if (timeout == 0) { - PFEXCEPTION_RAISE("ICEC_Timeout", "Read register timeout"); + char message[256]; + snprintf(message,256,"Read register 0x%x timeout",reg); + PFEXCEPTION_RAISE("ICEC_Timeout", message); } } wc = 0; @@ -77,8 +80,8 @@ std::vector lpGBT_ICEC_Simple::read_regs(uint16_t reg, int n) { if (wc >= 6 && int(retval.size()) < n) retval.push_back(abyte); wc++; // this seems to be sometimes too fast... - transport_.read(offset_ + REG_STATUS_READ); - val = transport_.read(offset_ + REG_STATUS_READ); + transport_.read(offset_status_ + REG_STATUS_READ); + val = transport_.read(offset_status_ + REG_STATUS_READ); } return retval; @@ -86,6 +89,7 @@ std::vector lpGBT_ICEC_Simple::read_regs(uint16_t reg, int n) { void lpGBT_ICEC_Simple::write_reg(uint16_t reg, uint8_t value) { std::vector vv(1, value); + // printf("%x %x %x\n",reg, value, lpgbt_i2c_addr_); write_regs(reg, vv); } @@ -107,13 +111,16 @@ void lpGBT_ICEC_Simple::write_regs(uint16_t reg, transport_.write(offset_ + REG_CTL_RESET_N_READ, MASK_START_WRITE); // wait for tx to be done int timeout = 1000; - for (uint32_t val = transport_.read(offset_ + REG_STATUS_READ); - (val & MASK_TX_EMPTY); - val = transport_.read(offset_ + REG_STATUS_READ)) { + for (uint32_t val = transport_.read(offset_status_ + REG_STATUS_READ); + !(val & MASK_TX_EMPTY); + val = transport_.read(offset_status_ + REG_STATUS_READ)) { + // printf("%02x\n",val); usleep(1); timeout--; if (timeout == 0) { - PFEXCEPTION_RAISE("ICEC_Timeout", "Write register timeout"); + char message[256]; + snprintf(message,256,"Write register 0x%x (+%d) timeout (%x)",reg,ic,lpgbt_i2c_addr_); + PFEXCEPTION_RAISE("ICEC_Timeout", message); } } ic = 0; From 20af6b55c32763490010da9b751b28617547b6e8 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 02:33:49 +0000 Subject: [PATCH 04/36] Move optolink into main library --- {app/lpgbt => include/pflib/zcu}/zcu_optolink.h | 1 - app/lpgbt/zcu_optolink.cc => src/pflib/zcu/zcu_optolink.cxx | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) rename {app/lpgbt => include/pflib/zcu}/zcu_optolink.h (99%) rename app/lpgbt/zcu_optolink.cc => src/pflib/zcu/zcu_optolink.cxx (99%) diff --git a/app/lpgbt/zcu_optolink.h b/include/pflib/zcu/zcu_optolink.h similarity index 99% rename from app/lpgbt/zcu_optolink.h rename to include/pflib/zcu/zcu_optolink.h index f12b69bd..0de82a67 100644 --- a/app/lpgbt/zcu_optolink.h +++ b/include/pflib/zcu/zcu_optolink.h @@ -29,7 +29,6 @@ class OptoLink { void capture_ec(int mode, std::vector& tx, std::vector& rx); void capture_ic(int mode, std::vector& tx, std::vector& rx); - private: ::pflib::UIO transright_; diff --git a/app/lpgbt/zcu_optolink.cc b/src/pflib/zcu/zcu_optolink.cxx similarity index 99% rename from app/lpgbt/zcu_optolink.cc rename to src/pflib/zcu/zcu_optolink.cxx index e9f1fc12..d887404e 100644 --- a/app/lpgbt/zcu_optolink.cc +++ b/src/pflib/zcu/zcu_optolink.cxx @@ -1,4 +1,4 @@ -#include "zcu_optolink.h" +#include "pflib/zcu/zcu_optolink.h" namespace pflib { namespace zcu { From aa3aa98c849f665cfbd049c1452486d0819aa48e Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:54:24 +0000 Subject: [PATCH 05/36] Adjust GPIO class to focus on names, not numbers --- include/pflib/GPIO.h | 46 +++++----------- src/pflib/GPIO.cxx | 36 ++++++------- src/pflib/GPIO_HcalHGCROCZCU.cxx | 91 +++++++++++++++----------------- 3 files changed, 72 insertions(+), 101 deletions(-) diff --git a/include/pflib/GPIO.h b/include/pflib/GPIO.h index 18a0407a..2a4971d9 100644 --- a/include/pflib/GPIO.h +++ b/include/pflib/GPIO.h @@ -11,58 +11,40 @@ namespace pflib { */ class GPIO { protected: - GPIO(int gpo, int gpi) : ngpo_{gpo}, ngpi_{gpi} {} + GPIO() {} public: /** - * Get the number of GPO bits + * Get the set of GPO pin names */ - int getGPOcount() { return ngpo_; } + virtual std::vector getGPOs() = 0; /** - * Get the number of GPI bits + * Get the set of GPI pin names */ - int getGPIcount() { return ngpi_; } + virtual std::vector getGPIs() = 0; - /** Get the name of a bit if possible */ - virtual std::string getBitName(int ibit, bool isgpo = true) { return ""; } + /** Check if a given GPO exists */ + virtual bool hasGPO(const std::string& name); + + /** Check if a given GPI exists */ + virtual bool hasGPI(const std::string& name); /** * Read a GPI bit */ - virtual bool getGPI(int ibit); + virtual bool getGPI(const std::string& name) = 0; /** - * Read all GPI bits + * Get current value of GPO bit */ - virtual std::vector getGPI() = 0; + virtual bool getGPO(const std::string& name) = 0; /** * Set a single GPO bit */ - virtual void setGPO(int ibit, bool toTrue = true); - - /** - * Set all GPO bits - */ - virtual void setGPO(const std::vector& bits) = 0; - - /** - * Read all GPO bits - */ - virtual std::vector getGPO() = 0; - - /// convenience wrapper for python bindings - bool getGPI_single(int ibit) { return getGPI(ibit); } - std::vector getGPI_all() { return getGPI(); } - void setGPO_single(int ibit, bool t) { return setGPO(ibit, t); } - void setGPO_all(const std::vector& b) { return setGPO(b); } + virtual void setGPO(const std::string& name, bool toTrue = true) = 0; - private: - /** - * Cached numbers of GPI and GPO bits - */ - int ngpi_, ngpo_; }; GPIO* make_GPIO_HcalHGCROCZCU(); diff --git a/src/pflib/GPIO.cxx b/src/pflib/GPIO.cxx index 72d3ff1e..db1ee0ea 100644 --- a/src/pflib/GPIO.cxx +++ b/src/pflib/GPIO.cxx @@ -2,32 +2,28 @@ #include + + #include "pflib/Exception.h" namespace pflib { -bool GPIO::getGPI(int ibit) { - if (ibit >= ngpi_) { - char message[120]; - snprintf(message, 120, "GPI bit %d is out of range with maxGPI %d", ibit, - ngpi_); - PFEXCEPTION_RAISE("GPIOError", message); + bool GPIO::hasGPO(const std::string& name) { + std::vector names=getGPOs(); + for (auto i : names) { + if (i==name) return true; + } + return false; } - std::vector bits = getGPI(); - return bits[ibit]; -} - -void GPIO::setGPO(int ibit, bool toTrue) { - if (ibit >= ngpo_) { - char message[120]; - snprintf(message, 120, "GPO bit %d is out of range with maxGPO=%d", ibit, - ngpo_); - PFEXCEPTION_RAISE("GPIOError", message); + bool GPIO::hasGPI(const std::string& name) { + std::vector names=getGPIs(); + for (auto i : names) { + if (i==name) return true; + } + return false; } - std::vector bits = getGPO(); - bits[ibit] = toTrue; - setGPO(bits); -} + + } // namespace pflib diff --git a/src/pflib/GPIO_HcalHGCROCZCU.cxx b/src/pflib/GPIO_HcalHGCROCZCU.cxx index 989cadbd..8499ed95 100644 --- a/src/pflib/GPIO_HcalHGCROCZCU.cxx +++ b/src/pflib/GPIO_HcalHGCROCZCU.cxx @@ -5,17 +5,21 @@ #include #include #include - +#include #include #include "pflib/Exception.h" #include "pflib/GPIO.h" +#include "pflib/utility/string_format.h" namespace pflib { class GPIO_HcalHGCROCZCU : public GPIO { public: - GPIO_HcalHGCROCZCU() : GPIO(8, 1) { + static constexpr int N_GPO = 8; + static constexpr int N_GPI = 1; + + GPIO_HcalHGCROCZCU() : GPIO() { gpiodev_ = open("/dev/gpiochip4", O_RDWR); if (gpiodev_ < 0) { char msg[100]; @@ -28,26 +32,31 @@ class GPIO_HcalHGCROCZCU : public GPIO { if (gpiodev_ > 0) close(gpiodev_); } - virtual std::vector getGPI(); - + virtual std::vector getGPOs() { + std::vector retval; + for (auto i: gpos_) + retval.push_back(i.first); + return retval; + } + virtual std::vector getGPIs() { + std::vector retval; + for (auto i: gpis_) + retval.push_back(i.first); + return retval; + } + + virtual bool getGPI(const std::string& name); + virtual bool getGPO(const std::string& name); static constexpr const char* gpo_names[] = { "HGCROC_RSTB_I2C", "HGCROC_SOFT_RSTB", "HGCROC_HARD_RSTB", "UNUSED1", "HGCROC_ADDR0", "HGCROC_ADDR1", "SCL_PHASE", "POWER_OFF"}; - virtual std::string getBitName(int ibit, bool isgpo) { - if (isgpo) - return gpo_names[ibit]; - else - return "HGCROC_ERROR"; - } - - virtual void setGPO(int ibit, bool toTrue = true); - virtual void setGPO(const std::vector& bits); - - virtual std::vector getGPO(); + virtual void setGPO(const std::string& name, bool toTrue = true); private: void setup(); + std::map gpos_; + std::map gpis_; int gpiodev_; int fd_gpo_; @@ -62,11 +71,12 @@ void GPIO_HcalHGCROCZCU::setup() { memset(&req, 0, sizeof(req)); // gpo request - for (int i = 0; i < getGPOcount(); i++) { + for (int i = 0; i < N_GPO; i++) { req.offsets[i] = i; + gpos_[gpo_names[i]]=i; } strncpy(req.consumer, myname, GPIO_MAX_NAME_SIZE); - req.num_lines = getGPOcount(); + req.num_lines = N_GPO; req.config.flags = GPIO_V2_LINE_FLAG_OUTPUT; req.config.num_attrs = 1; @@ -81,12 +91,16 @@ void GPIO_HcalHGCROCZCU::setup() { PFEXCEPTION_RAISE("DeviceFileAccessError", msg); } fd_gpo_ = req.fd; + } -void GPIO_HcalHGCROCZCU::setGPO(int ibit, bool toTrue) { - if (ibit < 0 || ibit >= getGPOcount()) { - PFEXCEPTION_RAISE("GPIOError", "Requested bit out of range"); +void GPIO_HcalHGCROCZCU::setGPO(const std::string& name, bool toTrue) { + auto ptr=gpos_.find(name); + if (ptr==gpos_.end()) { + PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); } + int ibit=ptr->second; + gpio_v2_line_values req; memset(&req, 0, sizeof(req)); req.mask = 1 << ibit; @@ -103,29 +117,14 @@ void GPIO_HcalHGCROCZCU::setGPO(int ibit, bool toTrue) { } } -void GPIO_HcalHGCROCZCU::setGPO(const std::vector& bits) { - if (int(bits.size()) != getGPOcount()) { - PFEXCEPTION_RAISE("GPIOError", "Requested bits out of range"); - } - - gpio_v2_line_values req; - memset(&req, 0, sizeof(req)); - req.mask = 0xFF; - req.bits = 0; - - for (int i = 0; i < getGPOcount(); i++) - if (bits[i]) req.bits |= (1 << i); - - if (ioctl(fd_gpo_, GPIO_V2_LINE_SET_VALUES_IOCTL, &req)) { - char msg[100]; - snprintf(msg, 100, "Error in writing GPOs : %d", errno); - PFEXCEPTION_RAISE("DeviceFileAccessError", msg); +bool GPIO_HcalHGCROCZCU::getGPO(const std::string& name) { + auto ptr=gpos_.find(name); + if (ptr==gpos_.end()) { + PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); } -} + int ibit=ptr->second; -std::vector GPIO_HcalHGCROCZCU::getGPO() { // GPOs are lines 0-7 - std::vector retval(getGPOcount(), false); gpio_v2_line_values req; memset(&req, 0, sizeof(req)); req.mask = 0xFF; @@ -135,14 +134,10 @@ std::vector GPIO_HcalHGCROCZCU::getGPO() { PFEXCEPTION_RAISE("DeviceFileAccessError", msg); } - for (int i = 0; i < getGPOcount(); i++) { - bool bval = (req.bits & (1 << i)) != 0; - retval[i] = bval; - } - return retval; + return (req.bits&(1< GPIO_HcalHGCROCZCU::getGPI() { +bool GPIO_HcalHGCROCZCU::getGPI(const std::string& name) { // GPIs are lines 8 std::vector retval; gpio_v2_line_values req; @@ -154,9 +149,7 @@ std::vector GPIO_HcalHGCROCZCU::getGPI() { PFEXCEPTION_RAISE("DeviceFileAccessError", msg); } - for (int i = 0; i < getGPIcount(); i++) - retval.push_back((req.bits & (1 << (i + getGPOcount()))) != 0); - return retval; + return (req.bits&0x800)!=0; } GPIO* make_GPIO_HcalHGCROCZCU() { return new GPIO_HcalHGCROCZCU(); } From 99c389a76158f67a438edad069d6035e723aafd4 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:55:11 +0000 Subject: [PATCH 06/36] Adjust to prepare for lpGBT-based Target --- include/pflib/Hcal.h | 17 +++++++++--- include/pflib/Target.h | 4 +-- src/pflib/Hcal.cxx | 31 +++++++++++++++------- src/pflib/TargetFiberless.cxx | 50 +++++++++++++++++------------------ 4 files changed, 60 insertions(+), 42 deletions(-) diff --git a/include/pflib/Hcal.h b/include/pflib/Hcal.h index 9d611564..8b7ac729 100644 --- a/include/pflib/Hcal.h +++ b/include/pflib/Hcal.h @@ -18,12 +18,14 @@ namespace pflib { */ class Hcal { public: - Hcal(const std::vector>& roc_i2c, - const std::vector>& bias_i2c); + Hcal(); /** number of boards */ int nrocs() { return nhgcroc_; } + /** do we have a roc with this id? */ + bool have_roc(int iroc) { return i2c_for_rocbd_.find(iroc)!=i2c_for_rocbd_.end(); } + /** Get a ROC interface for the given HGCROC board */ ROC roc(int which, const std::string& roc_type_version = "sipm_rocv3b"); @@ -52,6 +54,9 @@ class Hcal { virtual DAQ& daq() = 0; protected: + /** Add a ROC to the set of ROCs */ + void add_roc(int iroc, std::shared_ptr& roc_i2C, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c); + /** Number of HGCROC boards in this system */ int nhgcroc_; @@ -59,8 +64,12 @@ class Hcal { std::unique_ptr gpio_; /** The ROC I2C interfaces */ - std::vector> roc_i2c_; - std::vector> bias_i2c_; + struct I2C_per_ROC { + std::shared_ptr roc_i2c_; + std::shared_ptr bias_i2c_; + std::shared_ptr board_i2c_; + }; + std::map i2c_for_rocbd_; }; } // namespace pflib diff --git a/include/pflib/Target.h b/include/pflib/Target.h index 763790b5..49dbadaf 100644 --- a/include/pflib/Target.h +++ b/include/pflib/Target.h @@ -66,8 +66,8 @@ class Target { mutable logging::logger the_log_{logging::get("Target")}; }; -Target* makeTargetFiberless(); -Target* makeTargetHcalMB(); + Target* makeTargetFiberless(); + Target* makeTargetHcalBackplaneZCU(int ilink, uint8_t board_mask); } // namespace pflib diff --git a/src/pflib/Hcal.cxx b/src/pflib/Hcal.cxx index f3c56a34..387332ce 100644 --- a/src/pflib/Hcal.cxx +++ b/src/pflib/Hcal.cxx @@ -1,26 +1,37 @@ #include "pflib/Hcal.h" +#include "pflib/utility/string_format.h" namespace pflib { -Hcal::Hcal(const std::vector>& roc_i2c, - const std::vector>& bias_i2c) - : roc_i2c_{roc_i2c}, bias_i2c_{bias_i2c} { - nhgcroc_ = int(roc_i2c.size()); + Hcal::Hcal() { + nhgcroc_ = 0; + } + + void Hcal::add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c) { + if (have_roc(iroc)) { + PFEXCEPTION_RAISE("DuplicateROC",pflib::utility::string_format("Already have registered ROC with id %d",iroc)); + } + nhgcroc_++; + I2C_per_ROC handles; + handles.roc_i2c_=roc_i2c; + handles.bias_i2c_=bias_i2c; + handles.board_i2c_=board_i2c; + i2c_for_rocbd_[iroc]=handles; } ROC Hcal::roc(int which, const std::string& roc_type_version) { - if (which < 0 || which >= nhgcroc_) { - PFEXCEPTION_RAISE("InvalidROCid", "Requested out-of-range ROC id"); + if (!have_roc(which)) { + PFEXCEPTION_RAISE("InvalidROCid", pflib::utility::string_format("Unknown ROC id %d",which)); } - return ROC(*roc_i2c_[which], 0x20 | (which * 8), roc_type_version); + return ROC((*i2c_for_rocbd_[which].roc_i2c_), 0x20 | (which * 8), roc_type_version); } Bias Hcal::bias(int which) { - if (which < 0 || which >= nhgcroc_) { - PFEXCEPTION_RAISE("InvalidBoardId", "Requested out-of-range Board id"); + if (!have_roc(which)) { + PFEXCEPTION_RAISE("InvalidBoardId", pflib::utility::string_format("Unknown board id %d",which)); } - return Bias(bias_i2c_.at(which)); + return Bias((i2c_for_rocbd_[which].bias_i2c_)); } void Hcal::hardResetROCs() {} diff --git a/src/pflib/TargetFiberless.cxx b/src/pflib/TargetFiberless.cxx index 5cdb09c7..3fa18f0f 100644 --- a/src/pflib/TargetFiberless.cxx +++ b/src/pflib/TargetFiberless.cxx @@ -12,13 +12,22 @@ namespace pflib { class HcalFiberless : public Hcal { public: - static const int GPO_HGCROC_RESET_HARD = 2; - static const int GPO_HGCROC_RESET_SOFT = 1; - static const int GPO_HGCROC_RESET_I2C = 0; + static constexpr const char* GPO_HGCROC_RESET_HARD = "HGCROC_HARD_RSTB"; + static constexpr const char* GPO_HGCROC_RESET_SOFT = "HGCROC_SOFT_RSTB"; + static constexpr const char* GPO_HGCROC_RESET_I2C = "HGCROC_RSTB_I2C"; + + HcalFiberless() : Hcal() { + + i2croc_ = std::shared_ptr(new I2C_Linux("/dev/i2c-24")); + if (i2croc_ < 0) { + PFEXCEPTION_RAISE("I2CError", "Could not open ROC I2C bus"); + } + i2cboard_ = std::shared_ptr(new I2C_Linux("/dev/i2c-23")); + if (i2cboard_ < 0) { + PFEXCEPTION_RAISE("I2CError", "Could not open bias I2C bus"); + } + add_roc(0,i2croc_,i2cboard_,i2cboard_); - HcalFiberless(const std::vector>& roc_i2c, - const std::vector>& bias_i2c) - : Hcal(roc_i2c, bias_i2c) { gpio_.reset(make_GPIO_HcalHGCROCZCU()); // should already be done, but be SURE @@ -47,7 +56,9 @@ class HcalFiberless : public Hcal { virtual Elinks& elinks() { return *elinks_; } virtual DAQ& daq() { return *daq_; } - private: + public: + std::shared_ptr i2croc_; + std::shared_ptr i2cboard_; Elinks* elinks_; DAQ* daq_; }; @@ -55,26 +66,15 @@ class HcalFiberless : public Hcal { class TargetFiberless : public Target { public: TargetFiberless() : Target() { - i2croc_ = std::shared_ptr(new I2C_Linux("/dev/i2c-24")); - if (i2croc_ < 0) { - PFEXCEPTION_RAISE("I2CError", "Could not open ROC I2C bus"); - } - i2cboard_ = std::shared_ptr(new I2C_Linux("/dev/i2c-23")); - if (i2cboard_ < 0) { - PFEXCEPTION_RAISE("I2CError", "Could not open bias I2C bus"); - } - i2c_["HGCROC"] = i2croc_; - i2c_["BOARD"] = i2cboard_; - i2c_["BIAS"] = i2cboard_; + HcalFiberless* p_hcal=new HcalFiberless(); - std::vector> roc_i2cs; - roc_i2cs.push_back(i2croc_); + i2c_["HGCROC"] = p_hcal->i2croc_; + i2c_["BOARD"] = p_hcal->i2cboard_; + i2c_["BIAS"] = p_hcal->i2cboard_; - std::vector> bias_i2cs; - bias_i2cs.push_back(i2cboard_); - - hcal_ = std::shared_ptr(new HcalFiberless(roc_i2cs, bias_i2cs)); + + hcal_ = std::shared_ptr(p_hcal); fc_ = std::shared_ptr(make_FastControlCMS_MMap()); } @@ -82,8 +82,6 @@ class TargetFiberless : public Target { virtual std::vector read_event(); private: - std::shared_ptr i2croc_; - std::shared_ptr i2cboard_; int run_; DaqFormat daqformat_; From 5b138b90457da465858eb8bdf30590efe33b9785 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:55:54 +0000 Subject: [PATCH 07/36] Change design to share mappings where possible --- include/pflib/zcu/UIO.h | 2 ++ src/pflib/zcu/UIO.cxx | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/include/pflib/zcu/UIO.h b/include/pflib/zcu/UIO.h index 1bc69cb2..0869b89f 100644 --- a/include/pflib/zcu/UIO.h +++ b/include/pflib/zcu/UIO.h @@ -51,9 +51,11 @@ class UIO { if ((mask & (1 << i)) != 0) return i; return 32; } + std::string name_; size_t size_; uint32_t* ptr_; int handle_; + }; } // namespace pflib #endif diff --git a/src/pflib/zcu/UIO.cxx b/src/pflib/zcu/UIO.cxx index 9e0292d1..b8e40644 100644 --- a/src/pflib/zcu/UIO.cxx +++ b/src/pflib/zcu/UIO.cxx @@ -6,13 +6,31 @@ #include #include #include - +#include #include "pflib/Exception.h" namespace pflib { + struct Mapping { + uint32_t* ptr{0}; + int users{0}; + int handle{0}; + }; + + /// SHOULD REALLY BE PROTECTED BY MUTEX + std::map gl_mappings; + UIO::UIO(const std::string& name, size_t length) - : size_{length}, ptr_{0}, handle_{0} { + : name_{name},size_{length}, ptr_{0}, handle_{0} { + + auto gptr=gl_mappings.find(name); + if (gptr!=gl_mappings.end()) { + gptr->second.users++; + ptr_=gptr->second.ptr; + handle_=gptr->second.handle; + return; + } + /** first, look for the DTSI map */ FILE* fdtsi=fopen("/opt/ldmx-firmware/active/device-tree/pl-full.dtsi","r"); uint32_t baseaddr=0; @@ -69,6 +87,11 @@ UIO::UIO(const std::string& name, size_t length) handle_ = 0; PFEXCEPTION_RAISE("DeviceFileNotFoundError", msg); } + Mapping m; + m.ptr=ptr_; + m.users=1; + m.handle=handle_; + gl_mappings[name]=m; } void UIO::iopen(const std::string& path, size_t length) { @@ -88,6 +111,13 @@ void UIO::iopen(const std::string& path, size_t length) { } UIO::~UIO() { + + auto gptr=gl_mappings.find(name_); + if (gptr!=gl_mappings.end()) { + gptr->second.users--; + if (gptr->second.users>0) return; + } + if (handle_ != 0) { munmap(ptr_, size_); close(handle_); From 834725f07f5c69e50d2a670a12687a45d777240f Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:56:22 +0000 Subject: [PATCH 08/36] Add names, trig configuration --- src/pflib/lpgbt/lpGBT_standard_configs.cxx | 41 ++++++++++++++++------ 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/src/pflib/lpgbt/lpGBT_standard_configs.cxx b/src/pflib/lpgbt/lpGBT_standard_configs.cxx index cc9ca79c..15406056 100644 --- a/src/pflib/lpgbt/lpGBT_standard_configs.cxx +++ b/src/pflib/lpgbt/lpGBT_standard_configs.cxx @@ -7,17 +7,17 @@ namespace pflib { void setup_hcal_daq(pflib::lpGBT& lpgbt) { // setup the reset lines - lpgbt.gpio_cfg_set(0,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC2_HRST - lpgbt.gpio_set(0,true); - lpgbt.gpio_cfg_set(1,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC2_SRST - lpgbt.gpio_set(1,true); - lpgbt.gpio_cfg_set(2,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC1_HRST - lpgbt.gpio_set(2,true); - lpgbt.gpio_cfg_set(4,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC1_SRST - lpgbt.gpio_set(4,true); - lpgbt.gpio_cfg_set(8,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // HGCROC_I2C_RST + lpgbt.gpio_cfg_set(0,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC2_HRST"); + lpgbt.gpio_set(0,true); + lpgbt.gpio_cfg_set(1,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC2_SRST"); + lpgbt.gpio_set(1,true); + lpgbt.gpio_cfg_set(2,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC1_HRST"); + lpgbt.gpio_set(2,true); + lpgbt.gpio_cfg_set(4,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC1_SRST"); + lpgbt.gpio_set(4,true); + lpgbt.gpio_cfg_set(8,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC_I2C_RST"); lpgbt.gpio_set(8,true); - lpgbt.gpio_cfg_set(11,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG); // D2T_RSTB + lpgbt.gpio_cfg_set(11,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"TRIG_LPGBT_RSTB"); lpgbt.gpio_set(11,true); // setup clocks @@ -39,9 +39,30 @@ namespace pflib { lpgbt.setup_etx(5,true); // ECON-T1_FCMD lpgbt.setup_etx(6,true); // HGCROC1_FCMD + // setup the one input... + lpgbt.setup_erx(0, 0); + // setup the EC link lpgbt.setup_ec(false,4,false,0,false,true,false,true); } + + void setup_hcal_trig(pflib::lpGBT& lpgbt) { + + // setup the reset lines + lpgbt.gpio_cfg_set(4,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC0_HRST"); + lpgbt.gpio_set(4,true); + lpgbt.gpio_cfg_set(7,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC0_SRST"); + lpgbt.gpio_set(7,true); + lpgbt.gpio_cfg_set(6,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC3_HRST"); + lpgbt.gpio_set(6,true); + lpgbt.gpio_cfg_set(3,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC3_SRST"); + lpgbt.gpio_set(3,true); + + // setup the high speed inputs + for (int i=0; i<6; i++) { + lpgbt.setup_erx(i, 0); + } + } } } From 2f867882ffd9576d7e4e4a0f5392633fbb016d69 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:56:56 +0000 Subject: [PATCH 09/36] Add GPIO interface which keeps a list of names --- include/pflib/lpGBT.h | 9 ++++-- include/pflib/lpgbt/GPIO.h | 34 +++++++++++++++++++++ src/pflib/lpGBT.cxx | 5 ++-- src/pflib/lpgbt/GPIO.cxx | 61 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 5 deletions(-) create mode 100644 include/pflib/lpgbt/GPIO.h create mode 100644 src/pflib/lpgbt/GPIO.cxx diff --git a/include/pflib/lpGBT.h b/include/pflib/lpGBT.h index f9bbbd33..f94ca0ed 100644 --- a/include/pflib/lpGBT.h +++ b/include/pflib/lpGBT.h @@ -6,6 +6,7 @@ #include #include "pflib/Exception.h" +#include "pflib/lpgbt/GPIO.h" namespace pflib { @@ -95,8 +96,10 @@ class lpGBT { /** Get the GPIO pin configuration */ int gpio_cfg_get(int ibit); /** Set the GPIO pin configuration */ - void gpio_cfg_set(int ibit, int cfg); - + void gpio_cfg_set(int ibit, int cfg, const std::string& name=""); + /** Get the pflib GPIO object */ + GPIO& gpio_interface() { return gpio_; } + /** Carry out an ADC read for the given pair of channels Valid gain values are 1 or 2, 8, 16, and 32. @@ -191,7 +194,7 @@ class lpGBT { uint8_t ctl_reg; uint8_t read_len; } i2c_[3]; - + ::pflib::lpgbt::GPIO gpio_; }; } // namespace pflib diff --git a/include/pflib/lpgbt/GPIO.h b/include/pflib/lpgbt/GPIO.h new file mode 100644 index 00000000..1948d885 --- /dev/null +++ b/include/pflib/lpgbt/GPIO.h @@ -0,0 +1,34 @@ +#ifndef pflib_lpgbt_GPIO_h_included +#define pflib_lpgbt_GPIO_h_included + +#include "pflib/GPIO.h" +#include + +namespace pflib { + + class lpGBT; + + namespace lpgbt { + + class GPIO : public ::pflib::GPIO { + public: + GPIO(lpGBT& lpgbt) : lpgbt_(lpgbt) { } + virtual std::vector getGPOs(); + virtual std::vector getGPIs(); + virtual bool getGPI(const std::string& name); + virtual bool getGPO(const std::string& name); + virtual void setGPO(const std::string& name, bool toTrue = true); + + protected: + friend class ::pflib::lpGBT; + void add_pin(const std::string& name, int ibit, bool output); + private: + lpGBT& lpgbt_; + std::map gpos_, gpis_; + }; + + } +} + + +#endif // pflib_lpgbt_GPIO_h_included diff --git a/src/pflib/lpGBT.cxx b/src/pflib/lpGBT.cxx index 944451d2..38dd5989 100644 --- a/src/pflib/lpGBT.cxx +++ b/src/pflib/lpGBT.cxx @@ -14,7 +14,7 @@ void lpGBT_ConfigTransport::write_regs(uint16_t reg, for (size_t i = 0; i < value.size(); i++) write_reg(i + reg, value[i]); } -lpGBT::lpGBT(lpGBT_ConfigTransport& transport) : tport_{transport} {} +lpGBT::lpGBT(lpGBT_ConfigTransport& transport) : tport_{transport}, gpio_{*this} {} void lpGBT::write(const RegisterValueVector& regvalues) { std::vector tosend; @@ -250,7 +250,7 @@ int lpGBT::gpio_cfg_get(int ibit) { return cfg; } -void lpGBT::gpio_cfg_set(int ibit, int cfg) { +void lpGBT::gpio_cfg_set(int ibit, int cfg, const std::string& name) { if (ibit < 0 || ibit > 15) { char msg[100]; snprintf(msg, 100, "GPIO bit %d is out of range 0:15", ibit); @@ -277,6 +277,7 @@ void lpGBT::gpio_cfg_set(int ibit, int cfg) { } else { bit_clr(REG_PIOPULLENAH + offset, ibit % 8); } + gpio_.add_pin(name,ibit,cfg&GPIO_IS_OUTPUT); } uint16_t lpGBT::adc_resistance_read(int ipos, int current, int gain) { diff --git a/src/pflib/lpgbt/GPIO.cxx b/src/pflib/lpgbt/GPIO.cxx new file mode 100644 index 00000000..46ff9f77 --- /dev/null +++ b/src/pflib/lpgbt/GPIO.cxx @@ -0,0 +1,61 @@ +#include "pflib/lpGBT.h" +#include "pflib/lpgbt/GPIO.h" +#include "pflib/utility/string_format.h" + +namespace pflib { + namespace lpgbt { + + std::vector GPIO::getGPOs() { + std::vector retval; + for (auto item: gpos_) + retval.push_back(item.first); + return retval; + } + + std::vector GPIO::getGPIs() { + std::vector retval; + for (auto item: gpis_) + retval.push_back(item.first); + return retval; + } + bool GPIO::getGPI(const std::string& name) { + auto ptr=gpis_.find(name); + if (ptr==gpis_.end()) { + PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPI bit '%s'",name.c_str())); + } + int ibit=ptr->second; + return lpgbt_.gpio_get(ibit); + } + bool GPIO::getGPO(const std::string& name) { + auto ptr=gpos_.find(name); + if (ptr==gpos_.end()) { + PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); + } + int ibit=ptr->second; + return lpgbt_.gpio_get(ibit); + } + void GPIO::setGPO(const std::string& name, bool toTrue) { + auto ptr=gpos_.find(name); + if (ptr==gpos_.end()) { + PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); + } + int ibit=ptr->second; + lpgbt_.gpio_set(ibit, toTrue); + } + + void GPIO::add_pin(const std::string& name, int ibit, bool output) { + // remove this pin number or name if used anywhere + for (auto cur = gpos_.begin(); cur!=gpos_.end(); ) { + if (cur->second==ibit || cur->first==name) cur=gpos_.erase(cur); + else cur++; + } + for (auto cur = gpis_.begin(); cur!=gpis_.end(); ) { + if (cur->second==ibit || cur->first==name) cur=gpis_.erase(cur); + else cur++; + } + if (output) gpos_[name]=ibit; + else gpis_[name]=ibit; + } + + } +} From 41c4ec091f27abe0ed103528081740c63ed1f959 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:57:23 +0000 Subject: [PATCH 10/36] Add std::string varient --- include/pflib/zcu/zcu_optolink.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pflib/zcu/zcu_optolink.h b/include/pflib/zcu/zcu_optolink.h index 0de82a67..91e5df1c 100644 --- a/include/pflib/zcu/zcu_optolink.h +++ b/include/pflib/zcu/zcu_optolink.h @@ -11,6 +11,7 @@ namespace zcu { class OptoLink { public: OptoLink(const char* coder_name="singleLPGBT"); + OptoLink(const std::string& name) : OptoLink{name.c_str()} {} void reset_link(); From bc75f520eb71e9378fd23604d88b39401c908497 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:57:49 +0000 Subject: [PATCH 11/36] Add I2C interblock for lpGBT, including with MUX --- include/pflib/lpgbt/I2C.h | 45 ++++++++++++++++++++++++++++++++ src/pflib/lpgbt/I2C.cxx | 55 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 include/pflib/lpgbt/I2C.h create mode 100644 src/pflib/lpgbt/I2C.cxx diff --git a/include/pflib/lpgbt/I2C.h b/include/pflib/lpgbt/I2C.h new file mode 100644 index 00000000..871399a0 --- /dev/null +++ b/include/pflib/lpgbt/I2C.h @@ -0,0 +1,45 @@ +#ifndef pflib_lpgbt_I2C_h_included +#define pflib_lpgbt_I2C_h_included 1 + +#include "pflib/I2C.h" +#include "pflib/lpGBT.h" + +namespace pflib { + namespace lpgbt { + + /** Synchronous I2C implementation */ + class I2C : public ::pflib::I2C { + public: + I2C(lpGBT& lpGBT, int ibus) : lpgbt_{lpGBT},ibus_{ibus},ispeed_{100} { + } + + virtual void set_bus_speed(int speed = 100); + virtual int get_bus_speed(); + virtual void write_byte(uint8_t i2c_dev_addr, uint8_t data); + virtual uint8_t read_byte(uint8_t i2c_dev_addr); + virtual std::vector general_write_read(uint8_t i2c_dev_addr, const std::vector& wdata,int nread = 0); + + private: + lpGBT& lpgbt_; + int ibus_; + int ispeed_; + }; + + /** Synchronous I2C implementation */ + class I2CwithMux : public ::pflib::lpgbt::I2C { + public: + I2CwithMux(lpGBT& lpGBT, int ibus, uint8_t muxaddr, uint8_t tochoose) : ::pflib::lpgbt::I2C{lpGBT,ibus},muxaddr_{muxaddr},wval_{tochoose} { + } + + virtual void write_byte(uint8_t i2c_dev_addr, uint8_t data); + virtual uint8_t read_byte(uint8_t i2c_dev_addr); + virtual std::vector general_write_read(uint8_t i2c_dev_addr, const std::vector& wdata,int nread = 0); + + private: + uint8_t muxaddr_, wval_; + }; + } +} + +#endif // pflib_lpgbt_I2C_h_included + diff --git a/src/pflib/lpgbt/I2C.cxx b/src/pflib/lpgbt/I2C.cxx new file mode 100644 index 00000000..7b236ee1 --- /dev/null +++ b/src/pflib/lpgbt/I2C.cxx @@ -0,0 +1,55 @@ +#include "pflib/lpgbt/I2C.h" + +namespace pflib { + namespace lpgbt { + + void I2C::set_bus_speed(int speed) { + ispeed_=speed; + lpgbt_.setup_i2c(ibus_,speed); + } + + int I2C::get_bus_speed() { return ispeed_; } + + void I2C::write_byte(uint8_t i2c_dev_addr, uint8_t data) { + lpgbt_.i2c_write(ibus_,i2c_dev_addr,data); + lpgbt_.i2c_transaction_check(ibus_,true); + } + uint8_t I2C::read_byte(uint8_t i2c_dev_addr) { + lpgbt_.start_i2c_read(ibus_,i2c_dev_addr,1); + lpgbt_.i2c_transaction_check(ibus_,true); + std::vector data=lpgbt_.i2c_read_data(ibus_); + return data[0]; + } + std::vector I2C::general_write_read(uint8_t i2c_dev_addr, const std::vector& wdata,int nread) { + if (!wdata.empty()) { + if (wdata.size()==1) lpgbt_.i2c_write(ibus_,i2c_dev_addr,wdata[0]); + else lpgbt_.i2c_write(ibus_,i2c_dev_addr,wdata); + lpgbt_.i2c_transaction_check(ibus_,true); + } + if (nread>0) { + lpgbt_.start_i2c_read(ibus_,i2c_dev_addr,nread); + lpgbt_.i2c_transaction_check(ibus_,true); + return lpgbt_.i2c_read_data(ibus_); + } + std::vector rv; + return rv; + } + + + void I2CwithMux::write_byte(uint8_t i2c_dev_addr, uint8_t data) { + ::pflib::lpgbt::I2C::write_byte(muxaddr_, wval_); + ::pflib::lpgbt::I2C::write_byte(i2c_dev_addr, data); + } + uint8_t I2CwithMux::read_byte(uint8_t i2c_dev_addr) { + ::pflib::lpgbt::I2C::write_byte(muxaddr_, wval_); + return ::pflib::lpgbt::I2C::read_byte(i2c_dev_addr); + } + std::vector I2CwithMux::general_write_read(uint8_t i2c_dev_addr, const std::vector& wdata,int nread) { + ::pflib::lpgbt::I2C::write_byte(muxaddr_, wval_); + return ::pflib::lpgbt::I2C::general_write_read(i2c_dev_addr,wdata,nread); + } + + + + } +} From 14671dc36ebeb1749043e8e9429e0c3ece31f37a Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:58:09 +0000 Subject: [PATCH 12/36] Create Target and Hcal for backplane-via-ZCU --- src/pflib/zcu/HcalBackplaneZCU.cxx | 86 ++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 src/pflib/zcu/HcalBackplaneZCU.cxx diff --git a/src/pflib/zcu/HcalBackplaneZCU.cxx b/src/pflib/zcu/HcalBackplaneZCU.cxx new file mode 100644 index 00000000..d834b65f --- /dev/null +++ b/src/pflib/zcu/HcalBackplaneZCU.cxx @@ -0,0 +1,86 @@ +#include "pflib/Target.h" +#include "pflib/zcu/zcu_optolink.h" +#include "pflib/utility/string_format.h" +#include "pflib/lpgbt/I2C.h" +#include "pflib/zcu/lpGBT_ICEC_ZCU_Simple.h" + +namespace pflib { + + static constexpr int ADDR_HCAL_BACKPLANE_DAQ = 0x78|0x04; + static constexpr int ADDR_HCAL_BACKPLANE_TRIG = 0x78; + static constexpr int I2C_BUS_HGCROCS = 1; // DAQ + static constexpr int I2C_BUS_BIAS = 1; // TRIG + static constexpr int I2C_BUS_BOARD = 1; // TRIG + static constexpr int ADDR_MUX_BIAS = 0x70; + static constexpr int ADDR_MUX_BOARD = 0x71; + + + class HcalBackplaneZCUTarget : public Target, public Hcal { + public: + HcalBackplaneZCUTarget(int itarget, uint8_t board_mask) { + // first, setup the optical links + std::string uio_coder=pflib::utility::string_format("standardLpGBTpair-%d",itarget); + daq_tport_=std::make_unique(uio_coder, false, ADDR_HCAL_BACKPLANE_DAQ); + trig_tport_=std::make_unique(uio_coder, true, ADDR_HCAL_BACKPLANE_TRIG); + daq_lpgbt_=std::make_unique(*daq_tport_); + trig_lpgbt_=std::make_unique(*trig_tport_); + + // next, create the Hcal I2C objects + roc_i2c_=std::make_shared(*daq_lpgbt_, I2C_BUS_HGCROCS); + roc_i2c_->set_bus_speed(1000); + for (int ibd=0; ibd<4; ibd++) { + if ((board_mask&(1< bias_i2c=std::make_shared(*trig_lpgbt_,I2C_BUS_BIAS,ADDR_MUX_BIAS,(1< board_i2c=std::make_shared(*trig_lpgbt_,I2C_BUS_BOARD,ADDR_MUX_BOARD,(1<(this); + } + virtual void softResetROC(int which) { + // assuming everything was done with the standard config + if (which<0 || which==0) { + trig_lpgbt_->gpio_interface().setGPO("HGCROC0_SRST",false); + trig_lpgbt_->gpio_interface().setGPO("HGCROC0_SRST",true); + } + if (which<0 || which==1) { + daq_lpgbt_->gpio_interface().setGPO("HGCROC1_SRST",false); + daq_lpgbt_->gpio_interface().setGPO("HGCROC1_SRST",true); + } + if (which<0 || which==2) { + daq_lpgbt_->gpio_interface().setGPO("HGCROC2_SRST",false); + daq_lpgbt_->gpio_interface().setGPO("HGCROC2_SRST",true); + } + if (which<0 || which==3) { + trig_lpgbt_->gpio_interface().setGPO("HGCROC3_SRST",false); + trig_lpgbt_->gpio_interface().setGPO("HGCROC3_SRST",true); + } + + } + virtual void hardResetROCs() { + trig_lpgbt_->gpio_interface().setGPO("HGCROC0_HRST",false); + trig_lpgbt_->gpio_interface().setGPO("HGCROC0_HRST",true); + daq_lpgbt_->gpio_interface().setGPO("HGCROC1_HRST",false); + daq_lpgbt_->gpio_interface().setGPO("HGCROC1_HRST",true); + daq_lpgbt_->gpio_interface().setGPO("HGCROC2_HRST",false); + daq_lpgbt_->gpio_interface().setGPO("HGCROC2_HRST",true); + trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",false); + trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",true); + } + virtual Elinks& elinks() { } + virtual DAQ& daq() { } + virtual std::vector read_event() { std::vector empty; return empty; } + private: + std::unique_ptr daq_tport_, trig_tport_; + std::unique_ptr daq_lpgbt_, trig_lpgbt_; + std::shared_ptr roc_i2c_; + }; + + + Target* makeTargetHcalBackplaneZCU(int ilink, uint8_t board_mask) { + return new HcalBackplaneZCUTarget(ilink,board_mask); + } + +} From 42aa49a2b2e6e5ac2feb540db24493359eadb8ab Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:58:50 +0000 Subject: [PATCH 13/36] Start integration of the ZCU-optical path (needs a menu for getting the links up) --- app/tool/main.cxx | 43 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/app/tool/main.cxx b/app/tool/main.cxx index f9595ac0..4c14a611 100644 --- a/app/tool/main.cxx +++ b/app/tool/main.cxx @@ -86,17 +86,18 @@ std::string exec(const char* cmd) { } /// firmware name as it appears as a directory on disk -const std::string FW_SHORTNAME = "hcal-zcu102"; +const std::string FW_SHORTNAME_FIBERLESS = "hcal-zcu102"; +const std::string FW_SHORTNAME_UIO_ZCU = "dualtarget-zcu102"; /** * Check if the firmware supporting the HGCROC is active * * @return true if correct firmware is active */ -bool is_fw_active() { +bool is_fw_active(const std::string& name) { static const std::filesystem::path active_fw{"/opt/ldmx-firmware/active"}; auto resolved{std::filesystem::read_symlink(active_fw).stem()}; - return (resolved == FW_SHORTNAME); + return (resolved == name); } /** @@ -108,7 +109,9 @@ bool is_fw_active() { * @return string holding the full firmware version */ std::string fw_version() { - static const std::string QUERY_CMD = "rpm -qa '*" + FW_SHORTNAME + "*'"; + static const std::filesystem::path active_fw{"/opt/ldmx-firmware/active"}; + auto resolved{std::filesystem::read_symlink(active_fw).stem()}; + static const std::string QUERY_CMD = "rpm -qa '*" + std::string(resolved) + "*'"; auto output = exec(QUERY_CMD.c_str()); output.erase(std::remove(output.begin(), output.end(), '\n'), output.cend()); return output; @@ -123,11 +126,13 @@ std::string fw_version() { */ static void status(Target* pft) { pflib_log(info) << "pflib version: " << pflib::version::debug(); + /* if (is_fw_active()) { pflib_log(debug) << "fw is active"; } else { pflib_log(fatal) << "fw is not active!"; } + */ pflib_log(info) << "fw version : " << fw_version(); } @@ -205,12 +210,17 @@ int main(int argc, char* argv[]) { pflib::menu::Rcfile options; prepareOpts(options); + int boardmask=0xF; + int ilink=0; + // print help before attempting to load RC file incase the RC file is broken if (argc == 2 and (!strcmp(argv[1], "-h") or !strcmp(argv[1], "--help"))) { printf("\nUSAGE: (HCal HGCROC fiberless mode)\n"); - printf(" %s -z OPTIONS\n\n", argv[0]); + printf(" %s OPTIONS\n\n", argv[0]); printf("OPTIONS:\n"); printf(" -z : required for fiberless (no-polarfire, zcu102-based) mode\n"); + printf(" -z0 : fiber-based ZCU, backplane 0 (SFP0/SFP1)\n"); + printf(" -z1 : fiber-based ZCU, backplane 1 (SFP2/SFP3)\n"); printf(" -s : pass a script of commands to run through pftool\n"); printf(" -h|--help : print this help and exit\n"); printf( @@ -296,8 +306,24 @@ int main(int argc, char* argv[]) { sFile.close(); } else if (arg == "-z") { mode = Fiberless; - if (not is_fw_active()) { - pflib_log(fatal) << "'" << FW_SHORTNAME + if (not is_fw_active(FW_SHORTNAME_FIBERLESS)) { + pflib_log(fatal) << "'" << FW_SHORTNAME_FIBERLESS + << "' firmware is not active on ZCU."; + pflib_log(fatal) << "Connection will likely fail."; + } + } else if (arg == "-z0") { + mode = UIO_ZCU; + ilink = 0; + if (not is_fw_active(FW_SHORTNAME_UIO_ZCU)) { + pflib_log(fatal) << "'" << FW_SHORTNAME_UIO_ZCU + << "' firmware is not active on ZCU."; + pflib_log(fatal) << "Connection will likely fail."; + } + } else if (arg == "-z1") { + mode = UIO_ZCU; + ilink = 1; + if (not is_fw_active(FW_SHORTNAME_UIO_ZCU)) { + pflib_log(fatal) << "'" << FW_SHORTNAME_UIO_ZCU << "' firmware is not active on ZCU."; pflib_log(fatal) << "Connection will likely fail."; } @@ -370,8 +396,7 @@ int main(int argc, char* argv[]) { "Rogue communication mode not implemented"); break; case UIO_ZCU: - PFEXCEPTION_RAISE("BadComm", - "UIO_ZCU communcation mode not implemented"); + p_pft = std::unique_ptr(pflib::makeTargetHcalBackplaneZCU(ilink,boardmask)); break; default: PFEXCEPTION_RAISE( From cb607187203424175f058770b8d159eed60c23d2 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:59:10 +0000 Subject: [PATCH 14/36] Add TRIG standard configuration --- app/lpgbt/main.cxx | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/app/lpgbt/main.cxx b/app/lpgbt/main.cxx index 7be64426..cae3f434 100644 --- a/app/lpgbt/main.cxx +++ b/app/lpgbt/main.cxx @@ -10,7 +10,7 @@ #include "pflib/menu/Menu.h" #include "pflib/zcu/lpGBT_ICEC_ZCU_Simple.h" #include "power_ctl_mezz.h" -#include "zcu_optolink.h" +#include "pflib/zcu/zcu_optolink.h" struct ToolBox { pflib::lpGBT* lpgbt{0}; @@ -136,10 +136,14 @@ void general(const std::string& cmd, ToolBox* target) { target->lpgbt_ic->gpio_set(11,true); } } - if (cmd == "STANDARD_HCAL_DAQ") { - pflib::lpgbt::standard_config::setup_hcal_daq(*target->lpgbt); + if (cmd == "EXPERT_STANDARD_HCAL_DAQ" || cmd=="STANDARD_HCAL") { + pflib::lpgbt::standard_config::setup_hcal_daq(*target->lpgbt_ic); printf("Applied standard HCAL DAQ configuration\n"); } + if (cmd == "EXPERT_STANDARD_HCAL_TRIG" || cmd=="STANDARD_HCAL") { + pflib::lpgbt::standard_config::setup_hcal_trig(*target->lpgbt_ec); + printf("Applied standard HCAL TRIG configuration\n"); + } if (cmd == "MODE") { LPGBT_Mezz_Tester tester(target->olink->coder()); printf("MODE1 = 1 for Transceiver, MODE1=0 for Transmit-only\n"); @@ -720,7 +724,9 @@ namespace { auto gen = tool::menu("GENERAL", "GENERAL funcations") ->line("STATUS", "Status summary", general) ->line("MODE", "Setup the lpGBT ADDR and MODE1", general) - ->line("STANDARD_HCAL_DAQ", "Apply standard HCAL DAQ lpGBT setup", general) + ->line("STANDARD_HCA", "Apply standard HCAL lpGBT setups", general) + ->line("EXPERT_STANDARD_HCAL_DAQ", "Apply just standard HCAL DAQ lpGBT setup", general) + ->line("EXPERT_STANDARD_HCAL_TRIG", "Apply just standard HCAL TRIG lpGBT setup", general) ->line("RESET", "Reset the lpGBT", general) ->line("COMM", "Communication mode", general); From 9c7ede760c1a77150b5479ce41f8c87bbc6be317 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 20:59:21 +0000 Subject: [PATCH 15/36] Several new files to build --- CMakeLists.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2cd8593c..31c925ff 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -142,7 +142,7 @@ target_link_libraries(packing PUBLIC utility) # # src/pflib/FastControl.cxx -add_library(pflib SHARED +add_library(pflib SHARED src/pflib/I2C_Linux.cxx src/pflib/ROC.cxx src/pflib/Compile.cxx @@ -159,6 +159,8 @@ add_library(pflib SHARED src/pflib/lpgbt/lpGBT_Registers.cxx src/pflib/lpgbt/lpGBT_Utility.cxx src/pflib/lpgbt/lpGBT_standard_configs.cxx + src/pflib/lpgbt/I2C.cxx + src/pflib/lpgbt/GPIO.cxx src/pflib/TargetFiberless.cxx src/pflib/GPIO_HcalHGCROCZCU.cxx src/pflib/FastControlCMS_MMap.cxx @@ -166,6 +168,8 @@ add_library(pflib SHARED src/pflib/zcu/UIO.cxx src/pflib/zcu/Elinks_zcu.cxx src/pflib/zcu/lpGBT_ICEC_ZCU_Simple.cxx + src/pflib/zcu/zcu_optolink.cxx + src/pflib/zcu/HcalBackplaneZCU.cxx src/pflib/Bias.cxx src/pflib/algorithm/level_pedestals.cxx src/pflib/algorithm/toa_vref_scan.cxx @@ -213,7 +217,6 @@ target_link_libraries(pftool PRIVATE pflib menu) add_executable(pflpgbt app/lpgbt/main.cxx app/lpgbt/lpgbt_mezz_tester.cc - app/lpgbt/zcu_optolink.cc ) target_link_libraries(pflpgbt PRIVATE pflib menu) From f39c4c7cbe3782739573ee8a8378a67d5cd5c787 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Wed, 17 Sep 2025 21:05:32 +0000 Subject: [PATCH 16/36] Correct bus number for BOARD I2C --- src/pflib/zcu/HcalBackplaneZCU.cxx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/pflib/zcu/HcalBackplaneZCU.cxx b/src/pflib/zcu/HcalBackplaneZCU.cxx index d834b65f..e514190f 100644 --- a/src/pflib/zcu/HcalBackplaneZCU.cxx +++ b/src/pflib/zcu/HcalBackplaneZCU.cxx @@ -10,7 +10,7 @@ namespace pflib { static constexpr int ADDR_HCAL_BACKPLANE_TRIG = 0x78; static constexpr int I2C_BUS_HGCROCS = 1; // DAQ static constexpr int I2C_BUS_BIAS = 1; // TRIG - static constexpr int I2C_BUS_BOARD = 1; // TRIG + static constexpr int I2C_BUS_BOARD = 0; // TRIG static constexpr int ADDR_MUX_BIAS = 0x70; static constexpr int ADDR_MUX_BOARD = 0x71; From aae0088fa7f1f529559c6f5e1720d81e4ef12e75 Mon Sep 17 00:00:00 2001 From: taylorjcolaizzi Date: Wed, 17 Sep 2025 20:13:43 -0400 Subject: [PATCH 17/36] Added ECOND and ECONT register maps to register_maps directory. --- register_maps/ECOND_I2C_params_regmap.yaml | 42522 +++++++++++++++++++ register_maps/ECONT_I2C_params_regmap.yaml | 9820 +++++ 2 files changed, 52342 insertions(+) create mode 100644 register_maps/ECOND_I2C_params_regmap.yaml create mode 100644 register_maps/ECONT_I2C_params_regmap.yaml diff --git a/register_maps/ECOND_I2C_params_regmap.yaml b/register_maps/ECOND_I2C_params_regmap.yaml new file mode 100644 index 00000000..59e7ae09 --- /dev/null +++ b/register_maps/ECOND_I2C_params_regmap.yaml @@ -0,0 +1,42522 @@ +Aligner: + Global: + dbg_fc_cnt: + access: ro + address: 0x0398 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dbg_fc_cnt_clr: + access: rw + address: 0x0380 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + dbg_lreset_rcvd: + access: ro + address: 0x0398 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + dbg_orbsyn_rcvd: + access: ro + address: 0x0398 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + done: + access: ro + address: 0x0398 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + freeze_output_enable: + access: rw + address: 0x0380 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + freeze_output_enable_all_channels_locked: + access: rw + address: 0x0380 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + i2c_snapshot_en: + access: rw + address: 0x0380 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + idle_hdr_mask: + access: rw + address: 0x0392 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + idle_hdr_val: + access: rw + address: 0x0392 + default_value: 10 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + match_mask_val: + access: rw + address: 0x0389 + default_value: 18446744069414584320 + max_value: 18446744073709551615 + param_mask: 0xffffffffffffffff + param_shift: 0 + size_byte: 8 + match_pattern_val: + access: rw + address: 0x0381 + default_value: 2594876074 + max_value: 18446744073709551615 + param_mask: 0xffffffffffffffff + param_shift: 0 + size_byte: 8 + orbsyn_cnt_load_val: + access: rw + address: 0x0393 + default_value: 3513 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + orbsyn_cnt_max_val: + access: rw + address: 0x0393 + default_value: 3563 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 3 + orbsyn_cnt_snapshot: + access: rw + address: 0x0396 + default_value: 2 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + orbsyn_hdr_mask: + access: rw + address: 0x0391 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + orbsyn_hdr_val: + access: rw + address: 0x0391 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + snapshot_arm: + access: rw + address: 0x0380 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + snapshot_en: + access: rw + address: 0x0380 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + tmr_err_cnt_aligner: + access: ro + address: 0x0399 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +ChAligner: + 0: + force_ch_outputs: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x002e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0031 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0032 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0030 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0000 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0033 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0002 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0001 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0015 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0016 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0034 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0036 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0035 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0004 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0008 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x000c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0010 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + force_ch_outputs: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x006e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0071 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0072 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0070 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0040 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0073 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0042 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0041 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0055 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0056 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0074 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0076 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0075 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0044 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0048 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x004c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0050 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + force_ch_outputs: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x00ae + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x00b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x00b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x00b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0080 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x00b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0082 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0081 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0095 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0096 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x00b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x00b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x00b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0084 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0088 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x008c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0090 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + force_ch_outputs: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x00ee + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x00f1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x00f2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x00f0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x00c0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x00f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x00c2 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x00c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x00d5 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x00d6 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x00f4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x00f6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x00f5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x00c4 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x00c8 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x00cc + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x00d0 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 4: + force_ch_outputs: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x012e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0131 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0132 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0130 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0100 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0133 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0102 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0101 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0115 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0116 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0134 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0136 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0135 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0104 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0108 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x010c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0110 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 5: + force_ch_outputs: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x016e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0171 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0172 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0170 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0140 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0173 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0142 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0141 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0155 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0156 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0174 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0176 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0175 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0144 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0148 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x014c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0150 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 6: + force_ch_outputs: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x01ae + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x01b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x01b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x01b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0180 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x01b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0182 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0181 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0195 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0196 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x01b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x01b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x01b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0184 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0188 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x018c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0190 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 7: + force_ch_outputs: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x01ee + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x01f1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x01f2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x01f0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x01c0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x01f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x01c2 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x01c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x01d5 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x01d6 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x01f4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x01f6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x01f5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x01c4 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x01c8 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x01cc + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x01d0 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 8: + force_ch_outputs: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x022e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0231 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0232 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0230 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0200 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0233 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0202 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0201 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0215 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0216 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0234 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0236 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0235 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0204 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0208 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x020c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0210 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 9: + force_ch_outputs: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x026e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0271 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0272 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0270 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0240 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0273 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0242 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0241 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0255 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0256 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0274 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0276 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0275 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0244 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0248 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x024c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0250 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 10: + force_ch_outputs: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x02ae + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x02b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x02b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x02b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0280 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x02b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0282 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0281 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0295 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0296 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x02b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x02b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x02b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0284 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0288 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x028c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0290 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 11: + force_ch_outputs: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x02ee + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x02f1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x02f2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x02f0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x02c0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x02f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x02c2 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x02c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x02d5 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x02d6 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x02f4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x02f6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x02f5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x02c4 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x02c8 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x02cc + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x02d0 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 +ChEprxGrp: + 0: + channel_locked: + access: ro + address: 0x0341 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0341 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0342 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0342 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0342 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0340 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0341 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0340 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0341 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0340 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0340 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 1: + channel_locked: + access: ro + address: 0x0345 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0345 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0346 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0346 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0346 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0344 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0345 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0344 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0345 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0344 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0344 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 2: + channel_locked: + access: ro + address: 0x0349 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0349 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x034a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x034a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x034a + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0348 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0349 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0348 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0349 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0348 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0348 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 3: + channel_locked: + access: ro + address: 0x034d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x034d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x034e + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x034e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x034e + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x034c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x034d + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x034c + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x034d + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x034c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x034c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 4: + channel_locked: + access: ro + address: 0x0351 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0351 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0352 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0352 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0352 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0350 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0351 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0350 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0351 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0350 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0350 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 5: + channel_locked: + access: ro + address: 0x0355 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0355 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0356 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0356 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0356 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0354 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0355 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0354 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0355 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0354 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0354 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 6: + channel_locked: + access: ro + address: 0x0359 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0359 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x035a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x035a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x035a + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0358 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0359 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0358 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0359 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0358 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0358 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 7: + channel_locked: + access: ro + address: 0x035d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x035d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x035e + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x035e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x035e + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x035c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x035d + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x035c + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x035d + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x035c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x035c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 8: + channel_locked: + access: ro + address: 0x0361 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0361 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0362 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0362 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0362 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0360 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0361 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0360 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0361 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0360 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0360 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 9: + channel_locked: + access: ro + address: 0x0365 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0365 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0366 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0366 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0366 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0364 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0365 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0364 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0365 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0364 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0364 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 10: + channel_locked: + access: ro + address: 0x0369 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0369 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x036a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x036a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x036a + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0368 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0369 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0368 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0369 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0368 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0368 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 11: + channel_locked: + access: ro + address: 0x036d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x036d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x036e + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x036e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x036e + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x036c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x036d + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x036c + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x036d + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x036c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x036c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 +ChErr: + 0: + clr_on_read: + access: wo + address: 0x0300 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0303 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0303 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0301 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0302 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0300 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0300 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 1: + clr_on_read: + access: wo + address: 0x0304 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0307 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0307 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0305 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0306 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0304 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0304 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 2: + clr_on_read: + access: wo + address: 0x0308 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x030b + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x030b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0309 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x030a + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0308 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0308 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 3: + clr_on_read: + access: wo + address: 0x030c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x030f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x030f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x030d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x030e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x030c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x030c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 4: + clr_on_read: + access: wo + address: 0x0310 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0313 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0313 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0311 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0312 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0310 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0310 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 5: + clr_on_read: + access: wo + address: 0x0314 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0317 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0317 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0315 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0316 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0314 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0314 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 6: + clr_on_read: + access: wo + address: 0x0318 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x031b + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x031b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0319 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x031a + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0318 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0318 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 7: + clr_on_read: + access: wo + address: 0x031c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x031f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x031f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x031d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x031e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x031c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x031c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 8: + clr_on_read: + access: wo + address: 0x0320 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0323 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0323 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0321 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0322 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0320 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0320 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 9: + clr_on_read: + access: wo + address: 0x0324 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0327 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0327 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0325 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0326 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0324 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0324 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 10: + clr_on_read: + access: wo + address: 0x0328 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x032b + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x032b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0329 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x032a + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0328 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0328 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 11: + clr_on_read: + access: wo + address: 0x032c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x032f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x032f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x032d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x032e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x032c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x032c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 +ClocksAndResets: + Global: + calibration_end_of_count_select: + access: rw + address: 0x03c9 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 46 + size_byte: 7 + capbank_select: + access: rw + address: 0x03c9 + default_value: 31 + max_value: 511 + param_mask: 0x01ff + param_shift: 37 + size_byte: 7 + clk_tree_a_disable: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 7 + clk_tree_b_disable: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 7 + clk_tree_c_disable: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 7 + clk_tree_erx_disable: + access: rw + address: 0x03d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + clk_tree_etx_disable: + access: rw + address: 0x03d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + clk_tree_magic_number: + access: rw + address: 0x03c8 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + clk_tree_sram_disable: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 15 + size_byte: 2 + co_connect_pll: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 6 + co_dis_data_counter_ref: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 6 + co_dis_des_vbiasgen: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 6 + co_enable_pll: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 55 + size_byte: 7 + co_override_vc: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 6 + enable_capbank_override: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 36 + size_byte: 7 + enable_control_override: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 54 + size_byte: 7 + fc_locked_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + lock_filter_clk_always_enable: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 17 + size_byte: 6 + lock_filter_enable: + access: rw + address: 0x03d0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 6 + lock_filter_lock_threshold: + access: rw + address: 0x03d0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 5 + size_byte: 6 + lock_filter_locked: + access: ro + address: 0x03df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 4 + lock_filter_loss_of_lock_count: + access: ro + address: 0x03df + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 7 + size_byte: 4 + lock_filter_loss_of_lock_count_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + lock_filter_relock_threshold: + access: rw + address: 0x03d0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 9 + size_byte: 6 + lock_filter_state: + access: ro + address: 0x03df + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 4 + lock_filter_un_lock_threshold: + access: rw + address: 0x03d0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 13 + size_byte: 6 + pll_config_integral: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 11 + size_byte: 7 + pll_config_integral_when_locked: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 15 + size_byte: 7 + pll_config_proportional: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 19 + size_byte: 7 + pll_config_proportional_when_locked: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 23 + size_byte: 7 + pll_config_res: + access: rw + address: 0x03c9 + default_value: 2 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 7 + pll_config_res_when_locked: + access: rw + address: 0x03c9 + default_value: 2 + max_value: 15 + param_mask: 0x000f + param_shift: 7 + size_byte: 7 + pusm_force_magic: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 1 + size_byte: 3 + pusm_force_state: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 3 + pusm_left_ready_action_counter: + access: ro + address: 0x03dd + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_left_ready_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pusm_run: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 23 + size_byte: 3 + pusm_state: + access: ro + address: 0x03df + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 4 + pusm_state_forced: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 9 + size_byte: 3 + pusm_state_upset_action_counter: + access: ro + address: 0x03de + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_state_upset_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + pusm_timeout_dll_action_counter: + access: ro + address: 0x03da + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_timeout_dll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + pusm_timeout_dll_lock_config: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 19 + size_byte: 3 + pusm_timeout_pll_action_counter: + access: ro + address: 0x03d9 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_timeout_pll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + pusm_timeout_pll_lock_config: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 15 + size_byte: 3 + pusm_watchdog_dll_action_counter: + access: ro + address: 0x03dc + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_watchdog_dll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + pusm_watchdog_pll_action_counter: + access: ro + address: 0x03db + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_watchdog_pll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + pusm_wdog_dll_disable: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 14 + size_byte: 3 + pusm_wdog_pll_disable: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 13 + size_byte: 3 + ref_clk_sel_testclkin: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 14 + size_byte: 2 + sm_locked: + access: ro + address: 0x03df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 19 + size_byte: 4 + sm_state: + access: ro + address: 0x03df + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 15 + size_byte: 4 + test_output_drive_strength: + 0: + access: rw + address: 0x03d0 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 38 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 4 + size_byte: 2 + test_output_enable: + 0: + access: rw + address: 0x03d0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 34 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + test_output_invert_data: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 35 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 2 + test_output_low_supply_r: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 47 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 13 + size_byte: 2 + test_output_preemp_mode: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 36 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 2 + size_byte: 2 + test_output_preemp_strength: + 0: + access: rw + address: 0x03d0 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 41 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 7 + size_byte: 2 + test_output_preemp_width: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 44 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 10 + size_byte: 2 + test_output_select: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 18 + size_byte: 6 + 1: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 26 + size_byte: 6 + tmr_err_cnt_clocks_and_resets: + access: ro + address: 0x03e3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + vco_capbank: + access: ro + address: 0x03df + default_value: 0 + max_value: 511 + param_mask: 0x01ff + param_shift: 20 + size_byte: 4 + vco_config_biasgen: + access: rw + address: 0x03c9 + default_value: 8 + max_value: 15 + param_mask: 0x000f + param_shift: 27 + size_byte: 7 + vco_config_dac: + access: rw + address: 0x03c9 + default_value: 8 + max_value: 15 + param_mask: 0x000f + param_shift: 31 + size_byte: 7 + vco_rail_rail_mode: + access: rw + address: 0x03c9 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 35 + size_byte: 7 + wait_pll_time: + access: rw + address: 0x03c9 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 50 + size_byte: 7 +ELinkProcessors: + Global: + cm_erx_route: + access: rw + address: 0x0452 + default_value: 1250999896491 + max_value: 281474976710655 + param_mask: 0xffffffffffff + param_shift: 0 + size_byte: 6 + cm_selection_x: + 0: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 3 + size_byte: 3 + 2: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 3 + 3: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 3 + 4: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 12 + size_byte: 3 + 5: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 15 + size_byte: 3 + 6: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 18 + size_byte: 3 + 7: + access: rw + address: 0x0458 + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x045b + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x045b + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 3 + size_byte: 2 + 10: + access: rw + address: 0x045b + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 11: + access: rw + address: 0x045b + default_value: 6 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + cm_user_def_x: + 0: + access: rw + address: 0x045d + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 1: + access: rw + address: 0x045d + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 2: + access: rw + address: 0x045d + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 3: + access: rw + address: 0x045d + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + 4: + access: rw + address: 0x0462 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 5: + access: rw + address: 0x0462 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 6: + access: rw + address: 0x0462 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 7: + access: rw + address: 0x0462 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + 8: + access: rw + address: 0x0467 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 9: + access: rw + address: 0x0467 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 10: + access: rw + address: 0x0467 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 11: + access: rw + address: 0x0467 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + erx_mask_crc: + access: rw + address: 0x0470 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + erx_mask_ebo: + access: rw + address: 0x046e + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + erx_mask_ht: + access: rw + address: 0x046c + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + erx_override_subp_suppress: + access: rw + address: 0x0472 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + recon_mode_choice: + access: rw + address: 0x0451 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + recon_mode_result: + access: rw + address: 0x0451 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 1 + status_cm_mod: + access: ro + address: 0x048a + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 6 + status_cm_roc: + 0: + access: ro + address: 0x0485 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 1: + access: ro + address: 0x0485 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 2: + access: ro + address: 0x0485 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 3: + access: ro + address: 0x0485 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + 4: + access: ro + address: 0x048a + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 6 + 5: + access: ro + address: 0x048a + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 6 + status_raw_v_selected_match_set: + access: ro + address: 0x048a + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 30 + size_byte: 6 + status_selected_cm_erx: + 0: + access: ro + address: 0x0476 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 1: + access: ro + address: 0x0476 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 2: + access: ro + address: 0x0476 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 3: + access: ro + address: 0x0476 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + 4: + access: ro + address: 0x047b + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 5: + access: ro + address: 0x047b + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 6: + access: ro + address: 0x047b + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 7: + access: ro + address: 0x047b + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + 8: + access: ro + address: 0x0480 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 5 + 9: + access: ro + address: 0x0480 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 10 + size_byte: 5 + 10: + access: ro + address: 0x0480 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 20 + size_byte: 5 + 11: + access: ro + address: 0x0480 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 30 + size_byte: 5 + tmr_err_cnt_elink_processors: + access: ro + address: 0x0490 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + v_reconstruct_thresh: + access: rw + address: 0x0450 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + veto_pass_fail: + access: rw + address: 0x0474 + default_value: 771 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 +ERx: + 0: + enable: + access: rw + address: 0x03e4 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e4 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e4 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 1: + enable: + access: rw + address: 0x03e5 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e5 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e5 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 2: + enable: + access: rw + address: 0x03e6 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e6 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e6 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 3: + enable: + access: rw + address: 0x03e7 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e7 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e7 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 4: + enable: + access: rw + address: 0x03e8 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e8 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e8 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 5: + enable: + access: rw + address: 0x03e9 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e9 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e9 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 6: + enable: + access: rw + address: 0x03ea + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ea + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ea + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 7: + enable: + access: rw + address: 0x03eb + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03eb + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03eb + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 8: + enable: + access: rw + address: 0x03ec + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ec + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ec + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 9: + enable: + access: rw + address: 0x03ed + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ed + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ed + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ed + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ed + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 10: + enable: + access: rw + address: 0x03ee + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ee + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ee + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 11: + enable: + access: rw + address: 0x03ef + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ef + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ef + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + Global: + tmr_err_cnt_erx: + access: ro + address: 0x03f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + Mux00: + enable: + access: rw + address: 0x03f0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03f0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03f0 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + Mux01: + enable: + access: rw + address: 0x03f1 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03f1 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03f1 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + Mux02: + enable: + access: rw + address: 0x03f2 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03f2 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03f2 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 +ETx: + 0: + drive_strength: + access: rw + address: 0x03f4 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03f4 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 1: + drive_strength: + access: rw + address: 0x03f6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03f6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 2: + drive_strength: + access: rw + address: 0x03f8 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03f8 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 3: + drive_strength: + access: rw + address: 0x03fa + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03fa + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03fa + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03fa + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 4: + drive_strength: + access: rw + address: 0x03fc + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03fc + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03fc + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03fc + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 5: + drive_strength: + access: rw + address: 0x03fe + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03fe + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03fe + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03fe + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 6: + drive_strength: + access: rw + address: 0x0400 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0400 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0400 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0400 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0400 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0400 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 7: + drive_strength: + access: rw + address: 0x0402 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0402 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0402 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0402 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0402 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0402 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 8: + drive_strength: + access: rw + address: 0x0404 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0404 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0404 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0404 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0404 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0404 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 9: + drive_strength: + access: rw + address: 0x0406 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0406 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0406 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0406 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0406 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0406 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 10: + drive_strength: + access: rw + address: 0x0408 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0408 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0408 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0408 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0408 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0408 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 11: + drive_strength: + access: rw + address: 0x040a + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x040a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x040a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x040a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x040a + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x040a + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 12: + drive_strength: + access: rw + address: 0x040c + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x040c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x040c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x040c + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x040c + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x040c + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + Global: + tmr_err_cnt_etx: + access: ro + address: 0x040e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +EprxGrpTop: + Global: + data_gating_enable: + access: rw + address: 0x03a3 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 3 + dll_coarse_lock_detection: + access: rw + address: 0x03a3 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 3 + dll_confirm_count_select: + access: rw + address: 0x03a3 + default_value: 2 + max_value: 3 + param_mask: 0x0003 + param_shift: 15 + size_byte: 3 + dll_current_set: + access: rw + address: 0x03a3 + default_value: 1 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 3 + dll_init_sm_force_clock_enable: + access: rw + address: 0x03a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 17 + size_byte: 3 + dll_lock_threshold: + access: rw + address: 0x03a3 + default_value: 5 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 3 + dll_re_lock_threshold: + access: rw + address: 0x03a3 + default_value: 5 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 3 + dll_un_lock_threshold: + access: rw + address: 0x03a3 + default_value: 5 + max_value: 7 + param_mask: 0x0007 + param_shift: 12 + size_byte: 3 + enable_re_init: + access: rw + address: 0x03a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 18 + size_byte: 3 + tmr_err_cnt_eprxgrp_top: + access: ro + address: 0x03a6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + track_mode: + access: rw + address: 0x03a3 + default_value: 1 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 3 +ErrTop: + Global: + clr_on_read_top: + access: rw + address: 0x039a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat_top: + access: ro + address: 0x03a0 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + err_out_top: + access: ro + address: 0x03a0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + err_wr_data: + access: rw + address: 0x039d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat_top: + access: ro + address: 0x039e + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + tmr_err_cnt_err_top: + access: ro + address: 0x03a2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + wr_data_top: + access: rw + address: 0x039b + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + wren_err_top: + access: rw + address: 0x039a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk_top: + access: rw + address: 0x039a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 +FCtrl: + Global: + bcr_fcmd_count: + access: ro + address: 0x03ad + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + cal_pulse_ext_fcmd_count: + access: ro + address: 0x03b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + cal_pulse_int_fcmd_count: + access: ro + address: 0x03b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + capture_fcmd_ctrl: + access: rw + address: 0x03a8 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + command_rx_inverted: + access: ro + address: 0x03ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + ebr_fcmd_count: + access: ro + address: 0x03b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + ecr_fcmd_count: + access: ro + address: 0x03b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + edge_sel_t1: + access: rw + address: 0x03a7 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + fc_error_fcmd_count: + access: ro + address: 0x03c2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + invert_command_rx: + access: rw + address: 0x03a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + l1a_fcmd_count: + access: ro + address: 0x03af + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_econ_d_fcmd_count: + access: ro + address: 0x03b8 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_econ_t_fcmd_count: + access: ro + address: 0x03b7 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_roc_d_fcmd_count: + access: ro + address: 0x03b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_roc_t_fcmd_count: + access: ro + address: 0x03b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + lock_count: + access: ro + address: 0x03ac + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + locked: + access: ro + address: 0x03ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + nzs_fcmd_count: + access: ro + address: 0x03b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + ocr_fcmd_count: + access: ro + address: 0x03ae + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pre_l1a_offset: + access: rw + address: 0x03a7 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + spare_fcmd_count: + 0: + access: ro + address: 0x03b9 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: ro + address: 0x03ba + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: ro + address: 0x03bb + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: ro + address: 0x03bc + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: ro + address: 0x03bd + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: ro + address: 0x03be + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: ro + address: 0x03bf + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: ro + address: 0x03c0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_fast_ctrl_decoder: + access: ro + address: 0x03c3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + unassigned_fcmd_count: + access: ro + address: 0x03c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +FormatterBuffer: + Global: + active_etxs: + access: rw + address: 0x0f33 + default_value: 63 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + align_serializer: + 0: + access: rw + address: 0x0f29 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0f29 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 6 + size_byte: 3 + 2: + access: rw + address: 0x0f29 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 12 + size_byte: 3 + 3: + access: rw + address: 0x0f29 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 18 + size_byte: 3 + 4: + access: rw + address: 0x0f2c + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 7 + 5: + access: rw + address: 0x0f2c + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 6 + size_byte: 7 + buffer_status: + 0: + access: rw + address: 0x0f21 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x0f22 + default_value: 64 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x0f23 + default_value: 96 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0f24 + default_value: 128 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0f25 + default_value: 160 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0f26 + default_value: 192 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0f27 + default_value: 224 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + buffer_status_truncate_threshold_low: + access: rw + address: 0x0f28 + default_value: 128 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + errin_econt_error: + access: ro + address: 0x0f34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + errin_mask: + access: rw + address: 0x0f20 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + errin_roc_error: + access: ro + address: 0x0f34 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + error_count_format: + access: ro + address: 0x0f3b + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + error_count_hamming: + access: ro + address: 0x0f3c + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + error_count_pass_thru: + access: ro + address: 0x0f3d + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + header_marker: + access: rw + address: 0x0f2c + default_value: 486 + max_value: 511 + param_mask: 0x01ff + param_shift: 47 + size_byte: 7 + idle_pattern: + access: rw + address: 0x0f2c + default_value: 5592405 + max_value: 16777215 + param_mask: 0xffffff + param_shift: 23 + size_byte: 7 + link_reset_pattern: + access: rw + address: 0x0f2c + default_value: 290 + max_value: 2047 + param_mask: 0x07ff + param_shift: 12 + size_byte: 7 + ob_bist_result_test: + 1: + access: ro + address: 0x0f35 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 3 + 2: + access: ro + address: 0x0f35 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + 3: + access: ro + address: 0x0f38 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 3 + 4: + access: ro + address: 0x0f38 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + prbs_on: + access: rw + address: 0x0f33 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + roc_errin_polarity: + access: rw + address: 0x0f33 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + tmr_err_cnt_formatter_buffer: + access: ro + address: 0x0f3e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Misc: + Global: + ro: + 0: + access: ro + address: 0x0f40 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + rw_err_clr: + 0: + access: rw + address: 0x0f3f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + wbmaster_err_wb_adr_cnt: + access: ro + address: 0x0f41 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Misc_TMRErrCnt: + Global: + tmr_err_cnt_misc: + access: ro + address: 0x0f42 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +PingPongSRAM: + Global: + interface_select: + access: rw + address: 0x0491 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 0 + size_byte: 1 + sram_bist_result_test: + 1: + access: ro + address: 0x0492 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 3 + 2: + access: ro + address: 0x0492 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + 3: + access: ro + address: 0x0495 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 3 + 4: + access: ro + address: 0x0495 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + status_bad_pp_read_state: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 2 + status_data_available: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + status_empty_h_available: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 2 + status_empty_h_fifo_count: + access: ro + address: 0x0499 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 10 + size_byte: 2 + status_empty_h_fifo_full: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 9 + size_byte: 2 + status_empty_h_fifo_read: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 2 + status_interface: + 1: + access: ro + address: 0x049b + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 2: + access: ro + address: 0x049d + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 3: + access: ro + address: 0x049f + default_value: 0 + max_value: 1099511627775 + param_mask: 0xffffffffff + param_shift: 0 + size_byte: 5 + status_pong_rw: + access: ro + address: 0x0499 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 7 + size_byte: 2 + status_pp_finished: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 2 + status_pp_flush: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 2 + status_pp_state: + access: ro + address: 0x0498 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + status_read_state: + access: ro + address: 0x0498 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 2 + size_byte: 1 + status_start_readout: + access: ro + address: 0x0499 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 2 + tmr_err_cnt_bist_ctrl: + access: ro + address: 0x04a4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +RocDaqCtrl: + Global: + active_erxs: + access: rw + address: 0x0415 + default_value: 4095 + max_value: 4095 + param_mask: 0x0fff + param_shift: 4 + size_byte: 2 + bad_word_threshold: + access: rw + address: 0x0410 + default_value: 20 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + bcr_bucket_default: + access: rw + address: 0x0411 + default_value: 3514 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + confidence_x: + 0: + access: ro + address: 0x0438 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: ro + address: 0x0439 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: ro + address: 0x043a + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: ro + address: 0x043b + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: ro + address: 0x043c + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: ro + address: 0x043d + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: ro + address: 0x043e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: ro + address: 0x043f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 8: + access: ro + address: 0x0440 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 9: + access: ro + address: 0x0441 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 10: + access: ro + address: 0x0442 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 11: + access: ro + address: 0x0443 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + ebr_timeout: + access: rw + address: 0x041c + default_value: 64 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + econ_buffer_delay: + access: rw + address: 0x0413 + default_value: 7 + max_value: 31 + param_mask: 0x001f + param_shift: 5 + size_byte: 2 + error_flags_bunch_counter: + access: ro + address: 0x0444 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + error_flags_l1a_fifo_full: + access: ro + address: 0x0444 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + error_flags_missed_pkt: + access: ro + address: 0x0444 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + error_flags_predictor_fifo_full: + access: ro + address: 0x0444 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + error_flags_unused_state: + access: ro + address: 0x0444 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + first_sync_header: + access: rw + address: 0x0417 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 28 + size_byte: 4 + hdr_count_x: + 0: + access: ro + address: 0x0420 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 1: + access: ro + address: 0x0422 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 2: + access: ro + address: 0x0424 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 3: + access: ro + address: 0x0426 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 4: + access: ro + address: 0x0428 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 5: + access: ro + address: 0x042a + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 6: + access: ro + address: 0x042c + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 7: + access: ro + address: 0x042e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 8: + access: ro + address: 0x0430 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 9: + access: ro + address: 0x0432 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 10: + access: ro + address: 0x0434 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 11: + access: ro + address: 0x0436 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hgcroc_hdr_marker: + access: rw + address: 0x041b + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + l1a_offset: + access: rw + address: 0x0413 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 10 + size_byte: 2 + l1a_to_hgcroc_out: + access: rw + address: 0x0413 + default_value: 7 + max_value: 31 + param_mask: 0x001f + param_shift: 0 + size_byte: 2 + match_threshold: + access: rw + address: 0x0415 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + pass_thru_mode: + access: rw + address: 0x0411 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 13 + size_byte: 2 + prediction_confidence: + access: ro + address: 0x041e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + prediction_delay_count: + access: ro + address: 0x041f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + simple_mode: + access: rw + address: 0x0411 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + status_bucket: + access: ro + address: 0x0445 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + status_event: + access: ro + address: 0x0448 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 46 + size_byte: 7 + status_fcmd: + access: ro + address: 0x0448 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 39 + size_byte: 7 + status_fifo_top_bucket: + access: ro + address: 0x0448 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 14 + size_byte: 7 + status_fifo_top_event: + access: ro + address: 0x0448 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 29 + size_byte: 7 + status_fifo_top_nzs: + access: ro + address: 0x0448 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 35 + size_byte: 7 + status_fifo_top_orbit: + access: ro + address: 0x0448 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 26 + size_byte: 7 + status_idle_word_marker: + access: ro + address: 0x0448 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 36 + size_byte: 7 + status_l1a_fifo_cnt: + access: ro + address: 0x0448 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 5 + size_byte: 7 + status_l1a_fifo_empty: + access: ro + address: 0x0448 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 7 + status_l1a_fifo_full: + access: ro + address: 0x0448 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 7 + status_orbit: + access: ro + address: 0x0448 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 0 + size_byte: 7 + status_pred_state: + access: ro + address: 0x0445 + default_value: 60 + max_value: 63 + param_mask: 0x003f + param_shift: 6 + size_byte: 3 + status_predict: + access: ro + address: 0x0448 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 7 + status_predict_hgcroc: + access: ro + address: 0x0448 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 13 + size_byte: 7 + status_roc_header_marker: + access: ro + address: 0x0448 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 37 + size_byte: 7 + status_roc_state: + access: ro + address: 0x0445 + default_value: 60 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 3 + strobes_start_ob_bist: + 3: + access: wo + address: 0x040f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + strobes_start_ping_pong_bist: + 1: + access: wo + address: 0x040f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + strobes_status_capture: + 2: + access: wo + address: 0x040f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + strobes_status_clear: + 0: + access: wo + address: 0x040f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + sync_body: + access: rw + address: 0x0417 + default_value: 178956970 + max_value: 268435455 + param_mask: 0xfffffff + param_shift: 0 + size_byte: 4 + sync_header: + access: rw + address: 0x041b + default_value: 10 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + tmr_err_cnt_roc_daq_ctrl: + access: ro + address: 0x044f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Watchdog: + 0: + count_erx_subp_crc: + access: ro + address: 0x0e03 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e4b + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e93 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e1b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e63 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0eab + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + count_erx_subp_crc: + access: ro + address: 0x0e05 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e4d + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e95 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e1f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e67 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0eaf + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + count_erx_subp_crc: + access: ro + address: 0x0e07 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e4f + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e97 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e23 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e6b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0eb3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + count_erx_subp_crc: + access: ro + address: 0x0e09 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e51 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e99 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e27 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e6f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0eb7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 4: + count_erx_subp_crc: + access: ro + address: 0x0e0b + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e53 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e9b + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e2b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e73 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ebb + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 5: + count_erx_subp_crc: + access: ro + address: 0x0e0d + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e55 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e9d + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e2f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e77 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ebf + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 6: + count_erx_subp_crc: + access: ro + address: 0x0e0f + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e57 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0e9f + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e33 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e7b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ec3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 7: + count_erx_subp_crc: + access: ro + address: 0x0e11 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e59 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0ea1 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e37 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e7f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ec7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 8: + count_erx_subp_crc: + access: ro + address: 0x0e13 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e5b + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0ea3 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e3b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e83 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ecb + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 9: + count_erx_subp_crc: + access: ro + address: 0x0e15 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e5d + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0ea5 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e3f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e87 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ecf + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 10: + count_erx_subp_crc: + access: ro + address: 0x0e17 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e5f + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0ea7 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e43 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e8b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ed3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 11: + count_erx_subp_crc: + access: ro + address: 0x0e19 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ebo: + access: ro + address: 0x0e61 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_subp_ht: + access: ro + address: 0x0ea9 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + history_erx_subp_crc: + access: ro + address: 0x0e47 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ebo: + access: ro + address: 0x0e8f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_subp_ht: + access: ro + address: 0x0ed7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + Global: + cap_clear: + access: wo + address: 0x0d55 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + capture: + access: wo + address: 0x0d55 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + clearing_fcmd_ctrl: + access: rw + address: 0x0d66 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + count_e_h_match: + access: ro + address: 0x0edf + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_ebo_recon: + access: ro + address: 0x0ee3 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_erx_ham: + 0: + access: ro + address: 0x0dbb + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 1: + access: ro + address: 0x0dbd + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 2: + access: ro + address: 0x0dbf + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 3: + access: ro + address: 0x0dc1 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 4: + access: ro + address: 0x0dc3 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 5: + access: ro + address: 0x0dc5 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 6: + access: ro + address: 0x0dc7 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 7: + access: ro + address: 0x0dc9 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 8: + access: ro + address: 0x0dcb + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 9: + access: ro + address: 0x0dcd + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 10: + access: ro + address: 0x0dcf + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + 11: + access: ro + address: 0x0dd1 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_event_unexpected: + access: ro + address: 0x0edd + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_ht_recon: + access: ro + address: 0x0ee1 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_packet_veto: + access: ro + address: 0x0edb + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_roc_bunch_counter: + access: ro + address: 0x0ee5 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_roc_l1a_fifo_full: + access: ro + address: 0x0eed + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_roc_missed_pkt: + access: ro + address: 0x0ee9 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_roc_predictor_fifo_full: + access: ro + address: 0x0eeb + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + count_roc_unused_state: + access: ro + address: 0x0ee7 + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + enable_erx_ham: + access: rw + address: 0x0d7f + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + enable_erx_subp_crc: + access: rw + address: 0x0d8d + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + enable_erx_subp_ebo: + access: rw + address: 0x0d9b + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + enable_erx_subp_ht: + access: rw + address: 0x0da9 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + enable_event_e_h_match: + access: rw + address: 0x0d6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + enable_event_ebo_recon: + access: rw + address: 0x0d6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + enable_event_ht_recon: + access: rw + address: 0x0d6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + enable_event_unexpected: + access: rw + address: 0x0d6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + enable_packet_veto: + access: rw + address: 0x0d6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_roc_bunch_counter: + access: rw + address: 0x0d72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_roc_l1a_fifo_full: + access: rw + address: 0x0d72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + enable_roc_missed_pkt: + access: rw + address: 0x0d72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + enable_roc_predictor_fifo_full: + access: rw + address: 0x0d72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + enable_roc_unused_state: + access: rw + address: 0x0d72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + erx_status: + 0: + access: ro + address: 0x0dab + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + 1: + access: ro + address: 0x0dab + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + 2: + access: ro + address: 0x0dac + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + 3: + access: ro + address: 0x0dac + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + 4: + access: ro + address: 0x0dad + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + 5: + access: ro + address: 0x0dad + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + 6: + access: ro + address: 0x0dae + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + 7: + access: ro + address: 0x0dae + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + 8: + access: ro + address: 0x0daf + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + 9: + access: ro + address: 0x0daf + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + 10: + access: ro + address: 0x0db0 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + 11: + access: ro + address: 0x0db0 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + event_status: + access: ro + address: 0x0db1 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 0 + size_byte: 2 + history_e_h_match: + access: ro + address: 0x0ef7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_erx_ham: + 0: + access: ro + address: 0x0dd3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: ro + address: 0x0dd7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: ro + address: 0x0ddb + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: ro + address: 0x0ddf + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 4: + access: ro + address: 0x0de3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 5: + access: ro + address: 0x0de7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 6: + access: ro + address: 0x0deb + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 7: + access: ro + address: 0x0def + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 8: + access: ro + address: 0x0df3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 9: + access: ro + address: 0x0df7 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 10: + access: ro + address: 0x0dfb + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 11: + access: ro + address: 0x0dff + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_event_unexpected: + access: ro + address: 0x0ef3 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_lsb_ebo_recon: + access: ro + address: 0x0f03 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_lsb_ht_recon: + access: ro + address: 0x0efb + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_msb_ebo_recon: + access: ro + address: 0x0f07 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_msb_ht_recon: + access: ro + address: 0x0eff + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_packet_veto: + access: ro + address: 0x0eef + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_roc_bunch_counter: + access: ro + address: 0x0f0b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_roc_l1a_fifo_full: + access: ro + address: 0x0f1b + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_roc_missed_pkt: + access: ro + address: 0x0f13 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_roc_predictor_fifo_full: + access: ro + address: 0x0f17 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + history_roc_unused_state: + access: ro + address: 0x0f0f + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + limit_erx_ham: + 0: + access: rw + address: 0x0d73 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x0d74 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x0d75 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0d76 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0d77 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0d78 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0d79 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: rw + address: 0x0d7a + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 8: + access: rw + address: 0x0d7b + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 9: + access: rw + address: 0x0d7c + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 10: + access: rw + address: 0x0d7d + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 11: + access: rw + address: 0x0d7e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_erx_subp_crc: + 0: + access: rw + address: 0x0d81 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x0d82 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x0d83 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0d84 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0d85 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0d86 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0d87 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: rw + address: 0x0d88 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 8: + access: rw + address: 0x0d89 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 9: + access: rw + address: 0x0d8a + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 10: + access: rw + address: 0x0d8b + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 11: + access: rw + address: 0x0d8c + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_erx_subp_ebo: + 0: + access: rw + address: 0x0d8f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x0d90 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x0d91 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0d92 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0d93 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0d94 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0d95 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: rw + address: 0x0d96 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 8: + access: rw + address: 0x0d97 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 9: + access: rw + address: 0x0d98 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 10: + access: rw + address: 0x0d99 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 11: + access: rw + address: 0x0d9a + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_erx_subp_ht: + 0: + access: rw + address: 0x0d9d + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x0d9e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x0d9f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0da0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0da1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0da2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0da3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: rw + address: 0x0da4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 8: + access: rw + address: 0x0da5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 9: + access: rw + address: 0x0da6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 10: + access: rw + address: 0x0da7 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 11: + access: rw + address: 0x0da8 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_event_e_h_match: + access: rw + address: 0x0d69 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_event_ebo_recon: + access: rw + address: 0x0d6b + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_event_ht_recon: + access: rw + address: 0x0d6a + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_event_unexpected: + access: rw + address: 0x0d68 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_packet_veto: + access: rw + address: 0x0d67 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_roc_bunch_counter: + access: rw + address: 0x0d6d + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_roc_l1a_fifo_full: + access: rw + address: 0x0d71 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_roc_missed_pkt: + access: rw + address: 0x0d6f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_roc_predictor_fifo_full: + access: rw + address: 0x0d70 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + limit_roc_unused_state: + access: rw + address: 0x0d6e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + persistent: + access: ro + address: 0x0db3 + default_value: 0 + max_value: 18446744073709551615 + param_mask: 0xffffffffffffffff + param_shift: 0 + size_byte: 8 + req_clear: + access: wo + address: 0x0d55 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + roc_daq: + access: ro + address: 0x0db1 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 5 + size_byte: 2 + rst_req_a: + access: rw + address: 0x0d56 + default_value: 0 + max_value: 288230376151711743 + param_mask: 0x3ffffffffffffff + param_shift: 0 + size_byte: 8 + rst_req_b: + access: rw + address: 0x0d5e + default_value: 0 + max_value: 288230376151711743 + param_mask: 0x3ffffffffffffff + param_shift: 0 + size_byte: 8 + tmr_err_cnt_reset_request: + access: ro + address: 0x0f1f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +ZS: + 0: + zs_c_i: + 0: + access: rw + address: 0x04a7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x04aa + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x04ad + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x04b0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x04b3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x04b6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x04b9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x04bc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x04bf + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x04c2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x04c5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x04c8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x04cb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x04ce + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x04d1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x04d4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x04d7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x04da + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x04dd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x04e0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x04e3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x04e6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x04e9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x04ec + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x04ef + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x04f2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x04f5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x04f8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x04fb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x04fe + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x0501 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x0504 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x0507 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x050a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x050d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x0510 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x0513 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x04a7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x04aa + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x04ad + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x04b0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x04b3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x04b6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x04b9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x04bc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x04bf + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x04c2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x04c5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x04c8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x04cb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x04ce + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x04d1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x04d4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x04d7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x04da + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x04dd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x04e0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x04e3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x04e6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x04e9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x04ec + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x04ef + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x04f2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x04f5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x04f8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x04fb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x04fe + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x0501 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x0504 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x0507 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x050a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x050d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x0510 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x0513 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x04a7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x04aa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x04ad + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x04b0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x04b3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x04b6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x04b9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x04bc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x04bf + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x04c2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x04c5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x04c8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x04cb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x04ce + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x04d1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x04d4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x04d7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x04da + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x04dd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x04e0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x04e3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x04e6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x04e9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x04ec + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x04ef + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x04f2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x04f5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x04f8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x04fb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x04fe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x0501 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x0504 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x0507 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x050a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x050d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x0510 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x0513 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x04a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x04aa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x04ad + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x04b0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x04b3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x04b6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x04b9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x04bc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x04bf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x04c2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x04c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x04c8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x04cb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x04ce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x04d1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x04d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x04d7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x04da + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x04dd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x04e0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x04e3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x04e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x04e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x04ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x04ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x04f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x04f5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x04f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x04fb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x04fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x0501 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x0504 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x0507 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x050a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x050d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x0510 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x0513 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x04a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x04aa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x04ad + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x04b0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x04b3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x04b6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x04b9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x04bc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x04bf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x04c2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x04c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x04c8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x04cb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x04ce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x04d1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x04d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x04d7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x04da + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x04dd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x04e0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x04e3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x04e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x04e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x04ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x04ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x04f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x04f5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x04f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x04fb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x04fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x0501 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x0504 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x0507 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x050a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x050d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x0510 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x0513 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + zs_c_i: + 0: + access: rw + address: 0x0516 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0519 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x051c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x051f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x0522 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x0525 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x0528 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x052b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x052e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x0531 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x0534 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x0537 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x053a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x053d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x0540 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x0543 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x0546 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0549 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x054c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x054f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x0552 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x0555 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x0558 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x055b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x055e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x0561 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x0564 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x0567 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x056a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x056d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x0570 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x0573 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x0576 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x0579 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x057c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x057f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x0582 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x0516 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0519 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x051c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x051f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x0522 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x0525 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x0528 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x052b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x052e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x0531 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x0534 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x0537 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x053a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x053d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x0540 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x0543 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x0546 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0549 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x054c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x054f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x0552 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x0555 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x0558 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x055b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x055e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x0561 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x0564 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x0567 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x056a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x056d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x0570 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x0573 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x0576 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x0579 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x057c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x057f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x0582 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x0516 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0519 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x051c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x051f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x0522 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x0525 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x0528 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x052b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x052e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x0531 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x0534 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x0537 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x053a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x053d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x0540 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x0543 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x0546 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0549 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x054c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x054f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x0552 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x0555 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x0558 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x055b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x055e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x0561 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x0564 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x0567 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x056a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x056d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x0570 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x0573 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x0576 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0579 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x057c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x057f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x0582 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x0516 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0519 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x051c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x051f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x0522 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x0525 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x0528 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x052b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x052e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x0531 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x0534 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x0537 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x053a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x053d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x0540 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x0543 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x0546 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0549 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x054c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x054f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x0552 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x0555 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x0558 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x055b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x055e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x0561 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x0564 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x0567 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x056a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x056d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x0570 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x0573 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x0576 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x0579 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x057c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x057f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x0582 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x0516 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0519 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x051c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x051f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x0522 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x0525 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x0528 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x052b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x052e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x0531 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x0534 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x0537 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x053a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x053d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x0540 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x0543 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x0546 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0549 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x054c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x054f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x0552 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x0555 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x0558 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x055b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x055e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x0561 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x0564 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x0567 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x056a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x056d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x0570 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x0573 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x0576 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x0579 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x057c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x057f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x0582 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + zs_c_i: + 0: + access: rw + address: 0x0585 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0588 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x058b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x058e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x0591 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x0594 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x0597 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x059a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x059d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x05a0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x05a3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x05a6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x05a9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x05ac + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x05af + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x05b2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x05b5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x05b8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x05bb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x05be + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x05c1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x05c4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x05c7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x05ca + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x05cd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x05d0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x05d3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x05d6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x05d9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x05dc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x05df + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x05e2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x05e5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x05e8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x05eb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x05ee + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x05f1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x0585 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0588 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x058b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x058e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x0591 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x0594 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x0597 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x059a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x059d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x05a0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x05a3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x05a6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x05a9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x05ac + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x05af + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x05b2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x05b5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x05b8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x05bb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x05be + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x05c1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x05c4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x05c7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x05ca + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x05cd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x05d0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x05d3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x05d6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x05d9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x05dc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x05df + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x05e2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x05e5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x05e8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x05eb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x05ee + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x05f1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x0585 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0588 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x058b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x058e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x0591 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x0594 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x0597 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x059a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x059d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x05a0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x05a3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x05a6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x05a9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x05ac + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x05af + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x05b2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x05b5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x05b8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x05bb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x05be + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x05c1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x05c4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x05c7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x05ca + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x05cd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x05d0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x05d3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x05d6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x05d9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x05dc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x05df + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x05e2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x05e5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x05e8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x05eb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x05ee + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x05f1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x0585 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0588 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x058b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x058e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x0591 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x0594 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x0597 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x059a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x059d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x05a0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x05a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x05a6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x05a9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x05ac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x05af + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x05b2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x05b5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x05b8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x05bb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x05be + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x05c1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x05c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x05c7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x05ca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x05cd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x05d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x05d3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x05d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x05d9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x05dc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x05df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x05e2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x05e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x05e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x05eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x05ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x05f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x0585 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0588 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x058b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x058e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x0591 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x0594 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x0597 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x059a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x059d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x05a0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x05a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x05a6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x05a9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x05ac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x05af + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x05b2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x05b5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x05b8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x05bb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x05be + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x05c1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x05c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x05c7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x05ca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x05cd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x05d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x05d3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x05d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x05d9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x05dc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x05df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x05e2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x05e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x05e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x05eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x05ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x05f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + zs_c_i: + 0: + access: rw + address: 0x05f4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x05f7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x05fa + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x05fd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x0600 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x0603 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x0606 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x0609 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x060c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x060f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x0612 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x0615 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x0618 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x061b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x061e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x0621 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x0624 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0627 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x062a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x062d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x0630 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x0633 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x0636 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x0639 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x063c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x063f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x0642 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x0645 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x0648 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x064b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x064e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x0651 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x0654 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x0657 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x065a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x065d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x0660 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x05f4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x05f7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x05fa + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x05fd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x0600 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x0603 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x0606 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x0609 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x060c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x060f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x0612 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x0615 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x0618 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x061b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x061e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x0621 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x0624 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0627 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x062a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x062d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x0630 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x0633 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x0636 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x0639 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x063c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x063f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x0642 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x0645 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x0648 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x064b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x064e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x0651 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x0654 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x0657 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x065a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x065d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x0660 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x05f4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x05f7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x05fa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x05fd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x0600 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x0603 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x0606 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x0609 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x060c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x060f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x0612 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x0615 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x0618 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x061b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x061e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x0621 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x0624 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0627 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x062a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x062d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x0630 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x0633 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x0636 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x0639 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x063c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x063f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x0642 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x0645 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0648 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x064b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x064e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x0651 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x0654 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0657 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x065a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x065d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x0660 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x05f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x05f7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x05fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x05fd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x0600 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x0603 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x0606 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x0609 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x060c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x060f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x0612 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x0615 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x0618 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x061b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x061e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x0621 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x0624 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0627 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x062a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x062d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x0630 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x0633 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x0636 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x0639 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x063c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x063f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x0642 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x0645 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x0648 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x064b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x064e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x0651 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x0654 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x0657 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x065a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x065d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x0660 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x05f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x05f7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x05fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x05fd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x0600 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x0603 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x0606 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x0609 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x060c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x060f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x0612 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x0615 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x0618 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x061b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x061e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x0621 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x0624 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0627 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x062a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x062d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x0630 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x0633 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x0636 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x0639 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x063c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x063f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x0642 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x0645 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x0648 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x064b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x064e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x0651 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x0654 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x0657 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x065a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x065d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x0660 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + zs_c_i: + 0: + access: rw + address: 0x0663 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0666 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x0669 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x066c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x066f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x0672 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x0675 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x0678 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x067b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x067e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x0681 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x0684 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x0687 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x068a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x068d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x0690 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x0693 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0696 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x0699 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x069c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x069f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x06a2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x06a5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x06a8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x06ab + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x06ae + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x06b1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x06b4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x06b7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x06ba + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x06bd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x06c0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x06c3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x06c6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x06c9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x06cc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x06cf + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x0663 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0666 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x0669 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x066c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x066f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x0672 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x0675 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x0678 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x067b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x067e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x0681 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x0684 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x0687 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x068a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x068d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x0690 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x0693 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0696 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x0699 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x069c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x069f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x06a2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x06a5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x06a8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x06ab + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x06ae + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x06b1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x06b4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x06b7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x06ba + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x06bd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x06c0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x06c3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x06c6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x06c9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x06cc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x06cf + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x0663 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0666 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x0669 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x066c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x066f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x0672 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x0675 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x0678 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x067b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x067e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x0681 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x0684 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x0687 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x068a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x068d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x0690 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x0693 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0696 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x0699 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x069c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x069f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x06a2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x06a5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x06a8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x06ab + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x06ae + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x06b1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x06b4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x06b7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x06ba + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x06bd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x06c0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x06c3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x06c6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x06c9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x06cc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x06cf + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x0663 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0666 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x0669 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x066c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x066f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x0672 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x0675 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x0678 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x067b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x067e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x0681 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x0684 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x0687 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x068a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x068d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x0690 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x0693 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0696 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x0699 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x069c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x069f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x06a2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x06a5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x06a8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x06ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x06ae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x06b1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x06b4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x06b7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x06ba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x06bd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x06c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x06c3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x06c6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x06c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x06cc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x06cf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x0663 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0666 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x0669 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x066c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x066f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x0672 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x0675 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x0678 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x067b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x067e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x0681 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x0684 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x0687 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x068a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x068d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x0690 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x0693 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0696 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x0699 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x069c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x069f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x06a2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x06a5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x06a8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x06ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x06ae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x06b1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x06b4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x06b7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x06ba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x06bd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x06c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x06c3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x06c6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x06c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x06cc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x06cf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + zs_c_i: + 0: + access: rw + address: 0x06d2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x06d5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x06d8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x06db + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x06de + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x06e1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x06e4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x06e7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x06ea + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x06ed + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x06f0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x06f3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x06f6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x06f9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x06fc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x06ff + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x0702 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0705 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x0708 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x070b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x070e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x0711 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x0714 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x0717 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x071a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x071d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x0720 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x0723 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x0726 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x0729 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x072c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x072f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x0732 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x0735 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x0738 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x073b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x073e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x06d2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x06d5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x06d8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x06db + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x06de + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x06e1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x06e4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x06e7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x06ea + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x06ed + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x06f0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x06f3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x06f6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x06f9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x06fc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x06ff + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x0702 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0705 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x0708 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x070b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x070e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x0711 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x0714 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x0717 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x071a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x071d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x0720 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x0723 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x0726 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x0729 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x072c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x072f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x0732 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x0735 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x0738 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x073b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x073e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x06d2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x06d5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x06d8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x06db + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x06de + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x06e1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x06e4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x06e7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x06ea + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x06ed + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x06f0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x06f3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x06f6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x06f9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x06fc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x06ff + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x0702 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0705 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x0708 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x070b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x070e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x0711 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x0714 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x0717 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x071a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x071d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x0720 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x0723 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0726 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x0729 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x072c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x072f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x0732 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0735 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x0738 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x073b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x073e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x06d2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x06d5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x06d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x06db + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x06de + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x06e1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x06e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x06e7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x06ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x06ed + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x06f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x06f3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x06f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x06f9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x06fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x06ff + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x0702 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0705 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x0708 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x070b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x070e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x0711 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x0714 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x0717 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x071a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x071d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x0720 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x0723 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x0726 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x0729 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x072c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x072f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x0732 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x0735 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x0738 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x073b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x073e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x06d2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x06d5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x06d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x06db + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x06de + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x06e1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x06e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x06e7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x06ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x06ed + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x06f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x06f3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x06f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x06f9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x06fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x06ff + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x0702 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0705 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x0708 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x070b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x070e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x0711 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x0714 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x0717 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x071a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x071d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x0720 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x0723 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x0726 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x0729 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x072c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x072f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x0732 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x0735 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x0738 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x073b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x073e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + zs_c_i: + 0: + access: rw + address: 0x0741 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0744 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x0747 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x074a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x074d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x0750 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x0753 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x0756 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x0759 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x075c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x075f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x0762 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x0765 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x0768 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x076b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x076e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x0771 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0774 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x0777 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x077a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x077d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x0780 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x0783 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x0786 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x0789 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x078c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x078f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x0792 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x0795 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x0798 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x079b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x079e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x07a1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x07a4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x07a7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x07aa + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x07ad + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x0741 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0744 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x0747 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x074a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x074d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x0750 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x0753 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x0756 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x0759 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x075c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x075f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x0762 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x0765 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x0768 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x076b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x076e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x0771 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0774 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x0777 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x077a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x077d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x0780 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x0783 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x0786 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x0789 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x078c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x078f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x0792 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x0795 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x0798 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x079b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x079e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x07a1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x07a4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x07a7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x07aa + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x07ad + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x0741 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0744 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x0747 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x074a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x074d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x0750 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x0753 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x0756 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x0759 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x075c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x075f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x0762 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x0765 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x0768 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x076b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x076e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x0771 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0774 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x0777 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x077a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x077d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x0780 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x0783 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x0786 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x0789 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x078c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x078f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x0792 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0795 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x0798 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x079b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x079e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x07a1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x07a4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x07a7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x07aa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x07ad + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x0741 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0744 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x0747 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x074a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x074d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x0750 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x0753 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x0756 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x0759 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x075c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x075f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x0762 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x0765 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x0768 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x076b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x076e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x0771 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0774 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x0777 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x077a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x077d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x0780 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x0783 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x0786 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x0789 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x078c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x078f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x0792 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x0795 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x0798 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x079b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x079e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x07a1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x07a4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x07a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x07aa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x07ad + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x0741 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0744 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x0747 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x074a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x074d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x0750 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x0753 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x0756 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x0759 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x075c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x075f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x0762 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x0765 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x0768 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x076b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x076e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x0771 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0774 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x0777 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x077a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x077d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x0780 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x0783 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x0786 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x0789 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x078c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x078f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x0792 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x0795 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x0798 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x079b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x079e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x07a1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x07a4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x07a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x07aa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x07ad + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + zs_c_i: + 0: + access: rw + address: 0x07b0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x07b3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x07b6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x07b9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x07bc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x07bf + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x07c2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x07c5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x07c8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x07cb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x07ce + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x07d1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x07d4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x07d7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x07da + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x07dd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x07e0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x07e3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x07e6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x07e9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x07ec + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x07ef + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x07f2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x07f5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x07f8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x07fb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x07fe + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x0801 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x0804 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x0807 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x080a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x080d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x0810 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x0813 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x0816 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x0819 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x081c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x07b0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x07b3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x07b6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x07b9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x07bc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x07bf + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x07c2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x07c5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x07c8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x07cb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x07ce + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x07d1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x07d4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x07d7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x07da + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x07dd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x07e0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x07e3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x07e6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x07e9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x07ec + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x07ef + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x07f2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x07f5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x07f8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x07fb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x07fe + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x0801 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x0804 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x0807 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x080a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x080d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x0810 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x0813 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x0816 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x0819 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x081c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x07b0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x07b3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x07b6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x07b9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x07bc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x07bf + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x07c2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x07c5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x07c8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x07cb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x07ce + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x07d1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x07d4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x07d7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x07da + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x07dd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x07e0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x07e3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x07e6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x07e9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x07ec + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x07ef + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x07f2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x07f5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x07f8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x07fb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x07fe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x0801 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0804 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x0807 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x080a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x080d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x0810 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0813 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x0816 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x0819 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x081c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x07b0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x07b3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x07b6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x07b9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x07bc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x07bf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x07c2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x07c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x07c8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x07cb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x07ce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x07d1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x07d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x07d7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x07da + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x07dd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x07e0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x07e3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x07e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x07e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x07ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x07ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x07f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x07f5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x07f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x07fb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x07fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x0801 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x0804 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x0807 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x080a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x080d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x0810 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x0813 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x0816 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x0819 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x081c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x07b0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x07b3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x07b6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x07b9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x07bc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x07bf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x07c2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x07c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x07c8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x07cb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x07ce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x07d1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x07d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x07d7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x07da + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x07dd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x07e0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x07e3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x07e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x07e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x07ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x07ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x07f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x07f5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x07f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x07fb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x07fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x0801 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x0804 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x0807 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x080a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x080d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x0810 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x0813 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x0816 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x0819 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x081c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + zs_c_i: + 0: + access: rw + address: 0x081f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0822 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x0825 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x0828 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x082b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x082e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x0831 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x0834 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x0837 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x083a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x083d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x0840 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x0843 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x0846 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x0849 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x084c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x084f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0852 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x0855 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x0858 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x085b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x085e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x0861 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x0864 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x0867 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x086a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x086d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x0870 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x0873 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x0876 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x0879 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x087c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x087f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x0882 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x0885 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x0888 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x088b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x081f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0822 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x0825 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x0828 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x082b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x082e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x0831 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x0834 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x0837 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x083a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x083d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x0840 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x0843 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x0846 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x0849 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x084c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x084f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0852 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x0855 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x0858 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x085b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x085e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x0861 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x0864 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x0867 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x086a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x086d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x0870 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x0873 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x0876 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x0879 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x087c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x087f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x0882 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x0885 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x0888 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x088b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x081f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0822 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x0825 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x0828 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x082b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x082e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x0831 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x0834 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x0837 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x083a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x083d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x0840 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x0843 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x0846 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x0849 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x084c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x084f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0852 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x0855 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x0858 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x085b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x085e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x0861 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x0864 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x0867 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x086a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x086d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x0870 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0873 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x0876 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x0879 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x087c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x087f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0882 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x0885 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x0888 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x088b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x081f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0822 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x0825 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x0828 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x082b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x082e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x0831 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x0834 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x0837 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x083a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x083d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x0840 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x0843 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x0846 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x0849 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x084c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x084f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0852 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x0855 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x0858 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x085b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x085e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x0861 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x0864 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x0867 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x086a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x086d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x0870 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x0873 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x0876 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x0879 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x087c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x087f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x0882 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x0885 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x0888 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x088b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x081f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0822 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x0825 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x0828 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x082b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x082e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x0831 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x0834 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x0837 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x083a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x083d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x0840 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x0843 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x0846 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x0849 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x084c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x084f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0852 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x0855 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x0858 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x085b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x085e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x0861 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x0864 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x0867 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x086a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x086d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x0870 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x0873 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x0876 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x0879 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x087c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x087f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x0882 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x0885 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x0888 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x088b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + zs_c_i: + 0: + access: rw + address: 0x088e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0891 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x0894 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x0897 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x089a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x089d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x08a0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x08a3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x08a6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x08a9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x08ac + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x08af + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x08b2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x08b5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x08b8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x08bb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x08be + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x08c1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x08c4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x08c7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x08ca + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x08cd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x08d0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x08d3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x08d6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x08d9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x08dc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x08df + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x08e2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x08e5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x08e8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x08eb + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x08ee + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x08f1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x08f4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x08f7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x08fa + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x088e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0891 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x0894 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x0897 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x089a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x089d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x08a0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x08a3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x08a6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x08a9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x08ac + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x08af + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x08b2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x08b5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x08b8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x08bb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x08be + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x08c1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x08c4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x08c7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x08ca + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x08cd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x08d0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x08d3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x08d6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x08d9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x08dc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x08df + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x08e2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x08e5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x08e8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x08eb + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x08ee + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x08f1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x08f4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x08f7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x08fa + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x088e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0891 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x0894 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x0897 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x089a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x089d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x08a0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x08a3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x08a6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x08a9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x08ac + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x08af + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x08b2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x08b5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x08b8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x08bb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x08be + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x08c1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x08c4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x08c7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x08ca + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x08cd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x08d0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x08d3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x08d6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x08d9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x08dc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x08df + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x08e2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x08e5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x08e8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x08eb + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x08ee + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x08f1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x08f4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x08f7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x08fa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x088e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0891 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x0894 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x0897 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x089a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x089d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x08a0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x08a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x08a6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x08a9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x08ac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x08af + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x08b2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x08b5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x08b8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x08bb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x08be + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x08c1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x08c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x08c7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x08ca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x08cd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x08d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x08d3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x08d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x08d9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x08dc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x08df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x08e2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x08e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x08e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x08eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x08ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x08f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x08f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x08f7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x08fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x088e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0891 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x0894 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x0897 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x089a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x089d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x08a0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x08a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x08a6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x08a9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x08ac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x08af + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x08b2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x08b5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x08b8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x08bb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x08be + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x08c1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x08c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x08c7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x08ca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x08cd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x08d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x08d3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x08d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x08d9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x08dc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x08df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x08e2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x08e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x08e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x08eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x08ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x08f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x08f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x08f7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x08fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + zs_c_i: + 0: + access: rw + address: 0x08fd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x0900 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x0903 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x0906 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x0909 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x090c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x090f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x0912 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x0915 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x0918 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x091b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x091e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x0921 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x0924 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x0927 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x092a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x092d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x0930 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x0933 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x0936 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x0939 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x093c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x093f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x0942 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x0945 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x0948 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x094b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x094e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x0951 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x0954 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x0957 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x095a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x095d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x0960 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x0963 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x0966 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x0969 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x08fd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x0900 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x0903 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x0906 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x0909 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x090c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x090f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x0912 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x0915 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x0918 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x091b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x091e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x0921 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x0924 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x0927 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x092a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x092d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x0930 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x0933 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x0936 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x0939 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x093c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x093f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x0942 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x0945 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x0948 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x094b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x094e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x0951 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x0954 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x0957 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x095a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x095d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x0960 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x0963 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x0966 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x0969 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x08fd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x0900 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x0903 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x0906 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x0909 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x090c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x090f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x0912 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x0915 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x0918 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x091b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x091e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x0921 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x0924 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x0927 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x092a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x092d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x0930 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x0933 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x0936 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x0939 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x093c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x093f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x0942 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x0945 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x0948 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x094b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x094e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0951 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x0954 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x0957 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x095a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x095d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0960 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x0963 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x0966 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x0969 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x08fd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x0900 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x0903 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x0906 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x0909 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x090c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x090f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x0912 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x0915 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x0918 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x091b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x091e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x0921 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x0924 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x0927 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x092a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x092d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x0930 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x0933 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x0936 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x0939 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x093c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x093f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x0942 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x0945 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x0948 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x094b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x094e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x0951 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x0954 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x0957 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x095a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x095d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x0960 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x0963 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x0966 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x0969 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x08fd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x0900 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x0903 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x0906 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x0909 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x090c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x090f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x0912 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x0915 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x0918 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x091b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x091e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x0921 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x0924 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x0927 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x092a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x092d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x0930 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x0933 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x0936 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x0939 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x093c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x093f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x0942 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x0945 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x0948 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x094b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x094e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x0951 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x0954 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x0957 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x095a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x095d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x0960 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x0963 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x0966 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x0969 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + zs_c_i: + 0: + access: rw + address: 0x096c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 1: + access: rw + address: 0x096f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 2: + access: rw + address: 0x0972 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 3: + access: rw + address: 0x0975 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 4: + access: rw + address: 0x0978 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 5: + access: rw + address: 0x097b + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 6: + access: rw + address: 0x097e + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 7: + access: rw + address: 0x0981 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 8: + access: rw + address: 0x0984 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 9: + access: rw + address: 0x0987 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 10: + access: rw + address: 0x098a + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 11: + access: rw + address: 0x098d + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 12: + access: rw + address: 0x0990 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 13: + access: rw + address: 0x0993 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 14: + access: rw + address: 0x0996 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 15: + access: rw + address: 0x0999 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 16: + access: rw + address: 0x099c + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 17: + access: rw + address: 0x099f + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 18: + access: rw + address: 0x09a2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 19: + access: rw + address: 0x09a5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 20: + access: rw + address: 0x09a8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 21: + access: rw + address: 0x09ab + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 22: + access: rw + address: 0x09ae + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 23: + access: rw + address: 0x09b1 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 24: + access: rw + address: 0x09b4 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 25: + access: rw + address: 0x09b7 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 26: + access: rw + address: 0x09ba + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 27: + access: rw + address: 0x09bd + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 28: + access: rw + address: 0x09c0 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 29: + access: rw + address: 0x09c3 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 30: + access: rw + address: 0x09c6 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 31: + access: rw + address: 0x09c9 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 32: + access: rw + address: 0x09cc + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 33: + access: rw + address: 0x09cf + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 34: + access: rw + address: 0x09d2 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 35: + access: rw + address: 0x09d5 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + 36: + access: rw + address: 0x09d8 + default_value: 255 + max_value: 255 + param_mask: 0x00ff + param_shift: 13 + size_byte: 3 + zs_kappa: + 0: + access: rw + address: 0x096c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 1: + access: rw + address: 0x096f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 2: + access: rw + address: 0x0972 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 3: + access: rw + address: 0x0975 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 4: + access: rw + address: 0x0978 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 5: + access: rw + address: 0x097b + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 6: + access: rw + address: 0x097e + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 7: + access: rw + address: 0x0981 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 8: + access: rw + address: 0x0984 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 9: + access: rw + address: 0x0987 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 10: + access: rw + address: 0x098a + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 11: + access: rw + address: 0x098d + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 12: + access: rw + address: 0x0990 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 13: + access: rw + address: 0x0993 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 14: + access: rw + address: 0x0996 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 15: + access: rw + address: 0x0999 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 16: + access: rw + address: 0x099c + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 17: + access: rw + address: 0x099f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 18: + access: rw + address: 0x09a2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 19: + access: rw + address: 0x09a5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 20: + access: rw + address: 0x09a8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 21: + access: rw + address: 0x09ab + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 22: + access: rw + address: 0x09ae + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 23: + access: rw + address: 0x09b1 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 24: + access: rw + address: 0x09b4 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 25: + access: rw + address: 0x09b7 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 26: + access: rw + address: 0x09ba + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 27: + access: rw + address: 0x09bd + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 28: + access: rw + address: 0x09c0 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 29: + access: rw + address: 0x09c3 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 30: + access: rw + address: 0x09c6 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 31: + access: rw + address: 0x09c9 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 32: + access: rw + address: 0x09cc + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 33: + access: rw + address: 0x09cf + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 34: + access: rw + address: 0x09d2 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 35: + access: rw + address: 0x09d5 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + 36: + access: rw + address: 0x09d8 + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 7 + size_byte: 3 + zs_lambda: + 0: + access: rw + address: 0x096c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x096f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x0972 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x0975 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x0978 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x097b + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x097e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x0981 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x0984 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x0987 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x098a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x098d + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x0990 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x0993 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x0996 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x0999 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x099c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x099f + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x09a2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x09a5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x09a8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x09ab + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x09ae + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x09b1 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x09b4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x09b7 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x09ba + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x09bd + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x09c0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x09c3 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x09c6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x09c9 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x09cc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x09cf + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x09d2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x09d5 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x09d8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 3 + zs_mask_i: + 0: + access: rw + address: 0x096c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 1: + access: rw + address: 0x096f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 2: + access: rw + address: 0x0972 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 3: + access: rw + address: 0x0975 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 4: + access: rw + address: 0x0978 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 5: + access: rw + address: 0x097b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 6: + access: rw + address: 0x097e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 7: + access: rw + address: 0x0981 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 8: + access: rw + address: 0x0984 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 9: + access: rw + address: 0x0987 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 10: + access: rw + address: 0x098a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 11: + access: rw + address: 0x098d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 12: + access: rw + address: 0x0990 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 13: + access: rw + address: 0x0993 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 14: + access: rw + address: 0x0996 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 15: + access: rw + address: 0x0999 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 16: + access: rw + address: 0x099c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 17: + access: rw + address: 0x099f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 18: + access: rw + address: 0x09a2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 19: + access: rw + address: 0x09a5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 20: + access: rw + address: 0x09a8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 21: + access: rw + address: 0x09ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 22: + access: rw + address: 0x09ae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 23: + access: rw + address: 0x09b1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 24: + access: rw + address: 0x09b4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 25: + access: rw + address: 0x09b7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 26: + access: rw + address: 0x09ba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 27: + access: rw + address: 0x09bd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 28: + access: rw + address: 0x09c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 29: + access: rw + address: 0x09c3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 30: + access: rw + address: 0x09c6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 31: + access: rw + address: 0x09c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 32: + access: rw + address: 0x09cc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 33: + access: rw + address: 0x09cf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 34: + access: rw + address: 0x09d2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 35: + access: rw + address: 0x09d5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + 36: + access: rw + address: 0x09d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 22 + size_byte: 3 + zs_pass_i: + 0: + access: rw + address: 0x096c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 1: + access: rw + address: 0x096f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 2: + access: rw + address: 0x0972 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 3: + access: rw + address: 0x0975 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 4: + access: rw + address: 0x0978 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 5: + access: rw + address: 0x097b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 6: + access: rw + address: 0x097e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 7: + access: rw + address: 0x0981 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 8: + access: rw + address: 0x0984 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 9: + access: rw + address: 0x0987 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 10: + access: rw + address: 0x098a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 11: + access: rw + address: 0x098d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 12: + access: rw + address: 0x0990 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 13: + access: rw + address: 0x0993 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 14: + access: rw + address: 0x0996 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 15: + access: rw + address: 0x0999 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 16: + access: rw + address: 0x099c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 17: + access: rw + address: 0x099f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 18: + access: rw + address: 0x09a2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 19: + access: rw + address: 0x09a5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 20: + access: rw + address: 0x09a8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 21: + access: rw + address: 0x09ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 22: + access: rw + address: 0x09ae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 23: + access: rw + address: 0x09b1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 24: + access: rw + address: 0x09b4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 25: + access: rw + address: 0x09b7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 26: + access: rw + address: 0x09ba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 27: + access: rw + address: 0x09bd + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 28: + access: rw + address: 0x09c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 29: + access: rw + address: 0x09c3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 30: + access: rw + address: 0x09c6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 31: + access: rw + address: 0x09c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 32: + access: rw + address: 0x09cc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 33: + access: rw + address: 0x09cf + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 34: + access: rw + address: 0x09d2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 35: + access: rw + address: 0x09d5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + 36: + access: rw + address: 0x09d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 21 + size_byte: 3 + Global: + tmr_err_cnt_zero_suppress: + access: ro + address: 0x09db + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +ZSCommon: + Global: + zs_ce: + access: rw + address: 0x04a5 + default_value: 0 + max_value: 1023 + param_mask: 0x03ff + param_shift: 0 + size_byte: 2 +ZSmOne: + 0: + zs_beta_m: + 0: + access: rw + address: 0x09dc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x09de + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x09e0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x09e2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x09e4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x09e6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x09e8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x09ea + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x09ec + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x09ee + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x09f0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x09f2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x09f4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x09f6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x09f8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x09fa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x09fc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x09fe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0a00 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0a02 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0a04 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0a06 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0a08 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0a0a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0a0c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0a0e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0a10 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0a12 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0a14 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0a16 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0a18 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0a1a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0a1c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0a1e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0a20 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0a22 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0a24 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x09dc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x09de + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x09e0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x09e2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x09e4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x09e6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x09e8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x09ea + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x09ec + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x09ee + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x09f0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x09f2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x09f4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x09f6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x09f8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x09fa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x09fc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x09fe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0a00 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0a02 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0a04 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0a06 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0a08 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0a0a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0a0c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0a0e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0a10 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0a12 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0a14 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0a16 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0a18 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0a1a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0a1c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0a1e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0a20 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0a22 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0a24 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x09dc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x09de + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x09e0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x09e2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x09e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x09e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x09e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x09ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x09ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x09ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x09f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x09f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x09f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x09f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x09f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x09fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x09fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x09fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0a00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0a02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0a04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0a06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0a08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0a0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0a0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0a0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0a10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0a12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0a14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0a16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0a18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0a1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0a1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0a1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0a20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0a22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0a24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x09dc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x09de + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x09e0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x09e2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x09e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x09e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x09e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x09ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x09ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x09ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x09f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x09f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x09f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x09f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x09f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x09fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x09fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x09fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0a00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0a02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0a04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0a06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0a08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0a0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0a0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0a0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0a10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0a12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0a14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0a16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0a18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0a1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0a1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0a1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0a20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0a22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0a24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + zs_beta_m: + 0: + access: rw + address: 0x0a26 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0a28 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0a2a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0a2c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0a2e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0a30 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0a32 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0a34 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0a36 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0a38 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0a3a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0a3c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0a3e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0a40 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0a42 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0a44 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0a46 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0a48 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0a4a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0a4c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0a4e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0a50 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0a52 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0a54 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0a56 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0a58 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0a5a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0a5c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0a5e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0a60 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0a62 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0a64 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0a66 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0a68 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0a6a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0a6c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0a6e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0a26 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0a28 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0a2a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0a2c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0a2e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0a30 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0a32 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0a34 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0a36 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0a38 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0a3a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0a3c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0a3e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0a40 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0a42 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0a44 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0a46 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0a48 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0a4a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0a4c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0a4e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0a50 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0a52 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0a54 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0a56 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0a58 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0a5a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0a5c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0a5e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0a60 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0a62 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0a64 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0a66 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0a68 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0a6a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0a6c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0a6e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0a26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0a28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0a2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0a2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0a2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0a30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0a32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0a34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0a36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0a38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0a3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0a3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0a3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0a40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0a42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0a44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0a46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0a48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0a4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0a4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0a4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0a50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0a52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0a54 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0a56 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0a58 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0a5a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0a5c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0a5e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0a60 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0a62 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0a64 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0a66 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0a68 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0a6a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0a6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0a6e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0a26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0a28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0a2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0a2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0a2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0a30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0a32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0a34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0a36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0a38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0a3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0a3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0a3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0a40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0a42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0a44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0a46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0a48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0a4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0a4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0a4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0a50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0a52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0a54 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0a56 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0a58 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0a5a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0a5c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0a5e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0a60 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0a62 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0a64 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0a66 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0a68 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0a6a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0a6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0a6e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + zs_beta_m: + 0: + access: rw + address: 0x0a70 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0a72 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0a74 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0a76 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0a78 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0a7a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0a7c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0a7e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0a80 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0a82 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0a84 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0a86 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0a88 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0a8a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0a8c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0a8e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0a90 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0a92 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0a94 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0a96 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0a98 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0a9a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0a9c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0a9e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0aa0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0aa2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0aa4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0aa6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0aa8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0aaa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0aac + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0aae + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0ab0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0ab2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0ab4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0ab6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0ab8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0a70 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0a72 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0a74 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0a76 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0a78 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0a7a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0a7c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0a7e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0a80 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0a82 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0a84 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0a86 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0a88 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0a8a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0a8c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0a8e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0a90 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0a92 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0a94 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0a96 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0a98 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0a9a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0a9c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0a9e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0aa0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0aa2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0aa4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0aa6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0aa8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0aaa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0aac + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0aae + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0ab0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0ab2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0ab4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0ab6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0ab8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0a70 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0a72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0a74 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0a76 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0a78 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0a7a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0a7c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0a7e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0a80 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0a82 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0a84 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0a86 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0a88 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0a8a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0a8c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0a8e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0a90 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0a92 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0a94 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0a96 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0a98 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0a9a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0a9c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0a9e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0aa0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0aa2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0aa4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0aa6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0aa8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0aaa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0aac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0aae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0ab0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0ab2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0ab4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0ab6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0ab8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0a70 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0a72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0a74 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0a76 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0a78 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0a7a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0a7c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0a7e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0a80 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0a82 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0a84 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0a86 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0a88 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0a8a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0a8c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0a8e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0a90 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0a92 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0a94 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0a96 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0a98 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0a9a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0a9c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0a9e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0aa0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0aa2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0aa4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0aa6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0aa8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0aaa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0aac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0aae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0ab0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0ab2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0ab4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0ab6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0ab8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + zs_beta_m: + 0: + access: rw + address: 0x0aba + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0abc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0abe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0ac0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0ac2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0ac4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0ac6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0ac8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0aca + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0acc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0ace + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0ad0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0ad2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0ad4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0ad6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0ad8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0ada + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0adc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0ade + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0ae0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0ae2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0ae4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0ae6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0ae8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0aea + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0aec + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0aee + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0af0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0af2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0af4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0af6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0af8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0afa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0afc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0afe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0b00 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0b02 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0aba + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0abc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0abe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0ac0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0ac2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0ac4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0ac6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0ac8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0aca + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0acc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0ace + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0ad0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0ad2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0ad4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0ad6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0ad8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0ada + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0adc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0ade + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0ae0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0ae2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0ae4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0ae6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0ae8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0aea + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0aec + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0aee + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0af0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0af2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0af4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0af6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0af8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0afa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0afc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0afe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0b00 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0b02 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0aba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0abc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0abe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0ac0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0ac2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0ac4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0ac6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0ac8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0aca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0acc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0ace + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0ad0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0ad2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0ad4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0ad6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0ad8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0ada + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0adc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0ade + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0ae0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0ae2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0ae4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0ae6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0ae8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0aea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0aec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0aee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0af0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0af2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0af4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0af6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0af8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0afa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0afc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0afe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0b00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0b02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0aba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0abc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0abe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0ac0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0ac2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0ac4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0ac6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0ac8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0aca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0acc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0ace + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0ad0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0ad2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0ad4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0ad6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0ad8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0ada + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0adc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0ade + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0ae0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0ae2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0ae4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0ae6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0ae8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0aea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0aec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0aee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0af0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0af2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0af4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0af6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0af8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0afa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0afc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0afe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0b00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0b02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + zs_beta_m: + 0: + access: rw + address: 0x0b04 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0b06 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0b08 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0b0a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0b0c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0b0e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0b10 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0b12 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0b14 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0b16 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0b18 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0b1a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0b1c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0b1e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0b20 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0b22 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0b24 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0b26 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0b28 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0b2a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0b2c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0b2e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0b30 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0b32 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0b34 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0b36 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0b38 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0b3a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0b3c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0b3e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0b40 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0b42 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0b44 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0b46 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0b48 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0b4a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0b4c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0b04 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0b06 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0b08 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0b0a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0b0c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0b0e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0b10 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0b12 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0b14 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0b16 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0b18 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0b1a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0b1c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0b1e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0b20 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0b22 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0b24 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0b26 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0b28 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0b2a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0b2c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0b2e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0b30 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0b32 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0b34 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0b36 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0b38 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0b3a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0b3c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0b3e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0b40 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0b42 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0b44 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0b46 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0b48 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0b4a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0b4c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0b04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0b06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0b08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0b0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0b0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0b0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0b10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0b12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0b14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0b16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0b18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0b1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0b1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0b1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0b20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0b22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0b24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0b26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0b28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0b2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0b2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0b2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0b30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0b32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0b34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0b36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0b38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0b3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0b3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0b3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0b40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0b42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0b44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0b46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0b48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0b4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0b4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0b04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0b06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0b08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0b0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0b0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0b0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0b10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0b12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0b14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0b16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0b18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0b1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0b1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0b1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0b20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0b22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0b24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0b26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0b28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0b2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0b2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0b2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0b30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0b32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0b34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0b36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0b38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0b3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0b3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0b3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0b40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0b42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0b44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0b46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0b48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0b4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0b4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + zs_beta_m: + 0: + access: rw + address: 0x0b4e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0b50 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0b52 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0b54 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0b56 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0b58 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0b5a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0b5c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0b5e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0b60 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0b62 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0b64 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0b66 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0b68 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0b6a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0b6c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0b6e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0b70 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0b72 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0b74 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0b76 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0b78 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0b7a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0b7c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0b7e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0b80 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0b82 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0b84 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0b86 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0b88 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0b8a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0b8c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0b8e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0b90 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0b92 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0b94 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0b96 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0b4e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0b50 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0b52 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0b54 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0b56 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0b58 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0b5a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0b5c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0b5e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0b60 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0b62 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0b64 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0b66 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0b68 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0b6a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0b6c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0b6e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0b70 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0b72 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0b74 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0b76 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0b78 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0b7a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0b7c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0b7e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0b80 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0b82 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0b84 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0b86 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0b88 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0b8a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0b8c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0b8e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0b90 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0b92 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0b94 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0b96 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0b4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0b50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0b52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0b54 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0b56 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0b58 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0b5a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0b5c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0b5e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0b60 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0b62 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0b64 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0b66 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0b68 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0b6a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0b6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0b6e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0b70 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0b72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0b74 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0b76 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0b78 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0b7a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0b7c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0b7e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0b80 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0b82 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0b84 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0b86 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0b88 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0b8a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0b8c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0b8e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0b90 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0b92 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0b94 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0b96 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0b4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0b50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0b52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0b54 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0b56 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0b58 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0b5a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0b5c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0b5e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0b60 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0b62 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0b64 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0b66 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0b68 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0b6a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0b6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0b6e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0b70 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0b72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0b74 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0b76 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0b78 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0b7a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0b7c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0b7e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0b80 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0b82 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0b84 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0b86 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0b88 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0b8a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0b8c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0b8e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0b90 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0b92 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0b94 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0b96 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + zs_beta_m: + 0: + access: rw + address: 0x0b98 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0b9a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0b9c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0b9e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0ba0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0ba2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0ba4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0ba6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0ba8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0baa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0bac + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0bae + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0bb0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0bb2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0bb4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0bb6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0bb8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0bba + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0bbc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0bbe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0bc0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0bc2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0bc4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0bc6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0bc8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0bca + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0bcc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0bce + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0bd0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0bd2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0bd4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0bd6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0bd8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0bda + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0bdc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0bde + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0be0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0b98 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0b9a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0b9c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0b9e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0ba0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0ba2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0ba4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0ba6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0ba8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0baa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0bac + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0bae + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0bb0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0bb2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0bb4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0bb6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0bb8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0bba + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0bbc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0bbe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0bc0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0bc2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0bc4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0bc6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0bc8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0bca + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0bcc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0bce + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0bd0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0bd2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0bd4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0bd6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0bd8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0bda + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0bdc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0bde + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0be0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0b98 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0b9a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0b9c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0b9e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0ba0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0ba2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0ba4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0ba6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0ba8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0baa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0bac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0bae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0bb0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0bb2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0bb4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0bb6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0bb8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0bba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0bbc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0bbe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0bc0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0bc2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0bc4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0bc6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0bc8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0bca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0bcc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0bce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0bd0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0bd2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0bd4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0bd6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0bd8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0bda + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0bdc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0bde + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0be0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0b98 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0b9a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0b9c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0b9e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0ba0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0ba2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0ba4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0ba6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0ba8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0baa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0bac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0bae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0bb0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0bb2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0bb4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0bb6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0bb8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0bba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0bbc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0bbe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0bc0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0bc2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0bc4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0bc6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0bc8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0bca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0bcc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0bce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0bd0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0bd2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0bd4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0bd6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0bd8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0bda + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0bdc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0bde + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0be0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + zs_beta_m: + 0: + access: rw + address: 0x0be2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0be4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0be6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0be8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0bea + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0bec + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0bee + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0bf0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0bf2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0bf4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0bf6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0bf8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0bfa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0bfc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0bfe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0c00 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0c02 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0c04 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0c06 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0c08 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0c0a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0c0c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0c0e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0c10 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0c12 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0c14 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0c16 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0c18 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0c1a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0c1c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0c1e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0c20 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0c22 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0c24 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0c26 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0c28 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0c2a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0be2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0be4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0be6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0be8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0bea + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0bec + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0bee + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0bf0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0bf2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0bf4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0bf6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0bf8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0bfa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0bfc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0bfe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0c00 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0c02 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0c04 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0c06 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0c08 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0c0a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0c0c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0c0e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0c10 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0c12 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0c14 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0c16 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0c18 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0c1a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0c1c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0c1e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0c20 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0c22 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0c24 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0c26 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0c28 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0c2a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0be2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0be4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0be6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0be8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0bea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0bec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0bee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0bf0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0bf2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0bf4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0bf6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0bf8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0bfa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0bfc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0bfe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0c00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0c02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0c04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0c06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0c08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0c0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0c0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0c0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0c10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0c12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0c14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0c16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0c18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0c1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0c1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0c1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0c20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0c22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0c24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0c26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0c28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0c2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0be2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0be4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0be6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0be8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0bea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0bec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0bee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0bf0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0bf2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0bf4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0bf6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0bf8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0bfa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0bfc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0bfe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0c00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0c02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0c04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0c06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0c08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0c0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0c0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0c0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0c10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0c12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0c14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0c16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0c18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0c1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0c1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0c1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0c20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0c22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0c24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0c26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0c28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0c2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + zs_beta_m: + 0: + access: rw + address: 0x0c2c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0c2e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0c30 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0c32 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0c34 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0c36 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0c38 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0c3a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0c3c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0c3e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0c40 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0c42 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0c44 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0c46 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0c48 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0c4a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0c4c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0c4e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0c50 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0c52 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0c54 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0c56 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0c58 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0c5a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0c5c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0c5e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0c60 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0c62 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0c64 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0c66 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0c68 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0c6a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0c6c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0c6e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0c70 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0c72 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0c74 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0c2c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0c2e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0c30 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0c32 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0c34 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0c36 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0c38 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0c3a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0c3c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0c3e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0c40 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0c42 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0c44 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0c46 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0c48 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0c4a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0c4c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0c4e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0c50 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0c52 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0c54 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0c56 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0c58 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0c5a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0c5c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0c5e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0c60 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0c62 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0c64 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0c66 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0c68 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0c6a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0c6c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0c6e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0c70 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0c72 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0c74 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0c2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0c2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0c30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0c32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0c34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0c36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0c38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0c3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0c3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0c3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0c40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0c42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0c44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0c46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0c48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0c4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0c4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0c4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0c50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0c52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0c54 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0c56 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0c58 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0c5a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0c5c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0c5e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0c60 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0c62 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0c64 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0c66 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0c68 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0c6a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0c6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0c6e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0c70 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0c72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0c74 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0c2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0c2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0c30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0c32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0c34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0c36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0c38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0c3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0c3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0c3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0c40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0c42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0c44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0c46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0c48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0c4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0c4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0c4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0c50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0c52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0c54 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0c56 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0c58 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0c5a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0c5c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0c5e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0c60 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0c62 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0c64 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0c66 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0c68 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0c6a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0c6c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0c6e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0c70 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0c72 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0c74 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + zs_beta_m: + 0: + access: rw + address: 0x0c76 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0c78 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0c7a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0c7c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0c7e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0c80 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0c82 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0c84 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0c86 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0c88 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0c8a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0c8c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0c8e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0c90 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0c92 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0c94 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0c96 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0c98 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0c9a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0c9c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0c9e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0ca0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0ca2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0ca4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0ca6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0ca8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0caa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0cac + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0cae + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0cb0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0cb2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0cb4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0cb6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0cb8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0cba + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0cbc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0cbe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0c76 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0c78 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0c7a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0c7c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0c7e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0c80 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0c82 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0c84 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0c86 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0c88 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0c8a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0c8c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0c8e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0c90 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0c92 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0c94 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0c96 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0c98 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0c9a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0c9c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0c9e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0ca0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0ca2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0ca4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0ca6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0ca8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0caa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0cac + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0cae + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0cb0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0cb2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0cb4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0cb6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0cb8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0cba + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0cbc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0cbe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0c76 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0c78 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0c7a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0c7c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0c7e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0c80 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0c82 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0c84 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0c86 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0c88 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0c8a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0c8c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0c8e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0c90 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0c92 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0c94 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0c96 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0c98 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0c9a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0c9c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0c9e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0ca0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0ca2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0ca4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0ca6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0ca8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0caa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0cac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0cae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0cb0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0cb2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0cb4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0cb6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0cb8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0cba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0cbc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0cbe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0c76 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0c78 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0c7a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0c7c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0c7e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0c80 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0c82 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0c84 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0c86 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0c88 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0c8a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0c8c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0c8e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0c90 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0c92 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0c94 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0c96 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0c98 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0c9a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0c9c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0c9e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0ca0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0ca2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0ca4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0ca6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0ca8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0caa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0cac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0cae + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0cb0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0cb2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0cb4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0cb6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0cb8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0cba + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0cbc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0cbe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + zs_beta_m: + 0: + access: rw + address: 0x0cc0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0cc2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0cc4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0cc6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0cc8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0cca + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0ccc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0cce + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0cd0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0cd2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0cd4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0cd6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0cd8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0cda + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0cdc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0cde + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0ce0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0ce2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0ce4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0ce6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0ce8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0cea + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0cec + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0cee + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0cf0 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0cf2 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0cf4 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0cf6 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0cf8 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0cfa + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0cfc + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0cfe + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0d00 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0d02 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0d04 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0d06 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0d08 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0cc0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0cc2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0cc4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0cc6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0cc8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0cca + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0ccc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0cce + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0cd0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0cd2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0cd4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0cd6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0cd8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0cda + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0cdc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0cde + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0ce0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0ce2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0ce4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0ce6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0ce8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0cea + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0cec + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0cee + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0cf0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0cf2 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0cf4 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0cf6 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0cf8 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0cfa + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0cfc + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0cfe + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0d00 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0d02 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0d04 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0d06 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0d08 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0cc0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0cc2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0cc4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0cc6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0cc8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0cca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0ccc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0cce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0cd0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0cd2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0cd4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0cd6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0cd8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0cda + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0cdc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0cde + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0ce0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0ce2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0ce4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0ce6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0ce8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0cea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0cec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0cee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0cf0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0cf2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0cf4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0cf6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0cf8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0cfa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0cfc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0cfe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0d00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0d02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0d04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0d06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0d08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0cc0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0cc2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0cc4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0cc6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0cc8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0cca + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0ccc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0cce + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0cd0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0cd2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0cd4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0cd6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0cd8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0cda + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0cdc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0cde + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0ce0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0ce2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0ce4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0ce6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0ce8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0cea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0cec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0cee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0cf0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0cf2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0cf4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0cf6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0cf8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0cfa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0cfc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0cfe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0d00 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0d02 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0d04 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0d06 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0d08 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + zs_beta_m: + 0: + access: rw + address: 0x0d0a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 1: + access: rw + address: 0x0d0c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 2: + access: rw + address: 0x0d0e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 3: + access: rw + address: 0x0d10 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 4: + access: rw + address: 0x0d12 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 5: + access: rw + address: 0x0d14 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 6: + access: rw + address: 0x0d16 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 7: + access: rw + address: 0x0d18 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 8: + access: rw + address: 0x0d1a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 9: + access: rw + address: 0x0d1c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 10: + access: rw + address: 0x0d1e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 11: + access: rw + address: 0x0d20 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 12: + access: rw + address: 0x0d22 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 13: + access: rw + address: 0x0d24 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 14: + access: rw + address: 0x0d26 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 15: + access: rw + address: 0x0d28 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 16: + access: rw + address: 0x0d2a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 17: + access: rw + address: 0x0d2c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 18: + access: rw + address: 0x0d2e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 19: + access: rw + address: 0x0d30 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 20: + access: rw + address: 0x0d32 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 21: + access: rw + address: 0x0d34 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 22: + access: rw + address: 0x0d36 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 23: + access: rw + address: 0x0d38 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 24: + access: rw + address: 0x0d3a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 25: + access: rw + address: 0x0d3c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 26: + access: rw + address: 0x0d3e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 27: + access: rw + address: 0x0d40 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 28: + access: rw + address: 0x0d42 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 29: + access: rw + address: 0x0d44 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 30: + access: rw + address: 0x0d46 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 31: + access: rw + address: 0x0d48 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 32: + access: rw + address: 0x0d4a + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 33: + access: rw + address: 0x0d4c + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 34: + access: rw + address: 0x0d4e + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 35: + access: rw + address: 0x0d50 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + 36: + access: rw + address: 0x0d52 + default_value: 32 + max_value: 127 + param_mask: 0x007f + param_shift: 4 + size_byte: 2 + zs_c_i_m: + 0: + access: rw + address: 0x0d0a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0d0c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0d0e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0d10 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0d12 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0d14 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x0d16 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x0d18 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x0d1a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0d1c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0d1e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0d20 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0d22 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0d24 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x0d26 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x0d28 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x0d2a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0d2c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0d2e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0d30 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0d32 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0d34 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x0d36 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x0d38 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x0d3a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0d3c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0d3e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0d40 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0d42 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0d44 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x0d46 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x0d48 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x0d4a + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0d4c + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0d4e + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0d50 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0d52 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 2 + zs_mask_i_m: + 0: + access: rw + address: 0x0d0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 1: + access: rw + address: 0x0d0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 2: + access: rw + address: 0x0d0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 3: + access: rw + address: 0x0d10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 4: + access: rw + address: 0x0d12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 5: + access: rw + address: 0x0d14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 6: + access: rw + address: 0x0d16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 7: + access: rw + address: 0x0d18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 8: + access: rw + address: 0x0d1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 9: + access: rw + address: 0x0d1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 10: + access: rw + address: 0x0d1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 11: + access: rw + address: 0x0d20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 12: + access: rw + address: 0x0d22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 13: + access: rw + address: 0x0d24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 14: + access: rw + address: 0x0d26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 15: + access: rw + address: 0x0d28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 16: + access: rw + address: 0x0d2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 17: + access: rw + address: 0x0d2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 18: + access: rw + address: 0x0d2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 19: + access: rw + address: 0x0d30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 20: + access: rw + address: 0x0d32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 21: + access: rw + address: 0x0d34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 22: + access: rw + address: 0x0d36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 23: + access: rw + address: 0x0d38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 24: + access: rw + address: 0x0d3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 25: + access: rw + address: 0x0d3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 26: + access: rw + address: 0x0d3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 27: + access: rw + address: 0x0d40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 28: + access: rw + address: 0x0d42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 29: + access: rw + address: 0x0d44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 30: + access: rw + address: 0x0d46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 31: + access: rw + address: 0x0d48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 32: + access: rw + address: 0x0d4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 33: + access: rw + address: 0x0d4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 34: + access: rw + address: 0x0d4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 35: + access: rw + address: 0x0d50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + 36: + access: rw + address: 0x0d52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + zs_pass_i_m: + 0: + access: rw + address: 0x0d0a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 1: + access: rw + address: 0x0d0c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 2: + access: rw + address: 0x0d0e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 3: + access: rw + address: 0x0d10 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 4: + access: rw + address: 0x0d12 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 5: + access: rw + address: 0x0d14 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 6: + access: rw + address: 0x0d16 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 7: + access: rw + address: 0x0d18 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 8: + access: rw + address: 0x0d1a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 9: + access: rw + address: 0x0d1c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 10: + access: rw + address: 0x0d1e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 11: + access: rw + address: 0x0d20 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 12: + access: rw + address: 0x0d22 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 13: + access: rw + address: 0x0d24 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 14: + access: rw + address: 0x0d26 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 15: + access: rw + address: 0x0d28 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 16: + access: rw + address: 0x0d2a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 17: + access: rw + address: 0x0d2c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 18: + access: rw + address: 0x0d2e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 19: + access: rw + address: 0x0d30 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 20: + access: rw + address: 0x0d32 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 21: + access: rw + address: 0x0d34 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 22: + access: rw + address: 0x0d36 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 23: + access: rw + address: 0x0d38 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 24: + access: rw + address: 0x0d3a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 25: + access: rw + address: 0x0d3c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 26: + access: rw + address: 0x0d3e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 27: + access: rw + address: 0x0d40 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 28: + access: rw + address: 0x0d42 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 29: + access: rw + address: 0x0d44 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 30: + access: rw + address: 0x0d46 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 31: + access: rw + address: 0x0d48 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 32: + access: rw + address: 0x0d4a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 33: + access: rw + address: 0x0d4c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 34: + access: rw + address: 0x0d4e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 35: + access: rw + address: 0x0d50 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + 36: + access: rw + address: 0x0d52 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 11 + size_byte: 2 + Global: + tmr_err_cnt_zero_suppress_m: + access: ro + address: 0x0d54 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 diff --git a/register_maps/ECONT_I2C_params_regmap.yaml b/register_maps/ECONT_I2C_params_regmap.yaml new file mode 100644 index 00000000..7c3cb82c --- /dev/null +++ b/register_maps/ECONT_I2C_params_regmap.yaml @@ -0,0 +1,9820 @@ +Algo: + Global: + tmr_err_cnt_alg: + access: ro + address: 0x053f + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +AlgoDroplsb: + Global: + drop_lsb: + access: rw + address: 0x053e + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 0 + size_byte: 1 +AlgoThreshold: + 0: + access: rw + address: 0x04ae + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 1: + access: rw + address: 0x04b1 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 2: + access: rw + address: 0x04b4 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 3: + access: rw + address: 0x04b7 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 4: + access: rw + address: 0x04ba + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 5: + access: rw + address: 0x04bd + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 6: + access: rw + address: 0x04c0 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 7: + access: rw + address: 0x04c3 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 8: + access: rw + address: 0x04c6 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 9: + access: rw + address: 0x04c9 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 10: + access: rw + address: 0x04cc + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 11: + access: rw + address: 0x04cf + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 12: + access: rw + address: 0x04d2 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 13: + access: rw + address: 0x04d5 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 14: + access: rw + address: 0x04d8 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 15: + access: rw + address: 0x04db + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 16: + access: rw + address: 0x04de + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 17: + access: rw + address: 0x04e1 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 18: + access: rw + address: 0x04e4 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 19: + access: rw + address: 0x04e7 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 20: + access: rw + address: 0x04ea + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 21: + access: rw + address: 0x04ed + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 22: + access: rw + address: 0x04f0 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 23: + access: rw + address: 0x04f3 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 24: + access: rw + address: 0x04f6 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 25: + access: rw + address: 0x04f9 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 26: + access: rw + address: 0x04fc + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 27: + access: rw + address: 0x04ff + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 28: + access: rw + address: 0x0502 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 29: + access: rw + address: 0x0505 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 30: + access: rw + address: 0x0508 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 31: + access: rw + address: 0x050b + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 32: + access: rw + address: 0x050e + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 33: + access: rw + address: 0x0511 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 34: + access: rw + address: 0x0514 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 35: + access: rw + address: 0x0517 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 36: + access: rw + address: 0x051a + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 37: + access: rw + address: 0x051d + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 38: + access: rw + address: 0x0520 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 39: + access: rw + address: 0x0523 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 40: + access: rw + address: 0x0526 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 41: + access: rw + address: 0x0529 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 42: + access: rw + address: 0x052c + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 43: + access: rw + address: 0x052f + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 44: + access: rw + address: 0x0532 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 45: + access: rw + address: 0x0535 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 46: + access: rw + address: 0x0538 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + 47: + access: rw + address: 0x053b + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 +Aligner: + Global: + dbg_fc_cnt: + access: ro + address: 0x0398 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dbg_fc_cnt_clr: + access: rw + address: 0x0380 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + dbg_lreset_rcvd: + access: ro + address: 0x0398 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + dbg_orbsyn_rcvd: + access: ro + address: 0x0398 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + done: + access: ro + address: 0x0398 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + freeze_output_enable: + access: rw + address: 0x0380 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + freeze_output_enable_all_channels_locked: + access: rw + address: 0x0380 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + i2c_snapshot_en: + access: rw + address: 0x0380 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + idle_hdr_mask: + access: rw + address: 0x0392 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + idle_hdr_val: + access: rw + address: 0x0392 + default_value: 10 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + match_mask_val: + access: rw + address: 0x0389 + default_value: 18446744069414584320 + max_value: 18446744073709551615 + param_mask: 0xffffffffffffffff + param_shift: 0 + size_byte: 8 + match_pattern_val: + access: rw + address: 0x0381 + default_value: 2594876074 + max_value: 18446744073709551615 + param_mask: 0xffffffffffffffff + param_shift: 0 + size_byte: 8 + orbsyn_cnt_load_val: + access: rw + address: 0x0393 + default_value: 3513 + max_value: 4095 + param_mask: 0x0fff + param_shift: 12 + size_byte: 3 + orbsyn_cnt_max_val: + access: rw + address: 0x0393 + default_value: 3563 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 3 + orbsyn_cnt_snapshot: + access: rw + address: 0x0396 + default_value: 2 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + orbsyn_hdr_mask: + access: rw + address: 0x0391 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 4 + size_byte: 1 + orbsyn_hdr_val: + access: rw + address: 0x0391 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 1 + snapshot_arm: + access: rw + address: 0x0380 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + snapshot_en: + access: rw + address: 0x0380 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + tmr_err_cnt_aligner: + access: ro + address: 0x0399 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Cal: + 0: + access: rw + address: 0x043f + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 1: + access: rw + address: 0x0441 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 2: + access: rw + address: 0x0443 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 3: + access: rw + address: 0x0445 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 4: + access: rw + address: 0x0447 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 5: + access: rw + address: 0x0449 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 6: + access: rw + address: 0x044b + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 7: + access: rw + address: 0x044d + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 8: + access: rw + address: 0x044f + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 9: + access: rw + address: 0x0451 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 10: + access: rw + address: 0x0453 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 11: + access: rw + address: 0x0455 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 12: + access: rw + address: 0x0457 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 13: + access: rw + address: 0x0459 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 14: + access: rw + address: 0x045b + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 15: + access: rw + address: 0x045d + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 16: + access: rw + address: 0x045f + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 17: + access: rw + address: 0x0461 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 18: + access: rw + address: 0x0463 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 19: + access: rw + address: 0x0465 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 20: + access: rw + address: 0x0467 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 21: + access: rw + address: 0x0469 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 22: + access: rw + address: 0x046b + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 23: + access: rw + address: 0x046d + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 24: + access: rw + address: 0x046f + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 25: + access: rw + address: 0x0471 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 26: + access: rw + address: 0x0473 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 27: + access: rw + address: 0x0475 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 28: + access: rw + address: 0x0477 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 29: + access: rw + address: 0x0479 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 30: + access: rw + address: 0x047b + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 31: + access: rw + address: 0x047d + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 32: + access: rw + address: 0x047f + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 33: + access: rw + address: 0x0481 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 34: + access: rw + address: 0x0483 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 35: + access: rw + address: 0x0485 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 36: + access: rw + address: 0x0487 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 37: + access: rw + address: 0x0489 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 38: + access: rw + address: 0x048b + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 39: + access: rw + address: 0x048d + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 40: + access: rw + address: 0x048f + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 41: + access: rw + address: 0x0491 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 42: + access: rw + address: 0x0493 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 43: + access: rw + address: 0x0495 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 44: + access: rw + address: 0x0497 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 45: + access: rw + address: 0x0499 + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 46: + access: rw + address: 0x049b + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + 47: + access: rw + address: 0x049d + default_value: 2048 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 +ChAligner: + 0: + force_ch_outputs: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x002e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0031 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0032 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0030 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0000 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0033 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0002 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0000 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0001 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0015 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0016 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0014 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0034 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0036 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0035 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0004 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0008 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x000c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0010 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + force_ch_outputs: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x006e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0071 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0072 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0070 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0040 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0073 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0042 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0040 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0041 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0055 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0056 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0054 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0074 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0076 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0075 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0044 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0048 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x004c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0050 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + force_ch_outputs: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x00ae + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x00b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x00b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x00b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0080 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x00b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0082 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0080 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0081 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0095 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0096 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0094 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x00b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x00b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x00b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0084 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0088 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x008c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0090 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + force_ch_outputs: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x00ee + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x00f1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x00f2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x00f0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x00c0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x00f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x00c2 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x00c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x00c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x00d5 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x00d6 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x00d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x00f4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x00f6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x00f5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x00c4 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x00c8 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x00cc + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x00d0 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 4: + force_ch_outputs: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x012e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0131 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0132 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0130 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0100 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0133 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0102 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0100 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0101 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0115 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0116 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0114 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0134 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0136 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0135 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0104 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0108 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x010c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0110 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 5: + force_ch_outputs: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x016e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0171 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0172 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0170 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0140 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0173 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0142 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0140 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0141 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0155 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0156 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0154 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0174 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0176 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0175 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0144 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0148 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x014c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0150 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 6: + force_ch_outputs: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x01ae + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x01b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x01b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x01b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0180 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x01b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0182 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0180 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0181 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0195 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0196 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0194 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x01b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x01b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x01b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0184 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0188 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x018c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0190 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 7: + force_ch_outputs: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x01ee + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x01f1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x01f2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x01f0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x01c0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x01f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x01c2 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x01c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x01c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x01d5 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x01d6 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x01d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x01f4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x01f6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x01f5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x01c4 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x01c8 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x01cc + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x01d0 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 8: + force_ch_outputs: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x022e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0231 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0232 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0230 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0200 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0233 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0202 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0200 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0201 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0215 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0216 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0214 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0234 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0236 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0235 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0204 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0208 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x020c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0210 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 9: + force_ch_outputs: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x026e + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x0271 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x0272 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x0270 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0240 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x0273 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0242 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0240 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0241 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0255 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0256 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0254 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x0274 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x0276 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x0275 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0244 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0248 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x024c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0250 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 10: + force_ch_outputs: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x02ae + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x02b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x02b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x02b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x0280 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x02b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x0282 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x0280 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x0281 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x0295 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x0296 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x0294 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x02b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x02b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x02b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x0284 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x0288 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x028c + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x0290 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 11: + force_ch_outputs: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + hdr_mm_cntr: + access: ro + address: 0x02ee + default_value: 0 + max_value: 65535 + param_mask: 0xffff + param_shift: 0 + size_byte: 2 + hdr_mm_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + orbsyn_arr_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + orbsyn_arr_err_cnt: + access: ro + address: 0x02f1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_fc_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + orbsyn_fc_err_cnt: + access: ro + address: 0x02f2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + orbsyn_hdr_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + orbsyn_hdr_err_cnt: + access: ro + address: 0x02f0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + patt_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + patt_sel: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pattern_match: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + per_ch_align_en: + access: rw + address: 0x02c0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + prbs28_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + prbs_chk_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + prbs_chk_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + prbs_chk_err_cnt: + access: ro + address: 0x02f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + seed_in: + access: rw + address: 0x02c2 + default_value: 0 + max_value: 16383 + param_mask: 0x3fff + param_shift: 0 + size_byte: 2 + sel_override_en: + access: rw + address: 0x02c0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + sel_override_val: + access: rw + address: 0x02c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + select: + access: ro + address: 0x02d5 + default_value: 32 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + snapshot: + access: ro + address: 0x02d6 + default_value: 0 + max_value: 6277101735386680763835789423207666416102355444464034512895 + param_mask: 0xffffffffffffffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 24 + snapshot_dv: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + spare_err: + access: ro + address: 0x02d4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + tmr_err_cnt_chan_aligner: + access: ro + address: 0x02f4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_eprxgrp: + access: ro + address: 0x02f6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_chan_err: + access: ro + address: 0x02f5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + user_word: + 0: + access: rw + address: 0x02c4 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 1: + access: rw + address: 0x02c8 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 2: + access: rw + address: 0x02cc + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 + 3: + access: rw + address: 0x02d0 + default_value: 0 + max_value: 4294967295 + param_mask: 0xffffffff + param_shift: 0 + size_byte: 4 +ChEprxGrp: + 0: + channel_locked: + access: ro + address: 0x0341 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0341 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0342 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0342 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0342 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0340 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0341 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0340 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0341 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0340 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0340 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 1: + channel_locked: + access: ro + address: 0x0345 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0345 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0346 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0346 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0346 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0344 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0345 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0344 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0345 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0344 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0344 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 2: + channel_locked: + access: ro + address: 0x0349 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0349 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x034a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x034a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x034a + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0348 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0349 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0348 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0349 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0348 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0348 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 3: + channel_locked: + access: ro + address: 0x034d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x034d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x034e + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x034e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x034e + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x034c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x034d + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x034c + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x034d + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x034c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x034c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 4: + channel_locked: + access: ro + address: 0x0351 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0351 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0352 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0352 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0352 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0350 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0351 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0350 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0351 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0350 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0350 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 5: + channel_locked: + access: ro + address: 0x0355 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0355 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0356 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0356 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0356 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0354 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0355 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0354 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0355 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0354 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0354 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 6: + channel_locked: + access: ro + address: 0x0359 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0359 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x035a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x035a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x035a + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0358 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0359 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0358 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0359 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0358 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0358 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 7: + channel_locked: + access: ro + address: 0x035d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x035d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x035e + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x035e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x035e + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x035c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x035d + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x035c + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x035d + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x035c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x035c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 8: + channel_locked: + access: ro + address: 0x0361 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0361 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0362 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0362 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0362 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0360 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0361 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0360 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0361 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0360 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0360 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 9: + channel_locked: + access: ro + address: 0x0365 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0365 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x0366 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x0366 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x0366 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0364 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0365 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0364 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0365 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0364 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0364 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 10: + channel_locked: + access: ro + address: 0x0369 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x0369 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x036a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x036a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x036a + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x0368 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x0369 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x0368 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x0369 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x0368 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x0368 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 11: + channel_locked: + access: ro + address: 0x036d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + dll_instant_lock: + access: ro + address: 0x036d + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + dll_lock_filter_state: + access: ro + address: 0x036e + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + dll_locked: + access: ro + address: 0x036e + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_loss_of_lock_count: + access: ro + address: 0x036e + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 + dll_reset_req: + access: rw + address: 0x036c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + dll_state: + access: ro + address: 0x036d + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 1 + phase_select_channelinput: + access: rw + address: 0x036c + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 1 + phase_select_channeloutput: + access: ro + address: 0x036d + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 2 + size_byte: 1 + reset_channels: + access: rw + address: 0x036c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + train_channel: + access: rw + address: 0x036c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 +ChErr: + 0: + clr_on_read: + access: wo + address: 0x0300 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0303 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0303 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0301 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0302 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0300 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0300 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 1: + clr_on_read: + access: wo + address: 0x0304 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0307 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0307 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0305 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0306 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0304 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0304 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 2: + clr_on_read: + access: wo + address: 0x0308 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x030b + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x030b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0309 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x030a + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0308 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0308 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 3: + clr_on_read: + access: wo + address: 0x030c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x030f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x030f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x030d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x030e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x030c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x030c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 4: + clr_on_read: + access: wo + address: 0x0310 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0313 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0313 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0311 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0312 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0310 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0310 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 5: + clr_on_read: + access: wo + address: 0x0314 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0317 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0317 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0315 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0316 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0314 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0314 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 6: + clr_on_read: + access: wo + address: 0x0318 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x031b + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x031b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0319 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x031a + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0318 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0318 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 7: + clr_on_read: + access: wo + address: 0x031c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x031f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x031f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x031d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x031e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x031c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x031c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 8: + clr_on_read: + access: wo + address: 0x0320 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0323 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0323 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0321 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0322 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0320 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0320 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 9: + clr_on_read: + access: wo + address: 0x0324 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x0327 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x0327 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0325 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x0326 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0324 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0324 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 10: + clr_on_read: + access: wo + address: 0x0328 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x032b + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x032b + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x0329 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x032a + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x0328 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x0328 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + 11: + clr_on_read: + access: wo + address: 0x032c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat: + access: ro + address: 0x032f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + err_out: + access: ro + address: 0x032f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + err_raw_dat: + access: ro + address: 0x032d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat: + access: ro + address: 0x032e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + wren_err: + access: wo + address: 0x032c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk: + access: wo + address: 0x032c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 +ClocksAndResets: + Global: + calibration_end_of_count_select: + access: rw + address: 0x03c9 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 46 + size_byte: 7 + capbank_select: + access: rw + address: 0x03c9 + default_value: 31 + max_value: 511 + param_mask: 0x01ff + param_shift: 37 + size_byte: 7 + clk_tree_a_disable: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 7 + clk_tree_b_disable: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 7 + clk_tree_c_disable: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 7 + clk_tree_erx_disable: + access: rw + address: 0x03d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + clk_tree_etx_disable: + access: rw + address: 0x03d8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + clk_tree_magic_number: + access: rw + address: 0x03c8 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + clk_tree_sram_disable: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 15 + size_byte: 2 + co_connect_pll: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 6 + co_dis_data_counter_ref: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 6 + co_dis_des_vbiasgen: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 6 + co_enable_pll: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 55 + size_byte: 7 + co_override_vc: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 6 + enable_capbank_override: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 36 + size_byte: 7 + enable_control_override: + access: rw + address: 0x03c9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 54 + size_byte: 7 + fc_locked_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + lock_filter_clk_always_enable: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 17 + size_byte: 6 + lock_filter_enable: + access: rw + address: 0x03d0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 6 + lock_filter_lock_threshold: + access: rw + address: 0x03d0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 5 + size_byte: 6 + lock_filter_locked: + access: ro + address: 0x03df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 4 + lock_filter_loss_of_lock_count: + access: ro + address: 0x03df + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 7 + size_byte: 4 + lock_filter_loss_of_lock_count_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 6 + size_byte: 1 + lock_filter_relock_threshold: + access: rw + address: 0x03d0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 9 + size_byte: 6 + lock_filter_state: + access: ro + address: 0x03df + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 4 + lock_filter_un_lock_threshold: + access: rw + address: 0x03d0 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 13 + size_byte: 6 + pll_config_integral: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 11 + size_byte: 7 + pll_config_integral_when_locked: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 15 + size_byte: 7 + pll_config_proportional: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 19 + size_byte: 7 + pll_config_proportional_when_locked: + access: rw + address: 0x03c9 + default_value: 9 + max_value: 15 + param_mask: 0x000f + param_shift: 23 + size_byte: 7 + pll_config_res: + access: rw + address: 0x03c9 + default_value: 2 + max_value: 15 + param_mask: 0x000f + param_shift: 3 + size_byte: 7 + pll_config_res_when_locked: + access: rw + address: 0x03c9 + default_value: 2 + max_value: 15 + param_mask: 0x000f + param_shift: 7 + size_byte: 7 + pusm_force_magic: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 1 + size_byte: 3 + pusm_force_state: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 3 + pusm_left_ready_action_counter: + access: ro + address: 0x03dd + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_left_ready_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 4 + size_byte: 1 + pusm_run: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 23 + size_byte: 3 + pusm_state: + access: ro + address: 0x03df + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 0 + size_byte: 4 + pusm_state_forced: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 9 + size_byte: 3 + pusm_state_upset_action_counter: + access: ro + address: 0x03de + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_state_upset_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + pusm_timeout_dll_action_counter: + access: ro + address: 0x03da + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_timeout_dll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + pusm_timeout_dll_lock_config: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 19 + size_byte: 3 + pusm_timeout_pll_action_counter: + access: ro + address: 0x03d9 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_timeout_pll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + pusm_timeout_pll_lock_config: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 15 + size_byte: 3 + pusm_watchdog_dll_action_counter: + access: ro + address: 0x03dc + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_watchdog_dll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + pusm_watchdog_pll_action_counter: + access: ro + address: 0x03db + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pusm_watchdog_pll_action_rst: + access: wo + address: 0x03c4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + pusm_wdog_dll_disable: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 14 + size_byte: 3 + pusm_wdog_pll_disable: + access: rw + address: 0x03c5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 13 + size_byte: 3 + ref_clk_sel_testclkin: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 14 + size_byte: 2 + sm_locked: + access: ro + address: 0x03df + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 19 + size_byte: 4 + sm_state: + access: ro + address: 0x03df + default_value: 0 + max_value: 15 + param_mask: 0x000f + param_shift: 15 + size_byte: 4 + test_output_drive_strength: + 0: + access: rw + address: 0x03d0 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 38 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 4 + size_byte: 2 + test_output_enable: + 0: + access: rw + address: 0x03d0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 34 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + test_output_invert_data: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 35 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 2 + test_output_low_supply_r: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 47 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 13 + size_byte: 2 + test_output_preemp_mode: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 36 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 2 + size_byte: 2 + test_output_preemp_strength: + 0: + access: rw + address: 0x03d0 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 41 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 7 + size_byte: 2 + test_output_preemp_width: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 44 + size_byte: 6 + 1: + access: rw + address: 0x03d6 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 10 + size_byte: 2 + test_output_select: + 0: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 18 + size_byte: 6 + 1: + access: rw + address: 0x03d0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 26 + size_byte: 6 + tmr_err_cnt_clocks_and_resets: + access: ro + address: 0x03e3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + vco_capbank: + access: ro + address: 0x03df + default_value: 0 + max_value: 511 + param_mask: 0x01ff + param_shift: 20 + size_byte: 4 + vco_config_biasgen: + access: rw + address: 0x03c9 + default_value: 8 + max_value: 15 + param_mask: 0x000f + param_shift: 27 + size_byte: 7 + vco_config_dac: + access: rw + address: 0x03c9 + default_value: 8 + max_value: 15 + param_mask: 0x000f + param_shift: 31 + size_byte: 7 + vco_rail_rail_mode: + access: rw + address: 0x03c9 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 35 + size_byte: 7 + wait_pll_time: + access: rw + address: 0x03c9 + default_value: 15 + max_value: 15 + param_mask: 0x000f + param_shift: 50 + size_byte: 7 +Config: + 0: + bad_erx_err_out: + access: ro + address: 0x04a1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a1 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 1: + bad_erx_err_out: + access: ro + address: 0x04a2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a2 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 2: + bad_erx_err_out: + access: ro + address: 0x04a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a3 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 3: + bad_erx_err_out: + access: ro + address: 0x04a4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a4 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 4: + bad_erx_err_out: + access: ro + address: 0x04a5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a5 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 5: + bad_erx_err_out: + access: ro + address: 0x04a6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a6 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 6: + bad_erx_err_out: + access: ro + address: 0x04a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a7 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 7: + bad_erx_err_out: + access: ro + address: 0x04a8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a8 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 8: + bad_erx_err_out: + access: ro + address: 0x04a9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04a9 + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 9: + bad_erx_err_out: + access: ro + address: 0x04aa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04aa + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 10: + bad_erx_err_out: + access: ro + address: 0x04ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04ab + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + 11: + bad_erx_err_out: + access: ro + address: 0x04ac + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 7 + size_byte: 1 + bad_erx_pass_fail_counter: + access: ro + address: 0x04ac + default_value: 0 + max_value: 127 + param_mask: 0x007f + param_shift: 0 + size_byte: 1 + Global: + tmr_err_cnt_mfc: + access: ro + address: 0x04ad + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +ConfigAlgo: + Global: + alg_high_density: + access: rw + address: 0x049f + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 2 + alg_type: + access: rw + address: 0x049f + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 0 + size_byte: 2 + bad_erx_mode: + access: rw + address: 0x049f + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + invalid_threshold: + access: rw + address: 0x049f + default_value: 1 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + observation_window: + access: rw + address: 0x049f + default_value: 1 + max_value: 7 + param_mask: 0x0007 + param_shift: 12 + size_byte: 2 + valid_threshold: + access: rw + address: 0x049f + default_value: 1 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 +ERx: + 0: + enable: + access: rw + address: 0x03e4 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e4 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e4 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 1: + enable: + access: rw + address: 0x03e5 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e5 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e5 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e5 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 2: + enable: + access: rw + address: 0x03e6 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e6 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e6 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 3: + enable: + access: rw + address: 0x03e7 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e7 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e7 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 4: + enable: + access: rw + address: 0x03e8 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e8 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e8 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 5: + enable: + access: rw + address: 0x03e9 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03e9 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03e9 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03e9 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 6: + enable: + access: rw + address: 0x03ea + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ea + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ea + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ea + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 7: + enable: + access: rw + address: 0x03eb + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03eb + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03eb + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03eb + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 8: + enable: + access: rw + address: 0x03ec + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ec + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ec + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ec + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 9: + enable: + access: rw + address: 0x03ed + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ed + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ed + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ed + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ed + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 10: + enable: + access: rw + address: 0x03ee + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ee + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ee + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ee + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + 11: + enable: + access: rw + address: 0x03ef + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03ef + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03ef + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03ef + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + Global: + tmr_err_cnt_erx: + access: ro + address: 0x03f3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + Mux00: + enable: + access: rw + address: 0x03f0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03f0 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03f0 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03f0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + Mux01: + enable: + access: rw + address: 0x03f1 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03f1 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03f1 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03f1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 + Mux02: + enable: + access: rw + address: 0x03f2 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + enable_termination: + access: rw + address: 0x03f2 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + equalizer: + access: rw + address: 0x03f2 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 3 + size_byte: 1 + invert_data: + access: rw + address: 0x03f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + set_common_mode: + access: rw + address: 0x03f2 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 +ETx: + 0: + drive_strength: + access: rw + address: 0x03f4 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03f4 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03f4 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 1: + drive_strength: + access: rw + address: 0x03f6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03f6 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03f6 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 2: + drive_strength: + access: rw + address: 0x03f8 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03f8 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03f8 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 3: + drive_strength: + access: rw + address: 0x03fa + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03fa + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03fa + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03fa + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03fa + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 4: + drive_strength: + access: rw + address: 0x03fc + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03fc + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03fc + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03fc + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03fc + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 5: + drive_strength: + access: rw + address: 0x03fe + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x03fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x03fe + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x03fe + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x03fe + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x03fe + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 6: + drive_strength: + access: rw + address: 0x0400 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0400 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0400 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0400 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0400 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0400 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 7: + drive_strength: + access: rw + address: 0x0402 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0402 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0402 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0402 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0402 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0402 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 8: + drive_strength: + access: rw + address: 0x0404 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0404 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0404 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0404 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0404 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0404 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 9: + drive_strength: + access: rw + address: 0x0406 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0406 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0406 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0406 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0406 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0406 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 10: + drive_strength: + access: rw + address: 0x0408 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x0408 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x0408 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x0408 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x0408 + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x0408 + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 11: + drive_strength: + access: rw + address: 0x040a + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x040a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x040a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x040a + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x040a + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x040a + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + 12: + drive_strength: + access: rw + address: 0x040c + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 1 + size_byte: 2 + invert_data: + access: rw + address: 0x040c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 2 + low_supply_r: + access: rw + address: 0x040c + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + pre_emphasis_mode: + access: rw + address: 0x040c + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 2 + pre_emphasis_strength: + access: rw + address: 0x040c + default_value: 3 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 2 + pre_emphasis_width: + access: rw + address: 0x040c + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 2 + Global: + tmr_err_cnt_etx: + access: ro + address: 0x040e + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Encoder: + 0: + weights_byte0: + access: rw + address: 0x0600 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte112: + access: rw + address: 0x0670 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte128: + access: rw + address: 0x0680 + default_value: 0 + max_value: 281474976710655 + param_mask: 0xffffffffffff + param_shift: 0 + size_byte: 6 + weights_byte16: + access: rw + address: 0x0610 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte32: + access: rw + address: 0x0620 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte48: + access: rw + address: 0x0630 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte64: + access: rw + address: 0x0640 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 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0xffffffffffff + param_shift: 0 + size_byte: 6 + weights_byte16: + access: rw + address: 0x0696 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte32: + access: rw + address: 0x06a6 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte48: + access: rw + address: 0x06b6 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte64: + access: rw + address: 0x06c6 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 0xffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 16 + weights_byte80: + access: rw + address: 0x06d6 + default_value: 0 + max_value: 340282366920938463463374607431768211455 + param_mask: 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+ default_value: 1 + max_value: 3 + param_mask: 0x0003 + param_shift: 0 + size_byte: 3 + dll_init_sm_force_clock_enable: + access: rw + address: 0x03a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 17 + size_byte: 3 + dll_lock_threshold: + access: rw + address: 0x03a3 + default_value: 5 + max_value: 7 + param_mask: 0x0007 + param_shift: 6 + size_byte: 3 + dll_re_lock_threshold: + access: rw + address: 0x03a3 + default_value: 5 + max_value: 7 + param_mask: 0x0007 + param_shift: 9 + size_byte: 3 + dll_un_lock_threshold: + access: rw + address: 0x03a3 + default_value: 5 + max_value: 7 + param_mask: 0x0007 + param_shift: 12 + size_byte: 3 + enable_re_init: + access: rw + address: 0x03a3 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 18 + size_byte: 3 + tmr_err_cnt_eprxgrp_top: + access: ro + address: 0x03a6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + track_mode: + access: rw + address: 0x03a3 + default_value: 1 + max_value: 3 + param_mask: 0x0003 + param_shift: 4 + size_byte: 3 +ErrTop: + Global: + clr_on_read_top: + access: rw + address: 0x039a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + err_dat_top: + access: ro + address: 0x03a0 + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + err_out_top: + access: ro + address: 0x03a0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 12 + size_byte: 2 + err_wr_data: + access: rw + address: 0x039d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + msk_dat_top: + access: ro + address: 0x039e + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + tmr_err_cnt_err_top: + access: ro + address: 0x03a2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + wr_data_top: + access: rw + address: 0x039b + default_value: 0 + max_value: 4095 + param_mask: 0x0fff + param_shift: 0 + size_byte: 2 + wren_err_top: + access: rw + address: 0x039a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + wren_msk_top: + access: rw + address: 0x039a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 +FCtrl: + Global: + bcr_fcmd_count: + access: ro + address: 0x03ad + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + cal_pulse_ext_fcmd_count: + access: ro + address: 0x03b2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + cal_pulse_int_fcmd_count: + access: ro + address: 0x03b1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + capture_fcmd_ctrl: + access: rw + address: 0x03a8 + default_value: 0 + max_value: 4194303 + param_mask: 0x3fffff + param_shift: 0 + size_byte: 3 + command_rx_inverted: + access: ro + address: 0x03ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + ebr_fcmd_count: + access: ro + address: 0x03b3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + ecr_fcmd_count: + access: ro + address: 0x03b4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + edge_sel_t1: + access: rw + address: 0x03a7 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + fc_error_fcmd_count: + access: ro + address: 0x03c2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + invert_command_rx: + access: rw + address: 0x03a7 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 3 + size_byte: 1 + l1a_fcmd_count: + access: ro + address: 0x03af + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_econ_d_fcmd_count: + access: ro + address: 0x03b8 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_econ_t_fcmd_count: + access: ro + address: 0x03b7 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_roc_d_fcmd_count: + access: ro + address: 0x03b6 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + link_reset_roc_t_fcmd_count: + access: ro + address: 0x03b5 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + lock_count: + access: ro + address: 0x03ac + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + locked: + access: ro + address: 0x03ab + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + nzs_fcmd_count: + access: ro + address: 0x03b0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + ocr_fcmd_count: + access: ro + address: 0x03ae + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + pre_l1a_offset: + access: rw + address: 0x03a7 + default_value: 0 + max_value: 3 + param_mask: 0x0003 + param_shift: 1 + size_byte: 1 + spare_fcmd_count: + 0: + access: ro + address: 0x03b9 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 1: + access: ro + address: 0x03ba + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 2: + access: ro + address: 0x03bb + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 3: + access: ro + address: 0x03bc + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 4: + access: ro + address: 0x03bd + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 5: + access: ro + address: 0x03be + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 6: + access: ro + address: 0x03bf + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + 7: + access: ro + address: 0x03c0 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + tmr_err_cnt_fast_ctrl_decoder: + access: ro + address: 0x03c3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + unassigned_fcmd_count: + access: ro + address: 0x03c1 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +FormatterBuffer: + Global: + active_etxs: + access: rw + address: 0x0545 + default_value: 3 + max_value: 8191 + param_mask: 0x1fff + param_shift: 3 + size_byte: 2 + align_serializer: + 0: + access: rw + address: 0x055d + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x055e + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x055f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0560 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0561 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0562 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0563 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 7: + access: rw + address: 0x0564 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 8: + access: rw + address: 0x0565 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 9: + access: rw + address: 0x0566 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 10: + access: rw + address: 0x0567 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 11: + access: rw + address: 0x0568 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 12: + access: rw + address: 0x0569 + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + buff_t1: + access: rw + address: 0x0540 + default_value: 48 + max_value: 511 + param_mask: 0x01ff + param_shift: 0 + size_byte: 2 + buff_t2: + access: rw + address: 0x0542 + default_value: 511 + max_value: 511 + param_mask: 0x01ff + param_shift: 0 + size_byte: 2 + buff_t3: + access: rw + address: 0x0544 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 0 + size_byte: 1 + buffer_wr_ptr_ovflw_err: + access: ro + address: 0x056a + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + etx_pattern: + access: rw + address: 0x055b + default_value: 0 + max_value: 7 + param_mask: 0x0007 + param_shift: 11 + size_byte: 2 + idle_pattern: + access: rw + address: 0x0547 + default_value: 1450 + max_value: 2047 + param_mask: 0x07ff + param_shift: 0 + size_byte: 2 + keep_auto_encoder_bits: + access: rw + address: 0x0549 + default_value: 0xffffffffffffffffffffffffffffffffffff + max_value: 22300745198530623141535718272648361505980415 + param_mask: 0xffffffffffffffffffffffffffffffffffff + param_shift: 0 + size_byte: 18 + link_reset_pattern: + access: rw + address: 0x055b + default_value: 290 + max_value: 2047 + param_mask: 0x07ff + param_shift: 0 + size_byte: 2 + stc_type: + access: rw + address: 0x0545 + default_value: 1 + max_value: 7 + param_mask: 0x0007 + param_shift: 0 + size_byte: 2 + tmr_err_cnt_fmtbuf: + access: ro + address: 0x056b + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + use_sum: + access: rw + address: 0x0544 + default_value: 1 + max_value: 1 + param_mask: 0x0001 + param_shift: 5 + size_byte: 1 +Misc: + Global: + bad_erx_status_clear: + access: wo + address: 0x0ce0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 2 + size_byte: 1 + ro: + 0: + access: ro + address: 0x0ce2 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 + rw_err_clr: + 0: + access: rw + address: 0x0ce1 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + status_capture: + access: wo + address: 0x0ce0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 1 + size_byte: 1 + status_clear: + access: wo + address: 0x0ce0 + default_value: 0 + max_value: 1 + param_mask: 0x0001 + param_shift: 0 + size_byte: 1 + wbmaster_err_wb_adr_cnt: + access: ro + address: 0x0ce3 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Misc_TMR_ERR_CNT: + Global: + tmr_err_cnt_misc: + access: ro + address: 0x0ce4 + default_value: 0 + max_value: 255 + param_mask: 0x00ff + param_shift: 0 + size_byte: 1 +Mux: + 0: + access: rw + address: 0x040f + default_value: 0 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 1: + access: rw + address: 0x0410 + default_value: 1 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 2: + access: rw + address: 0x0411 + default_value: 2 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 3: + access: rw + address: 0x0412 + default_value: 3 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 4: + access: rw + address: 0x0413 + default_value: 4 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 5: + access: rw + address: 0x0414 + default_value: 5 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 6: + access: rw + address: 0x0415 + default_value: 6 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 7: + access: rw + address: 0x0416 + default_value: 7 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 8: + access: rw + address: 0x0417 + default_value: 8 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 9: + access: rw + address: 0x0418 + default_value: 9 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 10: + access: rw + address: 0x0419 + default_value: 10 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 11: + access: rw + address: 0x041a + default_value: 11 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 12: + access: rw + address: 0x041b + default_value: 12 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 13: + access: rw + address: 0x041c + default_value: 13 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 14: + access: rw + address: 0x041d + default_value: 14 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 15: + access: rw + address: 0x041e + default_value: 15 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 16: + access: rw + address: 0x041f + default_value: 16 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 17: + access: rw + address: 0x0420 + default_value: 17 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 18: + access: rw + address: 0x0421 + default_value: 18 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 19: + access: rw + address: 0x0422 + default_value: 19 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 20: + access: rw + address: 0x0423 + default_value: 20 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 21: + access: rw + address: 0x0424 + default_value: 21 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 22: + access: rw + address: 0x0425 + default_value: 22 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 23: + access: rw + address: 0x0426 + default_value: 23 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 24: + access: rw + address: 0x0427 + default_value: 24 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 25: + access: rw + address: 0x0428 + default_value: 25 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 26: + access: rw + address: 0x0429 + default_value: 26 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 27: + access: rw + address: 0x042a + default_value: 27 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 28: + access: rw + address: 0x042b + default_value: 28 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 29: + access: rw + address: 0x042c + default_value: 29 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 30: + access: rw + address: 0x042d + default_value: 30 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 31: + access: rw + address: 0x042e + default_value: 31 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 32: + access: rw + address: 0x042f + default_value: 32 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 33: + access: rw + address: 0x0430 + default_value: 33 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 34: + access: rw + address: 0x0431 + default_value: 34 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 35: + access: rw + address: 0x0432 + default_value: 35 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 36: + access: rw + address: 0x0433 + default_value: 36 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 37: + access: rw + address: 0x0434 + default_value: 37 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 38: + access: rw + address: 0x0435 + default_value: 38 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 39: + access: rw + address: 0x0436 + default_value: 39 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 40: + access: rw + address: 0x0437 + default_value: 40 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 41: + access: rw + address: 0x0438 + default_value: 41 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 42: + access: rw + address: 0x0439 + default_value: 42 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 43: + access: rw + address: 0x043a + default_value: 43 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 44: + access: rw + address: 0x043b + default_value: 44 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 45: + access: rw + address: 0x043c + default_value: 45 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 46: + access: rw + address: 0x043d + default_value: 46 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 + 47: + access: rw + address: 0x043e + default_value: 47 + max_value: 63 + param_mask: 0x003f + param_shift: 0 + size_byte: 1 From 6a6f6c6dbc76b4ceaa21dc1617053e0d306846fa Mon Sep 17 00:00:00 2001 From: taylorjcolaizzi Date: Thu, 18 Sep 2025 20:17:20 -0400 Subject: [PATCH 18/36] added test econd yaml to register_maps. it has only 1 parameter --- register_maps/test_econd_registers.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 register_maps/test_econd_registers.yaml diff --git a/register_maps/test_econd_registers.yaml b/register_maps/test_econd_registers.yaml new file mode 100644 index 00000000..005a9991 --- /dev/null +++ b/register_maps/test_econd_registers.yaml @@ -0,0 +1,10 @@ +Aligner: + Global: + dbg_fc_cnt: + access: ro + address: 0x0398 + default_value: 0 + max_value: 31 + param_mask: 0x001f + param_shift: 3 + size_byte: 1 \ No newline at end of file From dcfaf314bcc7dbca8ebe8b21f04e2224f1618837 Mon Sep 17 00:00:00 2001 From: Cristina Mantilla Suarez Date: Fri, 26 Sep 2025 12:40:14 -0400 Subject: [PATCH 19/36] add econ to header conversion --- CMakeLists.txt | 33 +++++++ register_maps/econ-to-header.py | 125 ++++++++++++++++++++++++ register_maps/test_econd_registers.yaml | 10 -- 3 files changed, 158 insertions(+), 10 deletions(-) create mode 100644 register_maps/econ-to-header.py delete mode 100644 register_maps/test_econd_registers.yaml diff --git a/CMakeLists.txt b/CMakeLists.txt index 8206b535..b32b9044 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -33,6 +33,9 @@ endif() # Boost for CRC calculator, Test, and Logging find_package(Boost COMPONENTS log unit_test_framework REQUIRED) +if(Boost_FOUND) + include_directories(${Boost_INCLUDE_DIRS}) +endif() # Generate the register map headers for the different supported ROCs # "v2" rocs were manually written so we just copy them into the correct spot @@ -100,6 +103,36 @@ add_custom_command( ) add_custom_target(lpgbt_regmap DEPENDS include/register_maps/lpgbt.h) +add_custom_command( + OUTPUT "include/register_maps/econd.h" + COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps + COMMAND python3 + ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py + ${PROJECT_SOURCE_DIR}/register_maps/ECOND_I2C_params_regmap.yaml + ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps/econd.h + DEPENDS + ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py + ${PROJECT_SOURCE_DIR}/register_maps/ECOND_I2C_params_regmap.yaml + COMMENT "Generating C++ ECOND register LUT from register_maps/ECOND_I2C_params_regmap.yaml" + VERBATIM +) +add_custom_target(econd_regmap DEPENDS include/register_maps/econd.h) + +add_custom_command( + OUTPUT "include/register_maps/econt.h" + COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps + COMMAND python3 + ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py + ${PROJECT_SOURCE_DIR}/register_maps/ECONT_I2C_params_regmap.yaml + ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps/econt.h + DEPENDS + ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py + ${PROJECT_SOURCE_DIR}/register_maps/ECONT_I2C_params_regmap.yaml + COMMENT "Generating C++ ECONT register LUT from register_maps/ECONT_I2C_params_regmap.yaml" + VERBATIM +) +add_custom_target(econt_regmap DEPENDS include/register_maps/econt.h) + add_custom_command( OUTPUT include/register_maps/register_maps.h COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps diff --git a/register_maps/econ-to-header.py b/register_maps/econ-to-header.py new file mode 100644 index 00000000..22582607 --- /dev/null +++ b/register_maps/econ-to-header.py @@ -0,0 +1,125 @@ +import sys +import yaml +from pathlib import Path + +def count_bits(mask): + """Count number of 1s in the binary representation of mask.""" + return bin(mask).count("1") + +def safe_int(val): + """Convert YAML value to int whether it's a string like '0x0398' or already an int.""" + if isinstance(val, str): + return int(val, 16) if val.startswith("0x") else int(val) + return int(val) + +def make_register_locations(address, mask, shift, size_byte): + """Split a register into 8-bit chunks if it spans multiple bytes. + syntax reminder: RegisterLocation(reg, min_bit, n_bits): + - min_bit = param_shift for the first chunk, 0 for others + - n_bits = number of 1's in the mask for the chunk + """ + reg_locs = [] + remaining_mask = mask + curr_addr = address + first_chunk = True + + for i in range(size_byte): + # take the lowest 8 bits for this byte + chunk_mask = remaining_mask & 0xFF + n_bits = bin(chunk_mask).count("1") + loc_shift = shift if first_chunk else 0 + reg_locs.append(f"RegisterLocation(0x{curr_addr:04x}, {loc_shift}, {n_bits})") + + # shift the remaining mask right by 8 bits to remove the bits we've already processed + remaining_mask >>= 8 + # address increments by 1 byte + curr_addr += 1 + # only the first chunk uses the original shift + first_chunk = False + + # break the loop if no bits are left to process + if remaining_mask == 0: + break + return reg_locs + +def process_register(name_prefix, props, lines): + """ + Process recursively a register or nested subregisters and append C++ lines. + name_prefix: current register name prefix (e.g., 'USER_WORD') + props: dict containing either address/mask/shift or nested subkeys + lines: list of strings to append to + """ + if isinstance(props, dict): + if "address" in props: + address = safe_int(props["address"]) + mask = safe_int(props["param_mask"]) + shift = safe_int(props["param_shift"]) + default_value = props.get("default_value", 0) + size_byte = props.get("size_byte", 1) + + # account for multi-byte registers + reg_locs = make_register_locations(address, mask, shift, size_byte) + reg_locs_str = ", ".join(reg_locs) + + cpp_name = name_prefix.upper() + lines.append(f' {{"{cpp_name}", Parameter({{{reg_locs_str}}}, {default_value})}},') + else: + # look for nested subkeys if props is a dict + if isinstance(props, dict): + for subkey, subval in props.items(): + new_prefix = f"{name_prefix}_{subkey}" + process_register(new_prefix, subval, lines) + +def generate_header(input_yaml, data): + """Generate the C++ header content for a given page.""" + lines = [] + lines.append(f'/* auto-generated LUT header from {input_yaml} */\n') + lines.append("#pragma once\n") + lines.append('#include "register_maps/register_maps_types.h"\n') + lines.append("namespace econd {\n") + + # Loop through all blocks (e.g. ALIGNER, CHALIGNER) + page_names = [] + for page_name, groups in data.items(): + page_var = page_name.upper() # uppercase page name + lines.append(f"const Page {page_var} = Page::Mapping({{") + for group_name, registers in groups.items(): + # check if registers itself has an "address" key → it is a single register + if isinstance(registers, dict) and "address" in registers: + # single register (e.g. AlgoThreshold 0 in ECON-T) + name_prefix = str(group_name) + process_register(name_prefix, registers, lines) + else: + for reg_name, props in registers.items(): + name_prefix = f"{group_name}_{reg_name}" + process_register(name_prefix, props, lines) + + for reg_name, props in registers.items(): + name_prefix = f"{group_name}_{reg_name}" + process_register(name_prefix, props, lines) + page_names.append(page_var) + lines.append(" });") + + lines.append("\nconst PageLUT PAGE_LUT = PageLUT::Mapping({") + for name in page_names: + lines.append(f' {{"{name}", {name}}},') + lines.append("});") + + lines.append("\n} // namespace econd\n") + + return "\n".join(lines) + +def compile_registers(yaml_file, output_file): + with open(yaml_file, "r") as f: + data = yaml.safe_load(f) + + content = generate_header(yaml_file, data) + with open(output_file, "w") as f: + f.write(content) + +if __name__ == "__main__": + if len(sys.argv) != 3: + print("Usage: python3 compile_registers.py ") + sys.exit(1) + + compile_registers(sys.argv[1], sys.argv[2]) \ No newline at end of file diff --git a/register_maps/test_econd_registers.yaml b/register_maps/test_econd_registers.yaml deleted file mode 100644 index 005a9991..00000000 --- a/register_maps/test_econd_registers.yaml +++ /dev/null @@ -1,10 +0,0 @@ -Aligner: - Global: - dbg_fc_cnt: - access: ro - address: 0x0398 - default_value: 0 - max_value: 31 - param_mask: 0x001f - param_shift: 3 - size_byte: 1 \ No newline at end of file From 5df8e0732f31aeb8aef2f51a5935c64490ecb8ce Mon Sep 17 00:00:00 2001 From: Cristina Mantilla Suarez Date: Mon, 29 Sep 2025 17:34:00 -0400 Subject: [PATCH 20/36] remove boost target --- CMakeLists.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b32b9044..d7c776f5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -33,9 +33,6 @@ endif() # Boost for CRC calculator, Test, and Logging find_package(Boost COMPONENTS log unit_test_framework REQUIRED) -if(Boost_FOUND) - include_directories(${Boost_INCLUDE_DIRS}) -endif() # Generate the register map headers for the different supported ROCs # "v2" rocs were manually written so we just copy them into the correct spot From 5ed918e79cc34dec05cc9b085806f95836b7371f Mon Sep 17 00:00:00 2001 From: cmantill Date: Wed, 1 Oct 2025 20:35:21 +0000 Subject: [PATCH 21/36] Josh: comitting recent changes to enable switch to branch with fixed leveling --- src/pflib/zcu/HcalBackplaneZCU.cxx | 22 ++++++++++++++-------- src/pflib/zcu/zcu_optolink.cxx | 4 ++-- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/src/pflib/zcu/HcalBackplaneZCU.cxx b/src/pflib/zcu/HcalBackplaneZCU.cxx index e514190f..827b5589 100644 --- a/src/pflib/zcu/HcalBackplaneZCU.cxx +++ b/src/pflib/zcu/HcalBackplaneZCU.cxx @@ -8,6 +8,7 @@ namespace pflib { static constexpr int ADDR_HCAL_BACKPLANE_DAQ = 0x78|0x04; static constexpr int ADDR_HCAL_BACKPLANE_TRIG = 0x78; + static constexpr int I2C_BUS_ECONS = 0; // DAQ static constexpr int I2C_BUS_HGCROCS = 1; // DAQ static constexpr int I2C_BUS_BIAS = 1; // TRIG static constexpr int I2C_BUS_BOARD = 0; // TRIG @@ -19,6 +20,7 @@ namespace pflib { public: HcalBackplaneZCUTarget(int itarget, uint8_t board_mask) { // first, setup the optical links + printf("Make Backplane ZCU target, setup optical links"); std::string uio_coder=pflib::utility::string_format("standardLpGBTpair-%d",itarget); daq_tport_=std::make_unique(uio_coder, false, ADDR_HCAL_BACKPLANE_DAQ); trig_tport_=std::make_unique(uio_coder, true, ADDR_HCAL_BACKPLANE_TRIG); @@ -26,14 +28,17 @@ namespace pflib { trig_lpgbt_=std::make_unique(*trig_tport_); // next, create the Hcal I2C objects - roc_i2c_=std::make_shared(*daq_lpgbt_, I2C_BUS_HGCROCS); - roc_i2c_->set_bus_speed(1000); - for (int ibd=0; ibd<4; ibd++) { - if ((board_mask&(1< bias_i2c=std::make_shared(*trig_lpgbt_,I2C_BUS_BIAS,ADDR_MUX_BIAS,(1< board_i2c=std::make_shared(*trig_lpgbt_,I2C_BUS_BOARD,ADDR_MUX_BOARD,(1<(*daq_lpgbt_, I2C_BUS_ECONS); + econ_i2c_->set_bus_speed(1000); + //roc_i2c_=std::make_shared(*daq_lpgbt_, I2C_BUS_HGCROCS); + //roc_i2c_->set_bus_speed(1000); + //for (int ibd=0; ibd<4; ibd++) { + //if ((board_mask&(1< bias_i2c=std::make_shared(*trig_lpgbt_,I2C_BUS_BIAS,ADDR_MUX_BIAS,(1< board_i2c=std::make_shared(*trig_lpgbt_,I2C_BUS_BOARD,ADDR_MUX_BOARD,(1< daq_tport_, trig_tport_; std::unique_ptr daq_lpgbt_, trig_lpgbt_; std::shared_ptr roc_i2c_; + std::shared_ptr econ_i2c_; }; diff --git a/src/pflib/zcu/zcu_optolink.cxx b/src/pflib/zcu/zcu_optolink.cxx index d887404e..f592d173 100644 --- a/src/pflib/zcu/zcu_optolink.cxx +++ b/src/pflib/zcu/zcu_optolink.cxx @@ -26,12 +26,12 @@ void OptoLink::reset_link() { transright_.write(0x0,0x1); //GTH_RESET usleep(1000); done=transright_.readMasked(REG_STATUS,0x8); - // printf(" After %d attempts, BUFFBYPASS_DONE is %d (GTH_RESET)\n",attempts,done); + printf(" After %d attempts, BUFFBYPASS_DONE is %d (GTH_RESET)\n",attempts,done); } else { transright_.write(0x0,0x4); //RX_RESET usleep(1000); done=transright_.readMasked(REG_STATUS,0x8); - // printf(" After %d attempts, BUFFBYPASS_DONE is %d (RX_RESET)\n",attempts,done); + printf(" After %d attempts, BUFFBYPASS_DONE is %d (RX_RESET)\n",attempts,done); } attempts += 1; } From 1443692829af043488f00e49ad1599503d70becb Mon Sep 17 00:00:00 2001 From: cmantill Date: Thu, 2 Oct 2025 15:40:10 +0000 Subject: [PATCH 22/36] add econ resets and base for i2c comm --- CMakeLists.txt | 1 + app/tool/econ.cxx | 105 +++++++++++++++++++++ app/tool/main.cxx | 10 +- app/tool/pftool.h | 6 ++ app/tool/roc.cxx | 2 +- include/pflib/ECON.h | 38 ++++++++ include/pflib/Hcal.h | 28 +++++- src/pflib/ECON.cxx | 60 ++++++++++++ src/pflib/Hcal.cxx | 38 ++++++-- src/pflib/lpgbt/lpGBT_standard_configs.cxx | 12 ++- src/pflib/zcu/HcalBackplaneZCU.cxx | 11 +++ 11 files changed, 300 insertions(+), 11 deletions(-) create mode 100644 app/tool/econ.cxx create mode 100644 include/pflib/ECON.h create mode 100644 src/pflib/ECON.cxx diff --git a/CMakeLists.txt b/CMakeLists.txt index 31c925ff..29f46a06 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -145,6 +145,7 @@ target_link_libraries(packing PUBLIC utility) add_library(pflib SHARED src/pflib/I2C_Linux.cxx src/pflib/ROC.cxx + src/pflib/ECON.cxx src/pflib/Compile.cxx src/pflib/Logging.cxx src/pflib/Hcal.cxx diff --git a/app/tool/econ.cxx b/app/tool/econ.cxx new file mode 100644 index 00000000..45299192 --- /dev/null +++ b/app/tool/econ.cxx @@ -0,0 +1,105 @@ +/** + * @file econ.cxx + * ECON menu commands and support functions + */ +#include "pftool.h" + +/** + * Simply print the currently selective ECON so that user is aware + * which ECON they are interacting with by default. + * + * @param[in] pft active target (not used) + */ +static void econ_render(Target* pft) { + printf(" Active ECON: %d (type_econ_ = %s)\n", pftool::state.iecon, pftool::state.type_econ().c_str()); +} + +/** + * Extra instruction for user + */ +static void econ_expert_render(Target* tgt) { + econ_render(tgt); + std::cout << "This menu avoids using the 'compiler' to translate parameter names into\n" + "register values and instead allows you to read/write registers directly.\n"; +} + +/** + * ECON.EXPERT menu commands + * + * Detailed interaction with ECON doing things like interacting + * with the registers that hold the ECON-D/ECON-T parameters without + * using the compiler + * + * ## Commands + * - POKE : set a specific register to a specific value pflib::ECON::setValue + */ +static void econ_expert(const std::string& cmd, Target* tgt) { + auto econ = tgt->hcal().econ(pftool::state.iecon, pftool::state.type_econ()); + if (cmd == "POKE") { + int page = pftool::readline_int("Which page? ", 0); + int entry = pftool::readline_int("Offset: ", 0); + int value = pftool::readline_int("New value: "); + + econ.setValue(page, entry, value); + } +} + +/** + * ECON menu commands + * + * When necessary, the ECON interaction object pflib::ECON is created + * via pflib::Hcal::econ with the currently active econ. + * + * ## Commands + * - HARDRESET : pflib::Hcal::hardResetECONs + * - SOFTRESET : pflib::Hcal::softResetECONs + * - RUNMODE : enable run bit on the ECON + * - IECON : Change which ECON to focus on + * - POKE : pflib::ECON::setValue + * + * @param[in] cmd ECON command + * @param[in] pft active target + */ +static void econ(const std::string& cmd, Target* pft) { + if (cmd == "HARDRESET") { + pft->hcal().hardResetECONs(); + } + if (cmd == "SOFTRESET") { + pft->hcal().softResetECONs(); + } + if (cmd == "IECON") { + pftool::state.iecon = pftool::readline_int("Which ECON to manage: ", pftool::state.iecon); + pftool::state.update_type_econ( + pftool::readline("type of the ECON (D or T): ", pftool::state.type_econ()) + ); + } + pflib::ECON econ = pft->hcal().econ(pftool::state.iecon, pftool::state.type_econ()); + if (cmd == "RUNMODE") { + bool isRunMode = econ.isRunMode(); + isRunMode = pftool::readline_bool("Set ECON runbit: ", isRunMode); + econ.setRunMode(isRunMode); + } + if (cmd == "POKE") { + //auto page = pftool::readline("Page: ", pftool::state.page_names()); + //auto param = pftool::readline("Parameter: ", pftool::state.param_names(page)); + //int val = pftool::readline_int("New value: "); + //econ.applyParameter(page, param, val); + } +} + + +namespace { +auto menu_econ = + pftool::menu("ECON", "ECON Chip Configuration", econ_render) + ->line("HARDRESET", "Hard reset to all econs", econ) + ->line("SOFTRESET", "Soft reset to all econs", econ) + ->line("IECON", "Change the active ECON number", econ) + ->line("RUNMODE", "set/clear the run mode", econ) + ->line("POKE", "change a single parameter value", econ) + ; + +auto menu_econ_expert = + menu_econ->submenu("EXPERT", "expert interaction with ECON", econ_expert_render) + ->line("POKE", "change a single register's value", econ_expert) + ; +} diff --git a/app/tool/main.cxx b/app/tool/main.cxx index 4c14a611..62e5448e 100644 --- a/app/tool/main.cxx +++ b/app/tool/main.cxx @@ -21,7 +21,15 @@ pflib::logging::logger get_by_file(const std::string& filepath) { return pflib::logging::get("pftool." + relative); } -pftool::State::State() { update_type_version("sipm_rocv3b"); } +pftool::State::State() { + update_type_version("sipm_rocv3b"); + update_type_econ("econd"); +} + +void pftool::State::update_type_econ(const std::string& type_econ) { + type_econ_ = type_econ; +} +const std::string& pftool::State::type_econ() const { return type_econ_; } void pftool::State::update_type_version(const std::string& type_version) { if (type_version != type_version_) { diff --git a/app/tool/pftool.h b/app/tool/pftool.h index 33ba4819..e3828db3 100644 --- a/app/tool/pftool.h +++ b/app/tool/pftool.h @@ -38,6 +38,8 @@ class pftool : public pflib::menu::Menu { public: /// static variables to share across menu class State { + /// type of ECON currently being interacted with + std::string type_econ_; /// type_version of HGCROC currently being interacted with std::string type_version_; /// list of page names for tab completion @@ -48,6 +50,10 @@ class pftool : public pflib::menu::Menu { public: /// default constructor which sets default type_version State(); + /// ECON + void update_type_econ(const std::string& type_econ); + const std::string& type_econ() const; + int iecon{0}; /// update roc type version, regenerating tab completion lists if needed void update_type_version(const std::string& type_version); /// get the type_version of the HGCROC currently being interacted with diff --git a/app/tool/roc.cxx b/app/tool/roc.cxx index 00b1e89d..32b09f57 100644 --- a/app/tool/roc.cxx +++ b/app/tool/roc.cxx @@ -16,7 +16,7 @@ static void roc_render(Target* pft) { } /** - * Extra instructsion for user + * Extra instruction for user */ static void roc_expert_render(Target* tgt) { roc_render(tgt); diff --git a/include/pflib/ECON.h b/include/pflib/ECON.h new file mode 100644 index 00000000..6ca9cb01 --- /dev/null +++ b/include/pflib/ECON.h @@ -0,0 +1,38 @@ +#ifndef PFLIB_ECON_H_INCLUDED +#define PFLIB_ECON_H_INCLUDED + +#include +#include +#include +#include + +#include "pflib/Compile.h" +#include "pflib/I2C.h" +#include "pflib/Logging.h" + +namespace pflib { + +/** + * @class ECON setup + */ +class ECON { + + public: + ECON(I2C& i2c, uint8_t econ_base_addr, const std::string& type_version); + + void setRunMode(bool active = true); + bool isRunMode(); + + uint8_t getValue(int page, int offset); + void setValue(int page, int offset, uint8_t value); + + private: + I2C& i2c_; + uint8_t econ_base_; + Compiler compiler_; + mutable ::pflib::logging::logger the_log_{::pflib::logging::get("econ")}; +}; + +} // namespace pflib + +#endif // PFLIB_ECON_H_INCLUDED diff --git a/include/pflib/Hcal.h b/include/pflib/Hcal.h index 8b7ac729..634ab78b 100644 --- a/include/pflib/Hcal.h +++ b/include/pflib/Hcal.h @@ -8,6 +8,7 @@ #include "pflib/GPIO.h" #include "pflib/I2C.h" #include "pflib/ROC.h" +#include "pflib/ECON.h" // #include "pflib/FastControl.h" #include "pflib/DAQ.h" @@ -23,12 +24,19 @@ class Hcal { /** number of boards */ int nrocs() { return nhgcroc_; } + int necons() { return necon_; } + /** do we have a roc with this id? */ bool have_roc(int iroc) { return i2c_for_rocbd_.find(iroc)!=i2c_for_rocbd_.end(); } + bool have_econ(int iecon) { return i2c_for_econbd_.find(iecon)!=i2c_for_econbd_.end(); } + /** Get a ROC interface for the given HGCROC board */ ROC roc(int which, const std::string& roc_type_version = "sipm_rocv3b"); + /** Get a ECON interface */ + ECON econ(int which, const std::string& type_econ = "econd"); + /** Get an I2C interface for the given HGCROC board's bias bus */ Bias bias(int which); @@ -41,6 +49,9 @@ class Hcal { /** Generate a soft reset to a specific HGCROC board, -1 for all */ virtual void softResetROC(int which = -1); + virtual void hardResetECONs(); + virtual void softResetECONs(); + /** Get the GPIO object for debugging purposes */ virtual GPIO& gpio() { return *gpio_; } @@ -53,13 +64,24 @@ class Hcal { /** get the DAQ object */ virtual DAQ& daq() = 0; + void print_i2c_map() { + for (const auto& [key, ptr] : i2c_for_econbd_) { + std::cout << "Hcal ECON I2C Key: " << key << ", I2C pointer: " << ptr.get() << std::endl; + } + } + protected: /** Add a ROC to the set of ROCs */ - void add_roc(int iroc, std::shared_ptr& roc_i2C, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c); + void add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c); + + /** Add an ECON to the set of ECONs */ + void add_econ(int iecon, std::shared_ptr& econ_i2c); /** Number of HGCROC boards in this system */ int nhgcroc_; + int necon_; + /** The GPIO interface */ std::unique_ptr gpio_; @@ -69,7 +91,11 @@ class Hcal { std::shared_ptr bias_i2c_; std::shared_ptr board_i2c_; }; + std::map i2c_for_rocbd_; + + std::map> i2c_for_econbd_; + }; } // namespace pflib diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx new file mode 100644 index 00000000..de1e0628 --- /dev/null +++ b/src/pflib/ECON.cxx @@ -0,0 +1,60 @@ +#include "pflib/ECON.h" + +#include + +#include +#include + +#include "pflib/packing/Hex.h" +#include "pflib/utility/load_integer_csv.h" + +namespace pflib { + +ECON::ECON(I2C& i2c, uint8_t econ_base_addr, const std::string& type_version) + : i2c_{i2c}, + econ_base_{econ_base_addr}, + compiler_{Compiler::get(type_version)} { + pflib_log(debug) << "base addr " << packing::hex(econ_base_); +} + +void ECON::setRunMode(bool active) { + // TODO: implement writing run mode to the hardware + uint8_t reg_value = getValue(0x03c5, 3); + const uint32_t MASK_RUN_BIT = 0x000F; + const int SHIFT_RUN_BIT = 0; + uint32_t param = (reg_value & MASK_RUN_BIT) >> SHIFT_RUN_BIT; + //if (active) cval |= MASK_RUN_MODE; + //setValue(TOP_PAGE, 0, cval); +} + +bool ECON::isRunMode() { + // TODO: implement reading run mode from the hardware + uint8_t reg_value = getValue(0x03c5, 3); + const uint32_t MASK_RUN_BIT = 0x000F; + const int SHIFT_RUN_BIT = 0; + uint32_t param = (reg_value & MASK_RUN_BIT) >> SHIFT_RUN_BIT; + return false; // placeholder +} + +uint8_t ECON::getValue(int addr, int nbytes) { + if(nbytes < 1) { + pflib_log(error) << "Invalid nbytes = " << nbytes; + } + + pflib_log(debug) << "ECON::getValue(" << addr << ", " << nbytes << ")"; + + std::vector waddr; + waddr.push_back(static_cast(addr & 0xFF)); + waddr.push_back(static_cast((addr >> 8) & 0xFF)); + + std::vector data = i2c_.general_write_read(econ_base_, waddr, nbytes); + for (size_t i = 0; i < data.size(); i++) { + printf("%02zu : %02x\n", i, data[i]); + } +} + +void ECON::setValue(int page, int offset, uint8_t value) { + // TODO: implement writing a register to the hardware +} + +} // namespace pflib diff --git a/src/pflib/Hcal.cxx b/src/pflib/Hcal.cxx index 387332ce..67ecf658 100644 --- a/src/pflib/Hcal.cxx +++ b/src/pflib/Hcal.cxx @@ -3,11 +3,12 @@ namespace pflib { - Hcal::Hcal() { - nhgcroc_ = 0; - } - - void Hcal::add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c) { +Hcal::Hcal() { + nhgcroc_ = 0; + necon_ = 0; +} + +void Hcal::add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c) { if (have_roc(iroc)) { PFEXCEPTION_RAISE("DuplicateROC",pflib::utility::string_format("Already have registered ROC with id %d",iroc)); } @@ -19,6 +20,27 @@ namespace pflib { i2c_for_rocbd_[iroc]=handles; } +ECON Hcal::econ(int which, const std::string& type_econ) { + if (!have_econ(which)) { + PFEXCEPTION_RAISE("InvalidECONid", pflib::utility::string_format("Unknown ECON id %d",which)); + } + if (type_econ == "econd") { + return ECON(*i2c_for_econbd_[which], 0x60 | (which * 8), type_econ); + } else if (type_econ == "econt") { + return ECON(*i2c_for_econbd_[which], 0x20 | (which * 8), type_econ); + } else { + throw std::runtime_error("Unknown ECON type: " + type_econ); + } +} + +void Hcal::add_econ(int iecon, std::shared_ptr& econ_i2c) { + if (have_econ(iecon)) { + PFEXCEPTION_RAISE("DuplicateECON",pflib::utility::string_format("Already have registered ECON with id %d",iecon)); + } + necon_++; + i2c_for_econbd_[iecon]=econ_i2c; +} + ROC Hcal::roc(int which, const std::string& roc_type_version) { if (!have_roc(which)) { PFEXCEPTION_RAISE("InvalidROCid", pflib::utility::string_format("Unknown ROC id %d",which)); @@ -38,6 +60,10 @@ void Hcal::hardResetROCs() {} void Hcal::softResetROC(int which) {} -uint32_t Hcal::getFirmwareVersion() { return 0; } +void Hcal::hardResetECONs() {} +void Hcal::softResetECONs() {} + +uint32_t Hcal::getFirmwareVersion() { return 0; } + } // namespace pflib diff --git a/src/pflib/lpgbt/lpGBT_standard_configs.cxx b/src/pflib/lpgbt/lpGBT_standard_configs.cxx index 15406056..1516687a 100644 --- a/src/pflib/lpgbt/lpGBT_standard_configs.cxx +++ b/src/pflib/lpgbt/lpGBT_standard_configs.cxx @@ -34,7 +34,7 @@ namespace pflib { lpgbt.setup_etx(0,true); // HGCROC2_FCMD lpgbt.setup_etx(1,true); // HGCROC0_FCMD lpgbt.setup_etx(2,true); // HGCROC3_FCMD - lpgbt.setup_etx(3,true); // ECON-T0_FCMF + lpgbt.setup_etx(3,true); // ECON-T0_FCMD lpgbt.setup_etx(4,true); // ECON-D_FCMD lpgbt.setup_etx(5,true); // ECON-T1_FCMD lpgbt.setup_etx(6,true); // HGCROC1_FCMD @@ -49,6 +49,8 @@ namespace pflib { void setup_hcal_trig(pflib::lpGBT& lpgbt) { // setup the reset lines + lpgbt.gpio_cfg_set(2,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"BOARD_I2C_RST"); + lpgbt.gpio_set(2, true); lpgbt.gpio_cfg_set(4,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC0_HRST"); lpgbt.gpio_set(4,true); lpgbt.gpio_cfg_set(7,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC0_SRST"); @@ -56,7 +58,13 @@ namespace pflib { lpgbt.gpio_cfg_set(6,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC3_HRST"); lpgbt.gpio_set(6,true); lpgbt.gpio_cfg_set(3,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC3_SRST"); - lpgbt.gpio_set(3,true); + lpgbt.gpio_set(3,true); + lpgbt.gpio_cfg_set(9,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"BIAS_I2C_RST"); + lpgbt.gpio_set(9, true); + lpgbt.gpio_cfg_set(8,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"ECON_HRST"); + lpgbt.gpio_set(8, true); + lpgbt.gpio_cfg_set(11,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"ECON_SRST"); + lpgbt.gpio_set(11, true); // setup the high speed inputs for (int i=0; i<6; i++) { diff --git a/src/pflib/zcu/HcalBackplaneZCU.cxx b/src/pflib/zcu/HcalBackplaneZCU.cxx index 827b5589..9c132c28 100644 --- a/src/pflib/zcu/HcalBackplaneZCU.cxx +++ b/src/pflib/zcu/HcalBackplaneZCU.cxx @@ -31,6 +31,7 @@ namespace pflib { printf("Create I2C objects "); econ_i2c_ = std::make_shared(*daq_lpgbt_, I2C_BUS_ECONS); econ_i2c_->set_bus_speed(1000); + add_econ(0, econ_i2c_); //roc_i2c_=std::make_shared(*daq_lpgbt_, I2C_BUS_HGCROCS); //roc_i2c_->set_bus_speed(1000); //for (int ibd=0; ibd<4; ibd++) { @@ -43,6 +44,8 @@ namespace pflib { // next, create the elinks object hcal_=std::shared_ptr(this); + hcal_->print_i2c_map(); + } virtual void softResetROC(int which) { // assuming everything was done with the standard config @@ -74,6 +77,14 @@ namespace pflib { trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",false); trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",true); } + virtual void hardResetECONs() { + trig_lpgbt_->gpio_interface().setGPO("ECON_HRST", false); + trig_lpgbt_->gpio_interface().setGPO("ECON_HRST", true); + } + virtual void softResetECONs() { + trig_lpgbt_->gpio_interface().setGPO("ECON_SRST", false); + trig_lpgbt_->gpio_interface().setGPO("ECON_SRST", true); + } virtual Elinks& elinks() { } virtual DAQ& daq() { } virtual std::vector read_event() { std::vector empty; return empty; } From 55d6b1c6a04d7d28ad4a2ec58a3656e67bdd6a57 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Thu, 2 Oct 2025 20:23:25 +0000 Subject: [PATCH 23/36] Adjust logic to exactly match iic.py --- src/pflib/lpGBT.cxx | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/pflib/lpGBT.cxx b/src/pflib/lpGBT.cxx index 38dd5989..fa31457a 100644 --- a/src/pflib/lpGBT.cxx +++ b/src/pflib/lpGBT.cxx @@ -505,10 +505,8 @@ static constexpr uint8_t CMD_I2C_READ_MULTI = 0xD; // copying all the data into the core... for (size_t i=0; i Date: Fri, 3 Oct 2025 13:41:34 +0000 Subject: [PATCH 24/36] add econ dev as checkpoint --- app/tool/econ.cxx | 44 +++++--- include/pflib/ECON.h | 6 +- include/pflib/Hcal.h | 43 ++++++-- src/pflib/ECON.cxx | 120 +++++++++++++++++---- src/pflib/GPIO.cxx | 5 + src/pflib/GPIO_HcalHGCROCZCU.cxx | 7 +- src/pflib/Hcal.cxx | 34 ++++-- src/pflib/lpGBT.cxx | 2 + src/pflib/lpgbt/GPIO.cxx | 12 +++ src/pflib/lpgbt/I2C.cxx | 5 + src/pflib/lpgbt/lpGBT_standard_configs.cxx | 2 + src/pflib/zcu/HcalBackplaneZCU.cxx | 28 ++--- 12 files changed, 236 insertions(+), 72 deletions(-) diff --git a/app/tool/econ.cxx b/app/tool/econ.cxx index 45299192..f958da47 100644 --- a/app/tool/econ.cxx +++ b/app/tool/econ.cxx @@ -31,16 +31,36 @@ static void econ_expert_render(Target* tgt) { * using the compiler * * ## Commands - * - POKE : set a specific register to a specific value pflib::ECON::setValue + * - READ : read a specific register + * - WRITE : write to a specific register */ static void econ_expert(const std::string& cmd, Target* tgt) { auto econ = tgt->hcal().econ(pftool::state.iecon, pftool::state.type_econ()); - if (cmd == "POKE") { - int page = pftool::readline_int("Which page? ", 0); - int entry = pftool::readline_int("Offset: ", 0); - int value = pftool::readline_int("New value: "); + if (cmd == "READ") { + std::string addr_str = pftool::readline("Register address (hex): ", "0x0000"); + int address = std::stoi(addr_str, nullptr, 16); + int nbytes = pftool::readline_int("Number of bytes to read: ", 1); - econ.setValue(page, entry, value); + std::vector data = econ.getValues(address, nbytes); + + printf("Read %d bytes from register 0x%04x:\n", nbytes, address); + for (size_t i = 0; i < data.size(); i++) { + printf(" [%02zu] = 0x%02x\n", i, data[i]); + } + } + else if (cmd == "WRITE") { + int address = pftool::readline_int("Register address (hex): ", 0x0000); + int nbytes = pftool::readline_int("Number of bytes to write: ", 1); + uint64_t value = pftool::readline_int("Value to write (hex): ", 0x0); + + // split value into bytes + std::vector data; + for (int i = 0; i < nbytes; ++i) { + data.push_back(static_cast((value >> (8 * i)) & 0xFF)); + } + + econ.setValues(address, data); + printf("Wrote 0x%llx to register 0x%04x (%d bytes)\n", value, address, nbytes); } } @@ -55,7 +75,6 @@ static void econ_expert(const std::string& cmd, Target* tgt) { * - SOFTRESET : pflib::Hcal::softResetECONs * - RUNMODE : enable run bit on the ECON * - IECON : Change which ECON to focus on - * - POKE : pflib::ECON::setValue * * @param[in] cmd ECON command * @param[in] pft active target @@ -79,12 +98,6 @@ static void econ(const std::string& cmd, Target* pft) { isRunMode = pftool::readline_bool("Set ECON runbit: ", isRunMode); econ.setRunMode(isRunMode); } - if (cmd == "POKE") { - //auto page = pftool::readline("Page: ", pftool::state.page_names()); - //auto param = pftool::readline("Parameter: ", pftool::state.param_names(page)); - //int val = pftool::readline_int("New value: "); - //econ.applyParameter(page, param, val); - } } @@ -99,7 +112,8 @@ auto menu_econ = ; auto menu_econ_expert = - menu_econ->submenu("EXPERT", "expert interaction with ECON", econ_expert_render) - ->line("POKE", "change a single register's value", econ_expert) + menu_econ->submenu("EXPERT", "expert interaction with ECON", econ_expert_render) + ->line("READ", "read a single register's value", econ_expert) + ->line("WRITE", "read a single register's value", econ_expert) ; } diff --git a/include/pflib/ECON.h b/include/pflib/ECON.h index 6ca9cb01..2c4d3a96 100644 --- a/include/pflib/ECON.h +++ b/include/pflib/ECON.h @@ -23,13 +23,13 @@ class ECON { void setRunMode(bool active = true); bool isRunMode(); - uint8_t getValue(int page, int offset); - void setValue(int page, int offset, uint8_t value); + std::vector getValues(int reg_addr, int nbytes); + void setValues(int reg_addr, const std::vector& values); private: I2C& i2c_; uint8_t econ_base_; - Compiler compiler_; + //Compiler compiler_; mutable ::pflib::logging::logger the_log_{::pflib::logging::get("econ")}; }; diff --git a/include/pflib/Hcal.h b/include/pflib/Hcal.h index 634ab78b..d643639f 100644 --- a/include/pflib/Hcal.h +++ b/include/pflib/Hcal.h @@ -24,12 +24,19 @@ class Hcal { /** number of boards */ int nrocs() { return nhgcroc_; } - int necons() { return necon_; } + int necons() { return necond_+necont_; } /** do we have a roc with this id? */ bool have_roc(int iroc) { return i2c_for_rocbd_.find(iroc)!=i2c_for_rocbd_.end(); } - bool have_econ(int iecon) { return i2c_for_econbd_.find(iecon)!=i2c_for_econbd_.end(); } + bool have_econ(int iecon, const std::string& type_econ) { + if (type_econ == "econd") { + return i2c_for_econd_.find(iecon) != i2c_for_econd_.end(); + } else if (type_econ == "econt") { + return i2c_for_econt_.find(iecon) != i2c_for_econt_.end(); + } + return false; + } /** Get a ROC interface for the given HGCROC board */ ROC roc(int which, const std::string& roc_type_version = "sipm_rocv3b"); @@ -64,9 +71,23 @@ class Hcal { /** get the DAQ object */ virtual DAQ& daq() = 0; - void print_i2c_map() { - for (const auto& [key, ptr] : i2c_for_econbd_) { - std::cout << "Hcal ECON I2C Key: " << key << ", I2C pointer: " << ptr.get() << std::endl; + void print_i2c_map() const { + std::cout << "=== ECON-D I2C Map ===" << std::endl; + if (i2c_for_econd_.empty()) { + std::cout << " (none)" << std::endl; + } else { + for (const auto& [key, ptr] : i2c_for_econd_) { + std::cout << " Key: " << key << ", I2C pointer: " << ptr.get() << std::endl; + } + } + + std::cout << "=== ECON-T I2C Map ===" << std::endl; + if (i2c_for_econt_.empty()) { + std::cout << " (none)" << std::endl; + } else { + for (const auto& [key, ptr] : i2c_for_econt_) { + std::cout << " Key: " << key << ", I2C pointer: " << ptr.get() << std::endl; + } } } @@ -75,13 +96,11 @@ class Hcal { void add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c); /** Add an ECON to the set of ECONs */ - void add_econ(int iecon, std::shared_ptr& econ_i2c); + void add_econ(int iecon, std::shared_ptr econ_i2c, const std::string& type_econ); /** Number of HGCROC boards in this system */ int nhgcroc_; - int necon_; - /** The GPIO interface */ std::unique_ptr gpio_; @@ -94,8 +113,12 @@ class Hcal { std::map i2c_for_rocbd_; - std::map> i2c_for_econbd_; - + /** The ECON I2C interface */ + std::map> i2c_for_econd_; // for econd + std::map> i2c_for_econt_; // for econt + int necond_; + int necont_; + }; } // namespace pflib diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx index de1e0628..2665aed7 100644 --- a/src/pflib/ECON.cxx +++ b/src/pflib/ECON.cxx @@ -12,49 +12,129 @@ namespace pflib { ECON::ECON(I2C& i2c, uint8_t econ_base_addr, const std::string& type_version) : i2c_{i2c}, - econ_base_{econ_base_addr}, - compiler_{Compiler::get(type_version)} { + econ_base_{econ_base_addr} + //compiler_{Compiler::get(type_version)} +{ pflib_log(debug) << "base addr " << packing::hex(econ_base_); } void ECON::setRunMode(bool active) { // TODO: implement writing run mode to the hardware - uint8_t reg_value = getValue(0x03c5, 3); - const uint32_t MASK_RUN_BIT = 0x000F; - const int SHIFT_RUN_BIT = 0; - uint32_t param = (reg_value & MASK_RUN_BIT) >> SHIFT_RUN_BIT; - //if (active) cval |= MASK_RUN_MODE; - //setValue(TOP_PAGE, 0, cval); } +uint32_t getParam(const std::vector& data, size_t shift, uint32_t mask) { + // combine bytes into a little-endian integer + // data[0] is the least significant byte, etc + uint64_t value = 0; + for (size_t i = 0; i < data.size(); ++i) { + value |= (static_cast(data[i]) << (8 * i)); + } + + // now extract the field + return (value >> shift) & mask; +} + +std::vector newParam(std::vector prev_value, uint16_t reg_addr, int nbytes, uint32_t mask, int shift, uint32_t value) { + // combine bytes into a single integer + uint32_t reg_val = 0; + for (int i = 0; i < nbytes; ++i) { + reg_val |= static_cast(prev_value[i]) << (8 * i); + } + + reg_val &= ~(mask << shift); + reg_val |= ((value & mask) << shift); + + // split back into bytes + std::vector new_data; + for (int i = 0; i < nbytes; ++i) { + new_data.push_back(static_cast((reg_val >> (8 * i)) & 0xFF)); + } + + printf("To update register 0x%04x: bits [%d:%d] set to 0x%x\n", + reg_addr, shift + static_cast(log2(mask)), shift, value); + + return new_data; +} + bool ECON::isRunMode() { - // TODO: implement reading run mode from the hardware - uint8_t reg_value = getValue(0x03c5, 3); - const uint32_t MASK_RUN_BIT = 0x000F; - const int SHIFT_RUN_BIT = 0; - uint32_t param = (reg_value & MASK_RUN_BIT) >> SHIFT_RUN_BIT; - return false; // placeholder + + std::vector data_03e4 = getValues(0x3e4, 1); + uint8_t reg_val_erxenable = getParam(data_03e4, 0, 1); + std::cout << "Register 0x3e4 erx0 enable: " << int(reg_val_erxenable) << std::endl; + + std::vector data_03e5 = getValues(0x3e5, 1); + std::cout << "Register 0x3e5 erx1 enable: " << int(getParam(data_03e5, 0, 1)) << std::endl; + + std::vector data_03AB = getValues(0x03AB, 1); + std::cout << "FCtrl_Global_command_rx_inverted value value " << getParam(data_03AB, 0, 1) << " locked " << getParam(data_03AB, 1, 1) << std::endl; + + // Read 3-byte register at 0x03C5 and extract run bit + std::vector data_03C5 = getValues(0x03C5, 3); + const uint32_t MASK_RUNBIT = 1; + const int SHIFT_RUNBIT = 23; + uint32_t pusm_run_value = getParam(data_03C5, SHIFT_RUNBIT, MASK_RUNBIT); + std::cout << "PUSM run value: " << pusm_run_value << std::endl; + + std::vector new_data_03C5 = newParam(data_03C5, 0x03C5, 3, MASK_RUNBIT, SHIFT_RUNBIT, 1); // set RUNBIT = 1 + //setValues(0x03C5, new_data_03C5); + + pusm_run_value = getParam(data_03C5, SHIFT_RUNBIT, MASK_RUNBIT); + std::cout << "new PUSM run value: " << pusm_run_value << std::endl; + + // Read 4-byte register at 0x03DF and extract PUSM state + std::vector data_03DF = getValues(0x3df, 4); + const uint32_t MASK_PUSMSTATE = 15; + const int SHIFT_PUSMSTATE = 0; + uint32_t pusm_state_value = getParam(data_03DF, SHIFT_PUSMSTATE, MASK_PUSMSTATE); + std::cout << "PUSM state value: " << pusm_state_value << std::endl; + + return pusm_run_value == 1 && pusm_state_value == 8; } -uint8_t ECON::getValue(int addr, int nbytes) { +std::vector ECON::getValues(int reg_addr, int nbytes) { if(nbytes < 1) { pflib_log(error) << "Invalid nbytes = " << nbytes; } - pflib_log(debug) << "ECON::getValue(" << addr << ", " << nbytes << ")"; + pflib_log(info) << "ECON::getValues(" << packing::hex(reg_addr) << ", " << nbytes << ") from " << packing::hex(econ_base_); std::vector waddr; - waddr.push_back(static_cast(addr & 0xFF)); - waddr.push_back(static_cast((addr >> 8) & 0xFF)); + waddr.push_back(static_cast((reg_addr >> 8) & 0xFF)); + waddr.push_back(static_cast(reg_addr & 0xFF)); std::vector data = i2c_.general_write_read(econ_base_, waddr, nbytes); for (size_t i = 0; i < data.size(); i++) { printf("%02zu : %02x\n", i, data[i]); } + + return data; } -void ECON::setValue(int page, int offset, uint8_t value) { - // TODO: implement writing a register to the hardware +void ECON::setValues(int reg_addr, const std::vector& values) { + if (values.empty()) { + pflib_log(error) << "ECON::setValues called with empty data vector"; + return; + } + + pflib_log(info) << "ECON::setValues(" + << packing::hex(reg_addr) + << ", nbytes = " << values.size() + << ") to " << packing::hex(econ_base_); + + // write buffer + std::vector wbuf; + wbuf.push_back(static_cast((reg_addr >> 8) & 0xFF)); + wbuf.push_back(static_cast(reg_addr & 0xFF)); + wbuf.insert(wbuf.end(), values.begin(), values.end()); + + // Perform write + i2c_.general_write_read(econ_base_, wbuf, values.size()); + + // Log written data + printf("Wrote %zu bytes to register 0x%04x:\n", values.size(), reg_addr); + for (size_t i = 0; i < values.size(); ++i) { + printf(" %02zu : %02x\n", i, values[i]); + } } } // namespace pflib diff --git a/src/pflib/GPIO.cxx b/src/pflib/GPIO.cxx index db1ee0ea..2124838b 100644 --- a/src/pflib/GPIO.cxx +++ b/src/pflib/GPIO.cxx @@ -10,6 +10,11 @@ namespace pflib { bool GPIO::hasGPO(const std::string& name) { std::vector names=getGPOs(); + printf("Available GPOs:\n"); + for (const auto& n : names) { + printf(" %s\n", n.c_str()); + } + for (auto i : names) { if (i==name) return true; } diff --git a/src/pflib/GPIO_HcalHGCROCZCU.cxx b/src/pflib/GPIO_HcalHGCROCZCU.cxx index 8499ed95..8caf9c28 100644 --- a/src/pflib/GPIO_HcalHGCROCZCU.cxx +++ b/src/pflib/GPIO_HcalHGCROCZCU.cxx @@ -120,7 +120,12 @@ void GPIO_HcalHGCROCZCU::setGPO(const std::string& name, bool toTrue) { bool GPIO_HcalHGCROCZCU::getGPO(const std::string& name) { auto ptr=gpos_.find(name); if (ptr==gpos_.end()) { - PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); + std::vector names = getGPOs(); + printf("HcalHGCROCZCU Available GPOs:\n"); + for (const auto& n : names) { + printf(" %s\n", n.c_str()); + } + PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("GPO ZCU Unknown GPO bit '%s'",name.c_str())); } int ibit=ptr->second; diff --git a/src/pflib/Hcal.cxx b/src/pflib/Hcal.cxx index 67ecf658..a9326ec5 100644 --- a/src/pflib/Hcal.cxx +++ b/src/pflib/Hcal.cxx @@ -5,7 +5,8 @@ namespace pflib { Hcal::Hcal() { nhgcroc_ = 0; - necon_ = 0; + necond_ = 0; + necont_ = 0; } void Hcal::add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr& bias_i2c, std::shared_ptr& board_i2c) { @@ -21,24 +22,35 @@ void Hcal::add_roc(int iroc, std::shared_ptr& roc_i2c, std::shared_ptr } ECON Hcal::econ(int which, const std::string& type_econ) { - if (!have_econ(which)) { - PFEXCEPTION_RAISE("InvalidECONid", pflib::utility::string_format("Unknown ECON id %d",which)); + if (!have_econ(which, type_econ)) { + PFEXCEPTION_RAISE("InvalidECONid", + pflib::utility::string_format("Unknown ECON id %d (type %s)", which, type_econ.c_str())); } + if (type_econ == "econd") { - return ECON(*i2c_for_econbd_[which], 0x60 | (which * 8), type_econ); + return ECON(*i2c_for_econd_[which], 0x60 | (which * 8), type_econ); } else if (type_econ == "econt") { - return ECON(*i2c_for_econbd_[which], 0x20 | (which * 8), type_econ); + return ECON(*i2c_for_econt_[which], 0x20 | (which * 8), type_econ); } else { - throw std::runtime_error("Unknown ECON type: " + type_econ); + throw std::runtime_error("Unknown ECON type in econ(): " + type_econ); } } -void Hcal::add_econ(int iecon, std::shared_ptr& econ_i2c) { - if (have_econ(iecon)) { - PFEXCEPTION_RAISE("DuplicateECON",pflib::utility::string_format("Already have registered ECON with id %d",iecon)); +void Hcal::add_econ(int iecon, std::shared_ptr econ_i2c, const std::string& type_econ) { + if (have_econ(iecon, type_econ)) { + PFEXCEPTION_RAISE("DuplicateECON", + pflib::utility::string_format("Already have registered %s with id %d", type_econ.c_str(), iecon)); + } + + if (type_econ == "econd") { + i2c_for_econd_[iecon] = econ_i2c; + necond_++; + } else if (type_econ == "econt") { + i2c_for_econt_[iecon] = econ_i2c; + necont_++; + } else { + throw std::runtime_error("Unknown ECON type in add_econ: " + type_econ); } - necon_++; - i2c_for_econbd_[iecon]=econ_i2c; } ROC Hcal::roc(int which, const std::string& roc_type_version) { diff --git a/src/pflib/lpGBT.cxx b/src/pflib/lpGBT.cxx index fa31457a..751bd4e8 100644 --- a/src/pflib/lpGBT.cxx +++ b/src/pflib/lpGBT.cxx @@ -498,6 +498,7 @@ static constexpr uint8_t CMD_I2C_READ_MULTI = 0xD; } void lpGBT::i2c_write(int ibus, uint8_t i2c_addr, const std::vector& values) { + printf("ibus %i\n", ibus); if (ibus<0 || ibus>2 || values.size()>16) return; write(REG_I2CM0ADDRESS+ibus*REG_I2C_WSTRIDE,i2c_addr); write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,i2c_[ibus].ctl_reg|(values.size()<<2)); @@ -505,6 +506,7 @@ static constexpr uint8_t CMD_I2C_READ_MULTI = 0xD; // copying all the data into the core... for (size_t i=0; i names = getGPOs(); + printf("lpGBT Available GPOs:\n"); + for (const auto& n : names) { + printf(" %s\n", n.c_str()); + } PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); } int ibit=ptr->second; @@ -37,6 +44,11 @@ namespace pflib { void GPIO::setGPO(const std::string& name, bool toTrue) { auto ptr=gpos_.find(name); if (ptr==gpos_.end()) { + std::vector names = getGPOs(); + printf("lpGBT set Available GPOs:\n"); + for (const auto& n : names) { + printf(" %s\n", n.c_str()); + } PFEXCEPTION_RAISE("GPIOError", pflib::utility::string_format("Unknown GPO bit '%s'",name.c_str())); } int ibit=ptr->second; diff --git a/src/pflib/lpgbt/I2C.cxx b/src/pflib/lpgbt/I2C.cxx index 7b236ee1..d8df9eee 100644 --- a/src/pflib/lpgbt/I2C.cxx +++ b/src/pflib/lpgbt/I2C.cxx @@ -22,6 +22,11 @@ namespace pflib { } std::vector I2C::general_write_read(uint8_t i2c_dev_addr, const std::vector& wdata,int nread) { if (!wdata.empty()) { + printf("I2C write to device 0x%02X, %zu bytes: ", i2c_dev_addr, wdata.size()); + for (size_t i = 0; i < wdata.size(); ++i) { + printf("0x%02X ", wdata[i]); + } + printf("\n"); if (wdata.size()==1) lpgbt_.i2c_write(ibus_,i2c_dev_addr,wdata[0]); else lpgbt_.i2c_write(ibus_,i2c_dev_addr,wdata); lpgbt_.i2c_transaction_check(ibus_,true); diff --git a/src/pflib/lpgbt/lpGBT_standard_configs.cxx b/src/pflib/lpgbt/lpGBT_standard_configs.cxx index 1516687a..935cb72e 100644 --- a/src/pflib/lpgbt/lpGBT_standard_configs.cxx +++ b/src/pflib/lpgbt/lpGBT_standard_configs.cxx @@ -7,6 +7,8 @@ namespace pflib { void setup_hcal_daq(pflib::lpGBT& lpgbt) { // setup the reset lines + // each call configures the pin number, mode, and assigns a name + // then we set an initial value (true = high, false = low) lpgbt.gpio_cfg_set(0,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC2_HRST"); lpgbt.gpio_set(0,true); lpgbt.gpio_cfg_set(1,lpGBT::GPIO_IS_OUTPUT|lpGBT::GPIO_IS_PULLUP|lpGBT::GPIO_IS_STRONG,"HGCROC2_SRST"); diff --git a/src/pflib/zcu/HcalBackplaneZCU.cxx b/src/pflib/zcu/HcalBackplaneZCU.cxx index 9c132c28..a1266d5e 100644 --- a/src/pflib/zcu/HcalBackplaneZCU.cxx +++ b/src/pflib/zcu/HcalBackplaneZCU.cxx @@ -3,6 +3,7 @@ #include "pflib/utility/string_format.h" #include "pflib/lpgbt/I2C.h" #include "pflib/zcu/lpGBT_ICEC_ZCU_Simple.h" +#include "pflib/lpgbt/lpGBT_standard_configs.h" namespace pflib { @@ -31,7 +32,9 @@ namespace pflib { printf("Create I2C objects "); econ_i2c_ = std::make_shared(*daq_lpgbt_, I2C_BUS_ECONS); econ_i2c_->set_bus_speed(1000); - add_econ(0, econ_i2c_); + add_econ(0, econ_i2c_, "econd"); + add_econ(0, econ_i2c_, "econt"); + add_econ(1, econ_i2c_, "econt"); //roc_i2c_=std::make_shared(*daq_lpgbt_, I2C_BUS_HGCROCS); //roc_i2c_->set_bus_speed(1000); //for (int ibd=0; ibd<4; ibd++) { @@ -42,10 +45,11 @@ namespace pflib { //} // next, create the elinks object - hcal_=std::shared_ptr(this); - hcal_->print_i2c_map(); - + //hcal_->print_i2c_map(); + + pflib::lpgbt::standard_config::setup_hcal_trig(*trig_lpgbt_); + pflib::lpgbt::standard_config::setup_hcal_daq(*daq_lpgbt_); } virtual void softResetROC(int which) { // assuming everything was done with the standard config @@ -68,14 +72,14 @@ namespace pflib { } virtual void hardResetROCs() { - trig_lpgbt_->gpio_interface().setGPO("HGCROC0_HRST",false); - trig_lpgbt_->gpio_interface().setGPO("HGCROC0_HRST",true); - daq_lpgbt_->gpio_interface().setGPO("HGCROC1_HRST",false); - daq_lpgbt_->gpio_interface().setGPO("HGCROC1_HRST",true); - daq_lpgbt_->gpio_interface().setGPO("HGCROC2_HRST",false); - daq_lpgbt_->gpio_interface().setGPO("HGCROC2_HRST",true); - trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",false); - trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",true); + trig_lpgbt_->gpio_interface().setGPO("HGCROC0_HRST",false); + trig_lpgbt_->gpio_interface().setGPO("HGCROC0_HRST",true); + daq_lpgbt_->gpio_interface().setGPO("HGCROC1_HRST",false); + daq_lpgbt_->gpio_interface().setGPO("HGCROC1_HRST",true); + daq_lpgbt_->gpio_interface().setGPO("HGCROC2_HRST",false); + daq_lpgbt_->gpio_interface().setGPO("HGCROC2_HRST",true); + trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",false); + trig_lpgbt_->gpio_interface().setGPO("HGCROC3_HRST",true); } virtual void hardResetECONs() { trig_lpgbt_->gpio_interface().setGPO("ECON_HRST", false); From a8df09de567aca298711240bf0b84ef17153b0b0 Mon Sep 17 00:00:00 2001 From: Jeremiah Mans Date: Fri, 3 Oct 2025 15:46:05 +0000 Subject: [PATCH 25/36] Correct multibyte I2C read for the strange lpGBT ordering... --- src/pflib/lpGBT.cxx | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/pflib/lpGBT.cxx b/src/pflib/lpGBT.cxx index fa31457a..eb4d1ee5 100644 --- a/src/pflib/lpGBT.cxx +++ b/src/pflib/lpGBT.cxx @@ -130,6 +130,7 @@ static constexpr uint16_t REG_I2CM0CMD = 0x106; static constexpr uint16_t REG_I2CM0STATUS = 0x171; static constexpr uint16_t REG_I2CM0READBYTE = 0x173; static constexpr uint16_t REG_I2CM0READ0 = 0x174; +static constexpr uint16_t REG_I2CM0READ15 = 0x183; static constexpr uint16_t REG_I2C_WSTRIDE = 7; static constexpr uint16_t REG_I2C_RSTRIDE = 21; @@ -544,7 +545,9 @@ static constexpr uint8_t CMD_I2C_READ_MULTI = 0xD; if (i2c_[ibus].read_len==1) { retval.push_back(read(REG_I2CM0READBYTE+ibus*REG_I2C_RSTRIDE)); } else { - return read(REG_I2CM0READBYTE+ibus*REG_I2C_RSTRIDE,i2c_[ibus].read_len); + // super-weird -- it's stored in backwards order... + retval=read(REG_I2CM0READ15+1-i2c_[ibus].read_len+ibus*REG_I2C_RSTRIDE,i2c_[ibus].read_len); + std::reverse(retval.begin(),retval.end()); } return retval; } From b5b4f9a843d3129dd9687ecab712b11f34ffcbb9 Mon Sep 17 00:00:00 2001 From: cmantill Date: Fri, 3 Oct 2025 21:14:31 +0000 Subject: [PATCH 26/36] checkpoint --- CMakeLists.txt | 9 ++-- register_maps/econ-to-header.py | 13 +++-- register_maps/write-unifying-header.py | 10 ++-- src/pflib/Compile.cxx | 10 ++-- src/pflib/ECON.cxx | 66 +++++++++++++++----------- src/pflib/Hcal.cxx | 13 +++++ src/pflib/lpGBT.cxx | 1 - src/pflib/lpgbt/I2C.cxx | 5 -- 8 files changed, 75 insertions(+), 52 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7206f94c..3dcc5629 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -113,7 +113,7 @@ add_custom_command( COMMENT "Generating C++ ECOND register LUT from register_maps/ECOND_I2C_params_regmap.yaml" VERBATIM ) -add_custom_target(econd_regmap DEPENDS include/register_maps/econd.h) +add_custom_target(econd DEPENDS include/register_maps/econd.h) add_custom_command( OUTPUT "include/register_maps/econt.h" @@ -128,7 +128,10 @@ add_custom_command( COMMENT "Generating C++ ECONT register LUT from register_maps/ECONT_I2C_params_regmap.yaml" VERBATIM ) -add_custom_target(econt_regmap DEPENDS include/register_maps/econt.h) +add_custom_target(econt DEPENDS include/register_maps/econt.h) + +#list(APPEND generate_headers econd) +#list(APPEND generate_headers econt) add_custom_command( OUTPUT include/register_maps/register_maps.h @@ -216,7 +219,7 @@ target_include_directories(pflib PUBLIC "$" "$") target_link_libraries(pflib PUBLIC yaml-cpp::yaml-cpp packing Boost::log version utility) -add_dependencies(pflib register_maps_header direct_access lpgbt_regmap) +add_dependencies(pflib register_maps_header direct_access lpgbt_regmap econd) add_library(menu SHARED src/pflib/menu/Menu.cc diff --git a/register_maps/econ-to-header.py b/register_maps/econ-to-header.py index 22582607..5169d489 100644 --- a/register_maps/econ-to-header.py +++ b/register_maps/econ-to-header.py @@ -94,12 +94,17 @@ def generate_header(input_yaml, data): name_prefix = f"{group_name}_{reg_name}" process_register(name_prefix, props, lines) - for reg_name, props in registers.items(): - name_prefix = f"{group_name}_{reg_name}" - process_register(name_prefix, props, lines) + # for reg_name, props in registers.items(): + # name_prefix = f"{group_name}_{reg_name}" + # process_register(name_prefix, props, lines) page_names.append(page_var) lines.append(" });") + #lines.append("\nconst ParameterLUT PARAMETER_LUT = ParameterLUT::Mapping({") + #for name in page_names: + # lines.append(f' {{"{name}", {name}}},') + #lines.append("});") + lines.append("\nconst PageLUT PAGE_LUT = PageLUT::Mapping({") for name in page_names: lines.append(f' {{"{name}", {name}}},') @@ -122,4 +127,4 @@ def compile_registers(yaml_file, output_file): print("Usage: python3 compile_registers.py ") sys.exit(1) - compile_registers(sys.argv[1], sys.argv[2]) \ No newline at end of file + compile_registers(sys.argv[1], sys.argv[2]) diff --git a/register_maps/write-unifying-header.py b/register_maps/write-unifying-header.py index 43c113bf..8dab0ac9 100644 --- a/register_maps/write-unifying-header.py +++ b/register_maps/write-unifying-header.py @@ -5,8 +5,8 @@ parser = argparse.ArgumentParser() parser.add_argument( - 'roc_types', - help='list of ROC types that were generated headers', + 'types', + help='list of types that were generated headers', nargs='+' ) parser.add_argument( @@ -20,13 +20,13 @@ f.write('/* auto generated from scratch */\n\n') f.write('#pragma once\n\n') f.write('// include the register maps for each ROC type/version\n') - for rt in args.roc_types: + for rt in args.types: f.write('#include "register_maps/{rt}.h"\n'.format(rt=rt)) f.write('\n// name the register maps so they can be retrieved by name\n') f.write('const std::map>\n') - f.write('REGISTER_MAP_BY_ROC_TYPE = {\n') + f.write('REGISTER_MAP_BY_TYPE = {\n') f.write(',\n'.join( ' {"%s", {%s::PAGE_LUT, %s::PARAMETER_LUT}}'%(rt,rt,rt) - for rt in args.roc_types + for rt in args.types )) f.write('\n};\n\n') diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index 1d59f04a..6bdcbcbd 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -20,11 +20,11 @@ std::string upper_cp(const std::string& str) { #include "register_maps/register_maps.h" -Compiler Compiler::get(const std::string& roc_type_version) { - auto reg_map_it = REGISTER_MAP_BY_ROC_TYPE.find(roc_type_version); - if (reg_map_it == REGISTER_MAP_BY_ROC_TYPE.end()) { - PFEXCEPTION_RAISE("BadRocType", "ROC type_version " + roc_type_version + - " is not present within the map."); +Compiler Compiler::get(const std::string& type_version) { + auto reg_map_it = REGISTER_MAP_BY_TYPE.find(type_version); + if (reg_map_it == REGISTER_MAP_BY_TYPE.end()) { + PFEXCEPTION_RAISE("BadType", "Type_version " + type_version + + " is not present within the map."); } return Compiler(reg_map_it->second.second, reg_map_it->second.first); } diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx index 2665aed7..0dfc17b4 100644 --- a/src/pflib/ECON.cxx +++ b/src/pflib/ECON.cxx @@ -15,11 +15,7 @@ ECON::ECON(I2C& i2c, uint8_t econ_base_addr, const std::string& type_version) econ_base_{econ_base_addr} //compiler_{Compiler::get(type_version)} { - pflib_log(debug) << "base addr " << packing::hex(econ_base_); -} - -void ECON::setRunMode(bool active) { - // TODO: implement writing run mode to the hardware + pflib_log(debug) << "ECON base addr " << packing::hex(econ_base_); } uint32_t getParam(const std::vector& data, size_t shift, uint32_t mask) { @@ -50,23 +46,40 @@ std::vector newParam(std::vector prev_value, uint16_t reg_addr new_data.push_back(static_cast((reg_val >> (8 * i)) & 0xFF)); } - printf("To update register 0x%04x: bits [%d:%d] set to 0x%x\n", - reg_addr, shift + static_cast(log2(mask)), shift, value); + //printf("To update register 0x%04x: bits [%d:%d] set to 0x%x\n", + // reg_addr, shift + static_cast(log2(mask)), shift, value); return new_data; } - -bool ECON::isRunMode() { - std::vector data_03e4 = getValues(0x3e4, 1); - uint8_t reg_val_erxenable = getParam(data_03e4, 0, 1); - std::cout << "Register 0x3e4 erx0 enable: " << int(reg_val_erxenable) << std::endl; +void ECON::setRunMode(bool active) { + int nbytes = 3; + const uint32_t MASK_RUNBIT = 1; + const int SHIFT_RUNBIT = 23; + std::vector data_03C5 = getValues(0x03C5, 3); + std::vector new_data_03C5 = newParam(data_03C5, 0x03C5, nbytes, MASK_RUNBIT, SHIFT_RUNBIT, 1); + auto value = getParam(new_data_03C5, SHIFT_RUNBIT, MASK_RUNBIT); + std::cout << "new 03C5 value to write: " << value << std::endl; + + std::vector data; + for (int i = 0; i < nbytes; ++i) { + data.push_back(static_cast((value >> (8 * i)) & 0xFF)); + } + + setValues(0x03C5, data); + printf("Wrote 0x%llx to register 0x%04x (%d bytes)\n", value, 0x03C5, nbytes); - std::vector data_03e5 = getValues(0x3e5, 1); - std::cout << "Register 0x3e5 erx1 enable: " << int(getParam(data_03e5, 0, 1)) << std::endl; + std::vector data_03DF = getValues(0x3df, 4); + const uint32_t MASK_PUSMSTATE = 15; + const int SHIFT_PUSMSTATE = 0; + uint32_t pusm_state_value = getParam(data_03DF, SHIFT_PUSMSTATE, MASK_PUSMSTATE); + std::cout << "new PUSM state value: " << pusm_state_value << std::endl; +} +bool ECON::isRunMode() { + std::vector data_03AB = getValues(0x03AB, 1); - std::cout << "FCtrl_Global_command_rx_inverted value value " << getParam(data_03AB, 0, 1) << " locked " << getParam(data_03AB, 1, 1) << std::endl; + std::cout << "FCtrl_Global_command_rx_inverted " << getParam(data_03AB, 0, 1) << " locked " << getParam(data_03AB, 1, 1) << std::endl; // Read 3-byte register at 0x03C5 and extract run bit std::vector data_03C5 = getValues(0x03C5, 3); @@ -75,12 +88,6 @@ bool ECON::isRunMode() { uint32_t pusm_run_value = getParam(data_03C5, SHIFT_RUNBIT, MASK_RUNBIT); std::cout << "PUSM run value: " << pusm_run_value << std::endl; - std::vector new_data_03C5 = newParam(data_03C5, 0x03C5, 3, MASK_RUNBIT, SHIFT_RUNBIT, 1); // set RUNBIT = 1 - //setValues(0x03C5, new_data_03C5); - - pusm_run_value = getParam(data_03C5, SHIFT_RUNBIT, MASK_RUNBIT); - std::cout << "new PUSM run value: " << pusm_run_value << std::endl; - // Read 4-byte register at 0x03DF and extract PUSM state std::vector data_03DF = getValues(0x3df, 4); const uint32_t MASK_PUSMSTATE = 15; @@ -94,18 +101,19 @@ bool ECON::isRunMode() { std::vector ECON::getValues(int reg_addr, int nbytes) { if(nbytes < 1) { pflib_log(error) << "Invalid nbytes = " << nbytes; + return {}; } - pflib_log(info) << "ECON::getValues(" << packing::hex(reg_addr) << ", " << nbytes << ") from " << packing::hex(econ_base_); + //pflib_log(info) << "ECON::getValues(" << packing::hex(reg_addr) << ", " << nbytes << ") from " << packing::hex(econ_base_); std::vector waddr; waddr.push_back(static_cast((reg_addr >> 8) & 0xFF)); waddr.push_back(static_cast(reg_addr & 0xFF)); - std::vector data = i2c_.general_write_read(econ_base_, waddr, nbytes); - for (size_t i = 0; i < data.size(); i++) { - printf("%02zu : %02x\n", i, data[i]); - } + + //for (size_t i = 0; i < data.size(); i++) { + // printf("%02zu : %02x\n", i, data[i]); + //} return data; } @@ -117,9 +125,9 @@ void ECON::setValues(int reg_addr, const std::vector& values) { } pflib_log(info) << "ECON::setValues(" - << packing::hex(reg_addr) + << packing::hex(reg_addr) << ", nbytes = " << values.size() - << ") to " << packing::hex(econ_base_); + << ") to " << packing::hex(econ_base_); // write buffer std::vector wbuf; @@ -127,7 +135,7 @@ void ECON::setValues(int reg_addr, const std::vector& values) { wbuf.push_back(static_cast(reg_addr & 0xFF)); wbuf.insert(wbuf.end(), values.begin(), values.end()); - // Perform write + // perform write i2c_.general_write_read(econ_base_, wbuf, values.size()); // Log written data diff --git a/src/pflib/Hcal.cxx b/src/pflib/Hcal.cxx index a9326ec5..1072694f 100644 --- a/src/pflib/Hcal.cxx +++ b/src/pflib/Hcal.cxx @@ -28,8 +28,10 @@ ECON Hcal::econ(int which, const std::string& type_econ) { } if (type_econ == "econd") { + std::cout << "econd " << (0x60 | (which * 8)) << std::endl; return ECON(*i2c_for_econd_[which], 0x60 | (which * 8), type_econ); } else if (type_econ == "econt") { + std::cout << "econt " << (0x20 | (which * 8)) << std::endl; return ECON(*i2c_for_econt_[which], 0x20 | (which * 8), type_econ); } else { throw std::runtime_error("Unknown ECON type in econ(): " + type_econ); @@ -51,6 +53,17 @@ void Hcal::add_econ(int iecon, std::shared_ptr econ_i2c, const std::string& } else { throw std::runtime_error("Unknown ECON type in add_econ: " + type_econ); } + + std::cout << "=== i2c_for_econd_ map ===" << std::endl; + for (const auto& [key, value] : i2c_for_econd_) { + std::cout << key << " : 0x" << std::hex << value << std::dec << std::endl; + } + std::cout << "===========================" << std::endl; + std::cout << "=== i2c_for_econt_ map ===" << std::endl; + for (const auto& [key, value] : i2c_for_econt_) { + std::cout << key << " : 0x" << std::hex << value << std::dec << std::endl; + } + std::cout << "===========================" << std::endl; } ROC Hcal::roc(int which, const std::string& roc_type_version) { diff --git a/src/pflib/lpGBT.cxx b/src/pflib/lpGBT.cxx index 25ae7d7e..1c7a5431 100644 --- a/src/pflib/lpGBT.cxx +++ b/src/pflib/lpGBT.cxx @@ -499,7 +499,6 @@ static constexpr uint8_t CMD_I2C_READ_MULTI = 0xD; } void lpGBT::i2c_write(int ibus, uint8_t i2c_addr, const std::vector& values) { - printf("ibus %i\n", ibus); if (ibus<0 || ibus>2 || values.size()>16) return; write(REG_I2CM0ADDRESS+ibus*REG_I2C_WSTRIDE,i2c_addr); write(REG_I2CM0DATA0+ibus*REG_I2C_WSTRIDE,i2c_[ibus].ctl_reg|(values.size()<<2)); diff --git a/src/pflib/lpgbt/I2C.cxx b/src/pflib/lpgbt/I2C.cxx index d8df9eee..7b236ee1 100644 --- a/src/pflib/lpgbt/I2C.cxx +++ b/src/pflib/lpgbt/I2C.cxx @@ -22,11 +22,6 @@ namespace pflib { } std::vector I2C::general_write_read(uint8_t i2c_dev_addr, const std::vector& wdata,int nread) { if (!wdata.empty()) { - printf("I2C write to device 0x%02X, %zu bytes: ", i2c_dev_addr, wdata.size()); - for (size_t i = 0; i < wdata.size(); ++i) { - printf("0x%02X ", wdata[i]); - } - printf("\n"); if (wdata.size()==1) lpgbt_.i2c_write(ibus_,i2c_dev_addr,wdata[0]); else lpgbt_.i2c_write(ibus_,i2c_dev_addr,wdata); lpgbt_.i2c_transaction_check(ibus_,true); From 215d039942f429fd2da1851d1a9817d1101b618f Mon Sep 17 00:00:00 2001 From: cmantill Date: Tue, 7 Oct 2025 20:13:46 +0000 Subject: [PATCH 27/36] split into 16 byte reads max --- register_maps/econ-to-header.py | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/register_maps/econ-to-header.py b/register_maps/econ-to-header.py index 5169d489..9009971e 100644 --- a/register_maps/econ-to-header.py +++ b/register_maps/econ-to-header.py @@ -14,7 +14,9 @@ def safe_int(val): def make_register_locations(address, mask, shift, size_byte): """Split a register into 8-bit chunks if it spans multiple bytes. - syntax reminder: RegisterLocation(reg, min_bit, n_bits): + syntax reminder: + RegisterLocation(reg, min_bit, n_bits): + - reg = register 16-bit address - min_bit = param_shift for the first chunk, 0 for others - n_bits = number of 1's in the mask for the chunk """ @@ -45,6 +47,7 @@ def make_register_locations(address, mask, shift, size_byte): def process_register(name_prefix, props, lines): """ Process recursively a register or nested subregisters and append C++ lines. + This will split big registers (>16 bytes) into multiple Parameters with suffixes (16 bytes is the max that lpGBT can handle). name_prefix: current register name prefix (e.g., 'USER_WORD') props: dict containing either address/mask/shift or nested subkeys lines: list of strings to append to @@ -57,12 +60,27 @@ def process_register(name_prefix, props, lines): default_value = props.get("default_value", 0) size_byte = props.get("size_byte", 1) - # account for multi-byte registers + # generate all register locations and account for multi-byte registers reg_locs = make_register_locations(address, mask, shift, size_byte) reg_locs_str = ", ".join(reg_locs) + + # split into chunks of 16 bytes + chunk_size = 16 + total_chunks = (len(reg_locs) + chunk_size - 1) // chunk_size + + for chunk_idx in range(total_chunks): + start = chunk_idx * chunk_size + end = start + chunk_size + chunk = reg_locs[start:end] + # use upper + chunk_name = ( + f"{name_prefix.upper()}" + if total_chunks == 1 + else f"{name_prefix.upper()}_{chunk_idx}" + ) + chunk_str = ", ".join(chunk) + lines.append(f' {{"{chunk_name}", Parameter({{{chunk_str}}}, {default_value})}},') - cpp_name = name_prefix.upper() - lines.append(f' {{"{cpp_name}", Parameter({{{reg_locs_str}}}, {default_value})}},') else: # look for nested subkeys if props is a dict if isinstance(props, dict): @@ -94,9 +112,6 @@ def generate_header(input_yaml, data): name_prefix = f"{group_name}_{reg_name}" process_register(name_prefix, props, lines) - # for reg_name, props in registers.items(): - # name_prefix = f"{group_name}_{reg_name}" - # process_register(name_prefix, props, lines) page_names.append(page_var) lines.append(" });") From eea8349a5d6e69a23e2ba1127b349f544b5f962f Mon Sep 17 00:00:00 2001 From: cmantill Date: Wed, 8 Oct 2025 18:05:01 +0000 Subject: [PATCH 28/36] fix header --- CMakeLists.txt | 9 +++--- app/pfcompile.cxx | 14 ++++----- register_maps/econ-to-header.py | 36 +++++++++++++---------- register_maps/write-unifying-header.py | 26 +++++++++++++---- src/pflib/Compile.cxx | 40 ++++++++++++++++++++++---- 5 files changed, 88 insertions(+), 37 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 3dcc5629..bf0a60b1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -130,16 +130,17 @@ add_custom_command( ) add_custom_target(econt DEPENDS include/register_maps/econt.h) -#list(APPEND generate_headers econd) -#list(APPEND generate_headers econt) +list(APPEND generate_headers_econ econd) +list(APPEND generate_headers_econ econt) add_custom_command( OUTPUT include/register_maps/register_maps.h COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps COMMAND python3 ${PROJECT_SOURCE_DIR}/register_maps/write-unifying-header.py - ${generate_headers} --output include/register_maps/register_maps.h + --roc_types ${generate_headers} --econ_types ${generate_headers_econ} --output include/register_maps/register_maps.h COMMAND cp ${PROJECT_SOURCE_DIR}/register_maps/register_maps_types.h include/register_maps/ DEPENDS ${generate_headers} ${PROJECT_SOURCE_DIR}/register_maps/register_maps_types.h + DEPENDS ${generate_headers_econ} ${PROJECT_SOURCE_DIR}/register_maps/register_maps_types.h COMMENT "Writing unifying header for parameter LUTs" VERBATIM ) @@ -219,7 +220,7 @@ target_include_directories(pflib PUBLIC "$" "$") target_link_libraries(pflib PUBLIC yaml-cpp::yaml-cpp packing Boost::log version utility) -add_dependencies(pflib register_maps_header direct_access lpgbt_regmap econd) +add_dependencies(pflib register_maps_header direct_access lpgbt_regmap) add_library(menu SHARED src/pflib/menu/Menu.cc diff --git a/app/pfcompile.cxx b/app/pfcompile.cxx index 895f1384..17772dcd 100644 --- a/app/pfcompile.cxx +++ b/app/pfcompile.cxx @@ -1,5 +1,5 @@ /** - * "compiler" translating YAML HGCROC settings files + * "compiler" translating YAML HGCROC/ECON settings files * into a CSV file that contains registers and their values * defined by the settings in the YAML. * @@ -24,7 +24,7 @@ static void usage() { " OPTIONS:\n" " -v,--version : Print pflib version\n" " -h,--help : Print this help and exit\n" - " -r,--roc : Define the ROC type_version that should be " + " -c,--chip : Define the CHIP type_version that should be " "used for compilation\n" " By default, we use the sipm_rocv3b register " "mapping.\n" @@ -48,7 +48,7 @@ int main(int argc, char* argv[]) { bool prepend_defaults = true; std::vector setting_files; - std::string roc_type_version{"sipm_rocv3b"}; + std::string type_version{"sipm_rocv3b"}; std::string output_filename; for (int i_arg{1}; i_arg < argc; i_arg++) { std::string arg{argv[i_arg]}; @@ -62,14 +62,14 @@ int main(int argc, char* argv[]) { } else if (arg == "--version" or arg == "-v") { std::cout << "pflib " << pflib::version::debug() << std::endl; return 0; - } else if (arg == "--roc" or arg == "-r") { + } else if (arg == "--chip" or arg == "-c") { if (i_arg + 1 == argc or argv[i_arg + 1][0] == '-') { pflib_log(fatal) << "The " << arg << " parameter requires are argument after it."; return 1; } i_arg++; - roc_type_version = argv[i_arg]; + type_version = argv[i_arg]; } else if (arg == "--output" or arg == "-o") { if (i_arg + 1 == argc or argv[i_arg + 1][0] == '-') { pflib_log(fatal) << "The " << arg @@ -89,7 +89,7 @@ int main(int argc, char* argv[]) { } if (setting_files.empty()) { - pflib_log(fatal) << "We need at least one settings YAML file to compile."; + pflib_log(fatal) << "We need at least one settings YAML file as argument to compile."; return 2; } @@ -114,7 +114,7 @@ int main(int argc, char* argv[]) { std::map> settings; try { // compilation checks parameter/page names - settings = pflib::Compiler::get(roc_type_version) + settings = pflib::Compiler::get(type_version) .compile(setting_files, prepend_defaults); } catch (const pflib::Exception& e) { pflib_log(fatal) << "[" << e.name() << "] " << e.message(); diff --git a/register_maps/econ-to-header.py b/register_maps/econ-to-header.py index 9009971e..38619378 100644 --- a/register_maps/econ-to-header.py +++ b/register_maps/econ-to-header.py @@ -64,23 +64,28 @@ def process_register(name_prefix, props, lines): reg_locs = make_register_locations(address, mask, shift, size_byte) reg_locs_str = ", ".join(reg_locs) - # split into chunks of 16 bytes - chunk_size = 16 + # split into chunks of 8 bytes (the lpGBT can do 16 byte operations, but keeping it to 8 bytes allows us to do keep 64-bit integers as default?) + chunk_size = 8 total_chunks = (len(reg_locs) + chunk_size - 1) // chunk_size - for chunk_idx in range(total_chunks): start = chunk_idx * chunk_size end = start + chunk_size chunk = reg_locs[start:end] - # use upper + + # compute bit offset (each reg_loc corresponds to 1 byte) + bit_offset = chunk_idx * 8 * 8 # 8 bits/byte * 8 bytes = 64 bits per chunk + chunk_bits = len(chunk) * 8 + chunk_mask = (1 << chunk_bits) - 1 + chunk_default = (default_value >> bit_offset) & chunk_mask + chunk_name = ( f"{name_prefix.upper()}" if total_chunks == 1 else f"{name_prefix.upper()}_{chunk_idx}" ) chunk_str = ", ".join(chunk) - lines.append(f' {{"{chunk_name}", Parameter({{{chunk_str}}}, {default_value})}},') - + lines.append(f' {{"{chunk_name}", Parameter({{{chunk_str}}}, {chunk_default})}},') + #print(chunk_str, hex(chunk_default)) else: # look for nested subkeys if props is a dict if isinstance(props, dict): @@ -88,13 +93,13 @@ def process_register(name_prefix, props, lines): new_prefix = f"{name_prefix}_{subkey}" process_register(new_prefix, subval, lines) -def generate_header(input_yaml, data): +def generate_header(input_yaml, data, econ_type): """Generate the C++ header content for a given page.""" lines = [] lines.append(f'/* auto-generated LUT header from {input_yaml} */\n') lines.append("#pragma once\n") lines.append('#include "register_maps/register_maps_types.h"\n') - lines.append("namespace econd {\n") + lines.append(f"namespace econ{econ_type}"+" {\n") # Loop through all blocks (e.g. ALIGNER, CHALIGNER) page_names = [] @@ -115,16 +120,16 @@ def generate_header(input_yaml, data): page_names.append(page_var) lines.append(" });") - #lines.append("\nconst ParameterLUT PARAMETER_LUT = ParameterLUT::Mapping({") - #for name in page_names: - # lines.append(f' {{"{name}", {name}}},') - #lines.append("});") - lines.append("\nconst PageLUT PAGE_LUT = PageLUT::Mapping({") for name in page_names: lines.append(f' {{"{name}", {name}}},') lines.append("});") + lines.append("\nconst ParameterLUT PARAMETER_LUT = ParameterLUT::Mapping({") + for name in page_names: + lines.append(f' {{"{name}", {{0, {name}}}}},') + lines.append("});") + lines.append("\n} // namespace econd\n") return "\n".join(lines) @@ -133,13 +138,14 @@ def compile_registers(yaml_file, output_file): with open(yaml_file, "r") as f: data = yaml.safe_load(f) - content = generate_header(yaml_file, data) + econ_type = "d" if "ECOND" in yaml_file else "t" + content = generate_header(yaml_file, data, econ_type) with open(output_file, "w") as f: f.write(content) if __name__ == "__main__": if len(sys.argv) != 3: - print("Usage: python3 compile_registers.py ") + print("Usage: python3 econ-to-header.py ") sys.exit(1) compile_registers(sys.argv[1], sys.argv[2]) diff --git a/register_maps/write-unifying-header.py b/register_maps/write-unifying-header.py index 8dab0ac9..2417efbd 100644 --- a/register_maps/write-unifying-header.py +++ b/register_maps/write-unifying-header.py @@ -5,8 +5,13 @@ parser = argparse.ArgumentParser() parser.add_argument( - 'types', - help='list of types that were generated headers', + '--roc_types', + help='list of ROC types that were generated headers', + nargs='+' +) +parser.add_argument( + '--econ_types', + help='list of ECON types that were generated headers', nargs='+' ) parser.add_argument( @@ -20,13 +25,24 @@ f.write('/* auto generated from scratch */\n\n') f.write('#pragma once\n\n') f.write('// include the register maps for each ROC type/version\n') - for rt in args.types: + for rt in args.roc_types: + f.write('#include "register_maps/{rt}.h"\n'.format(rt=rt)) + for rt in args.econ_types: f.write('#include "register_maps/{rt}.h"\n'.format(rt=rt)) f.write('\n// name the register maps so they can be retrieved by name\n') f.write('const std::map>\n') - f.write('REGISTER_MAP_BY_TYPE = {\n') + f.write('REGISTER_MAP_BY_ROC_TYPE = {\n') + f.write(',\n'.join( + ' {"%s", {%s::PAGE_LUT, %s::PARAMETER_LUT}}'%(rt,rt,rt) + for rt in args.roc_types + )) + f.write('\n};\n') + # f.write('const std::map\n') + f.write('const std::map>\n') + f.write('REGISTER_MAP_BY_ECON_TYPE = {\n') f.write(',\n'.join( + #' {"%s", {%s::PAGE_LUT}}'%(rt,rt) ' {"%s", {%s::PAGE_LUT, %s::PARAMETER_LUT}}'%(rt,rt,rt) - for rt in args.types + for rt in args.econ_types )) f.write('\n};\n\n') diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index 6bdcbcbd..6d4c17be 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -21,12 +21,21 @@ std::string upper_cp(const std::string& str) { #include "register_maps/register_maps.h" Compiler Compiler::get(const std::string& type_version) { - auto reg_map_it = REGISTER_MAP_BY_TYPE.find(type_version); - if (reg_map_it == REGISTER_MAP_BY_TYPE.end()) { - PFEXCEPTION_RAISE("BadType", "Type_version " + type_version + - " is not present within the map."); + // Try ROC type map first + auto roc_it = REGISTER_MAP_BY_ROC_TYPE.find(type_version); + if (roc_it != REGISTER_MAP_BY_ROC_TYPE.end()) { + return Compiler(roc_it->second.second, roc_it->second.first); } - return Compiler(reg_map_it->second.second, reg_map_it->second.first); + + // Try ECON type map next + auto econ_it = REGISTER_MAP_BY_ECON_TYPE.find(type_version); + if (econ_it != REGISTER_MAP_BY_ECON_TYPE.end()) { + return Compiler(econ_it->second.second, econ_it->second.first); + + } + + PFEXCEPTION_RAISE("BadType", "Type_version " + type_version + + " is not present within ROC or ECON register maps."); } Compiler::Compiler(const ParameterLUT& parameter_lut, const PageLUT& page_lut) @@ -321,7 +330,26 @@ void Compiler::extract( for (const auto& page : matching_pages) { for (const auto& param : page_settings) { - std::string sval = param.second.as(); + std::string sval; + if (param.second.IsScalar()) { + try { + // try to parse as string first + sval = param.second.as(); + } catch (const YAML::TypedBadConversion&) { + try { + // fallback: parse as int and convert to string + int ival = param.second.as(); + sval = std::to_string(ival); + } catch (const YAML::TypedBadConversion&) { + PFEXCEPTION_RAISE("BadFormat", "Value for parameter " + + param.first.as() + " is neither string nor int."); + } + } + } else { + PFEXCEPTION_RAISE("BadFormat", "Non-scalar value for parameter " + + param.first.as()); + } + if (sval.empty()) { PFEXCEPTION_RAISE("BadFormat", "Non-existent value for parameter " + param.first.as()); From 7d6d305a66c6d29240e63adac472760ab1396ed2 Mon Sep 17 00:00:00 2001 From: cmantill Date: Wed, 8 Oct 2025 18:29:49 +0000 Subject: [PATCH 29/36] checkpoint w compiler --- CMakeLists.txt | 3 +- app/tool/econ.cxx | 22 +++++++++----- include/pflib/ECON.h | 6 +++- src/pflib/Compile.cxx | 16 +++++++++- src/pflib/ECON.cxx | 70 +++++++++++++++++++++++++++++-------------- src/pflib/Hcal.cxx | 19 +++--------- 6 files changed, 89 insertions(+), 47 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index bf0a60b1..d3bbc885 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -105,7 +105,8 @@ add_custom_command( COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps COMMAND python3 ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py - ${PROJECT_SOURCE_DIR}/register_maps/ECOND_I2C_params_regmap.yaml + #${PROJECT_SOURCE_DIR}/register_maps/ECOND_I2C_params_regmap.yaml + ${PROJECT_SOURCE_DIR}/register_maps/ECOND_test.yaml ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps/econd.h DEPENDS ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py diff --git a/app/tool/econ.cxx b/app/tool/econ.cxx index f958da47..65d7ad42 100644 --- a/app/tool/econ.cxx +++ b/app/tool/econ.cxx @@ -53,13 +53,7 @@ static void econ_expert(const std::string& cmd, Target* tgt) { int nbytes = pftool::readline_int("Number of bytes to write: ", 1); uint64_t value = pftool::readline_int("Value to write (hex): ", 0x0); - // split value into bytes - std::vector data; - for (int i = 0; i < nbytes; ++i) { - data.push_back(static_cast((value >> (8 * i)) & 0xFF)); - } - - econ.setValues(address, data); + econ.setValue(address, value, nbytes); printf("Wrote 0x%llx to register 0x%04x (%d bytes)\n", value, address, nbytes); } } @@ -75,6 +69,7 @@ static void econ_expert(const std::string& cmd, Target* tgt) { * - SOFTRESET : pflib::Hcal::softResetECONs * - RUNMODE : enable run bit on the ECON * - IECON : Change which ECON to focus on + * - LOAD : Load parameters from a YAML file * * @param[in] cmd ECON command * @param[in] pft active target @@ -98,6 +93,18 @@ static void econ(const std::string& cmd, Target* pft) { isRunMode = pftool::readline_bool("Set ECON runbit: ", isRunMode); econ.setRunMode(isRunMode); } + if (cmd == "LOAD") { + std::cout << "\n" + " --- This command expects a YAML file with page names, " + "parameter names and their values.\n" + << std::flush; + std::string fname = pftool::readline("Filename: "); + bool prepend_defaults = pftool::readline_bool( + "Update all parameter values on the chip using the defaults in the " + "manual for any values not provided? ", + false); + econ.loadParameters(fname, prepend_defaults); + } } @@ -109,6 +116,7 @@ auto menu_econ = ->line("IECON", "Change the active ECON number", econ) ->line("RUNMODE", "set/clear the run mode", econ) ->line("POKE", "change a single parameter value", econ) + ->line("LOAD", "load all parameters", econ) ; auto menu_econ_expert = diff --git a/include/pflib/ECON.h b/include/pflib/ECON.h index 2c4d3a96..62787701 100644 --- a/include/pflib/ECON.h +++ b/include/pflib/ECON.h @@ -24,12 +24,16 @@ class ECON { bool isRunMode(); std::vector getValues(int reg_addr, int nbytes); + void setValue(int reg_addr, uint64_t value, int nbytes); void setValues(int reg_addr, const std::vector& values); + void setRegisters(const std::map>& registers); + void loadParameters(const std::string& file_path, bool prepend_defaults); + private: I2C& i2c_; uint8_t econ_base_; - //Compiler compiler_; + Compiler compiler_; mutable ::pflib::logging::logger the_log_{::pflib::logging::get("econ")}; }; diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index 6d4c17be..f23133a8 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -60,7 +60,8 @@ void Compiler::compile(const std::string& page_name, std::map>& register_values) { const auto& page_id{parameter_lut_.at(page_name).first}; const Parameter& spec{parameter_lut_.at(page_name).second.at(param_name)}; - uint32_t uval{static_cast(val)}; + uint64_t uval{static_cast(val)}; + //uint32_t uval{static_cast(val)}; std::size_t total_nbits = std::accumulate(spec.registers.begin(), spec.registers.end(), 0, @@ -68,6 +69,9 @@ void Compiler::compile(const std::string& page_name, return bit_count + rhs.n_bits; }); std::size_t val_msb = msb(uval); + printf("Setting parameter %s.%s = %u (MSB=%zu, total bits=%zu)\n", + page_name.c_str(), param_name.c_str(), uval, val_msb, total_nbits); + if (val_msb >= total_nbits) { std::stringstream msg; msg << "Parameter " << page_name << '.' << param_name @@ -77,10 +81,14 @@ void Compiler::compile(const std::string& page_name, } std::size_t value_curr_min_bit{0}; + printf("%s.%s -> page %u\n", page_name.c_str(), param_name.c_str(), page_id); pflib_log(trace) << page_name << "." << param_name << " -> page " << page_id; for (const RegisterLocation& location : spec.registers) { // grab sub value of parameter in this register uint8_t sub_val = ((uval >> value_curr_min_bit) & location.mask); + printf(" Sub-value: %u (uval %u) (mask=0x%02X, shift=%zu) -> register 0x%04X\n", + sub_val, uval, location.mask, location.min_bit, location.reg); + pflib_log(trace) << " " << sub_val << " at " << location.reg << ", " << location.n_bits << " bits"; value_curr_min_bit += location.n_bits; @@ -88,14 +96,20 @@ void Compiler::compile(const std::string& page_name, register_values[page_id].end()) { // initialize register value to zero if it hasn't been touched before register_values[page_id][location.reg] = 0; + printf(" Initialized register 0x%04X to 0\n", location.reg); } else { // make sure to clear old value register_values[page_id][location.reg] &= ((location.mask << location.min_bit) ^ 0b11111111); + printf(" Cleared old bits in register 0x%04X\n", location.reg); } // put value into register at the specified location register_values[page_id][location.reg] += (sub_val << location.min_bit); + + printf(" Updated register 0x%04X = 0x%02X\n", location.reg, + register_values[page_id][location.reg]); } // loop over register locations + printf("Finished setting %s.%s\n", page_name.c_str(), param_name.c_str()); return; } diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx index 0dfc17b4..64d05a9a 100644 --- a/src/pflib/ECON.cxx +++ b/src/pflib/ECON.cxx @@ -12,8 +12,8 @@ namespace pflib { ECON::ECON(I2C& i2c, uint8_t econ_base_addr, const std::string& type_version) : i2c_{i2c}, - econ_base_{econ_base_addr} - //compiler_{Compiler::get(type_version)} + econ_base_{econ_base_addr}, + compiler_{Compiler::get(type_version)} { pflib_log(debug) << "ECON base addr " << packing::hex(econ_base_); } @@ -46,8 +46,8 @@ std::vector newParam(std::vector prev_value, uint16_t reg_addr new_data.push_back(static_cast((reg_val >> (8 * i)) & 0xFF)); } - //printf("To update register 0x%04x: bits [%d:%d] set to 0x%x\n", - // reg_addr, shift + static_cast(log2(mask)), shift, value); + printf("To update register 0x%04x: bits [%d:%d] set to 0x%x\n", + reg_addr, shift + static_cast(log2(mask)), shift, reg_val); return new_data; } @@ -58,29 +58,19 @@ void ECON::setRunMode(bool active) { const int SHIFT_RUNBIT = 23; std::vector data_03C5 = getValues(0x03C5, 3); std::vector new_data_03C5 = newParam(data_03C5, 0x03C5, nbytes, MASK_RUNBIT, SHIFT_RUNBIT, 1); - auto value = getParam(new_data_03C5, SHIFT_RUNBIT, MASK_RUNBIT); - std::cout << "new 03C5 value to write: " << value << std::endl; - - std::vector data; - for (int i = 0; i < nbytes; ++i) { - data.push_back(static_cast((value >> (8 * i)) & 0xFF)); - } - - setValues(0x03C5, data); - printf("Wrote 0x%llx to register 0x%04x (%d bytes)\n", value, 0x03C5, nbytes); + setValues(0x03C5, new_data_03C5); std::vector data_03DF = getValues(0x3df, 4); const uint32_t MASK_PUSMSTATE = 15; const int SHIFT_PUSMSTATE = 0; uint32_t pusm_state_value = getParam(data_03DF, SHIFT_PUSMSTATE, MASK_PUSMSTATE); std::cout << "new PUSM state value: " << pusm_state_value << std::endl; -} - -bool ECON::isRunMode() { std::vector data_03AB = getValues(0x03AB, 1); std::cout << "FCtrl_Global_command_rx_inverted " << getParam(data_03AB, 0, 1) << " locked " << getParam(data_03AB, 1, 1) << std::endl; +} +bool ECON::isRunMode() { // Read 3-byte register at 0x03C5 and extract run bit std::vector data_03C5 = getValues(0x03C5, 3); const uint32_t MASK_RUNBIT = 1; @@ -94,7 +84,6 @@ bool ECON::isRunMode() { const int SHIFT_PUSMSTATE = 0; uint32_t pusm_state_value = getParam(data_03DF, SHIFT_PUSMSTATE, MASK_PUSMSTATE); std::cout << "PUSM state value: " << pusm_state_value << std::endl; - return pusm_run_value == 1 && pusm_state_value == 8; } @@ -118,6 +107,21 @@ std::vector ECON::getValues(int reg_addr, int nbytes) { return data; } +void ECON::setValue(int reg_addr, uint64_t value, int nbytes) { + if (nbytes <= 0 || nbytes > 8) { + pflib_log(error) << "ECON::setValue called with invalid nbytes = " << nbytes; + return; + } + + // split the value into bytes (little endian) + std::vector data; + for (int i = 0; i < nbytes; ++i) { + data.push_back(static_cast((value >> (8 * i)) & 0xFF)); + } + + setValues(reg_addr, data); +} + void ECON::setValues(int reg_addr, const std::vector& values) { if (values.empty()) { pflib_log(error) << "ECON::setValues called with empty data vector"; @@ -138,10 +142,32 @@ void ECON::setValues(int reg_addr, const std::vector& values) { // perform write i2c_.general_write_read(econ_base_, wbuf, values.size()); - // Log written data - printf("Wrote %zu bytes to register 0x%04x:\n", values.size(), reg_addr); - for (size_t i = 0; i < values.size(); ++i) { - printf(" %02zu : %02x\n", i, values[i]); + // printf("Wrote %zu bytes to register 0x%04x:\n", values.size(), reg_addr); + // for (size_t i = 0; i < values.size(); ++i) { + // printf(" %02zu : %02x\n", i, values[i]); + // } +} + +void ECON::setRegisters(const std::map>& registers) { + for (auto& page : registers) { + int page_id = page.first; + for (auto& reg : page.second) { + printf("Page %d: setValue(0x%04x, 0x%02x)\n", page_id, reg.first, reg.second); + //this->setValue(reg.first, reg.second); + } + } +} + +void ECON::loadParameters(const std::string& file_path, bool prepend_defaults) { + if (prepend_defaults) { + /** + * If we prepend defaults, then ALL of the parameters will be + * touched and so we do need to bother reading the current + * values and overlaying the new ones, instead we jump straight + * to setting the registers. + */ + auto settings = compiler_.compile(file_path, true); + setRegisters(settings); } } diff --git a/src/pflib/Hcal.cxx b/src/pflib/Hcal.cxx index 1072694f..d99f6e51 100644 --- a/src/pflib/Hcal.cxx +++ b/src/pflib/Hcal.cxx @@ -28,11 +28,11 @@ ECON Hcal::econ(int which, const std::string& type_econ) { } if (type_econ == "econd") { - std::cout << "econd " << (0x60 | (which * 8)) << std::endl; - return ECON(*i2c_for_econd_[which], 0x60 | (which * 8), type_econ); + // std::cout << "econd " << (0x60 | (which)) << std::endl; + return ECON(*i2c_for_econd_[which], 0x60 | which, type_econ); } else if (type_econ == "econt") { - std::cout << "econt " << (0x20 | (which * 8)) << std::endl; - return ECON(*i2c_for_econt_[which], 0x20 | (which * 8), type_econ); + // std::cout << "econt " << (0x20 | (which)) << std::endl; + return ECON(*i2c_for_econt_[which], 0x20 | which, type_econ); } else { throw std::runtime_error("Unknown ECON type in econ(): " + type_econ); } @@ -53,17 +53,6 @@ void Hcal::add_econ(int iecon, std::shared_ptr econ_i2c, const std::string& } else { throw std::runtime_error("Unknown ECON type in add_econ: " + type_econ); } - - std::cout << "=== i2c_for_econd_ map ===" << std::endl; - for (const auto& [key, value] : i2c_for_econd_) { - std::cout << key << " : 0x" << std::hex << value << std::dec << std::endl; - } - std::cout << "===========================" << std::endl; - std::cout << "=== i2c_for_econt_ map ===" << std::endl; - for (const auto& [key, value] : i2c_for_econt_) { - std::cout << key << " : 0x" << std::hex << value << std::dec << std::endl; - } - std::cout << "===========================" << std::endl; } ROC Hcal::roc(int which, const std::string& roc_type_version) { From 4e53f030985391970850190ec62e205897bba73b Mon Sep 17 00:00:00 2001 From: cmantill Date: Wed, 8 Oct 2025 19:45:28 +0000 Subject: [PATCH 30/36] checkpoint w compiler --- include/pflib/Compile.h | 8 +++++- register_maps/econ-to-header.py | 9 ++++++- register_maps/register_maps_types.h | 10 +++---- src/pflib/Compile.cxx | 9 ++++++- src/pflib/ECON.cxx | 42 ++++++++++++++++++++++++++--- test/compile.cxx | 20 ++++++++++++++ 6 files changed, 86 insertions(+), 12 deletions(-) diff --git a/include/pflib/Compile.h b/include/pflib/Compile.h index 57b50d16..f20be55f 100644 --- a/include/pflib/Compile.h +++ b/include/pflib/Compile.h @@ -79,9 +79,14 @@ class Compiler { * values to apply parameter to */ void compile(const std::string& page, const std::string& param, - const int& val, + const uint64_t val, std::map>& registers); + //void compile(const std::string& page_name, + //const std::string& param_name, + // const int& val, + //std::map>& register_values); + /** * Compile a single parameter into the (potentially several) * registers that it should set. Any other bits in the register(s) @@ -95,6 +100,7 @@ class Compiler { std::map> compile(const std::string& page_name, const std::string& param_name, const int& val); + //const uint64_t val); /** * Compiling which translates parameter values for the HGCROC diff --git a/register_maps/econ-to-header.py b/register_maps/econ-to-header.py index 38619378..ef75c70c 100644 --- a/register_maps/econ-to-header.py +++ b/register_maps/econ-to-header.py @@ -12,6 +12,13 @@ def safe_int(val): return int(val, 16) if val.startswith("0x") else int(val) return int(val) +def format_cpp_int(value: int) -> str: + """Append 'ULL' if value is larger than 32-bit signed int""" + if value < 0 or value > 0x7FFFFFFF: + return f'{value}ULL' + else: + return str(value) + def make_register_locations(address, mask, shift, size_byte): """Split a register into 8-bit chunks if it spans multiple bytes. syntax reminder: @@ -84,7 +91,7 @@ def process_register(name_prefix, props, lines): else f"{name_prefix.upper()}_{chunk_idx}" ) chunk_str = ", ".join(chunk) - lines.append(f' {{"{chunk_name}", Parameter({{{chunk_str}}}, {chunk_default})}},') + lines.append(f' {{"{chunk_name}", Parameter({{{chunk_str}}}, {format_cpp_int(chunk_default)})}},') #print(chunk_str, hex(chunk_default)) else: # look for nested subkeys if props is a dict diff --git a/register_maps/register_maps_types.h b/register_maps/register_maps_types.h index 83d89f2c..6de59cf7 100644 --- a/register_maps/register_maps_types.h +++ b/register_maps/register_maps_types.h @@ -43,15 +43,15 @@ struct RegisterLocation { */ struct Parameter { /// the default parameter value - const int def; + const uint64_t def; /// the locations that the parameter is split over const std::vector registers; /// pass locations and default value of parameter - Parameter(std::initializer_list r, int def) - : def{def}, registers{r} {} + Parameter(std::initializer_list r, uint64_t def) + : def{def}, registers{r} {} /// short constructor for single-location parameters - Parameter(int r, int m, int n, int def) - : Parameter({RegisterLocation(r, m, n)}, def) {} + Parameter(int r, int m, int n, uint64_t def) + : Parameter({RegisterLocation(r, m, n)}, def) {} }; /** diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index f23133a8..6d9e3b25 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -56,8 +56,15 @@ std::size_t msb(uint32_t v) { } void Compiler::compile(const std::string& page_name, - const std::string& param_name, const int& val, + const std::string& param_name, const uint64_t val, std::map>& register_values) { + for (const auto& p : parameter_lut_) { + std::cout << "Page: " << p.first << "\n"; + for (const auto& param : p.second.second) { + std::cout << " Param: " << param.first << "\n"; + } + } + const auto& page_id{parameter_lut_.at(page_name).first}; const Parameter& spec{parameter_lut_.at(page_name).second.at(param_name)}; uint64_t uval{static_cast(val)}; diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx index 64d05a9a..6246472d 100644 --- a/src/pflib/ECON.cxx +++ b/src/pflib/ECON.cxx @@ -149,12 +149,46 @@ void ECON::setValues(int reg_addr, const std::vector& values) { } void ECON::setRegisters(const std::map>& registers) { - for (auto& page : registers) { - int page_id = page.first; - for (auto& reg : page.second) { + for (auto& page_pair : registers) { + int page_id = page_pair.first; + const auto& reg_map = page_pair.second; + + for (auto& reg : page_pair.second) { printf("Page %d: setValue(0x%04x, 0x%02x)\n", page_id, reg.first, reg.second); - //this->setValue(reg.first, reg.second); } + + for (const auto& reg_pair : reg_map) { + bool adjacent = false; + std::vector adjacent_vals; + int start_addr{}; + int last_addr{}; // initialize so first register triggers new sequence + for (const auto& reg_pair : reg_map) { + int addr = reg_pair.first; + uint8_t value = reg_pair.second; + if (last_addr+1 == reg_pair.first) { + adjacent_vals.push_back(reg_pair.second); + last_addr++; + } else { + // aren't adjacent anymore, write and start a new one + if (!adjacent_vals.empty()) { + printf("Page %d, start_addr %d, values: ", page_id, start_addr); + for (auto v : adjacent_vals) { + printf("0x%02X ", v); + } + printf("\n"); + + // TODO: call hardware write function here + // this->writeRegisters(page_id, start_addr, adjacent_vals); + } + } + + adjacent_vals.clear(); + adjacent_vals.push_back(value); + start_addr = addr; + } + //this->setValue(page.first, reg.first, reg.second); + } + } } diff --git a/test/compile.cxx b/test/compile.cxx index 76eeea32..db608ff9 100644 --- a/test/compile.cxx +++ b/test/compile.cxx @@ -75,6 +75,25 @@ BOOST_AUTO_TEST_CASE(big_32bit_params) { BOOST_CHECK(registers == expected); } +BOOST_AUTO_TEST_CASE(single_register_econd) { + pflib::Compiler c = pflib::Compiler::get("econd"); + std::map> registers, expected; + expected[0][0x0389] = 0xff; + expected[0][0x038a] = 0xff; + expected[0][0x038b] = 0xff; + expected[0][0x038c] = 0xff; + expected[0][0x038d] = 0; + expected[0][0x038e] = 0; + expected[0][0x038f] = 0; + expected[0][0x0390] = 0; + + uint64_t mask_val = 0xFFFFFFFF00000000ULL; + + // Call compile() with uint64_t value + c.compile("ALIGNER", "GLOBAL_MATCH_MASK_VAL", mask_val, registers); + BOOST_CHECK(registers == expected); +} + BOOST_AUTO_TEST_CASE(glob_pages) { pflib::Compiler c = pflib::Compiler::get("sipm_rocv3"); std::string test_filepath{"settings.yaml"}; @@ -124,4 +143,5 @@ BOOST_AUTO_TEST_CASE(overwrite_with_later_settings) { "overwrite parameter with subsequent settings file"); } + BOOST_AUTO_TEST_SUITE_END() From 68fae1d5db2f295fda61e1316083ffa77cf572f2 Mon Sep 17 00:00:00 2001 From: cmantill Date: Wed, 8 Oct 2025 21:57:04 +0000 Subject: [PATCH 31/36] yaml for testing --- register_maps/ECOND_test.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 register_maps/ECOND_test.yaml diff --git a/register_maps/ECOND_test.yaml b/register_maps/ECOND_test.yaml new file mode 100644 index 00000000..968ee877 --- /dev/null +++ b/register_maps/ECOND_test.yaml @@ -0,0 +1,10 @@ +Aligner: + Global: + match_mask_val: + access: rw + address: 0x0389 + default_value: 18446744069414584320 + max_value: 18446744073709551615 + param_mask: 0xffffffffffffffff + param_shift: 0 + size_byte: 8 \ No newline at end of file From 5ccebd00a53b3cee11fddabb763c4c3ed1531e7d Mon Sep 17 00:00:00 2001 From: cmantill Date: Wed, 8 Oct 2025 21:57:22 +0000 Subject: [PATCH 32/36] debug --- src/pflib/Compile.cxx | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index 6d9e3b25..83eb83ef 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -8,6 +8,8 @@ #include #include +#include + #include "pflib/Exception.h" namespace pflib { @@ -58,6 +60,14 @@ std::size_t msb(uint32_t v) { void Compiler::compile(const std::string& page_name, const std::string& param_name, const uint64_t val, std::map>& register_values) { + std::cout << "[uint64_t overload] value = " << val + << " sizeof=" << sizeof(val) << std::endl; + + std::cout << "Setting parameter " << page_name << "." << param_name + << " = " << val + << " (MSB=" << (64 - __builtin_clzll(val)) << ", total bits=64)\n"; + std::cout << "sizeof(val) = " << sizeof(val) << std::endl; + for (const auto& p : parameter_lut_) { std::cout << "Page: " << p.first << "\n"; for (const auto& param : p.second.second) { @@ -76,8 +86,8 @@ void Compiler::compile(const std::string& page_name, return bit_count + rhs.n_bits; }); std::size_t val_msb = msb(uval); - printf("Setting parameter %s.%s = %u (MSB=%zu, total bits=%zu)\n", - page_name.c_str(), param_name.c_str(), uval, val_msb, total_nbits); + printf("Setting parameter %s.%s = %" PRIu64 " (MSB=%zu, total bits=%zu)\n", + page_name.c_str(), param_name.c_str(), uval, val_msb, total_nbits); if (val_msb >= total_nbits) { std::stringstream msg; @@ -93,6 +103,8 @@ void Compiler::compile(const std::string& page_name, for (const RegisterLocation& location : spec.registers) { // grab sub value of parameter in this register uint8_t sub_val = ((uval >> value_curr_min_bit) & location.mask); + uint64_t sub_val64 = ((uval >> value_curr_min_bit) & location.mask); + printf(" Sub-value debug: %" PRIu64 " -> 0x%02" PRIX64 "\n", sub_val64, sub_val64); printf(" Sub-value: %u (uval %u) (mask=0x%02X, shift=%zu) -> register 0x%04X\n", sub_val, uval, location.mask, location.min_bit, location.reg); From 9b694e752a9f1eb7bdda8c54a9e4e0f363c61299 Mon Sep 17 00:00:00 2001 From: cmantill Date: Thu, 9 Oct 2025 17:12:44 +0000 Subject: [PATCH 33/36] test extract functions --- config/econd_test.yaml | 13 +++++ config/econd_test_param.yaml | 2 + include/pflib/Compile.h | 12 ++--- src/pflib/Compile.cxx | 64 ++++++++++++------------ src/pflib/ECON.cxx | 85 +++++++++++++++---------------- test/compile.cxx | 97 +++++++++++++++++++++++++++++++++--- 6 files changed, 184 insertions(+), 89 deletions(-) create mode 100644 config/econd_test.yaml create mode 100644 config/econd_test_param.yaml diff --git a/config/econd_test.yaml b/config/econd_test.yaml new file mode 100644 index 00000000..9a563676 --- /dev/null +++ b/config/econd_test.yaml @@ -0,0 +1,13 @@ +FormatterBuffer: + Global_active_etxs: 0 + Global_link_reset_pattern: 0 +Aligner: + Global_i2c_snapshot_en: 0 +ClocksAndResets: + Global_pusm_state: 0 + Global_pusm_run: 0 +FCtrl: + Global_locked: 0 + Global_lock_count: 0 + Global_command_rx_inverted: 0 + Global_invert_command_rx: 0 \ No newline at end of file diff --git a/config/econd_test_param.yaml b/config/econd_test_param.yaml new file mode 100644 index 00000000..a1e9c4ea --- /dev/null +++ b/config/econd_test_param.yaml @@ -0,0 +1,2 @@ +Aligner: + Global_match_mask_val: 18446744069414584320 \ No newline at end of file diff --git a/include/pflib/Compile.h b/include/pflib/Compile.h index f20be55f..8b28f850 100644 --- a/include/pflib/Compile.h +++ b/include/pflib/Compile.h @@ -82,11 +82,6 @@ class Compiler { const uint64_t val, std::map>& registers); - //void compile(const std::string& page_name, - //const std::string& param_name, - // const int& val, - //std::map>& register_values); - /** * Compile a single parameter into the (potentially several) * registers that it should set. Any other bits in the register(s) @@ -100,7 +95,6 @@ class Compiler { std::map> compile(const std::string& page_name, const std::string& param_name, const int& val); - //const uint64_t val); /** * Compiling which translates parameter values for the HGCROC @@ -223,8 +217,9 @@ class Compiler { * @param[in,out] settings page name, parameter name, parameter value settings * extracted from YAML file(s) */ + template void extract(const std::vector& setting_files, - std::map>& settings); + std::map>& settings); /** * compile a series of yaml files @@ -271,8 +266,9 @@ class Compiler { * @param[in] params a YAML::Node to start extraction from * @param[in,out] settings map of names to values for extract parameters */ + template void extract(YAML::Node params, - std::map>& settings); + std::map>& settings); private: const ParameterLUT& parameter_lut_; diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index 83eb83ef..5125af53 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -60,25 +60,25 @@ std::size_t msb(uint32_t v) { void Compiler::compile(const std::string& page_name, const std::string& param_name, const uint64_t val, std::map>& register_values) { - std::cout << "[uint64_t overload] value = " << val - << " sizeof=" << sizeof(val) << std::endl; + //std::cout << "[uint64_t overload] value = " << val + //<< " sizeof=" << sizeof(val) << std::endl; - std::cout << "Setting parameter " << page_name << "." << param_name - << " = " << val - << " (MSB=" << (64 - __builtin_clzll(val)) << ", total bits=64)\n"; - std::cout << "sizeof(val) = " << sizeof(val) << std::endl; - - for (const auto& p : parameter_lut_) { - std::cout << "Page: " << p.first << "\n"; - for (const auto& param : p.second.second) { - std::cout << " Param: " << param.first << "\n"; - } - } + //std::cout << "Setting parameter " << page_name << "." << param_name + // << " = " << val + // << " (MSB=" << (64 - __builtin_clzll(val)) << ", total bits=64)\n"; + //std::cout << "sizeof(val) = " << sizeof(val) << std::endl; + + // To print out the full map of that chip + //for (const auto& p : parameter_lut_) { + // std::cout << "Page: " << p.first << "\n"; + // for (const auto& param : p.second.second) { + // std::cout << " Param: " << param.first << "\n"; + // } + //} const auto& page_id{parameter_lut_.at(page_name).first}; const Parameter& spec{parameter_lut_.at(page_name).second.at(param_name)}; uint64_t uval{static_cast(val)}; - //uint32_t uval{static_cast(val)}; std::size_t total_nbits = std::accumulate(spec.registers.begin(), spec.registers.end(), 0, @@ -86,8 +86,8 @@ void Compiler::compile(const std::string& page_name, return bit_count + rhs.n_bits; }); std::size_t val_msb = msb(uval); - printf("Setting parameter %s.%s = %" PRIu64 " (MSB=%zu, total bits=%zu)\n", - page_name.c_str(), param_name.c_str(), uval, val_msb, total_nbits); + //printf("Setting parameter %s.%s = %" PRIu64 " (MSB=%zu, total bits=%zu)\n", + // page_name.c_str(), param_name.c_str(), uval, val_msb, total_nbits); if (val_msb >= total_nbits) { std::stringstream msg; @@ -98,15 +98,15 @@ void Compiler::compile(const std::string& page_name, } std::size_t value_curr_min_bit{0}; - printf("%s.%s -> page %u\n", page_name.c_str(), param_name.c_str(), page_id); + //printf("%s.%s -> page %u\n", page_name.c_str(), param_name.c_str(), page_id); pflib_log(trace) << page_name << "." << param_name << " -> page " << page_id; for (const RegisterLocation& location : spec.registers) { // grab sub value of parameter in this register uint8_t sub_val = ((uval >> value_curr_min_bit) & location.mask); - uint64_t sub_val64 = ((uval >> value_curr_min_bit) & location.mask); - printf(" Sub-value debug: %" PRIu64 " -> 0x%02" PRIX64 "\n", sub_val64, sub_val64); - printf(" Sub-value: %u (uval %u) (mask=0x%02X, shift=%zu) -> register 0x%04X\n", - sub_val, uval, location.mask, location.min_bit, location.reg); + //uint64_t sub_val64 = ((uval >> value_curr_min_bit) & location.mask); + //printf(" Sub-value debug: %" PRIu64 " -> 0x%02" PRIX64 "\n", sub_val64, sub_val64); + //printf(" Sub-value: %u (uval %u) (mask=0x%02X, shift=%zu) -> register 0x%04X\n", + //sub_val, uval, location.mask, location.min_bit, location.reg); pflib_log(trace) << " " << sub_val << " at " << location.reg << ", " << location.n_bits << " bits"; @@ -115,20 +115,20 @@ void Compiler::compile(const std::string& page_name, register_values[page_id].end()) { // initialize register value to zero if it hasn't been touched before register_values[page_id][location.reg] = 0; - printf(" Initialized register 0x%04X to 0\n", location.reg); + //printf(" Initialized register 0x%04X to 0\n", location.reg); } else { // make sure to clear old value register_values[page_id][location.reg] &= ((location.mask << location.min_bit) ^ 0b11111111); - printf(" Cleared old bits in register 0x%04X\n", location.reg); + //printf(" Cleared old bits in register 0x%04X\n", location.reg); } // put value into register at the specified location register_values[page_id][location.reg] += (sub_val << location.min_bit); - printf(" Updated register 0x%04X = 0x%02X\n", location.reg, - register_values[page_id][location.reg]); + //printf(" Updated register 0x%04X = 0x%02X\n", location.reg, + //register_values[page_id][location.reg]); } // loop over register locations - printf("Finished setting %s.%s\n", page_name.c_str(), param_name.c_str()); + //printf("Finished setting %s.%s\n", page_name.c_str(), param_name.c_str()); return; } @@ -272,9 +272,9 @@ std::map> Compiler::defaults() { return settings; } -void Compiler::extract( - const std::vector& setting_files, - std::map>& settings) { +template +void Compiler::extract(const std::vector& setting_files, + std::map>& settings) { for (auto& setting_file : setting_files) { YAML::Node setting_yaml; try { @@ -308,9 +308,10 @@ std::map> Compiler::compile( return compile(std::vector{setting_file}, prepend_defaults); } +template void Compiler::extract( YAML::Node params, - std::map>& settings) { + std::map>& settings) { // deduce list of page names for search // only do this once per program run static std::vector page_names; @@ -388,7 +389,8 @@ void Compiler::extract( param.first.as()); } std::string param_name = upper_cp(param.first.as()); - settings[page][param_name] = utility::str_to_int(sval); + settings[page][param_name] = std::stoull(sval, nullptr, 0); // base 0 allows hex + //settings[page][param_name] = utility::str_to_int(sval); } } } diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx index 6246472d..c1fe2989 100644 --- a/src/pflib/ECON.cxx +++ b/src/pflib/ECON.cxx @@ -100,10 +100,6 @@ std::vector ECON::getValues(int reg_addr, int nbytes) { waddr.push_back(static_cast(reg_addr & 0xFF)); std::vector data = i2c_.general_write_read(econ_base_, waddr, nbytes); - //for (size_t i = 0; i < data.size(); i++) { - // printf("%02zu : %02x\n", i, data[i]); - //} - return data; } @@ -149,46 +145,51 @@ void ECON::setValues(int reg_addr, const std::vector& values) { } void ECON::setRegisters(const std::map>& registers) { - for (auto& page_pair : registers) { - int page_id = page_pair.first; - const auto& reg_map = page_pair.second; + // registers[0] holds the actual register map + const auto& reg_map = registers.at(0); - for (auto& reg : page_pair.second) { - printf("Page %d: setValue(0x%04x, 0x%02x)\n", page_id, reg.first, reg.second); - } - - for (const auto& reg_pair : reg_map) { - bool adjacent = false; - std::vector adjacent_vals; - int start_addr{}; - int last_addr{}; // initialize so first register triggers new sequence - for (const auto& reg_pair : reg_map) { - int addr = reg_pair.first; - uint8_t value = reg_pair.second; - if (last_addr+1 == reg_pair.first) { - adjacent_vals.push_back(reg_pair.second); - last_addr++; - } else { - // aren't adjacent anymore, write and start a new one - if (!adjacent_vals.empty()) { - printf("Page %d, start_addr %d, values: ", page_id, start_addr); - for (auto v : adjacent_vals) { - printf("0x%02X ", v); - } - printf("\n"); - - // TODO: call hardware write function here - // this->writeRegisters(page_id, start_addr, adjacent_vals); - } - } - - adjacent_vals.clear(); - adjacent_vals.push_back(value); - start_addr = addr; - } - //this->setValue(page.first, reg.first, reg.second); + // print every register addr and value pair + for (const auto& [reg_addr, value] : reg_map) { + printf("setValue(0x%04x, 0x%02x)\n", reg_addr, value); + } + + // combine adjacent registers into one write + std::vector adjacent_vals; + int start_addr = -1; + int last_addr = -1; + + for (const auto& [addr, value] : reg_map) { + if (start_addr == -1) { + // first register + start_addr = addr; + last_addr = addr; + adjacent_vals.push_back(value); + } else if (addr == last_addr + 1) { + // contiguous, keep adding + adjacent_vals.push_back(value); + last_addr = addr; + } else { + // non-contiguous → write previous block + printf("start_addr 0x%04x, values:", start_addr); + for (auto v : adjacent_vals) printf(" 0x%02X", v); + printf("\n"); + + //this->setValues(start_addr, adjacent_vals); + + // reset for new block + adjacent_vals.clear(); + adjacent_vals.push_back(value); + start_addr = addr; + last_addr = addr; } - + } + + // write the final block + if (!adjacent_vals.empty()) { + printf("start_addr 0x%04x, values:", start_addr); + for (auto v : adjacent_vals) printf(" 0x%02X", v); + printf("\n"); + //this->setValues(start_addr, adjacent_vals); } } diff --git a/test/compile.cxx b/test/compile.cxx index db608ff9..3bde5fa4 100644 --- a/test/compile.cxx +++ b/test/compile.cxx @@ -77,23 +77,104 @@ BOOST_AUTO_TEST_CASE(big_32bit_params) { BOOST_AUTO_TEST_CASE(single_register_econd) { pflib::Compiler c = pflib::Compiler::get("econd"); + // Note: this map is going to return a vector where the lowest address (0x0389) gets the least significant byte (rightmost) i.e. 0 + // and the highest address (0x0390) gets the most significant byte (leftmost) i.e. 0xff std::map> registers, expected; - expected[0][0x0389] = 0xff; - expected[0][0x038a] = 0xff; - expected[0][0x038b] = 0xff; - expected[0][0x038c] = 0xff; - expected[0][0x038d] = 0; - expected[0][0x038e] = 0; - expected[0][0x038f] = 0; - expected[0][0x0390] = 0; + expected[0][0x0389] = 0; + expected[0][0x038a] = 0; + expected[0][0x038b] = 0; + expected[0][0x038c] = 0; + expected[0][0x038d] = 0xff; + expected[0][0x038e] = 0xff; + expected[0][0x038f] = 0xff; + expected[0][0x0390] = 0xff; uint64_t mask_val = 0xFFFFFFFF00000000ULL; // Call compile() with uint64_t value c.compile("ALIGNER", "GLOBAL_MATCH_MASK_VAL", mask_val, registers); + + // The registers are already in the form that we need it in ECON (little endian first), so we can just flatten it out + std::vector data; + int page = 0; + for (const auto& [addr, val] : registers[page]) { + data.push_back(val); + } + + for (const auto& [page_id, reg_map] : registers) { + printf("Page %d:", page_id); + for (const auto& [addr, value] : reg_map) + printf(" [0x%04X]=0x%02X", addr, value); + printf("\n"); + } + + for (uint8_t byte : data) + printf("0x%02X ", byte); + printf("\n"); + BOOST_CHECK(registers == expected); } +BOOST_AUTO_TEST_CASE(extract_largehexstr_econd){ + pflib::Compiler c = pflib::Compiler::get("econd"); + + std::string yaml_path = "aligner_test.yaml"; + { + std::ofstream yaml_file{yaml_path}; + yaml_file << "ALIGNER:\n" + << " GLOBAL_MATCH_MASK_VAL: 0xFFFFFFFF00000000\n"; + } + + std::map> settings, expected ; + expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] == 0xFFFFFFFF00000000ULL; + c.extract({yaml_path}, settings); + + for (const auto& page_pair : settings) { + const std::string& page = page_pair.first; + const auto& param_map = page_pair.second; + std::cout << "Page: " << page << "\n"; + for (const auto& param_pair : param_map) { + const std::string& param = param_pair.first; + uint64_t value = param_pair.second; + // Print decimal and hex + std::cout << " " << param << " = " << value + << " (0x" << std::hex << std::uppercase << value << std::dec << ")\n"; + } + } + + BOOST_CHECK_MESSAGE(settings == expected, "ALIGNER.GLOBAL_MATCH_MASK_VAL mismatch"); +} + +BOOST_AUTO_TEST_CASE(extract_largeint_econd) { + pflib::Compiler c = pflib::Compiler::get("econd"); + + std::string yaml_path = "aligner_test.yaml"; + { + std::ofstream yaml_file{yaml_path}; + yaml_file << "ALIGNER:\n" + << " GLOBAL_MATCH_MASK_VAL: '18446744069414584320'\n"; + } + + std::map> settings, expected ; + expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] == 0xFFFFFFFF00000000ULL; + c.extract({yaml_path}, settings); + + for (const auto& page_pair : settings) { + const std::string& page = page_pair.first; + const auto& param_map = page_pair.second; + std::cout << "Page: " << page << "\n"; + for (const auto& param_pair : param_map) { + const std::string& param = param_pair.first; + uint64_t value = param_pair.second; + // Print decimal and hex + std::cout << " " << param << " = " << value + << " (0x" << std::hex << std::uppercase << value << std::dec << ")\n"; + } + } + + BOOST_CHECK_MESSAGE(settings == expected, "ALIGNER.GLOBAL_MATCH_MASK_VAL mismatch"); +} + BOOST_AUTO_TEST_CASE(glob_pages) { pflib::Compiler c = pflib::Compiler::get("sipm_rocv3"); std::string test_filepath{"settings.yaml"}; From f4edade9b4371568a2f8a88d940a44c5f01a2d1e Mon Sep 17 00:00:00 2001 From: cmantill Date: Thu, 9 Oct 2025 17:19:05 +0000 Subject: [PATCH 34/36] move template functions --- include/pflib/Compile.h | 106 ++++++++++++++++++++++++++++++++++++++-- src/pflib/Compile.cxx | 106 ---------------------------------------- 2 files changed, 103 insertions(+), 109 deletions(-) diff --git a/include/pflib/Compile.h b/include/pflib/Compile.h index 8b28f850..31f3a7ba 100644 --- a/include/pflib/Compile.h +++ b/include/pflib/Compile.h @@ -219,7 +219,23 @@ class Compiler { */ template void extract(const std::vector& setting_files, - std::map>& settings); + std::map>& settings) { + for (const auto& file : setting_files) { + YAML::Node node; + try { + node = YAML::LoadFile(file); + } catch (const YAML::BadFile& e) { + throw std::runtime_error("Unable to load file " + file); + } + + if (node.IsSequence()) { + for (std::size_t i = 0; i < node.size(); i++) + extract(node[i], settings); + } else { + extract(node, settings); + } + } + } /** * compile a series of yaml files @@ -267,8 +283,92 @@ class Compiler { * @param[in,out] settings map of names to values for extract parameters */ template - void extract(YAML::Node params, - std::map>& settings); +void Compiler::extract( + YAML::Node params, + std::map>& settings) { + // deduce list of page names for search + // only do this once per program run + static std::vector page_names; + if (page_names.empty()) { + for (auto& page : parameter_lut_) page_names.push_back(page.first); + } + + if (params.IsNull()) { + // skip null nodes (probably comments) + return; + } + + if (not params.IsMap()) { + PFEXCEPTION_RAISE("BadFormat", "The YAML node provided is not a map."); + } + + for (const auto& page_pair : params) { + std::string page_name = page_pair.first.as(); + YAML::Node page_settings = page_pair.second; + if (not page_settings.IsMap()) { + PFEXCEPTION_RAISE("BadFormat", "The YAML node for a page " + page_name + + " is not a map."); + } + + // apply these settings only to pages the input name + std::vector matching_pages; + // determine matching function depending on format of input page + // if input page contains glob character '*', then match prefix, + // otherwise match entire word + if (page_name.find('*') == std::string::npos) { + std::string PAGE_NAME = upper_cp(page_name); + std::copy_if(page_names.begin(), page_names.end(), + std::back_inserter(matching_pages), + [&](const std::string& page) { return PAGE_NAME == page; }); + } else { + page_name = page_name.substr(0, page_name.find('*')); + std::copy_if(page_names.begin(), page_names.end(), + std::back_inserter(matching_pages), + [&](const std::string& page) { + return strncasecmp(page.c_str(), page_name.c_str(), + page_name.size()) == 0; + }); + } + + if (matching_pages.empty()) { + PFEXCEPTION_RAISE("NotFound", + "The page " + page_name + + " does not match any pages in the look up table."); + } + + for (const auto& page : matching_pages) { + for (const auto& param : page_settings) { + std::string sval; + if (param.second.IsScalar()) { + try { + // try to parse as string first + sval = param.second.as(); + } catch (const YAML::TypedBadConversion&) { + try { + // fallback: parse as int and convert to string + int ival = param.second.as(); + sval = std::to_string(ival); + } catch (const YAML::TypedBadConversion&) { + PFEXCEPTION_RAISE("BadFormat", "Value for parameter " + + param.first.as() + " is neither string nor int."); + } + } + } else { + PFEXCEPTION_RAISE("BadFormat", "Non-scalar value for parameter " + + param.first.as()); + } + + if (sval.empty()) { + PFEXCEPTION_RAISE("BadFormat", "Non-existent value for parameter " + + param.first.as()); + } + std::string param_name = upper_cp(param.first.as()); + settings[page][param_name] = std::stoull(sval, nullptr, 0); // base 0 allows hex + //settings[page][param_name] = utility::str_to_int(sval); + } + } + } + } private: const ParameterLUT& parameter_lut_; diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index 5125af53..dcf306d8 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -272,25 +272,6 @@ std::map> Compiler::defaults() { return settings; } -template -void Compiler::extract(const std::vector& setting_files, - std::map>& settings) { - for (auto& setting_file : setting_files) { - YAML::Node setting_yaml; - try { - setting_yaml = YAML::LoadFile(setting_file); - } catch (const YAML::BadFile& e) { - PFEXCEPTION_RAISE("BadFile", "Unable to load file " + setting_file); - } - if (setting_yaml.IsSequence()) { - for (std::size_t i{0}; i < setting_yaml.size(); i++) - Compiler::extract(setting_yaml[i], settings); - } else { - Compiler::extract(setting_yaml, settings); - } - } -} - std::map> Compiler::compile( const std::vector& setting_files, bool prepend_defaults) { std::map> settings; @@ -308,92 +289,5 @@ std::map> Compiler::compile( return compile(std::vector{setting_file}, prepend_defaults); } -template -void Compiler::extract( - YAML::Node params, - std::map>& settings) { - // deduce list of page names for search - // only do this once per program run - static std::vector page_names; - if (page_names.empty()) { - for (auto& page : parameter_lut_) page_names.push_back(page.first); - } - - if (params.IsNull()) { - // skip null nodes (probably comments) - return; - } - - if (not params.IsMap()) { - PFEXCEPTION_RAISE("BadFormat", "The YAML node provided is not a map."); - } - - for (const auto& page_pair : params) { - std::string page_name = page_pair.first.as(); - YAML::Node page_settings = page_pair.second; - if (not page_settings.IsMap()) { - PFEXCEPTION_RAISE("BadFormat", "The YAML node for a page " + page_name + - " is not a map."); - } - - // apply these settings only to pages the input name - std::vector matching_pages; - // determine matching function depending on format of input page - // if input page contains glob character '*', then match prefix, - // otherwise match entire word - if (page_name.find('*') == std::string::npos) { - std::string PAGE_NAME = upper_cp(page_name); - std::copy_if(page_names.begin(), page_names.end(), - std::back_inserter(matching_pages), - [&](const std::string& page) { return PAGE_NAME == page; }); - } else { - page_name = page_name.substr(0, page_name.find('*')); - std::copy_if(page_names.begin(), page_names.end(), - std::back_inserter(matching_pages), - [&](const std::string& page) { - return strncasecmp(page.c_str(), page_name.c_str(), - page_name.size()) == 0; - }); - } - - if (matching_pages.empty()) { - PFEXCEPTION_RAISE("NotFound", - "The page " + page_name + - " does not match any pages in the look up table."); - } - - for (const auto& page : matching_pages) { - for (const auto& param : page_settings) { - std::string sval; - if (param.second.IsScalar()) { - try { - // try to parse as string first - sval = param.second.as(); - } catch (const YAML::TypedBadConversion&) { - try { - // fallback: parse as int and convert to string - int ival = param.second.as(); - sval = std::to_string(ival); - } catch (const YAML::TypedBadConversion&) { - PFEXCEPTION_RAISE("BadFormat", "Value for parameter " + - param.first.as() + " is neither string nor int."); - } - } - } else { - PFEXCEPTION_RAISE("BadFormat", "Non-scalar value for parameter " + - param.first.as()); - } - - if (sval.empty()) { - PFEXCEPTION_RAISE("BadFormat", "Non-existent value for parameter " + - param.first.as()); - } - std::string param_name = upper_cp(param.first.as()); - settings[page][param_name] = std::stoull(sval, nullptr, 0); // base 0 allows hex - //settings[page][param_name] = utility::str_to_int(sval); - } - } - } -} } // namespace pflib From 8a8ba10b983c48be5384490619a86915e43ff755 Mon Sep 17 00:00:00 2001 From: cmantill Date: Thu, 9 Oct 2025 13:54:50 -0400 Subject: [PATCH 35/36] fix test --- include/pflib/Compile.h | 5 ++++- test/compile.cxx | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/pflib/Compile.h b/include/pflib/Compile.h index 31f3a7ba..5547acf0 100644 --- a/include/pflib/Compile.h +++ b/include/pflib/Compile.h @@ -13,6 +13,9 @@ #include #include +#include +#include "pflib/Exception.h" + #include "pflib/Logging.h" #include "pflib/utility/str_to_int.h" #include "register_maps/register_maps_types.h" @@ -283,7 +286,7 @@ class Compiler { * @param[in,out] settings map of names to values for extract parameters */ template -void Compiler::extract( + void extract( YAML::Node params, std::map>& settings) { // deduce list of page names for search diff --git a/test/compile.cxx b/test/compile.cxx index 3bde5fa4..d9241ebb 100644 --- a/test/compile.cxx +++ b/test/compile.cxx @@ -126,7 +126,7 @@ BOOST_AUTO_TEST_CASE(extract_largehexstr_econd){ } std::map> settings, expected ; - expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] == 0xFFFFFFFF00000000ULL; + expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] = 0xFFFFFFFF00000000ULL; c.extract({yaml_path}, settings); for (const auto& page_pair : settings) { @@ -156,7 +156,7 @@ BOOST_AUTO_TEST_CASE(extract_largeint_econd) { } std::map> settings, expected ; - expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] == 0xFFFFFFFF00000000ULL; + expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] = 0xFFFFFFFF00000000ULL; c.extract({yaml_path}, settings); for (const auto& page_pair : settings) { From ff1e7f00f0fd9c0df1175b24176bfcf767cc8d4d Mon Sep 17 00:00:00 2001 From: cmantill Date: Thu, 9 Oct 2025 16:11:07 -0400 Subject: [PATCH 36/36] checkpoint --- CMakeLists.txt | 19 ++++++- include/pflib/Compile.h | 64 +++++++++++++++++++++-- include/pflib/ECON.h | 3 ++ register_maps/econ-to-header.py | 61 ++++++++++++++++++++-- src/pflib/Compile.cxx | 91 +++++++++++++++------------------ src/pflib/ECON.cxx | 77 ++++++++++++++++++++++++++-- test/compile.cxx | 46 ++++++++--------- 7 files changed, 274 insertions(+), 87 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index d3bbc885..966206b8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -101,12 +101,26 @@ add_custom_command( add_custom_target(lpgbt_regmap DEPENDS include/register_maps/lpgbt.h) add_custom_command( - OUTPUT "include/register_maps/econd.h" + OUTPUT "include/register_maps/econd_test.h" COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps COMMAND python3 ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py - #${PROJECT_SOURCE_DIR}/register_maps/ECOND_I2C_params_regmap.yaml ${PROJECT_SOURCE_DIR}/register_maps/ECOND_test.yaml + ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps/econd_test.h + DEPENDS + ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py + ${PROJECT_SOURCE_DIR}/register_maps/ECOND_test.yaml + COMMENT "Generating C++ ECOND test register LUT from register_maps/ECOND_test.yaml" + VERBATIM +) +add_custom_target(econd_test DEPENDS include/register_maps/econd_test.h) + +add_custom_command( + OUTPUT "include/register_maps/econd.h" + COMMAND mkdir -p ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps + COMMAND python3 + ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py + ${PROJECT_SOURCE_DIR}/register_maps/ECOND_I2C_params_regmap.yaml ${CMAKE_CURRENT_BINARY_DIR}/include/register_maps/econd.h DEPENDS ${PROJECT_SOURCE_DIR}/register_maps/econ-to-header.py @@ -131,6 +145,7 @@ add_custom_command( ) add_custom_target(econt DEPENDS include/register_maps/econt.h) +list(APPEND generate_headers_econ econd_test) list(APPEND generate_headers_econ econd) list(APPEND generate_headers_econ econt) diff --git a/include/pflib/Compile.h b/include/pflib/Compile.h index 5547acf0..43740be4 100644 --- a/include/pflib/Compile.h +++ b/include/pflib/Compile.h @@ -95,10 +95,36 @@ class Compiler { * @param[in] val value parameter should be set to * @return page numbers, register numbers, and register values to set */ - std::map> compile(const std::string& page_name, - const std::string& param_name, - const int& val); + template + std::map> compile( + const std::string& page_name, const std::string& param_name, + const T& val) + { + std::string PAGE_NAME(upper_cp(page_name)); + std::string PARAM_NAME(upper_cp(param_name)); + + if (parameter_lut_.find(PAGE_NAME) == parameter_lut_.end()) { + PFEXCEPTION_RAISE("NotFound", "The page named '" + PAGE_NAME + + "' is not found in the look up table."); + } + + const auto& page_lut{parameter_lut_.at(PAGE_NAME).second}; + + if (page_lut.find(PARAM_NAME) == page_lut.end()) { + PFEXCEPTION_RAISE("NotFound", + "The parameter named '" + PARAM_NAME + + "' is not found in the look up table for page " + + PAGE_NAME); + } + + std::map> rv; + + compile(page_name, param_name, static_cast(val), rv); + return rv; + } + + /** * Compiling which translates parameter values for the HGCROC * into register values that can be written to the chip @@ -126,9 +152,39 @@ class Compiler { * settings * @return page numbers, register numbers, and register value settings */ + template std::map> compile( - const std::map>& settings); + const std::map>& settings) + { + std::map> register_values; + for (const auto& page : settings) { + std::string page_name = upper_cp(page.first); + if (parameter_lut_.find(page_name) == parameter_lut_.end()) { + PFEXCEPTION_RAISE("NotFound", + "The page named '" + page.first + "' is not found in the look up table."); + } + const auto& page_lut{parameter_lut_.at(page_name).second}; + for (const auto& param : page.second) { + std::string param_name = upper_cp(param.first); + if (page_lut.find(param_name) == page_lut.end()) { + PFEXCEPTION_RAISE("NotFound", + "The parameter named '" + param.first + + "' is not found in the look up table for page " + + page.first); + } + compile(page_name, param_name, static_cast(param.second), register_values); + } + } + return register_values; + } + + + /** + * Get all register address -> nbytes map + */ + std::map build_register_byte_lut(); + /** * Get the known pages from the LUTs * diff --git a/include/pflib/ECON.h b/include/pflib/ECON.h index 62787701..c1ee312e 100644 --- a/include/pflib/ECON.h +++ b/include/pflib/ECON.h @@ -29,11 +29,14 @@ class ECON { void setRegisters(const std::map>& registers); void loadParameters(const std::string& file_path, bool prepend_defaults); + std::map> getRegisters(const std::map>& selected); + std::map> applyParameters(const std::map>& parameters); private: I2C& i2c_; uint8_t econ_base_; Compiler compiler_; + std::map econ_reg_nbytes_lut_; mutable ::pflib::logging::logger the_log_{::pflib::logging::get("econ")}; }; diff --git a/register_maps/econ-to-header.py b/register_maps/econ-to-header.py index ef75c70c..ce48c551 100644 --- a/register_maps/econ-to-header.py +++ b/register_maps/econ-to-header.py @@ -18,6 +18,57 @@ def format_cpp_int(value: int) -> str: return f'{value}ULL' else: return str(value) + +def get_global_register_range(data): + """ + Compute the minimum and maximum register addresses across all pages and registers + in the YAML LUT. + """ + min_addr = None + max_addr = None + used_addresses = set() + + def update_range(address, mask, shift, size_byte): + nonlocal min_addr, max_addr + reg_locs = make_register_locations(address, mask, shift, size_byte) + for loc in reg_locs: + addr = int(loc.split("(")[1].split(",")[0], 16) + used_addresses.add(addr) + if min_addr is None or addr < min_addr: + min_addr = addr + if max_addr is None or addr > max_addr: + max_addr = addr + + def process_node(props): + if isinstance(props, dict): + if "address" in props: + address = int(props["address"]) + mask = int(props["param_mask"]) + shift = int(props["param_shift"]) + size_byte = props.get("size_byte", 1) + update_range(address, mask, shift, size_byte) + else: + for subval in props.values(): + process_node(subval) + + # loop over all pages and registers + for page, groups in data.items(): + for group_name, registers in groups.items(): + if isinstance(registers, dict) and "address" in registers: + process_node(registers) + else: + for reg_name, props in registers.items(): + process_node(props) + + # compute unused addresses + unused_addresses = [] + if min_addr is not None and max_addr is not None: + full_range = set(range(min_addr, max_addr + 1)) + unused_addresses = sorted(full_range - used_addresses) + + print(f"Global register range: 0x{min_addr:04X} - 0x{max_addr:04X}") + print(f"Unused addresses length: {len(unused_addresses)}") + def make_register_locations(address, mask, shift, size_byte): """Split a register into 8-bit chunks if it spans multiple bytes. @@ -108,7 +159,7 @@ def generate_header(input_yaml, data, econ_type): lines.append('#include "register_maps/register_maps_types.h"\n') lines.append(f"namespace econ{econ_type}"+" {\n") - # Loop through all blocks (e.g. ALIGNER, CHALIGNER) + # loop through all blocks (e.g. ALIGNER, CHALIGNER) page_names = [] for page_name, groups in data.items(): page_var = page_name.upper() # uppercase page name @@ -137,7 +188,7 @@ def generate_header(input_yaml, data, econ_type): lines.append(f' {{"{name}", {{0, {name}}}}},') lines.append("});") - lines.append("\n} // namespace econd\n") + lines.append("\n} //"+f" namespace econ{econ_type}\n") return "\n".join(lines) @@ -146,10 +197,14 @@ def compile_registers(yaml_file, output_file): data = yaml.safe_load(f) econ_type = "d" if "ECOND" in yaml_file else "t" + if "test" in yaml_file: + econ_type += "_test" content = generate_header(yaml_file, data, econ_type) with open(output_file, "w") as f: f.write(content) - + + #get_global_register_range(data) + if __name__ == "__main__": if len(sys.argv) != 3: print("Usage: python3 econ-to-header.py ") diff --git a/src/pflib/Compile.cxx b/src/pflib/Compile.cxx index dcf306d8..6b3c79ac 100644 --- a/src/pflib/Compile.cxx +++ b/src/pflib/Compile.cxx @@ -131,59 +131,52 @@ void Compiler::compile(const std::string& page_name, //printf("Finished setting %s.%s\n", page_name.c_str(), param_name.c_str()); return; } - -std::map> Compiler::compile( - const std::string& page_name, const std::string& param_name, - const int& val) { - std::string PAGE_NAME(upper_cp(page_name)), PARAM_NAME(upper_cp(param_name)); - if (parameter_lut_.find(PAGE_NAME) == parameter_lut_.end()) { - PFEXCEPTION_RAISE("NotFound", "The page named '" + PAGE_NAME + - "' is not found in the look up table."); - } - const auto& page_lut{parameter_lut_.at(PAGE_NAME).second}; - if (page_lut.find(PARAM_NAME) == page_lut.end()) { - PFEXCEPTION_RAISE("NotFound", - "The parameter named '" + PARAM_NAME + - "' is not found in the look up table for page " + - PAGE_NAME); - } - std::map> rv; - compile(PAGE_NAME, PARAM_NAME, val, rv); - return rv; -} - -std::map> Compiler::compile( - const std::map>& settings) { - std::map> register_values; - for (const auto& page : settings) { - // page.first => page name - // page.second => parameter to value map - std::string page_name = upper_cp(page.first); - if (parameter_lut_.find(page_name) == parameter_lut_.end()) { - // this exception shouldn't really ever happen because we check if the - // input page matches any of the pages in the LUT in detail::apply, but we - // leave this check in here for future development - PFEXCEPTION_RAISE("NotFound", "The page named '" + page.first + - "' is not found in the look up table."); - } - const auto& page_lut{parameter_lut_.at(page_name).second}; - for (const auto& param : page.second) { - // param.first => parameter name - // param.second => value - std::string param_name = upper_cp(param.first); - if (page_lut.find(param_name) == page_lut.end()) { - PFEXCEPTION_RAISE("NotFound", - "The parameter named '" + param.first + - "' is not found in the look up table for page " + - page.first); + +std::map Compiler::build_register_byte_lut() { + // register address -> number of bytes used) + std::map reg_byte_lut; + + for (const auto& page_pair : page_lut_) { + const std::string& page_name = page_pair.first; + const Page& page = page_pair.second; + + std::set all_used_regs; + + for (const auto& param_pair : page) { + const Parameter& param = param_pair.second; + + std::vector regs = param.registers; + + // start tracking a contiguous region + uint16_t start = regs[0].reg; + uint16_t end = start + (regs[0].min_bit + regs[0].n_bits + 7) / 8 - 1; + + for (size_t i = 1; i < regs.size(); ++i) { + uint16_t loc_start = regs[i].reg; + uint16_t loc_end = loc_start + (regs[i].min_bit + regs[i].n_bits + 7) / 8 - 1; + + if (loc_start <= end + 1) { + // Extend the contiguous block + end = std::max(end, loc_end); + } else { + // Save previous block + reg_byte_lut[start] = end - start + 1; + + // Start a new one + start = loc_start; + end = loc_end; + } } - compile(page_name, param_name, param.second, register_values); - } // loop over parameters in page - } // loop over pages + + // Save last block for this parameter + reg_byte_lut[start] = end - start + 1; + } + } - return register_values; + return reg_byte_lut; } + std::vector Compiler::get_known_pages() { std::vector known_pages; known_pages.reserve(parameter_lut_.size()); diff --git a/src/pflib/ECON.cxx b/src/pflib/ECON.cxx index c1fe2989..f745fc73 100644 --- a/src/pflib/ECON.cxx +++ b/src/pflib/ECON.cxx @@ -15,6 +15,8 @@ ECON::ECON(I2C& i2c, uint8_t econ_base_addr, const std::string& type_version) econ_base_{econ_base_addr}, compiler_{Compiler::get(type_version)} { + econ_reg_nbytes_lut_ = compiler_.build_register_byte_lut(); + pflib_log(debug) << "ECON base addr " << packing::hex(econ_base_); } @@ -174,7 +176,7 @@ void ECON::setRegisters(const std::map>& registers) for (auto v : adjacent_vals) printf(" 0x%02X", v); printf("\n"); - //this->setValues(start_addr, adjacent_vals); + this->setValues(start_addr, adjacent_vals); // reset for new block adjacent_vals.clear(); @@ -189,20 +191,89 @@ void ECON::setRegisters(const std::map>& registers) printf("start_addr 0x%04x, values:", start_addr); for (auto v : adjacent_vals) printf(" 0x%02X", v); printf("\n"); - //this->setValues(start_addr, adjacent_vals); + this->setValues(start_addr, adjacent_vals); } } + +std::map> ECON::getRegisters( + const std::map>& selected) { + // output map: page_id -> (register address -> value) + std::map> chip_reg; + const int page_id = 0; // always page 0 + + // read all registers from the chip + for (const auto& [reg_addr, nbytes] : econ_reg_nbytes_lut_) { + std::vector on_chip_reg_values = getValues(reg_addr, nbytes); + } + + /* + if (selected.empty()) { + // if no specific registers are requested, read all registers + for (int reg = 0; reg < N_REGISTERS_PER_PAGE; ++reg) { + chip_reg[page_id][reg] = on_chip_reg_values.at(reg); + } + } else { + // only read the registers in selected[0] + const auto& reg_map = selected.at(page_id); + for (const auto& [reg, _] : reg_map) { + chip_reg[page_id][reg] = on_chip_reg_values.at(reg); + } + } + */ + + return chip_reg; +} + +std::map> ECON::applyParameters(const std::map>& parameters) { + /** + * 1. get registers YAML file contains by compiling without defaults + */ + auto touched_registers = compiler_.compile(parameters); + /** + * 2. get the current register values on the chip which is + */ + auto chip_reg{getRegisters(touched_registers)}; + // copy of current chip values to return + auto ret_val = chip_reg; + /** + * 3. compile this parameter onto those register values + * we can use the lower-level compile here because the + * compile in step 1 checks that all of the page and param + * names are correct + */ + for (auto& page : parameters) { + std::string page_name = upper_cp(page.first); + for (auto& param : page.second) { + compiler_.compile(page_name, upper_cp(param.first), param.second, + chip_reg); + } + } + /** + * 4. put these updated values onto the chip + */ + this->setRegisters(chip_reg); + return ret_val; +} void ECON::loadParameters(const std::string& file_path, bool prepend_defaults) { if (prepend_defaults) { /** * If we prepend defaults, then ALL of the parameters will be - * touched and so we do need to bother reading the current + * touched and so we do NOT need to bother reading the current * values and overlaying the new ones, instead we jump straight * to setting the registers. */ auto settings = compiler_.compile(file_path, true); setRegisters(settings); + } else { + /** + * If we don't prepend the defaults, then we use the other applyParameters + * function to overlay the parameters we passed on top of the ones currently + * on the chip after extracting them from the YAML file. + */ + std::map> parameters; + compiler_.extract(std::vector{file_path}, parameters); + applyParameters(parameters); } } diff --git a/test/compile.cxx b/test/compile.cxx index d9241ebb..5c63226c 100644 --- a/test/compile.cxx +++ b/test/compile.cxx @@ -6,6 +6,8 @@ #include "pflib/Exception.h" +#include + BOOST_AUTO_TEST_SUITE(compile) BOOST_AUTO_TEST_CASE(get_by_name) { @@ -129,19 +131,6 @@ BOOST_AUTO_TEST_CASE(extract_largehexstr_econd){ expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] = 0xFFFFFFFF00000000ULL; c.extract({yaml_path}, settings); - for (const auto& page_pair : settings) { - const std::string& page = page_pair.first; - const auto& param_map = page_pair.second; - std::cout << "Page: " << page << "\n"; - for (const auto& param_pair : param_map) { - const std::string& param = param_pair.first; - uint64_t value = param_pair.second; - // Print decimal and hex - std::cout << " " << param << " = " << value - << " (0x" << std::hex << std::uppercase << value << std::dec << ")\n"; - } - } - BOOST_CHECK_MESSAGE(settings == expected, "ALIGNER.GLOBAL_MATCH_MASK_VAL mismatch"); } @@ -159,22 +148,27 @@ BOOST_AUTO_TEST_CASE(extract_largeint_econd) { expected["ALIGNER"]["GLOBAL_MATCH_MASK_VAL"] = 0xFFFFFFFF00000000ULL; c.extract({yaml_path}, settings); - for (const auto& page_pair : settings) { - const std::string& page = page_pair.first; - const auto& param_map = page_pair.second; - std::cout << "Page: " << page << "\n"; - for (const auto& param_pair : param_map) { - const std::string& param = param_pair.first; - uint64_t value = param_pair.second; - // Print decimal and hex - std::cout << " " << param << " = " << value - << " (0x" << std::hex << std::uppercase << value << std::dec << ")\n"; - } - } - BOOST_CHECK_MESSAGE(settings == expected, "ALIGNER.GLOBAL_MATCH_MASK_VAL mismatch"); } +BOOST_AUTO_TEST_CASE(full_lut_econd) { + pflib::Compiler c = pflib::Compiler::get("econd_test"); + + std::map page_reg_byte_lut, expected; + expected[0x0389] = 8; + page_reg_byte_lut = c.build_register_byte_lut(); + + for (const auto& [reg, nbytes] : page_reg_byte_lut) { + std::cout << "0x" + << std::hex << std::uppercase << std::setw(4) << std::setfill('0') << reg + << " -> " + << std::dec << nbytes << " bytes\n"; + } + + BOOST_CHECK_MESSAGE(page_reg_byte_lut == expected, + "The generated register LUT does not match the expected LUT"); +} + BOOST_AUTO_TEST_CASE(glob_pages) { pflib::Compiler c = pflib::Compiler::get("sipm_rocv3"); std::string test_filepath{"settings.yaml"};