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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | + |
| 3 | +/dts-v1/; |
| 4 | + |
| 5 | +#include "ipq8074.dtsi" |
| 6 | +#include "ipq8074-ac-cpu.dtsi" |
| 7 | +#include "ipq8074-ess.dtsi" |
| 8 | +#include "ipq8074-nss.dtsi" |
| 9 | +#include <dt-bindings/gpio/gpio.h> |
| 10 | +#include <dt-bindings/input/input.h> |
| 11 | + |
| 12 | +/ { |
| 13 | + model = "Aliyun AP8220"; |
| 14 | + compatible = "aliyun,ap8220", "qcom,ipq8074"; |
| 15 | + |
| 16 | + aliases { |
| 17 | + serial0 = &blsp1_uart5; |
| 18 | + led-boot = &led_pwr; |
| 19 | + led-failsafe = &led_pwr; |
| 20 | + led-running = &led_pwr; |
| 21 | + led-upgrade = &led_pwr; |
| 22 | + }; |
| 23 | + |
| 24 | + chosen { |
| 25 | + stdout-path = "serial0:115200n8"; |
| 26 | + bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1 coherent_pool=2M"; |
| 27 | + }; |
| 28 | + |
| 29 | + keys { |
| 30 | + compatible = "gpio-keys"; |
| 31 | + pinctrl-0 = <&button_pins>; |
| 32 | + pinctrl-names = "default"; |
| 33 | + |
| 34 | + reset { |
| 35 | + label = "reset"; |
| 36 | + linux,code = <KEY_RESTART>; |
| 37 | + gpios = <&tlmm 0x42 GPIO_ACTIVE_LOW>; |
| 38 | + }; |
| 39 | + }; |
| 40 | + |
| 41 | + leds { |
| 42 | + compatible = "gpio-leds"; |
| 43 | + pinctrl-0 = <&led_pins>; |
| 44 | + pinctrl-names = "default"; |
| 45 | + |
| 46 | + led_pwr: power { |
| 47 | + label = "pwr"; |
| 48 | + gpio = <&tlmm 0x2e GPIO_ACTIVE_HIGH>; |
| 49 | + }; |
| 50 | + |
| 51 | + led_2g: 2g { |
| 52 | + label = "wlan2g"; |
| 53 | + gpio = <&tlmm 0x2f GPIO_ACTIVE_HIGH>; |
| 54 | + }; |
| 55 | + |
| 56 | + led_5g: 5g { |
| 57 | + label = "wlan5g"; |
| 58 | + gpio = <&tlmm 0x30 GPIO_ACTIVE_HIGH>; |
| 59 | + }; |
| 60 | + |
| 61 | + led_ble: ble { |
| 62 | + label = "ble"; |
| 63 | + gpio = <&tlmm 0x32 GPIO_ACTIVE_HIGH>; |
| 64 | + }; |
| 65 | + }; |
| 66 | +}; |
| 67 | + |
| 68 | +&tlmm { |
| 69 | + button_pins: button_pins { |
| 70 | + phandle = <0x52>; |
| 71 | + |
| 72 | + wps_button { |
| 73 | + pins = "gpio66"; |
| 74 | + function = "gpio"; |
| 75 | + drive-strength = <0x08>; |
| 76 | + bias-pull-up; |
| 77 | + }; |
| 78 | + }; |
| 79 | + |
| 80 | + usb_mux_pins { |
| 81 | + |
| 82 | + mux { |
| 83 | + pins = "gpio27"; |
| 84 | + function = "gpio"; |
| 85 | + drive-strength = <0x08>; |
| 86 | + bias-pull-down; |
| 87 | + }; |
| 88 | + }; |
| 89 | + |
| 90 | + pcie_pins { |
| 91 | + |
| 92 | + pcie0_rst { |
| 93 | + pins = "gpio58"; |
| 94 | + function = "pcie0_rst"; |
| 95 | + drive-strength = <0x08>; |
| 96 | + bias-pull-down; |
| 97 | + }; |
| 98 | + |
| 99 | + pcie0_wake { |
| 100 | + pins = "gpio59"; |
| 101 | + function = "pcie0_wake"; |
| 102 | + drive-strength = <0x08>; |
| 103 | + bias-pull-down; |
| 104 | + }; |
| 105 | + }; |
| 106 | + |
| 107 | + mdio_pins: mdio-pins { |
| 108 | + phandle = <0x27>; |
| 109 | + |
| 110 | + mux_0 { |
| 111 | + pins = "gpio68"; |
| 112 | + function = "mdc"; |
| 113 | + drive-strength = <0x08>; |
| 114 | + bias-pull-up; |
| 115 | + }; |
| 116 | + |
| 117 | + mux_1 { |
| 118 | + pins = "gpio69"; |
| 119 | + function = "mdio"; |
| 120 | + drive-strength = <0x08>; |
| 121 | + bias-pull-up; |
| 122 | + }; |
| 123 | + |
| 124 | + mux_2 { |
| 125 | + pins = "gpio33"; |
| 126 | + function = "gpio"; |
| 127 | + bias-pull-up; |
| 128 | + }; |
| 129 | + |
| 130 | + mux_3 { |
| 131 | + pins = "gpio44"; |
| 132 | + function = "gpio"; |
| 133 | + bias-pull-up; |
| 134 | + }; |
| 135 | + }; |
| 136 | + |
| 137 | + led_pins: led-pins { |
| 138 | + phandle = <0x53>; |
| 139 | + |
| 140 | + led_pwr { |
| 141 | + pins = "gpio46"; |
| 142 | + function = "gpio"; |
| 143 | + drive-strength = <0x02>; |
| 144 | + bias-pull-up; |
| 145 | + }; |
| 146 | + |
| 147 | + led_2g { |
| 148 | + pins = "gpio47"; |
| 149 | + function = "gpio"; |
| 150 | + drive-strength = <0x02>; |
| 151 | + bias-pull-down; |
| 152 | + }; |
| 153 | + |
| 154 | + led_5g { |
| 155 | + pins = "gpio48"; |
| 156 | + function = "gpio"; |
| 157 | + drive-strength = <0x02>; |
| 158 | + bias-pull-down; |
| 159 | + }; |
| 160 | + |
| 161 | + led_ble { |
| 162 | + pins = "gpio50"; |
| 163 | + function = "gpio"; |
| 164 | + drive-strength = <0x02>; |
| 165 | + bias-pull-down; |
| 166 | + }; |
| 167 | + }; |
| 168 | + |
| 169 | +}; |
| 170 | + |
| 171 | +&blsp1_spi1 { |
| 172 | + pinctrl-0 = <&spi_0_pins>; |
| 173 | + pinctrl-names = "default"; |
| 174 | + cs-select = <0>; |
| 175 | + status = "okay"; |
| 176 | + |
| 177 | + flash@0 { |
| 178 | + compatible = "jedec,spi-nor"; |
| 179 | + #address-cells = <1>; |
| 180 | + #size-cells = <1>; |
| 181 | + reg = <0>; |
| 182 | + spi-max-frequency = <50000000>; |
| 183 | + |
| 184 | + partitions { |
| 185 | + compatible = "fixed-partitions"; |
| 186 | + #address-cells = <1>; |
| 187 | + #size-cells = <1>; |
| 188 | + |
| 189 | + partition@0 { |
| 190 | + label = "0:SBL1"; |
| 191 | + reg = <0x00 0x50000>; |
| 192 | + }; |
| 193 | + |
| 194 | + partition@50000 { |
| 195 | + label = "0:MIBIB"; |
| 196 | + reg = <0x50000 0x10000>; |
| 197 | + }; |
| 198 | + |
| 199 | + partition@60000 { |
| 200 | + label = "0:QSEE"; |
| 201 | + reg = <0x60000 0x180000>; |
| 202 | + }; |
| 203 | + |
| 204 | + partition@1e0000 { |
| 205 | + label = "0:DEVCFG"; |
| 206 | + reg = <0x1e0000 0x10000>; |
| 207 | + }; |
| 208 | + |
| 209 | + partition@1f0000 { |
| 210 | + label = "0:APDP"; |
| 211 | + reg = <0x1f0000 0x10000>; |
| 212 | + }; |
| 213 | + |
| 214 | + partition@200000 { |
| 215 | + label = "0:RPM"; |
| 216 | + reg = <0x200000 0x40000>; |
| 217 | + }; |
| 218 | + |
| 219 | + partition@240000 { |
| 220 | + label = "0:CDT"; |
| 221 | + reg = <0x240000 0x10000>; |
| 222 | + }; |
| 223 | + |
| 224 | + partition@250000 { |
| 225 | + label = "0:APPSBLENV"; |
| 226 | + reg = <0x250000 0x10000>; |
| 227 | + }; |
| 228 | + |
| 229 | + partition@260000 { |
| 230 | + label = "0:APPSBL"; |
| 231 | + reg = <0x260000 0xa0000>; |
| 232 | + }; |
| 233 | + |
| 234 | + partition@300000 { |
| 235 | + label = "0:ART"; |
| 236 | + reg = <0x300000 0x40000>; |
| 237 | + }; |
| 238 | + |
| 239 | + partition@340000 { |
| 240 | + label = "0:ETHPHYFW"; |
| 241 | + reg = <0x340000 0x80000>; |
| 242 | + }; |
| 243 | + |
| 244 | + partition@3c0000 { |
| 245 | + label = "product_info"; |
| 246 | + reg = <0x3c0000 0x10000>; |
| 247 | + }; |
| 248 | + |
| 249 | + partition@3d0000 { |
| 250 | + label = "mtdoops"; |
| 251 | + reg = <0x3d0000 0x20000>; |
| 252 | + }; |
| 253 | + |
| 254 | + partition@3f0000 { |
| 255 | + label = "priv_data1"; |
| 256 | + reg = <0x3f0000 0x10000>; |
| 257 | + }; |
| 258 | + }; |
| 259 | + }; |
| 260 | +}; |
| 261 | + |
| 262 | +&blsp1_uart5 { |
| 263 | + status = "okay"; |
| 264 | +}; |
| 265 | + |
| 266 | +&cryptobam { |
| 267 | + status = "okay"; |
| 268 | +}; |
| 269 | + |
| 270 | +&crypto { |
| 271 | + status = "okay"; |
| 272 | +}; |
| 273 | + |
| 274 | +&prng { |
| 275 | + status = "okay"; |
| 276 | +}; |
| 277 | + |
| 278 | +&qpic_bam { |
| 279 | + status = "okay"; |
| 280 | +}; |
| 281 | + |
| 282 | +&qpic_nand { |
| 283 | + status = "okay"; |
| 284 | + |
| 285 | + nand@0 { |
| 286 | + reg = <0>; |
| 287 | + #address-cells = <0x01>; |
| 288 | + #size-cells = <0x01>; |
| 289 | + nand-ecc-strength = <0x04>; |
| 290 | + nand-ecc-step-size = <0x200>; |
| 291 | + nand-bus-width = <0x08>; |
| 292 | + |
| 293 | + partition@0 { |
| 294 | + label = "rootfs"; |
| 295 | + reg = <0x00 0x8000000>; |
| 296 | + }; |
| 297 | + }; |
| 298 | +}; |
| 299 | + |
| 300 | +&mdio { |
| 301 | + status = "okay"; |
| 302 | + |
| 303 | + pinctrl-0 = <&mdio_pins>; |
| 304 | + pinctrl-names = "default"; |
| 305 | + |
| 306 | + qca8081_24: ethernet-phy@24 { |
| 307 | + compatible = "ethernet-phy-id004d.d101"; |
| 308 | + reg = <24>; |
| 309 | + reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; |
| 310 | + }; |
| 311 | + |
| 312 | + qca8081_28: ethernet-phy@28 { |
| 313 | + compatible = "ethernet-phy-id004d.d101"; |
| 314 | + reg = <28>; |
| 315 | + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; |
| 316 | + }; |
| 317 | +}; |
| 318 | + |
| 319 | +&switch { |
| 320 | + status = "okay"; |
| 321 | + |
| 322 | + switch_lan_bmp = <0x3e>; /* lan port bitmap */ |
| 323 | + switch_wan_bmp = <0x40>; /* wan port bitmap */ |
| 324 | + switch_mac_mode = <0>; /* mac mode for uniphy instance0*/ |
| 325 | + switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/ |
| 326 | + switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/ |
| 327 | + bm_tick_mode = <0>; /* bm tick mode */ |
| 328 | + tm_tick_mode = <0>; /* tm tick mode */ |
| 329 | + |
| 330 | + qcom,port_phyinfo { |
| 331 | + port@5 { |
| 332 | + port_id = <5>; |
| 333 | + phy_address = <24>; |
| 334 | + port_mac_sel = "QGMAC_PORT"; |
| 335 | + }; |
| 336 | + port@6 { |
| 337 | + port_id = <6>; |
| 338 | + phy_address = <28>; |
| 339 | + port_mac_sel = "QGMAC_PORT"; |
| 340 | + }; |
| 341 | + }; |
| 342 | +}; |
| 343 | + |
| 344 | +&edma { |
| 345 | + status = "okay"; |
| 346 | +}; |
| 347 | + |
| 348 | +&dp5 { |
| 349 | + status = "okay"; |
| 350 | + phy-handle = <&qca8081_24>; |
| 351 | +}; |
| 352 | + |
| 353 | +&dp6 { |
| 354 | + status = "okay"; |
| 355 | + phy-handle = <&qca8081_28>; |
| 356 | +}; |
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