From 8c92ca07c51c6c0b4cc6e60d30b36bf759b01dbd Mon Sep 17 00:00:00 2001 From: Portisch Date: Thu, 30 Nov 2017 14:58:29 +0100 Subject: [PATCH] First commit --- .cproject | 92 + .gitignore | 2 + .project | 27 + ...bs.ss.framework.ide.project.sls.core.prefs | 2 + Keil 8051 v9.53 - Release/RF_Bridge.hex | 174 + Keil 8051 v9.53 - Release/RF_Bridge.lnp | 8 + Keil 8051 v9.53 - Release/RF_Bridge.m51 | 3036 +++++++++++++++++ Keil 8051 v9.53 - Release/RF_Bridge.omf | Bin 0 -> 64264 bytes Keil 8051 v9.53 - Release/makefile | 52 + Keil 8051 v9.53 - Release/objects.mk | 8 + Keil 8051 v9.53 - Release/sources.mk | 18 + README.md | 58 + RF_Bridge.hwconf | 101 + inc/Globals.h | 27 + inc/InitDevice.h | 35 + inc/RF_Handling.h | 48 + inc/RF_Protocols.h | 60 + inc/efm8_config.h | 15 + inc/uart.h | 74 + lib/efm8bb1/peripheralDrivers/inc/pca_0.h | 601 ++++ lib/efm8bb1/peripheralDrivers/inc/uart_0.h | 632 ++++ lib/efm8bb1/peripheralDrivers/src/pca_0.c | 269 ++ lib/efm8bb1/peripheralDrivers/src/uart_0.c | 193 ++ src/InitDevice.c | 542 +++ src/RF_Bridge_main.c | 211 ++ src/RF_Handling.c | 364 ++ src/SILABS_STARTUP.A51 | 203 ++ src/uart.c | 266 ++ 28 files changed, 7118 insertions(+) create mode 100644 .cproject create mode 100644 .gitignore create mode 100644 .project create mode 100644 .settings/com.silabs.ss.framework.ide.project.sls.core.prefs create mode 100644 Keil 8051 v9.53 - Release/RF_Bridge.hex create mode 100644 Keil 8051 v9.53 - Release/RF_Bridge.lnp create mode 100644 Keil 8051 v9.53 - Release/RF_Bridge.m51 create mode 100644 Keil 8051 v9.53 - Release/RF_Bridge.omf create mode 100644 Keil 8051 v9.53 - Release/makefile create mode 100644 Keil 8051 v9.53 - Release/objects.mk create mode 100644 Keil 8051 v9.53 - Release/sources.mk create mode 100644 README.md create mode 100644 RF_Bridge.hwconf create mode 100644 inc/Globals.h create mode 100644 inc/InitDevice.h create mode 100644 inc/RF_Handling.h create mode 100644 inc/RF_Protocols.h create mode 100644 inc/efm8_config.h create mode 100644 inc/uart.h create mode 100644 lib/efm8bb1/peripheralDrivers/inc/pca_0.h create mode 100644 lib/efm8bb1/peripheralDrivers/inc/uart_0.h create mode 100644 lib/efm8bb1/peripheralDrivers/src/pca_0.c create mode 100644 lib/efm8bb1/peripheralDrivers/src/uart_0.c create mode 100644 src/InitDevice.c create mode 100644 src/RF_Bridge_main.c create mode 100644 src/RF_Handling.c create mode 100644 src/SILABS_STARTUP.A51 create mode 100644 src/uart.c diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..91f8c75 --- /dev/null +++ b/.cproject @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a2fcded --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +Keil 8051 v9.53 - Release/lib/* +Keil 8051 v9.53 - Release/src/* \ No newline at end of file diff --git a/.project b/.project new file mode 100644 index 0000000..283a450 --- /dev/null +++ b/.project @@ -0,0 +1,27 @@ + + + RF_Bridge + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.silabs.ss.framework.ide.project.sls.core.SLSProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/com.silabs.ss.framework.ide.project.sls.core.prefs b/.settings/com.silabs.ss.framework.ide.project.sls.core.prefs new file mode 100644 index 0000000..b4554b4 --- /dev/null +++ b/.settings/com.silabs.ss.framework.ide.project.sls.core.prefs @@ -0,0 +1,2 @@ +copiedFilesOriginState={} +eclipse.preferences.version=1 diff --git a/Keil 8051 v9.53 - Release/RF_Bridge.hex b/Keil 8051 v9.53 - Release/RF_Bridge.hex new file mode 100644 index 0000000..9ac5d9c --- /dev/null +++ b/Keil 8051 v9.53 - Release/RF_Bridge.hex @@ -0,0 +1,174 @@ +:020000040000FA +:100000000205DAE4FDFCFF120A0753DAFE120AAB1E +:1000100053E2FDC28043E2029000D0E06003120987 +:10002000BF2222020760C0E0C083C082C0D05391CB +:100030007FD39000D4E094009000D3E0940050036C +:100040005391FB9000D4E024FBF09000D3E034FF08 +:10005000F0D0D0D082D083D0E03222020669C2DE56 +:1000600075D90575F9FF75960143F74022C2DE5335 +:10007000DBFE22020026EF8DF0A4A8F0CF8CF0A4C6 +:1000800028CE8DF0A42EFE22BC000BBE0029EF8DE1 +:10009000F084FFADF022E4CCF875F008EF2FFFEE0E +:1000A00033FEEC33FCEE9DEC984005FCEE9DFE0F1C +:1000B000D5F0E9E4CEFD22EDF8F5F0EE8420D21C77 +:1000C000FEADF075F008EF2FFFED33FD40079850BF +:1000D00006D5F0F222C398FD0FD5F0EA22C2D5EC86 +:1000E00030E709B2D5E4C39DFDE49CFCEE30E71592 +:1000F000B2D5E4C39FFFE49EFE120088C3E49DFDD9 +:10010000E49CFC800312008830D507C3E49FFFE421 +:100110009EFE22E88FF0A4CC8BF0A42CFCE98EF09C +:10012000A42CFC8AF0EDA42CFCEA8EF0A4CDA8F05F +:100130008BF0A42DCC3825F0FDE98FF0A42CCD3523 +:10014000F0FCEB8EF0A4FEA9F0EB8FF0A4CFC5F08D +:100150002ECD39FEE43CFCEAA42DCE35F0FDE43C86 +:10016000FC2275F008758200EF2FFFEE33FECD33D1 +:10017000CDCC33CCC58233C5829BED9AEC99E58218 +:1001800098400CF582EE9BFEED9AFDEC99FC0FD5A4 +:10019000F0D6E4CEFBE4CDFAE4CCF9A88222B80094 +:1001A000C1B90059BA002DEC8BF084CFCECDFCE55F +:1001B000F0CBF97818EF2FFFEE33FEED33FDEC3383 +:1001C000FCEB33FB10D703994004EB99FB0FD8E508 +:1001D000E4F9FA227818EF2FFFEE33FEED33FDEC51 +:1001E00033FCC933C910D7059BE99A4007EC9BFC47 +:1001F000E99AF90FD8E0E4C9FAE4CCFB2275F010D3 +:10020000EF2FFFEE33FEED33FDCC33CCC833C810F7 +:10021000D7079BEC9AE899400AED9BFDEC9AFCE825 +:1002200099F80FD5F0DAE4CDFBE4CCFAE4C8F92272 +:10023000EF4E6012EF60010EEDBB010B89828A83E5 +:10024000F0A3DFFCDEFA2289F05007F709DFFCA9F2 +:10025000F022BBFEFCF309DFFCA9F022120998C2D0 +:1002600090C296D280E4FBFD7F10120A7030000528 +:100270001209BF800312006DD2AF1209318E438F75 +:1002800044E5447004E54364017003020339E51D4D +:1002900014602214700302032C146063146073242E +:1002A000046003020339E54464AA6003020339755C +:1002B0001D01020339E544F51C751D02E51C245A95 +:1002C000602214602414602B2407702C9000D374D7 +:1002D000C3F0A37450F0D296439104E59120E2FB61 +:1002E000C29680551209BF805012006DE49000D074 +:1002F000F08046751D038041E4F51CF51D803AE44D +:10030000F546E544F545E545D39400401A751D04CE +:100310008027748D2546F582E43400F583E544F0AA +:100320000546E546B54512751D02800DE544645548 +:100330007007F51D7FA0120A51E51C245860232484 +:1003400002600302027A9000D1E020E70302027A01 +:10035000547FF547FD7FA612089DE49000D1F0027E +:10036000027AE51D600302027A9000D0E060031279 +:10037000006D90008DE0FF12053E9000D7EFF0F485 +:10038000604F9000D57408F0E014F09000CD740137 +:10039000F09000CFF09000CDE0248DF582E43400A1 +:1003A000F583E0FF9000D5E0FEEFA806088002C3C9 +:1003B00013D8FC30E0059000CE80039000D6E07D9D +:1003C00000FCE4FF120A079000D7E0FF1207D1D229 +:1003D000DEE4F51C02027AAFE9AEEA7C007D0A1287 +:1003E00000768E218F2220930302052A8521238502 +:1003F0002224C3E5229526F52AE5219525F52990A5 +:1004000000D2E014700302049104600302053D90E1 +:1004100000D1E0600302053DE4F52BE52B75F00A01 +:10042000A4242F120911E5289DE5279C405AEF24AA +:10043000C8FFE43EFEC3E5289FE5279E504AE52B12 +:1004400075F00AA42431120911E52A9DE5299C4082 +:1004500037EF24C8FFE43EFEC3E52A9FE5299E50FE +:10046000279000D57408F0E49000CDF09000CFF014 +:10047000F52CF52DFE7F40FD7B017A00798D12026F +:10048000309000D27401F022052BE52B6402708BB2 +:10049000229000D5E014F09000CFE004F0D3E528DE +:1004A000952AE527952940081208EFE0C39F400FE1 +:1004B00012092040461208EF9000CFE0B5073CD269 +:1004C000909000CFE024FFFFE434FFFE7C007D0825 +:1004D0001200DD748D2FF58274003EF583C083C059 +:1004E00082E0FF9000D5E0FE7401A806088002C3F8 +:1004F00033D8FC4FD082D083F0800DC290120920F7 +:10050000400685272C85282D9000D5E070037408BF +:10051000F01208EF9000CFE0B507229000D1E52B54 +:10052000F04480F0C290E4A3F022852125852226A4 +:10053000C3E5229524F528E5219523F52722754862 +:10054000FFEFD3940050030205D7EF9480400302DD +:1005500005D7E4FEEE75F00AA4242EF8E6B50704EC +:100560008E4880040EBE02ECE548F4606A12092A47 +:100570002433F8E6FE08E6FBAA06E4F9F87F407E9D +:10058000427D0FFC12019EE47BFFFAF9F812011381 +:10059000A804A905AA06AB077F207ED77D757C013C +:1005A00012019EEFF404AF885388EFF58CEF5410DE +:1005B000428812092A24351208FBE49E9000CEEFEF +:1005C000F012092A24361208FB9000D6EFF043DA25 +:1005D0000153DBFE75F9FFAF4822120022787FE459 +:1005E000F6D8FD75814802062402025CE493A3F864 +:1005F000E493A34003F68001F208DFF48029E4933A +:10060000A3F85407240CC8C333C4540F4420C88330 +:100610004004F456800146F6DFE4800B0102040832 +:10062000102040809006EEE47E019360BCA3FF544E +:100630003F30E509541FFEE493A360010ECF54C080 +:1006400025E060A840B8E493A3FAE493A3F8E49308 +:10065000A3C8C582C8CAC583CAF0A3C8C582C8CA10 +:10066000C583CADFE9DEE780BEC0E0C0F0C083C05A +:1006700082C0D075D000C000C001C002C003C00459 +:10068000C005C006C007E5D85487F542F452D8E546 +:10069000F730E508E5F730E603120AB153F7DFE576 +:1006A0004230E708E5D930E00312005AE54230E075 +:1006B00008E5DA30E00312083BE54230E108E5DB0B +:1006C00030E0031203D7E54230E208E5DC30E00316 +:1006D000120AB2D007D006D005D004D003D002D081 +:1006E00001D000D0D0D082D083D0F0D0E032011D34 +:1006F00000011C00C100142E0112C005DC03E81E1D +:100700004628020BB8232805DC194B184100D100FC +:100710004100D2004200D300004100D0004100CE91 +:10072000564100D6AB4100D5004100CF004100CD7D +:10073000004100D70014080112C005DC03E81E4682 +:1007400028020BB8232805DC194B1841008B004107 +:10075000008C004100890041008A004100880000AF +:10076000C0E0C083C082C0D075D000C007E59854F7 +:1007700003FFF45298EF30E01B90008BE0B4440587 +:10078000120987800F90008B120971E599F0900093 +:100790008BE004F0EF30E12E90008CE0B4440512C1 +:1007A00009878022120967C39F500C12097CE0F56B +:1007B0009990008AE004F0120967B5070990008C4F +:1007C000E4F090008AF0D007D0D0D082D083D0E07F +:1007D0003253E2FD9000D3740BF0A374B8F0D280D2 +:1007E000439104E59120E2FBC2809000D3E4F0A3A2 +:1007F0007464F0439104E59120E2FBD280EF75F040 +:100800000AA4242FF8E6FD08E69000D3CDF0A3ED6E +:10081000F0439104E59120E2FBC280EF75F00AA459 +:100820002431F8E6FF08E69000D3CFF0A3EFF043C1 +:100830009104E59120E2FB43E202229000D5E070B2 +:100840000C9000CDE004F09000D57408F09000D733 +:10085000E01208F19000CFE0B5070302000390001A +:10086000CFE004F09000D5E014F09000CDE0248DAE +:10087000F582E43400F583E0FF9000D5E0FEEFA8B8 +:1008800006088002C313D8FC30E0059000CE800338 +:100890009000D6E07D00FCE4FF120A0722AE07E4D8 +:1008A000FCFB1209E7ED75F00AA42411F8E6FFEC51 +:1008B000C39F500774082CFC0B80EAEB04FF12095D +:1008C000EEED75F00AA42408F8E6FF1209EEE4FC48 +:1008D000ECC39B5012748D2CF582E43400F583E058 +:1008E000FF1209EE0C80E97F551209EE020AAEE50F +:1008F0002B75F00AA42437F8E6FF22F8E675F0FF1E +:10090000A4FFAEF07C007D64120088C374FF9FFFDB +:1009100022F8E6FE08E6FF2438FDEE34FFFCD32281 +:10092000D3E528952DE527952C22E54875F00AA4F6 +:100930002212098EB507057E017F002290008912E0 +:100940000971E0FD7C00900089E004F012098EB589 +:100950000706E4F090008BF0900088E0FEEE420481 +:10096000E4F0AE04AF052290008CE0FF90008AE036 +:1009700022E02400F582E43400F58322E02444F5EB +:1009800082E43400F583229000887402F022900003 +:100990008BE0FF900089E022120A79120A80120A85 +:1009A00087120A5C120AA3120A25120A3B120A666F +:1009B00012005E120A8E120A95120AA7020A9CAF52 +:1009C000885388EF758C0BEF54104288C2DE43DBEE +:1009D0000153DAFED2DEE49000D2F09000D1F09024 +:1009E00000D004F022AE077FAA1209EEAF069000F5 +:1009F0008CE0B4440312098790008C12097CEFF05C +:100A000090008CE004F022AB07AF04EB14600C14F0 +:100A1000600E2402700E8DFB8FFC228DE98FEA227E +:100A20008DEB8FEC22AF885388AF758C0B758D964C +:100A3000EF5440FEEF54104E428822E59154045387 +:100A400091FB7595FF7594FF7593FF7592864291A2 +:100A5000221209E57F551209EE020AAE75E34075D0 +:100A6000E10175E20222758E447589224388502285 +:100A700053984FEB4F4DF598227597DE7597AD2241 +:100A800075A41175D4CE2275A54175D5772253F77B +:100A90007F75DA4A2253F77F75DB302275E6907551 +:100AA000A89022E4F5A92243981022C2DE22D2990E +:030AB000222222DD +:00000001FF diff --git a/Keil 8051 v9.53 - Release/RF_Bridge.lnp b/Keil 8051 v9.53 - Release/RF_Bridge.lnp new file mode 100644 index 0000000..5aab2e5 --- /dev/null +++ b/Keil 8051 v9.53 - Release/RF_Bridge.lnp @@ -0,0 +1,8 @@ +"./lib/efm8bb1/peripheralDrivers/src/pca_0.OBJ", +"./lib/efm8bb1/peripheralDrivers/src/uart_0.OBJ", +"./src/InitDevice.OBJ", +"./src/RF_Bridge_main.OBJ", +"./src/RF_Handling.OBJ", +"./src/SILABS_STARTUP.OBJ", +"./src/uart.OBJ" +TO "RF_BRIDGE.OMF.CRBUILD" REMOVEUNUSED PRINT(.\RF_Bridge.m51) PAGEWIDTH (120) PAGELENGTH (65) CLASSES( CODE(C:0x0 - C:0x1ffe), CONST(C:0x0 - C:0x1ffe), ECODE(C:0x0 - C:0x1ffe), HCONST(C:0x0 - C:0x1ffe), XDATA(X:0x0 - X:0xff), HDATA(X:0x0 - X:0xff)) \ No newline at end of file diff --git a/Keil 8051 v9.53 - Release/RF_Bridge.m51 b/Keil 8051 v9.53 - Release/RF_Bridge.m51 new file mode 100644 index 0000000..d545e24 --- /dev/null +++ b/Keil 8051 v9.53 - Release/RF_Bridge.m51 @@ -0,0 +1,3036 @@ +LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 1 + + +LX51 LINKER/LOCATER V4.66.30.0, INVOKED BY: +C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\BIN\LX51.EXE ./lib/efm8bb1/peripheralDrivers/src/ +>> pca_0.OBJ, ./lib/efm8bb1/peripheralDrivers/src/uart_0.OBJ, ./src/InitDevice.OBJ, ./src/RF_Bridge_main.OBJ, ./src/RF_H +>> andling.OBJ, ./src/SILABS_STARTUP.OBJ, ./src/uart.OBJ TO RF_BRIDGE.OMF.CRBUILD REMOVEUNUSED PRINT (.\RF_Bridge.m51) P +>> AGEWIDTH (120) PAGELENGTH (65) CLASSES (CODE (C:0X0-C:0X1FFE), CONST (C:0X0-C:0X1FFE), ECODE (C:0X0-C:0X1FFE), HCONST +>> (C:0X0-C:0X1FFE), XDATA (X:0X0-X:0XFF), HDATA (X:0X0-X:0XFF)) + + +CPU MODE: 8051 MODE +MEMORY MODEL: SMALL + + +INPUT MODULES INCLUDED: + ./lib/efm8bb1/peripheralDrivers/src/pca_0.OBJ (PCA_0) + COMMENT TYPE 0: C51 V9.53.0.0 + ./lib/efm8bb1/peripheralDrivers/src/uart_0.OBJ (UART_0) + COMMENT TYPE 0: C51 V9.53.0.0 + ./src/InitDevice.OBJ (INITDEVICE) + COMMENT TYPE 0: C51 V9.53.0.0 + ./src/RF_Bridge_main.OBJ (RF_BRIDGE_MAIN) + COMMENT TYPE 0: C51 V9.53.0.0 + ./src/RF_Handling.OBJ (RF_HANDLING) + COMMENT TYPE 0: C51 V9.53.0.0 + ./src/SILABS_STARTUP.OBJ (?C_STARTUP) + COMMENT TYPE 0: AX51 V3.12.0.0 + ./src/uart.OBJ (UART) + COMMENT TYPE 0: C51 V9.53.0.0 + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C_INIT) + COMMENT TYPE 1: A51 / ASM51 Assembler + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C?IMUL) + COMMENT TYPE 1: A51 / ASM51 Assembler + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C?UIDIV) + COMMENT TYPE 1: A51 / ASM51 Assembler + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C?SIDIV) + COMMENT TYPE 1: A51 / ASM51 Assembler + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C?LMUL) + COMMENT TYPE 1: A51 / ASM51 Assembler + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C?ULDIV) + COMMENT TYPE 1: A51 / ASM51 Assembler + C:\SILICONLABS\SIMPLICITYSTUDIO\V4\DEVELOPER\TOOLCHAINS\KEIL_8051\9.53\LIB\C51S.LIB (?C?MEMSET) + COMMENT TYPE 1: A51 / ASM51 Assembler + + +ACTIVE MEMORY CLASSES OF MODULE: RF_BRIDGE.OMF.CRBUILD (PCA_0) + +BASE START END USED MEMORY CLASS +========================================================== +C:000000H C:000000H C:001FFEH 000AB3H CODE +C:000000H C:000000H C:001FFEH CONST +C:000000H C:000000H C:001FFEH ECODE +B00:0000H C:000000H C:001FFEH HCONST +X:000000H X:000000H X:0000FFH 0000D8H XDATA +X:000000H X:000000H X:0000FFH HDATA +I:000020H.0 I:000020H.0 I:00002FH.7 000000H.1 BIT +I:000000H I:000000H I:00007FH 000046H DATA +I:000000H I:000000H I:0000FFH 000001H IDATA + + +MEMORY MAP OF MODULE: RF_BRIDGE.OMF.CRBUILD (PCA_0) + + +START STOP LENGTH ALIGN RELOC MEMORY CLASS SEGMENT NAME +========================================================================= + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 2 + + + +* * * * * * * * * * * D A T A M E M O R Y * * * * * * * * * * * * * +000000H 000007H 000008H --- AT.. DATA "REG BANK 0" +000008H 00001BH 000014H BYTE UNIT DATA ?DT?UART +00001CH 00001DH 000002H BYTE UNIT DATA ?DT?RF_BRIDGE_MAIN +00001EH.0 00001FH.7 000002H.0 --- --- **GAP** +000020H.0 000020H.0 000000H.1 BIT UNIT BIT ?BI?RF_BRIDGE_MAIN +000020H.1 000020H 000000H.7 --- --- **GAP** +000021H 000041H 000021H BYTE UNIT DATA ?DT?RF_HANDLING +000042H 000048H 000007H BYTE UNIT DATA _DATA_GROUP_ +000049H 000049H 000001H BYTE UNIT IDATA ?STACK + +* * * * * * * * * * * C O D E M E M O R Y * * * * * * * * * * * * * +000000H 000002H 000003H --- OFFS.. CODE ?CO?SILABS_STARTUP?3 +000003H 000021H 00001FH BYTE UNIT CODE ?PR?PCA0_STOPTRANSMIT?RF_HANDLING +000022H 000022H 000001H BYTE UNIT CODE ?PR?SILABS_STARTUP?RF_BRIDGE_MAIN +000023H 000025H 000003H BYTE OFFS.. CODE ?UART?00023 +000026H 000059H 000034H BYTE UNIT CODE ?PR?TIMER3_ISR?RF_HANDLING +00005AH 00005AH 000001H BYTE UNIT CODE ?PR?PCA0_OVERFLOWCB?RF_HANDLING +00005BH 00005DH 000003H BYTE OFFS.. CODE ?PCA_0?0005B +00005EH 00006CH 00000FH BYTE UNIT CODE ?PR?PCA_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +00006DH 000072H 000006H BYTE UNIT CODE ?PR?PCA0_STOPSNIFFING?RF_HANDLING +000073H 000075H 000003H BYTE OFFS.. CODE ?RF_HANDLING?00073 +000076H 00025BH 0001E6H BYTE UNIT CODE ?C?LIB_CODE +00025CH 0003D6H 00017BH BYTE UNIT CODE ?PR?MAIN?RF_BRIDGE_MAIN +0003D7H 00053DH 000167H BYTE UNIT CODE ?PR?PCA0_CHANNEL1EVENTCB?RF_HANDLING +00053EH 0005D9H 00009CH BYTE UNIT CODE ?PR?_PCA0_DOTRANSMIT?RF_HANDLING +0005DAH 000668H 00008FH BYTE UNIT CODE ?C_C51STARTUP +000669H 0006EDH 000085H BYTE UNIT CODE ?PR?PCA0_ISR?PCA_0 +0006EEH 00075FH 000072H BYTE UNIT CODE ?C_INITSEG +000760H 0007D0H 000071H BYTE UNIT CODE ?PR?UART0_ISR?UART +0007D1H 00083AH 00006AH BYTE UNIT CODE ?PR?_SENDRF_SYNC?RF_HANDLING +00083BH 00089CH 000062H BYTE UNIT CODE ?PR?PCA0_CHANNEL0EVENTCB?RF_HANDLING +00089DH 0008EEH 000052H BYTE UNIT CODE ?PR?_UART_PUT_RF_DATA?UART +0008EFH 000930H 000042H BYTE UNIT CODE ?PR?RF_HANDLING +000931H 000966H 000036H BYTE UNIT CODE ?PR?UART_GETC?UART +000967H 000997H 000031H BYTE UNIT CODE ?PR?UART +000998H 0009BEH 000027H BYTE UNIT CODE ?PR?ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +0009BFH 0009E4H 000026H BYTE UNIT CODE ?PR?PCA0_DOSNIFFING?RF_HANDLING +0009E5H 000A06H 000022H BYTE UNIT CODE ?PR?_UART_PUTC?UART +000A07H 000A24H 00001EH BYTE UNIT CODE ?PR?_PCA0_WRITECHANNEL?PCA_0 +000A25H 000A3AH 000016H BYTE UNIT CODE ?PR?TIMER01_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A3BH 000A50H 000016H BYTE UNIT CODE ?PR?TIMER16_3_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A51H 000A5BH 00000BH BYTE UNIT CODE ?PR?_UART_PUT_COMMAND?UART +000A5CH 000A65H 00000AH BYTE UNIT CODE ?PR?PBCFG_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A66H 000A6FH 00000AH BYTE UNIT CODE ?PR?TIMER_SETUP_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A70H 000A78H 000009H BYTE UNIT CODE ?PR?_UART0_INIT?UART_0 +000A79H 000A7FH 000007H BYTE UNIT CODE ?PR?WDT_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A80H 000A86H 000007H BYTE UNIT CODE ?PR?PORTS_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A87H 000A8DH 000007H BYTE UNIT CODE ?PR?PORTS_1_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A8EH 000A94H 000007H BYTE UNIT CODE ?PR?PCACH_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A95H 000A9BH 000007H BYTE UNIT CODE ?PR?PCACH_1_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000A9CH 000AA2H 000007H BYTE UNIT CODE ?PR?INTERRUPT_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000AA3H 000AA6H 000004H BYTE UNIT CODE ?PR?CLOCK_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000AA7H 000AAAH 000004H BYTE UNIT CODE ?PR?UART_0_ENTER_DEFAULTMODE_FROM_RESET?INITDEVICE +000AABH 000AADH 000003H BYTE UNIT CODE ?PR?PCA0_HALT?PCA_0 +000AAEH 000AB0H 000003H BYTE UNIT CODE ?PR?UART0_INITTXPOLLING?UART_0 +000AB1H 000AB1H 000001H BYTE UNIT CODE ?PR?PCA0_INTERMEDIATEOVERFLOWCB?RF_HANDLING +000AB2H 000AB2H 000001H BYTE UNIT CODE ?PR?PCA0_CHANNEL2EVENTCB?RF_HANDLING + +* * * * * * * * * * * X D A T A M E M O R Y * * * * * * * * * * * * * +000000H 00008CH 00008DH BYTE UNIT XDATA ?XD?UART + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 3 + + +00008DH 0000D7H 00004BH BYTE UNIT XDATA ?XD?RF_HANDLING + +* * * * * * * * * R E M O V E D S E G M E N T S * * * * * * * * + *DEL*: 00000CH BYTE UNIT CODE ?PR?PCA0_GETINTFLAGS?PCA_0 + *DEL*: 00000DH BYTE UNIT CODE ?PR?_PCA0_CLEARINTFLAG?PCA_0 + *DEL*: 00003DH BYTE UNIT CODE ?PR?_PCA0_ENABLEINT?PCA_0 + *DEL*: 000000H.1 BIT UNIT BIT ?BI?_PCA0_ENABLEINT?PCA_0 + *DEL*: 00001EH BYTE UNIT CODE ?PR?_PCA0_READCHANNEL?PCA_0 + *DEL*: 00000FH BYTE UNIT CODE ?PR?PCA0_READCOUNTER?PCA_0 + *DEL*: 000005H BYTE UNIT CODE ?PR?_PCA0_WRITECOUNTER?PCA_0 + *DEL*: 000003H BYTE UNIT CODE ?PR?PCA0_RUN?PCA_0 + *DEL*: 000008H BYTE UNIT CODE ?PR?_PCA0_INIT?PCA_0 + *DEL*: 00006FH BYTE UNIT CODE ?PR?_PCA0_INITCHANNEL?PCA_0 + *DEL*: 00001DH BYTE UNIT CODE ?PR?PCA0_RESET?PCA_0 + *DEL*: 000001H BYTE UNIT DATA ?DT?PCA0_RESET?PCA_0 + *DEL*: 000033H BYTE UNIT CODE ?PR?_PCA0_RESETCHANNEL?PCA_0 + *DEL*: 000006H BYTE UNIT CODE ?PR?UART0_GETINTFLAGS?UART_0 + *DEL*: 000005H BYTE UNIT CODE ?PR?_UART0_CLEARINTFLAG?UART_0 + *DEL*: 000003H BYTE UNIT CODE ?PR?_UART0_WRITE?UART_0 + *DEL*: 000003H BYTE UNIT CODE ?PR?UART0_READ?UART_0 + *DEL*: 00000CH BYTE UNIT CODE ?PR?_UART0_WRITEWITHEXTRABIT?UART_0 + *DEL*: 000011H BYTE UNIT CODE ?PR?UART0_READWITHEXTRABIT?UART_0 + *DEL*: 000004H BYTE UNIT CODE ?PR?UART0_RESET?UART_0 + *DEL*: 000001H BYTE UNIT CODE ?PR?UART0_RECEIVECOMPLETECB?UART + *DEL*: 000001H BYTE UNIT CODE ?PR?UART0_TRANSMITCOMPLETECB?UART + *DEL*: 000012H BYTE UNIT CODE ?PR?UART_BUFFER_RESET?UART + *DEL*: 00000DH BYTE UNIT CODE ?PR?UART_GETLEN?UART + *DEL*: 00000BH BYTE UNIT CODE ?PR?UART_TRANSFER_FINISHED?UART + *DEL*: 000015H BYTE UNIT CODE ?PR?_UART_PUT_UINT16_T?UART + + + +OVERLAY MAP OF MODULE: RF_BRIDGE.OMF.CRBUILD (PCA_0) + + +FUNCTION/MODULE BIT_GROUP DATA_GROUP +--> CALLED FUNCTION/MODULE START STOP START STOP +====================================================================== +PCA0_ISR/PCA_0 ----- ----- 0042H 0042H + +--> PCA0_INTERMEDIATEOVERFLOWCB/RF_HANDLING + +--> PCA0_OVERFLOWCB/RF_HANDLING + +--> PCA0_CHANNEL0EVENTCB/RF_HANDLING + +--> PCA0_CHANNEL1EVENTCB/RF_HANDLING + +--> PCA0_CHANNEL2EVENTCB/RF_HANDLING + +PCA0_INTERMEDIATEOVERFLOWCB/RF_HANDLING ----- ----- ----- ----- + +PCA0_OVERFLOWCB/RF_HANDLING ----- ----- ----- ----- + +PCA0_CHANNEL0EVENTCB/RF_HANDLING ----- ----- ----- ----- + +--> RF_HANDLING + +--> PCA0_STOPTRANSMIT/RF_HANDLING + +--> _PCA0_WRITECHANNEL/PCA_0 + +RF_HANDLING ----- ----- ----- ----- + +PCA0_STOPTRANSMIT/RF_HANDLING ----- ----- ----- ----- + +--> _PCA0_WRITECHANNEL/PCA_0 + +--> PCA0_HALT/PCA_0 + +--> PCA0_DOSNIFFING/RF_HANDLING + +_PCA0_WRITECHANNEL/PCA_0 ----- ----- ----- ----- + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 4 + + + +PCA0_HALT/PCA_0 ----- ----- ----- ----- + +PCA0_DOSNIFFING/RF_HANDLING ----- ----- ----- ----- + +PCA0_CHANNEL1EVENTCB/RF_HANDLING ----- ----- ----- ----- + +--> RF_HANDLING + +PCA0_CHANNEL2EVENTCB/RF_HANDLING ----- ----- ----- ----- + +*** NEW ROOT ******************************** + +TIMER3_ISR/RF_HANDLING ----- ----- ----- ----- + +*** NEW ROOT ******************************** + +?C_C51STARTUP ----- ----- ----- ----- + +--> SILABS_STARTUP/RF_BRIDGE_MAIN + +--> MAIN/RF_BRIDGE_MAIN + +--> ?C_INITSEG + +SILABS_STARTUP/RF_BRIDGE_MAIN ----- ----- ----- ----- + +MAIN/RF_BRIDGE_MAIN ----- ----- 0043H 0047H + +--> ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> _UART0_INIT/UART_0 + +--> PCA0_DOSNIFFING/RF_HANDLING + +--> PCA0_STOPSNIFFING/RF_HANDLING + +--> UART_GETC/UART + +--> _UART_PUT_COMMAND/UART + +--> _UART_PUT_RF_DATA/UART + +--> _PCA0_DOTRANSMIT/RF_HANDLING + +--> _PCA0_WRITECHANNEL/PCA_0 + +--> _SENDRF_SYNC/RF_HANDLING + +ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE ----- ----- ----- ----- + +--> WDT_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> PORTS_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> PORTS_1_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> PBCFG_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> CLOCK_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> TIMER01_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> TIMER16_3_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> TIMER_SETUP_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> PCA_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> PCACH_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> PCACH_1_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> UART_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +--> INTERRUPT_0_ENTER_DEFAULTMODE_FROM_RESET/INITDEVICE + +WDT_0_ENTER_DEFAULTMODE_FROM_RESET/INITD+ ----- ----- ----- ----- +... EVICE + +PORTS_0_ENTER_DEFAULTMODE_FROM_RESET/INI+ ----- ----- ----- ----- +... TDEVICE + +PORTS_1_ENTER_DEFAULTMODE_FROM_RESET/INI+ ----- ----- ----- ----- +... TDEVICE + +PBCFG_0_ENTER_DEFAULTMODE_FROM_RESET/INI+ ----- ----- ----- ----- +... TDEVICE + + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 5 + + +CLOCK_0_ENTER_DEFAULTMODE_FROM_RESET/INI+ ----- ----- ----- ----- +... TDEVICE + +TIMER01_0_ENTER_DEFAULTMODE_FROM_RESET/I+ ----- ----- ----- ----- +... NITDEVICE + +TIMER16_3_ENTER_DEFAULTMODE_FROM_RESET/I+ ----- ----- ----- ----- +... NITDEVICE + +TIMER_SETUP_0_ENTER_DEFAULTMODE_FROM_RES+ ----- ----- ----- ----- +... ET/INITDEVICE + +PCA_0_ENTER_DEFAULTMODE_FROM_RESET/INITD+ ----- ----- ----- ----- +... EVICE + +PCACH_0_ENTER_DEFAULTMODE_FROM_RESET/INI+ ----- ----- ----- ----- +... TDEVICE + +PCACH_1_ENTER_DEFAULTMODE_FROM_RESET/INI+ ----- ----- ----- ----- +... TDEVICE + +UART_0_ENTER_DEFAULTMODE_FROM_RESET/INIT+ ----- ----- ----- ----- +... DEVICE + +INTERRUPT_0_ENTER_DEFAULTMODE_FROM_RESET+ ----- ----- ----- ----- +... /INITDEVICE + +_UART0_INIT/UART_0 ----- ----- ----- ----- + +PCA0_STOPSNIFFING/RF_HANDLING ----- ----- ----- ----- + +UART_GETC/UART ----- ----- ----- ----- + +--> UART + +UART ----- ----- ----- ----- + +_UART_PUT_COMMAND/UART ----- ----- ----- ----- + +--> _UART_PUTC/UART + +--> UART0_INITTXPOLLING/UART_0 + +_UART_PUTC/UART ----- ----- ----- ----- + +--> UART + +UART0_INITTXPOLLING/UART_0 ----- ----- ----- ----- + +_UART_PUT_RF_DATA/UART ----- ----- ----- ----- + +--> _UART_PUTC/UART + +--> UART0_INITTXPOLLING/UART_0 + +_PCA0_DOTRANSMIT/RF_HANDLING ----- ----- 0048H 0048H + +--> RF_HANDLING + +_SENDRF_SYNC/RF_HANDLING ----- ----- ----- ----- + +?C_INITSEG ----- ----- ----- ----- + +*** NEW ROOT ******************************** + +UART0_ISR/UART ----- ----- ----- ----- + +--> UART + + + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 6 + + + +PUBLIC SYMBOLS OF MODULE: RF_BRIDGE.OMF.CRBUILD (PCA_0) + + + VALUE CLASS TYPE PUBLIC SYMBOL NAME + ================================================= +*DEL*:00000000H.0 BIT BIT ?_PCA0_enableInt?BIT + 00000000H NUMBER --- ?C?CODESEG + 01000076H CODE --- ?C?IMUL + 01000113H CODE --- ?C?LMUL + 01000230H CODE --- ?C?MEMSET + 010000DDH CODE --- ?C?SIDIV + 01000088H CODE --- ?C?UIDIV + 0100019EH CODE --- ?C?ULDIV + 00000000H NUMBER --- ?C?XDATASEG + 01000624H CODE --- ?C_START + 01000000H CODE NEAR LAB ?C_STARTUP +*DEL*:00000000H CODE --- _PCA0_clearIntFlag + 0100053EH CODE --- _PCA0_DoTransmit +*DEL*:00000000H CODE --- _PCA0_enableInt +*DEL*:00000000H CODE --- _PCA0_init +*DEL*:00000000H CODE --- _PCA0_initChannel +*DEL*:00000000H CODE --- _PCA0_readChannel +*DEL*:00000000H CODE --- _PCA0_resetChannel + 01000A07H CODE --- _PCA0_writeChannel +*DEL*:00000000H CODE --- _PCA0_writeCounter + 010007D1H CODE --- _SendRF_SYNC +*DEL*:00000000H CODE --- _UART0_clearIntFlag + 01000A70H CODE --- _UART0_init +*DEL*:00000000H CODE --- _UART0_write +*DEL*:00000000H CODE --- _UART0_writeWithExtraBit + 01000A51H CODE --- _uart_put_command + 0100089DH CODE --- _uart_put_RF_Data +*DEL*:00000000H CODE --- _uart_put_uint16_t + 010009EEH CODE --- _uart_putc +*SFR* 000000E0H DATA BYTE ACC +*SFR* 000000E0H DATA BIT ACC_ACC0 +*SFR* 000000E0H.1 DATA BIT ACC_ACC1 +*SFR* 000000E0H.2 DATA BIT ACC_ACC2 +*SFR* 000000E0H.3 DATA BIT ACC_ACC3 +*SFR* 000000E0H.4 DATA BIT ACC_ACC4 +*SFR* 000000E0H.5 DATA BIT ACC_ACC5 +*SFR* 000000E0H.6 DATA BIT ACC_ACC6 +*SFR* 000000E0H.7 DATA BIT ACC_ACC7 + 020000CFH XDATA BYTE actual_bit + 020000D5H XDATA BYTE actual_bit_of_byte + 020000CDH XDATA BYTE actual_byte +*SFR* 000000BDH DATA WORD ADC0 +*SFR* 000000B3H DATA BYTE ADC0AC +*SFR* 000000BCH DATA BYTE ADC0CF +*SFR* 000000E8H DATA BYTE ADC0CN0 +*SFR* 000000E8H.6 DATA BIT ADC0CN0_ADBMEN +*SFR* 000000E8H.4 DATA BIT ADC0CN0_ADBUSY +*SFR* 000000E8H DATA BIT ADC0CN0_ADCM0 +*SFR* 000000E8H.1 DATA BIT ADC0CN0_ADCM1 +*SFR* 000000E8H.2 DATA BIT ADC0CN0_ADCM2 +*SFR* 000000E8H.7 DATA BIT ADC0CN0_ADEN +*SFR* 000000E8H.5 DATA BIT ADC0CN0_ADINT +*SFR* 000000E8H.3 DATA BIT ADC0CN0_ADWINT +*SFR* 000000B2H DATA BYTE ADC0CN1 +*SFR* 000000C3H DATA WORD ADC0GT +*SFR* 000000C4H DATA BYTE ADC0GTH + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 7 + + +*SFR* 000000C3H DATA BYTE ADC0GTL +*SFR* 000000BEH DATA BYTE ADC0H +*SFR* 000000BDH DATA BYTE ADC0L +*SFR* 000000C5H DATA WORD ADC0LT +*SFR* 000000C6H DATA BYTE ADC0LTH +*SFR* 000000C5H DATA BYTE ADC0LTL +*SFR* 000000BBH DATA BYTE ADC0MX +*SFR* 000000DFH DATA BYTE ADC0PWR +*SFR* 000000B9H DATA BYTE ADC0TK +*SFR* 000000F0H DATA BYTE B +*SFR* 000000F0H DATA BIT B_B0 +*SFR* 000000F0H.1 DATA BIT B_B1 +*SFR* 000000F0H.2 DATA BIT B_B2 +*SFR* 000000F0H.3 DATA BIT B_B3 +*SFR* 000000F0H.4 DATA BIT B_B4 +*SFR* 000000F0H.5 DATA BIT B_B5 +*SFR* 000000F0H.6 DATA BIT B_B6 +*SFR* 000000F0H.7 DATA BIT B_B7 +*SFR* 00000090H.6 DATA BIT BUZZER +*SFR* 0000008EH DATA BYTE CKCON0 +*SFR* 000000A9H DATA BYTE CLKSEL + 01000AA3H CODE --- CLOCK_0_enter_DefaultMode_from_RESET +*SFR* 0000009BH DATA BYTE CMP0CN0 +*SFR* 0000009DH DATA BYTE CMP0MD +*SFR* 0000009FH DATA BYTE CMP0MX +*SFR* 000000BFH DATA BYTE CMP1CN0 +*SFR* 000000ABH DATA BYTE CMP1MD +*SFR* 000000AAH DATA BYTE CMP1MX +*SFR* 000000D2H DATA BYTE CRC0AUTO +*SFR* 000000CEH DATA BYTE CRC0CN0 +*SFR* 000000D3H DATA BYTE CRC0CNT +*SFR* 000000DEH DATA BYTE CRC0DAT +*SFR* 000000CFH DATA BYTE CRC0FLIP +*SFR* 000000DDH DATA BYTE CRC0IN +*SFR* 000000ADH DATA BYTE DERIVID +*SFR* 000000B5H DATA BYTE DEVICEID +*SFR* 00000082H DATA WORD DP +*SFR* 00000083H DATA BYTE DPH +*SFR* 00000082H DATA BYTE DPL + 020000CEH XDATA BYTE DUTY_CYCLE_HIGH + 020000D6H XDATA BYTE DUTY_CYLCE_LOW +*SFR* 000000E6H DATA BYTE EIE1 +*SFR* 000000F3H DATA BYTE EIP1 + 01000998H CODE --- enter_DefaultMode_from_RESET +*SFR* 000000B7H DATA BYTE FLKEY +*SFR* 000000C7H DATA BYTE HFO0CAL +*SFR* 000000A8H DATA BYTE IE +*SFR* 000000A8H.7 DATA BIT IE_EA +*SFR* 000000A8H.4 DATA BIT IE_ES0 +*SFR* 000000A8H.6 DATA BIT IE_ESPI0 +*SFR* 000000A8H.1 DATA BIT IE_ET0 +*SFR* 000000A8H.3 DATA BIT IE_ET1 +*SFR* 000000A8H.5 DATA BIT IE_ET2 +*SFR* 000000A8H DATA BIT IE_EX0 +*SFR* 000000A8H.2 DATA BIT IE_EX1 + 01000A9CH CODE --- INTERRUPT_0_enter_DefaultMode_from_RESET +*SFR* 000000B8H DATA BYTE IP +*SFR* 000000B8H.4 DATA BIT IP_PS0 +*SFR* 000000B8H.6 DATA BIT IP_PSPI0 +*SFR* 000000B8H.1 DATA BIT IP_PT0 +*SFR* 000000B8H.3 DATA BIT IP_PT1 +*SFR* 000000B8H.5 DATA BIT IP_PT2 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 8 + + +*SFR* 000000B8H DATA BIT IP_PX0 +*SFR* 000000B8H.2 DATA BIT IP_PX1 +*SFR* 000000E4H DATA BYTE IT01CF +*SFR* 00000090H DATA BIT LED +*SFR* 000000B1H DATA BYTE LFO0CN + 0100025CH CODE --- main +*SFR* 00000080H DATA BYTE P0 +*SFR* 00000080H DATA BIT P0_B0 +*SFR* 00000080H.1 DATA BIT P0_B1 +*SFR* 00000080H.2 DATA BIT P0_B2 +*SFR* 00000080H.3 DATA BIT P0_B3 +*SFR* 00000080H.4 DATA BIT P0_B4 +*SFR* 00000080H.5 DATA BIT P0_B5 +*SFR* 00000080H.6 DATA BIT P0_B6 +*SFR* 00000080H.7 DATA BIT P0_B7 +*SFR* 000000FEH DATA BYTE P0MASK +*SFR* 000000FDH DATA BYTE P0MAT +*SFR* 000000F1H DATA BYTE P0MDIN +*SFR* 000000A4H DATA BYTE P0MDOUT +*SFR* 000000D4H DATA BYTE P0SKIP +*SFR* 00000090H DATA BYTE P1 +*SFR* 00000090H DATA BIT P1_B0 +*SFR* 00000090H.1 DATA BIT P1_B1 +*SFR* 00000090H.2 DATA BIT P1_B2 +*SFR* 00000090H.3 DATA BIT P1_B3 +*SFR* 00000090H.4 DATA BIT P1_B4 +*SFR* 00000090H.5 DATA BIT P1_B5 +*SFR* 00000090H.6 DATA BIT P1_B6 +*SFR* 00000090H.7 DATA BIT P1_B7 +*SFR* 000000EEH DATA BYTE P1MASK +*SFR* 000000EDH DATA BYTE P1MAT +*SFR* 000000F2H DATA BYTE P1MDIN +*SFR* 000000A5H DATA BYTE P1MDOUT +*SFR* 000000D5H DATA BYTE P1SKIP +*SFR* 000000A0H DATA BYTE P2 +*SFR* 000000A0H DATA BIT P2_B0 +*SFR* 000000A0H.1 DATA BIT P2_B1 +*SFR* 000000A6H DATA BYTE P2MDOUT + 01000A5CH CODE --- PBCFG_0_enter_DefaultMode_from_RESET +*SFR* 000000F9H DATA WORD PCA0 + 0100083BH CODE --- PCA0_channel0EventCb + 010003D7H CODE --- PCA0_channel1EventCb + 01000AB2H CODE --- PCA0_channel2EventCb + 010009BFH CODE --- PCA0_DoSniffing +*DEL*:00000000H CODE --- PCA0_getIntFlags + 01000AABH CODE --- PCA0_halt + 01000AB1H CODE --- PCA0_intermediateOverflowCb + 01000669H CODE --- PCA0_ISR + 0100005AH CODE --- PCA0_overflowCb +*DEL*:00000000H CODE --- PCA0_readCounter +*DEL*:00000000H CODE --- PCA0_reset +*DEL*:00000000H CODE --- PCA0_run + 0100006DH CODE --- PCA0_StopSniffing + 01000003H CODE --- PCA0_StopTransmit +*SFR* 0000009EH DATA BYTE PCA0CENT +*SFR* 0000009CH DATA BYTE PCA0CLR +*SFR* 000000D8H DATA BYTE PCA0CN0 +*SFR* 000000D8H DATA BIT PCA0CN0_CCF0 +*SFR* 000000D8H.1 DATA BIT PCA0CN0_CCF1 +*SFR* 000000D8H.2 DATA BIT PCA0CN0_CCF2 +*SFR* 000000D8H.7 DATA BIT PCA0CN0_CF +*SFR* 000000D8H.6 DATA BIT PCA0CN0_CR + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 9 + + +*SFR* 000000FBH DATA WORD PCA0CP0 +*SFR* 000000E9H DATA WORD PCA0CP1 +*SFR* 000000EBH DATA WORD PCA0CP2 +*SFR* 000000FCH DATA BYTE PCA0CPH0 +*SFR* 000000EAH DATA BYTE PCA0CPH1 +*SFR* 000000ECH DATA BYTE PCA0CPH2 +*SFR* 000000FBH DATA BYTE PCA0CPL0 +*SFR* 000000E9H DATA BYTE PCA0CPL1 +*SFR* 000000EBH DATA BYTE PCA0CPL2 +*SFR* 000000DAH DATA BYTE PCA0CPM0 +*SFR* 000000DBH DATA BYTE PCA0CPM1 +*SFR* 000000DCH DATA BYTE PCA0CPM2 +*SFR* 000000FAH DATA BYTE PCA0H +*SFR* 000000F9H DATA BYTE PCA0L +*SFR* 000000D9H DATA BYTE PCA0MD +*SFR* 00000096H DATA BYTE PCA0POL +*SFR* 000000F7H DATA BYTE PCA0PWM + 0100005EH CODE --- PCA_0_enter_DefaultMode_from_RESET + 01000A8EH CODE --- PCACH_0_enter_DefaultMode_from_RESET + 01000A95H CODE --- PCACH_1_enter_DefaultMode_from_RESET +*SFR* 00000087H DATA BYTE PCON0 + 01000A80H CODE --- PORTS_0_enter_DefaultMode_from_RESET + 01000A87H CODE --- PORTS_1_enter_DefaultMode_from_RESET +*SFR* 000000A0H DATA BYTE PPAGE_SFR + 020000D7H XDATA BYTE protocol_index +*SFR* 000000F6H DATA BYTE PRTDRV +*SFR* 0000008FH DATA BYTE PSCTL +*SFR* 000000D0H DATA BYTE PSW +*SFR* 000000D0H.6 DATA BIT PSW_AC +*SFR* 000000D0H.7 DATA BIT PSW_CY +*SFR* 000000D0H.5 DATA BIT PSW_F0 +*SFR* 000000D0H.1 DATA BIT PSW_F1 +*SFR* 000000D0H.2 DATA BIT PSW_OV +*SFR* 000000D0H DATA BIT PSW_PARITY +*SFR* 000000D0H.3 DATA BIT PSW_RS0 +*SFR* 000000D0H.4 DATA BIT PSW_RS1 +*SFR* 00000090H.3 DATA BIT R_DATA +*SFR* 000000D1H DATA BYTE REF0CN +*SFR* 000000C9H DATA BYTE REG0CN +*SFR* 000000B6H DATA BYTE REVID + 0200008DH XDATA --- RF_DATA + 020000D1H XDATA BYTE RF_DATA_STATUS + 020000D2H XDATA BYTE rf_state +*SFR* 000000EFH DATA BYTE RSTSRC +*SFR* 00000099H DATA BYTE SBUF0 +*SFR* 00000098H DATA BYTE SCON0 +*SFR* 00000098H.5 DATA BIT SCON0_MCE +*SFR* 00000098H.2 DATA BIT SCON0_RB8 +*SFR* 00000098H.4 DATA BIT SCON0_REN +*SFR* 00000098H DATA BIT SCON0_RI +*SFR* 00000098H.7 DATA BIT SCON0_SMODE +*SFR* 00000098H.3 DATA BIT SCON0_TB8 +*SFR* 00000098H.1 DATA BIT SCON0_TI + 01000022H CODE --- SiLabs_Startup +*SFR* 000000D6H DATA BYTE SMB0ADM +*SFR* 000000D7H DATA BYTE SMB0ADR +*SFR* 000000C1H DATA BYTE SMB0CF +*SFR* 000000C0H DATA BYTE SMB0CN0 +*SFR* 000000C0H.1 DATA BIT SMB0CN0_ACK +*SFR* 000000C0H.3 DATA BIT SMB0CN0_ACKRQ +*SFR* 000000C0H.2 DATA BIT SMB0CN0_ARBLOST +*SFR* 000000C0H.7 DATA BIT SMB0CN0_MASTER + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 10 + + +*SFR* 000000C0H DATA BIT SMB0CN0_SI +*SFR* 000000C0H.5 DATA BIT SMB0CN0_STA +*SFR* 000000C0H.4 DATA BIT SMB0CN0_STO +*SFR* 000000C0H.6 DATA BIT SMB0CN0_TXMODE +*SFR* 000000C2H DATA BYTE SMB0DAT +*SFR* 000000ACH DATA BYTE SMB0TC + 00000020H.0 BIT BIT Sniffing + 020000D0H XDATA BYTE sniffing_is_on +*SFR* 00000081H DATA BYTE SP +*SFR* 000000A1H DATA BYTE SPI0CFG +*SFR* 000000A2H DATA BYTE SPI0CKR +*SFR* 000000F8H DATA BYTE SPI0CN0 +*SFR* 000000F8H.5 DATA BIT SPI0CN0_MODF +*SFR* 000000F8H.2 DATA BIT SPI0CN0_NSSMD0 +*SFR* 000000F8H.3 DATA BIT SPI0CN0_NSSMD1 +*SFR* 000000F8H.4 DATA BIT SPI0CN0_RXOVRN +*SFR* 000000F8H DATA BIT SPI0CN0_SPIEN +*SFR* 000000F8H.7 DATA BIT SPI0CN0_SPIF +*SFR* 000000F8H.1 DATA BIT SPI0CN0_TXBMT +*SFR* 000000F8H.6 DATA BIT SPI0CN0_WCOL +*SFR* 000000A3H DATA BYTE SPI0DAT +*SFR* 00000080H DATA BIT T_DATA +*SFR* 00000088H DATA BYTE TCON +*SFR* 00000088H.1 DATA BIT TCON_IE0 +*SFR* 00000088H.3 DATA BIT TCON_IE1 +*SFR* 00000088H DATA BIT TCON_IT0 +*SFR* 00000088H.2 DATA BIT TCON_IT1 +*SFR* 00000088H.5 DATA BIT TCON_TF0 +*SFR* 00000088H.7 DATA BIT TCON_TF1 +*SFR* 00000088H.4 DATA BIT TCON_TR0 +*SFR* 00000088H.6 DATA BIT TCON_TR1 +*SFR* 0000008CH DATA BYTE TH0 +*SFR* 0000008DH DATA BYTE TH1 + 01000A25H CODE --- TIMER01_0_enter_DefaultMode_from_RESET + 01000A3BH CODE --- TIMER16_3_enter_DefaultMode_from_RESET + 01000026H CODE --- TIMER3_ISR + 020000D3H XDATA WORD Timer_3_Timeout + 01000A66H CODE --- TIMER_SETUP_0_enter_DefaultMode_from_RESET +*SFR* 0000008AH DATA BYTE TL0 +*SFR* 0000008BH DATA BYTE TL1 +*SFR* 00000089H DATA BYTE TMOD +*SFR* 000000CCH DATA WORD TMR2 +*SFR* 000000C8H DATA BYTE TMR2CN0 +*SFR* 000000C8H.3 DATA BIT TMR2CN0_T2SPLIT +*SFR* 000000C8H DATA BIT TMR2CN0_T2XCLK +*SFR* 000000C8H.4 DATA BIT TMR2CN0_TF2CEN +*SFR* 000000C8H.7 DATA BIT TMR2CN0_TF2H +*SFR* 000000C8H.6 DATA BIT TMR2CN0_TF2L +*SFR* 000000C8H.5 DATA BIT TMR2CN0_TF2LEN +*SFR* 000000C8H.2 DATA BIT TMR2CN0_TR2 +*SFR* 000000CDH DATA BYTE TMR2H +*SFR* 000000CCH DATA BYTE TMR2L +*SFR* 000000CAH DATA WORD TMR2RL +*SFR* 000000CBH DATA BYTE TMR2RLH +*SFR* 000000CAH DATA BYTE TMR2RLL +*SFR* 00000094H DATA WORD TMR3 +*SFR* 00000091H DATA BYTE TMR3CN0 +*SFR* 00000095H DATA BYTE TMR3H +*SFR* 00000094H DATA BYTE TMR3L +*SFR* 00000092H DATA WORD TMR3RL +*SFR* 00000093H DATA BYTE TMR3RLH +*SFR* 00000092H DATA BYTE TMR3RLL + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 11 + + +*DEL*:00000000H CODE --- UART0_getIntFlags + 01000AAEH CODE --- UART0_initTxPolling + 01000760H CODE --- UART0_ISR +*DEL*:00000000H CODE --- UART0_read +*DEL*:00000000H CODE --- UART0_readWithExtraBit +*DEL*:00000000H CODE --- UART0_receiveCompleteCb +*DEL*:00000000H CODE --- UART0_reset +*DEL*:00000000H CODE --- UART0_transmitCompleteCb + 01000AA7H CODE --- UART_0_enter_DefaultMode_from_RESET +*DEL*:00000000H CODE --- uart_buffer_reset + 0000001CH DATA BYTE uart_command + 01000931H CODE --- uart_getc +*DEL*:00000000H CODE --- uart_getlen + 02000000H XDATA --- UART_RX_Buffer + 0000001DH DATA BYTE uart_state +*DEL*:00000000H CODE --- uart_transfer_finished + 02000044H XDATA --- UART_TX_Buffer +*SFR* 000000FFH DATA BYTE VDM0CN + 01000A79H CODE --- WDT_0_enter_DefaultMode_from_RESET +*SFR* 00000097H DATA BYTE WDTCN +*SFR* 000000E1H DATA BYTE XBR0 +*SFR* 000000E2H DATA BYTE XBR1 +*SFR* 000000E3H DATA BYTE XBR2 + + + +SYMBOL TABLE OF MODULE: RF_BRIDGE.OMF.CRBUILD (PCA_0) + + VALUE REP CLASS TYPE SYMBOL NAME + ==================================================== + --- MODULE --- --- PCA_0 + 01000669H PUBLIC CODE --- PCA0_ISR + 01000AABH PUBLIC CODE --- PCA0_halt + 01000A07H PUBLIC CODE --- _PCA0_writeChannel + 000000A2H SFRSYM DATA BYTE SPI0CKR + 00000080H SFRSYM DATA BYTE P0 + 000000D0H.2 SFRSYM DATA BIT PSW_OV + 00000090H SFRSYM DATA BYTE P1 + 00000097H SFRSYM DATA BYTE WDTCN + 000000A0H SFRSYM DATA BYTE P2 + 000000BCH SFRSYM DATA BYTE ADC0CF + 000000C8H SFRSYM DATA BIT TMR2CN0_T2XCLK + 000000C0H.7 SFRSYM DATA BIT SMB0CN0_MASTER + 000000F9H SFRSYM DATA WORD PCA0 + 000000E6H SFRSYM DATA BYTE EIE1 + 000000C0H.1 SFRSYM DATA BIT SMB0CN0_ACK + 0000008FH SFRSYM DATA BYTE PSCTL + 000000E4H SFRSYM DATA BYTE IT01CF + 000000C0H.6 SFRSYM DATA BIT SMB0CN0_TXMODE + 000000ADH SFRSYM DATA BYTE DERIVID + 000000A4H SFRSYM DATA BYTE P0MDOUT + 000000A5H SFRSYM DATA BYTE P1MDOUT + 000000E8H.5 SFRSYM DATA BIT ADC0CN0_ADINT + 000000CBH SFRSYM DATA BYTE TMR2RLH + 000000A6H SFRSYM DATA BYTE P2MDOUT + 000000A8H SFRSYM DATA BYTE IE + 00000093H SFRSYM DATA BYTE TMR3RLH + 000000F3H SFRSYM DATA BYTE EIP1 + 00000098H.2 SFRSYM DATA BIT SCON0_RB8 + 000000CAH SFRSYM DATA BYTE TMR2RLL + 000000FCH SFRSYM DATA BYTE PCA0CPH0 + 00000092H SFRSYM DATA BYTE TMR3RLL + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 12 + + + 000000EAH SFRSYM DATA BYTE PCA0CPH1 + 00000098H.3 SFRSYM DATA BIT SCON0_TB8 + 000000F0H SFRSYM DATA BIT B_B0 + 00000082H SFRSYM DATA WORD DP + 000000ECH SFRSYM DATA BYTE PCA0CPH2 + 000000F0H.1 SFRSYM DATA BIT B_B1 + 000000C3H SFRSYM DATA WORD ADC0GT + 000000F0H.2 SFRSYM DATA BIT B_B2 + 000000FBH SFRSYM DATA BYTE PCA0CPL0 + 000000F0H.3 SFRSYM DATA BIT B_B3 + 000000D9H SFRSYM DATA BYTE PCA0MD + 000000DAH SFRSYM DATA BYTE PCA0CPM0 + 000000E9H SFRSYM DATA BYTE PCA0CPL1 + 000000F0H.4 SFRSYM DATA BIT B_B4 + 000000DBH SFRSYM DATA BYTE PCA0CPM1 + 000000EBH SFRSYM DATA BYTE PCA0CPL2 + 000000F0H.5 SFRSYM DATA BIT B_B5 + 000000DCH SFRSYM DATA BYTE PCA0CPM2 + 000000B8H SFRSYM DATA BYTE IP + 000000B9H SFRSYM DATA BYTE ADC0TK + 000000F0H.6 SFRSYM DATA BIT B_B6 + 000000C5H SFRSYM DATA WORD ADC0LT + 00000098H.5 SFRSYM DATA BIT SCON0_MCE + 000000F0H.7 SFRSYM DATA BIT B_B7 + 000000E1H SFRSYM DATA BYTE XBR0 + 000000C1H SFRSYM DATA BYTE SMB0CF + 000000E2H SFRSYM DATA BYTE XBR1 + 000000C0H.5 SFRSYM DATA BIT SMB0CN0_STA + 000000E3H SFRSYM DATA BYTE XBR2 + 000000BBH SFRSYM DATA BYTE ADC0MX + 000000E0H SFRSYM DATA BIT ACC_ACC0 + 000000D1H SFRSYM DATA BYTE REF0CN + 0000008EH SFRSYM DATA BYTE CKCON0 + 000000E0H.1 SFRSYM DATA BIT ACC_ACC1 + 000000C9H SFRSYM DATA BYTE REG0CN + 000000DDH SFRSYM DATA BYTE CRC0IN + 000000C8H.2 SFRSYM DATA BIT TMR2CN0_TR2 + 000000E0H.2 SFRSYM DATA BIT ACC_ACC2 + 000000E0H.3 SFRSYM DATA BIT ACC_ACC3 + 00000081H SFRSYM DATA BYTE SP + 0000009DH SFRSYM DATA BYTE CMP0MD + 000000E0H.4 SFRSYM DATA BIT ACC_ACC4 + 000000B1H SFRSYM DATA BYTE LFO0CN + 000000ABH SFRSYM DATA BYTE CMP1MD + 000000D8H SFRSYM DATA BIT PCA0CN0_CCF0 + 000000E0H.5 SFRSYM DATA BIT ACC_ACC5 + 000000D8H.1 SFRSYM DATA BIT PCA0CN0_CCF1 + 000000E0H.6 SFRSYM DATA BIT ACC_ACC6 + 000000CCH SFRSYM DATA WORD TMR2 + 000000D8H.2 SFRSYM DATA BIT PCA0CN0_CCF2 + 000000E0H.7 SFRSYM DATA BIT ACC_ACC7 + 00000094H SFRSYM DATA WORD TMR3 + 000000C0H.3 SFRSYM DATA BIT SMB0CN0_ACKRQ + 000000FFH SFRSYM DATA BYTE VDM0CN + 000000F1H SFRSYM DATA BYTE P0MDIN + 00000098H.4 SFRSYM DATA BIT SCON0_REN + 000000ACH SFRSYM DATA BYTE SMB0TC + 000000F2H SFRSYM DATA BYTE P1MDIN + 000000C0H.4 SFRSYM DATA BIT SMB0CN0_STO + 000000FEH SFRSYM DATA BYTE P0MASK + 000000EEH SFRSYM DATA BYTE P1MASK + 000000D0H.3 SFRSYM DATA BIT PSW_RS0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 13 + + + 000000D8H.7 SFRSYM DATA BIT PCA0CN0_CF + 0000009EH SFRSYM DATA BYTE PCA0CENT + 000000F8H.4 SFRSYM DATA BIT SPI0CN0_RXOVRN + 000000D0H.4 SFRSYM DATA BIT PSW_RS1 + 000000E8H.7 SFRSYM DATA BIT ADC0CN0_ADEN + 00000089H SFRSYM DATA BYTE TMOD + 00000088H SFRSYM DATA BYTE TCON + 000000CFH SFRSYM DATA BYTE CRC0FLIP + 000000D0H SFRSYM DATA BIT PSW_PARITY + 000000A8H.4 SFRSYM DATA BIT IE_ES0 + 0000009FH SFRSYM DATA BYTE CMP0MX + 000000A8H.1 SFRSYM DATA BIT IE_ET0 + 000000AAH SFRSYM DATA BYTE CMP1MX + 000000A8H.3 SFRSYM DATA BIT IE_ET1 + 000000D4H SFRSYM DATA BYTE P0SKIP + 000000A8H.5 SFRSYM DATA BIT IE_ET2 + 000000D5H SFRSYM DATA BYTE P1SKIP + 000000E8H SFRSYM DATA BYTE ADC0CN0 + 000000A8H SFRSYM DATA BIT IE_EX0 + 000000B2H SFRSYM DATA BYTE ADC0CN1 + 000000D8H.6 SFRSYM DATA BIT PCA0CN0_CR + 000000A8H.2 SFRSYM DATA BIT IE_EX1 + 00000098H.7 SFRSYM DATA BIT SCON0_SMODE + 000000B5H SFRSYM DATA BYTE DEVICEID + 000000A9H SFRSYM DATA BYTE CLKSEL + 000000F8H SFRSYM DATA BIT SPI0CN0_SPIEN + 000000F0H SFRSYM DATA BYTE B + 000000BEH SFRSYM DATA BYTE ADC0H + 000000D2H SFRSYM DATA BYTE CRC0AUTO + 000000E8H.6 SFRSYM DATA BIT ADC0CN0_ADBMEN + 000000CAH SFRSYM DATA WORD TMR2RL + 000000BDH SFRSYM DATA BYTE ADC0L + 00000092H SFRSYM DATA WORD TMR3RL + 000000D8H SFRSYM DATA BYTE PCA0CN0 + 000000E0H SFRSYM DATA BYTE ACC + 000000FBH SFRSYM DATA WORD PCA0CP0 + 000000E9H SFRSYM DATA WORD PCA0CP1 + 000000EBH SFRSYM DATA WORD PCA0CP2 + 000000CEH SFRSYM DATA BYTE CRC0CN0 + 0000008CH SFRSYM DATA BYTE TH0 + 000000B8H.4 SFRSYM DATA BIT IP_PS0 + 0000008DH SFRSYM DATA BYTE TH1 + 000000FAH SFRSYM DATA BYTE PCA0H + 000000B8H.1 SFRSYM DATA BIT IP_PT0 + 000000B8H.3 SFRSYM DATA BIT IP_PT1 + 000000C0H.2 SFRSYM DATA BIT SMB0CN0_ARBLOST + 000000B8H.5 SFRSYM DATA BIT IP_PT2 + 0000008AH SFRSYM DATA BYTE TL0 + 000000F8H.1 SFRSYM DATA BIT SPI0CN0_TXBMT + 000000D0H.5 SFRSYM DATA BIT PSW_F0 + 000000A8H.6 SFRSYM DATA BIT IE_ESPI0 + 0000008BH SFRSYM DATA BYTE TL1 + 000000F9H SFRSYM DATA BYTE PCA0L + 000000C0H SFRSYM DATA BIT SMB0CN0_SI + 000000D0H.1 SFRSYM DATA BIT PSW_F1 + 00000080H SFRSYM DATA BIT P0_B0 + 000000B8H SFRSYM DATA BIT IP_PX0 + 00000090H SFRSYM DATA BIT P1_B0 + 00000080H.1 SFRSYM DATA BIT P0_B1 + 000000B8H.2 SFRSYM DATA BIT IP_PX1 + 0000009BH SFRSYM DATA BYTE CMP0CN0 + 00000088H.1 SFRSYM DATA BIT TCON_IE0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 14 + + + 000000A0H SFRSYM DATA BIT P2_B0 + 00000090H.1 SFRSYM DATA BIT P1_B1 + 00000080H.2 SFRSYM DATA BIT P0_B2 + 000000BFH SFRSYM DATA BYTE CMP1CN0 + 00000088H.3 SFRSYM DATA BIT TCON_IE1 + 000000A0H.1 SFRSYM DATA BIT P2_B1 + 00000090H.2 SFRSYM DATA BIT P1_B2 + 00000080H.3 SFRSYM DATA BIT P0_B3 + 000000C0H SFRSYM DATA BYTE SMB0CN0 + 00000090H.3 SFRSYM DATA BIT P1_B3 + 00000080H.4 SFRSYM DATA BIT P0_B4 + 00000090H.4 SFRSYM DATA BIT P1_B4 + 00000080H.5 SFRSYM DATA BIT P0_B5 + 00000090H.5 SFRSYM DATA BIT P1_B5 + 00000080H.6 SFRSYM DATA BIT P0_B6 + 00000090H.6 SFRSYM DATA BIT P1_B6 + 00000080H.7 SFRSYM DATA BIT P0_B7 + 00000090H.7 SFRSYM DATA BIT P1_B7 + 00000083H SFRSYM DATA BYTE DPH + 000000C4H SFRSYM DATA BYTE ADC0GTH + 000000C8H.7 SFRSYM DATA BIT TMR2CN0_TF2H + 000000C8H.3 SFRSYM DATA BIT TMR2CN0_T2SPLIT + 000000D0H.6 SFRSYM DATA BIT PSW_AC + 000000F8H SFRSYM DATA BYTE SPI0CN0 + 000000C7H SFRSYM DATA BYTE HFO0CAL + 00000088H.5 SFRSYM DATA BIT TCON_TF0 + 00000098H SFRSYM DATA BIT SCON0_RI + 00000082H SFRSYM DATA BYTE DPL + 00000088H.7 SFRSYM DATA BIT TCON_TF1 + 00000099H SFRSYM DATA BYTE SBUF0 + 00000087H SFRSYM DATA BYTE PCON0 + 000000C3H SFRSYM DATA BYTE ADC0GTL + 000000C8H.6 SFRSYM DATA BIT TMR2CN0_TF2L + 00000098H.1 SFRSYM DATA BIT SCON0_TI + 000000E8H SFRSYM DATA BIT ADC0CN0_ADCM0 + 000000C6H SFRSYM DATA BYTE ADC0LTH + 00000088H SFRSYM DATA BIT TCON_IT0 + 000000E8H.1 SFRSYM DATA BIT ADC0CN0_ADCM1 + 000000EFH SFRSYM DATA BYTE RSTSRC + 000000FDH SFRSYM DATA BYTE P0MAT + 000000DEH SFRSYM DATA BYTE CRC0DAT + 00000088H.2 SFRSYM DATA BIT TCON_IT1 + 000000E8H.2 SFRSYM DATA BIT ADC0CN0_ADCM2 + 00000098H SFRSYM DATA BYTE SCON0 + 000000F6H SFRSYM DATA BYTE PRTDRV + 000000EDH SFRSYM DATA BYTE P1MAT + 000000E8H.3 SFRSYM DATA BIT ADC0CN0_ADWINT + 000000E8H.4 SFRSYM DATA BIT ADC0CN0_ADBUSY + 000000D6H SFRSYM DATA BYTE SMB0ADM + 000000C5H SFRSYM DATA BYTE ADC0LTL + 000000F8H.5 SFRSYM DATA BIT SPI0CN0_MODF + 000000B8H.6 SFRSYM DATA BIT IP_PSPI0 + 0000009CH SFRSYM DATA BYTE PCA0CLR + 000000C8H SFRSYM DATA BYTE TMR2CN0 + 00000091H SFRSYM DATA BYTE TMR3CN0 + 000000D7H SFRSYM DATA BYTE SMB0ADR + 00000088H.4 SFRSYM DATA BIT TCON_TR0 + 000000C8H.4 SFRSYM DATA BIT TMR2CN0_TF2CEN + 00000088H.6 SFRSYM DATA BIT TCON_TR1 + 000000C2H SFRSYM DATA BYTE SMB0DAT + 000000CDH SFRSYM DATA BYTE TMR2H + 000000A1H SFRSYM DATA BYTE SPI0CFG + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 15 + + + 00000095H SFRSYM DATA BYTE TMR3H + 000000D3H SFRSYM DATA BYTE CRC0CNT + 00000096H SFRSYM DATA BYTE PCA0POL + 000000CCH SFRSYM DATA BYTE TMR2L + 000000F8H.7 SFRSYM DATA BIT SPI0CN0_SPIF + 00000094H SFRSYM DATA BYTE TMR3L + 000000DFH SFRSYM DATA BYTE ADC0PWR + 000000A8H.7 SFRSYM DATA BIT IE_EA + 000000C8H.5 SFRSYM DATA BIT TMR2CN0_TF2LEN + 000000F8H.6 SFRSYM DATA BIT SPI0CN0_WCOL + 000000F8H.2 SFRSYM DATA BIT SPI0CN0_NSSMD0 + 000000D0H.7 SFRSYM DATA BIT PSW_CY + 000000A3H SFRSYM DATA BYTE SPI0DAT + 000000F8H.3 SFRSYM DATA BIT SPI0CN0_NSSMD1 + 000000BDH SFRSYM DATA WORD ADC0 + 000000D0H SFRSYM DATA BYTE PSW + 000000F7H SFRSYM DATA BYTE PCA0PWM + 000000B6H SFRSYM DATA BYTE REVID + 000000B7H SFRSYM DATA BYTE FLKEY + 000000B3H SFRSYM DATA BYTE ADC0AC + 00000007H SYMBOL DATA BYTE val + 00000007H SYMBOL DATA BYTE flag + 00000007H SYMBOL DATA BYTE flag + 00000006H SYMBOL DATA BYTE en + 00000007H SYMBOL DATA BYTE channel + + 01000A07H BLOCK CODE --- LVL=0 + 00000003H SYMBOL DATA BYTE channel + 00000004H SYMBOL DATA WORD value + 01000A09H BLOCK CODE NEAR LAB LVL=1 + 00000007H SYMBOL DATA BYTE lower + --- BLOCKEND --- --- LVL=1 + 01000A07H LINE CODE --- #67 + 01000A09H LINE CODE --- #68 + 01000A09H LINE CODE --- #69 + 01000A0BH LINE CODE --- #70 + 01000A16H LINE CODE --- #71 + 01000A16H LINE CODE --- #72 + 01000A16H LINE CODE --- #73 + 01000A18H LINE CODE --- #74 + 01000A1AH LINE CODE --- #75 + 01000A1BH LINE CODE --- #76 + 01000A1BH LINE CODE --- #77 + 01000A1DH LINE CODE --- #78 + 01000A1FH LINE CODE --- #79 + 01000A20H LINE CODE --- #80 + 01000A20H LINE CODE --- #81 + 01000A22H LINE CODE --- #82 + 01000A24H LINE CODE --- #83 + 01000A24H LINE CODE --- #84 + 01000A24H LINE CODE --- #85 + --- BLOCKEND --- --- LVL=0 + 00000006H SYMBOL DATA WORD value + + 01000AABH BLOCK CODE --- LVL=0 + 01000AABH LINE CODE --- #104 + 01000AABH LINE CODE --- #105 + 01000AABH LINE CODE --- #106 + 01000AADH LINE CODE --- #107 + --- BLOCKEND --- --- LVL=0 + 00000007H SYMBOL DATA BYTE timebase + 00000005H SYMBOL DATA BYTE idleState + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 16 + + + 00000007H SYMBOL DATA BYTE channel + 00000005H SYMBOL DATA BYTE mode + 00000003H SYMBOL DATA BYTE pol + 00000006H SYMBOL DATA BYTE pwmValue + 00000007H SYMBOL DATA BYTE channel + + 01000669H BLOCK CODE --- LVL=0 + 01000686H BLOCK CODE NEAR LAB LVL=1 + 00000042H SYMBOL DATA BYTE flags + --- BLOCKEND --- --- LVL=1 + 01000669H LINE CODE --- #230 + 01000686H LINE CODE --- #233 + 0100068CH LINE CODE --- #237 + 0100068FH LINE CODE --- #239 + 01000699H LINE CODE --- #241 + 01000699H LINE CODE --- #242 + 0100069CH LINE CODE --- #243 + 0100069CH LINE CODE --- #244 + 0100069FH LINE CODE --- #246 + 010006A9H LINE CODE --- #248 + 010006A9H LINE CODE --- #249 + 010006ACH LINE CODE --- #250 + 010006ACH LINE CODE --- #251 + 010006B6H LINE CODE --- #253 + 010006B6H LINE CODE --- #254 + 010006B9H LINE CODE --- #255 + 010006B9H LINE CODE --- #256 + 010006C3H LINE CODE --- #258 + 010006C3H LINE CODE --- #259 + 010006C6H LINE CODE --- #260 + 010006C6H LINE CODE --- #261 + 010006D0H LINE CODE --- #263 + 010006D0H LINE CODE --- #264 + 010006D3H LINE CODE --- #265 + 010006D3H LINE CODE --- #266 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- UART_0 + 01000A70H PUBLIC CODE --- _UART0_init + 01000AAEH PUBLIC CODE --- UART0_initTxPolling + 000000A2H SFRSYM DATA BYTE SPI0CKR + 00000080H SFRSYM DATA BYTE P0 + 000000D0H.2 SFRSYM DATA BIT PSW_OV + 00000090H SFRSYM DATA BYTE P1 + 00000097H SFRSYM DATA BYTE WDTCN + 000000A0H SFRSYM DATA BYTE P2 + 000000BCH SFRSYM DATA BYTE ADC0CF + 000000C8H SFRSYM DATA BIT TMR2CN0_T2XCLK + 000000C0H.7 SFRSYM DATA BIT SMB0CN0_MASTER + 000000F9H SFRSYM DATA WORD PCA0 + 000000E6H SFRSYM DATA BYTE EIE1 + 000000C0H.1 SFRSYM DATA BIT SMB0CN0_ACK + 0000008FH SFRSYM DATA BYTE PSCTL + 000000E4H SFRSYM DATA BYTE IT01CF + 000000C0H.6 SFRSYM DATA BIT SMB0CN0_TXMODE + 000000ADH SFRSYM DATA BYTE DERIVID + 000000A4H SFRSYM DATA BYTE P0MDOUT + 000000A5H SFRSYM DATA BYTE P1MDOUT + 000000E8H.5 SFRSYM DATA BIT ADC0CN0_ADINT + 000000CBH SFRSYM DATA BYTE TMR2RLH + 000000A6H SFRSYM DATA BYTE P2MDOUT + 000000A8H SFRSYM DATA BYTE IE + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 17 + + + 00000093H SFRSYM DATA BYTE TMR3RLH + 000000F3H SFRSYM DATA BYTE EIP1 + 00000098H.2 SFRSYM DATA BIT SCON0_RB8 + 000000CAH SFRSYM DATA BYTE TMR2RLL + 000000FCH SFRSYM DATA BYTE PCA0CPH0 + 00000092H SFRSYM DATA BYTE TMR3RLL + 000000EAH SFRSYM DATA BYTE PCA0CPH1 + 00000098H.3 SFRSYM DATA BIT SCON0_TB8 + 000000F0H SFRSYM DATA BIT B_B0 + 00000082H SFRSYM DATA WORD DP + 000000ECH SFRSYM DATA BYTE PCA0CPH2 + 000000F0H.1 SFRSYM DATA BIT B_B1 + 000000C3H SFRSYM DATA WORD ADC0GT + 000000F0H.2 SFRSYM DATA BIT B_B2 + 000000FBH SFRSYM DATA BYTE PCA0CPL0 + 000000F0H.3 SFRSYM DATA BIT B_B3 + 000000D9H SFRSYM DATA BYTE PCA0MD + 000000DAH SFRSYM DATA BYTE PCA0CPM0 + 000000E9H SFRSYM DATA BYTE PCA0CPL1 + 000000F0H.4 SFRSYM DATA BIT B_B4 + 000000DBH SFRSYM DATA BYTE PCA0CPM1 + 000000EBH SFRSYM DATA BYTE PCA0CPL2 + 000000F0H.5 SFRSYM DATA BIT B_B5 + 000000DCH SFRSYM DATA BYTE PCA0CPM2 + 000000B8H SFRSYM DATA BYTE IP + 000000B9H SFRSYM DATA BYTE ADC0TK + 000000F0H.6 SFRSYM DATA BIT B_B6 + 000000C5H SFRSYM DATA WORD ADC0LT + 00000098H.5 SFRSYM DATA BIT SCON0_MCE + 000000F0H.7 SFRSYM DATA BIT B_B7 + 000000E1H SFRSYM DATA BYTE XBR0 + 000000C1H SFRSYM DATA BYTE SMB0CF + 000000E2H SFRSYM DATA BYTE XBR1 + 000000C0H.5 SFRSYM DATA BIT SMB0CN0_STA + 000000E3H SFRSYM DATA BYTE XBR2 + 000000BBH SFRSYM DATA BYTE ADC0MX + 000000E0H SFRSYM DATA BIT ACC_ACC0 + 000000D1H SFRSYM DATA BYTE REF0CN + 0000008EH SFRSYM DATA BYTE CKCON0 + 000000E0H.1 SFRSYM DATA BIT ACC_ACC1 + 000000C9H SFRSYM DATA BYTE REG0CN + 000000DDH SFRSYM DATA BYTE CRC0IN + 000000C8H.2 SFRSYM DATA BIT TMR2CN0_TR2 + 000000E0H.2 SFRSYM DATA BIT ACC_ACC2 + 000000E0H.3 SFRSYM DATA BIT ACC_ACC3 + 00000081H SFRSYM DATA BYTE SP + 0000009DH SFRSYM DATA BYTE CMP0MD + 000000E0H.4 SFRSYM DATA BIT ACC_ACC4 + 000000B1H SFRSYM DATA BYTE LFO0CN + 000000ABH SFRSYM DATA BYTE CMP1MD + 000000D8H SFRSYM DATA BIT PCA0CN0_CCF0 + 000000E0H.5 SFRSYM DATA BIT ACC_ACC5 + 000000D8H.1 SFRSYM DATA BIT PCA0CN0_CCF1 + 000000E0H.6 SFRSYM DATA BIT ACC_ACC6 + 000000CCH SFRSYM DATA WORD TMR2 + 000000D8H.2 SFRSYM DATA BIT PCA0CN0_CCF2 + 000000E0H.7 SFRSYM DATA BIT ACC_ACC7 + 00000094H SFRSYM DATA WORD TMR3 + 000000C0H.3 SFRSYM DATA BIT SMB0CN0_ACKRQ + 000000FFH SFRSYM DATA BYTE VDM0CN + 000000F1H SFRSYM DATA BYTE P0MDIN + 00000098H.4 SFRSYM DATA BIT SCON0_REN + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 18 + + + 000000ACH SFRSYM DATA BYTE SMB0TC + 000000F2H SFRSYM DATA BYTE P1MDIN + 000000C0H.4 SFRSYM DATA BIT SMB0CN0_STO + 000000FEH SFRSYM DATA BYTE P0MASK + 000000EEH SFRSYM DATA BYTE P1MASK + 000000D0H.3 SFRSYM DATA BIT PSW_RS0 + 000000D8H.7 SFRSYM DATA BIT PCA0CN0_CF + 0000009EH SFRSYM DATA BYTE PCA0CENT + 000000F8H.4 SFRSYM DATA BIT SPI0CN0_RXOVRN + 000000D0H.4 SFRSYM DATA BIT PSW_RS1 + 000000E8H.7 SFRSYM DATA BIT ADC0CN0_ADEN + 00000089H SFRSYM DATA BYTE TMOD + 00000088H SFRSYM DATA BYTE TCON + 000000CFH SFRSYM DATA BYTE CRC0FLIP + 000000D0H SFRSYM DATA BIT PSW_PARITY + 000000A8H.4 SFRSYM DATA BIT IE_ES0 + 0000009FH SFRSYM DATA BYTE CMP0MX + 000000A8H.1 SFRSYM DATA BIT IE_ET0 + 000000AAH SFRSYM DATA BYTE CMP1MX + 000000A8H.3 SFRSYM DATA BIT IE_ET1 + 000000D4H SFRSYM DATA BYTE P0SKIP + 000000A8H.5 SFRSYM DATA BIT IE_ET2 + 000000D5H SFRSYM DATA BYTE P1SKIP + 000000E8H SFRSYM DATA BYTE ADC0CN0 + 000000A8H SFRSYM DATA BIT IE_EX0 + 000000B2H SFRSYM DATA BYTE ADC0CN1 + 000000D8H.6 SFRSYM DATA BIT PCA0CN0_CR + 000000A8H.2 SFRSYM DATA BIT IE_EX1 + 00000098H.7 SFRSYM DATA BIT SCON0_SMODE + 000000B5H SFRSYM DATA BYTE DEVICEID + 000000A9H SFRSYM DATA BYTE CLKSEL + 000000F8H SFRSYM DATA BIT SPI0CN0_SPIEN + 000000F0H SFRSYM DATA BYTE B + 000000BEH SFRSYM DATA BYTE ADC0H + 000000D2H SFRSYM DATA BYTE CRC0AUTO + 000000E8H.6 SFRSYM DATA BIT ADC0CN0_ADBMEN + 000000CAH SFRSYM DATA WORD TMR2RL + 000000BDH SFRSYM DATA BYTE ADC0L + 00000092H SFRSYM DATA WORD TMR3RL + 000000D8H SFRSYM DATA BYTE PCA0CN0 + 000000E0H SFRSYM DATA BYTE ACC + 000000FBH SFRSYM DATA WORD PCA0CP0 + 000000E9H SFRSYM DATA WORD PCA0CP1 + 000000EBH SFRSYM DATA WORD PCA0CP2 + 000000CEH SFRSYM DATA BYTE CRC0CN0 + 0000008CH SFRSYM DATA BYTE TH0 + 000000B8H.4 SFRSYM DATA BIT IP_PS0 + 0000008DH SFRSYM DATA BYTE TH1 + 000000FAH SFRSYM DATA BYTE PCA0H + 000000B8H.1 SFRSYM DATA BIT IP_PT0 + 000000B8H.3 SFRSYM DATA BIT IP_PT1 + 000000C0H.2 SFRSYM DATA BIT SMB0CN0_ARBLOST + 000000B8H.5 SFRSYM DATA BIT IP_PT2 + 0000008AH SFRSYM DATA BYTE TL0 + 000000F8H.1 SFRSYM DATA BIT SPI0CN0_TXBMT + 000000D0H.5 SFRSYM DATA BIT PSW_F0 + 000000A8H.6 SFRSYM DATA BIT IE_ESPI0 + 0000008BH SFRSYM DATA BYTE TL1 + 000000F9H SFRSYM DATA BYTE PCA0L + 000000C0H SFRSYM DATA BIT SMB0CN0_SI + 000000D0H.1 SFRSYM DATA BIT PSW_F1 + 00000080H SFRSYM DATA BIT P0_B0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 19 + + + 000000B8H SFRSYM DATA BIT IP_PX0 + 00000090H SFRSYM DATA BIT P1_B0 + 00000080H.1 SFRSYM DATA BIT P0_B1 + 000000B8H.2 SFRSYM DATA BIT IP_PX1 + 0000009BH SFRSYM DATA BYTE CMP0CN0 + 00000088H.1 SFRSYM DATA BIT TCON_IE0 + 000000A0H SFRSYM DATA BIT P2_B0 + 00000090H.1 SFRSYM DATA BIT P1_B1 + 00000080H.2 SFRSYM DATA BIT P0_B2 + 000000BFH SFRSYM DATA BYTE CMP1CN0 + 00000088H.3 SFRSYM DATA BIT TCON_IE1 + 000000A0H.1 SFRSYM DATA BIT P2_B1 + 00000090H.2 SFRSYM DATA BIT P1_B2 + 00000080H.3 SFRSYM DATA BIT P0_B3 + 000000C0H SFRSYM DATA BYTE SMB0CN0 + 00000090H.3 SFRSYM DATA BIT P1_B3 + 00000080H.4 SFRSYM DATA BIT P0_B4 + 00000090H.4 SFRSYM DATA BIT P1_B4 + 00000080H.5 SFRSYM DATA BIT P0_B5 + 00000090H.5 SFRSYM DATA BIT P1_B5 + 00000080H.6 SFRSYM DATA BIT P0_B6 + 00000090H.6 SFRSYM DATA BIT P1_B6 + 00000080H.7 SFRSYM DATA BIT P0_B7 + 00000090H.7 SFRSYM DATA BIT P1_B7 + 00000083H SFRSYM DATA BYTE DPH + 000000C4H SFRSYM DATA BYTE ADC0GTH + 000000C8H.7 SFRSYM DATA BIT TMR2CN0_TF2H + 000000C8H.3 SFRSYM DATA BIT TMR2CN0_T2SPLIT + 000000D0H.6 SFRSYM DATA BIT PSW_AC + 000000F8H SFRSYM DATA BYTE SPI0CN0 + 000000C7H SFRSYM DATA BYTE HFO0CAL + 00000088H.5 SFRSYM DATA BIT TCON_TF0 + 00000098H SFRSYM DATA BIT SCON0_RI + 00000082H SFRSYM DATA BYTE DPL + 00000088H.7 SFRSYM DATA BIT TCON_TF1 + 00000099H SFRSYM DATA BYTE SBUF0 + 00000087H SFRSYM DATA BYTE PCON0 + 000000C3H SFRSYM DATA BYTE ADC0GTL + 000000C8H.6 SFRSYM DATA BIT TMR2CN0_TF2L + 00000098H.1 SFRSYM DATA BIT SCON0_TI + 000000E8H SFRSYM DATA BIT ADC0CN0_ADCM0 + 000000C6H SFRSYM DATA BYTE ADC0LTH + 00000088H SFRSYM DATA BIT TCON_IT0 + 000000E8H.1 SFRSYM DATA BIT ADC0CN0_ADCM1 + 000000EFH SFRSYM DATA BYTE RSTSRC + 000000FDH SFRSYM DATA BYTE P0MAT + 000000DEH SFRSYM DATA BYTE CRC0DAT + 00000088H.2 SFRSYM DATA BIT TCON_IT1 + 000000E8H.2 SFRSYM DATA BIT ADC0CN0_ADCM2 + 00000098H SFRSYM DATA BYTE SCON0 + 000000F6H SFRSYM DATA BYTE PRTDRV + 000000EDH SFRSYM DATA BYTE P1MAT + 000000E8H.3 SFRSYM DATA BIT ADC0CN0_ADWINT + 000000E8H.4 SFRSYM DATA BIT ADC0CN0_ADBUSY + 000000D6H SFRSYM DATA BYTE SMB0ADM + 000000C5H SFRSYM DATA BYTE ADC0LTL + 000000F8H.5 SFRSYM DATA BIT SPI0CN0_MODF + 000000B8H.6 SFRSYM DATA BIT IP_PSPI0 + 0000009CH SFRSYM DATA BYTE PCA0CLR + 000000C8H SFRSYM DATA BYTE TMR2CN0 + 00000091H SFRSYM DATA BYTE TMR3CN0 + 000000D7H SFRSYM DATA BYTE SMB0ADR + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 20 + + + 00000088H.4 SFRSYM DATA BIT TCON_TR0 + 000000C8H.4 SFRSYM DATA BIT TMR2CN0_TF2CEN + 00000088H.6 SFRSYM DATA BIT TCON_TR1 + 000000C2H SFRSYM DATA BYTE SMB0DAT + 000000CDH SFRSYM DATA BYTE TMR2H + 000000A1H SFRSYM DATA BYTE SPI0CFG + 00000095H SFRSYM DATA BYTE TMR3H + 000000D3H SFRSYM DATA BYTE CRC0CNT + 00000096H SFRSYM DATA BYTE PCA0POL + 000000CCH SFRSYM DATA BYTE TMR2L + 000000F8H.7 SFRSYM DATA BIT SPI0CN0_SPIF + 00000094H SFRSYM DATA BYTE TMR3L + 000000DFH SFRSYM DATA BYTE ADC0PWR + 000000A8H.7 SFRSYM DATA BIT IE_EA + 000000C8H.5 SFRSYM DATA BIT TMR2CN0_TF2LEN + 000000F8H.6 SFRSYM DATA BIT SPI0CN0_WCOL + 000000F8H.2 SFRSYM DATA BIT SPI0CN0_NSSMD0 + 000000D0H.7 SFRSYM DATA BIT PSW_CY + 000000A3H SFRSYM DATA BYTE SPI0DAT + 000000F8H.3 SFRSYM DATA BIT SPI0CN0_NSSMD1 + 000000BDH SFRSYM DATA WORD ADC0 + 000000D0H SFRSYM DATA BYTE PSW + 000000F7H SFRSYM DATA BYTE PCA0PWM + 000000B6H SFRSYM DATA BYTE REVID + 000000B7H SFRSYM DATA BYTE FLKEY + 000000B3H SFRSYM DATA BYTE ADC0AC + 00000007H SYMBOL DATA BYTE flag + + 01000AAEH BLOCK CODE --- LVL=0 + 01000AAEH LINE CODE --- #19 + 01000AAEH LINE CODE --- #20 + 01000AAEH LINE CODE --- #21 + 01000AB0H LINE CODE --- #22 + --- BLOCKEND --- --- LVL=0 + 00000007H SYMBOL DATA BYTE value + 00000002H SYMBOL DATA WORD value + + 01000A70H BLOCK CODE --- LVL=0 + 00000007H SYMBOL DATA BYTE rxen + 00000005H SYMBOL DATA BYTE width + 00000003H SYMBOL DATA BYTE mce + 01000A70H LINE CODE --- #44 + 01000A70H LINE CODE --- #45 + 01000A70H LINE CODE --- #46 + 01000A73H LINE CODE --- #49 + 01000A78H LINE CODE --- #50 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- INITDEVICE + 01000A9CH PUBLIC CODE --- INTERRUPT_0_enter_DefaultMode_from_RESET + 01000AA7H PUBLIC CODE --- UART_0_enter_DefaultMode_from_RESET + 01000A95H PUBLIC CODE --- PCACH_1_enter_DefaultMode_from_RESET + 01000A8EH PUBLIC CODE --- PCACH_0_enter_DefaultMode_from_RESET + 0100005EH PUBLIC CODE --- PCA_0_enter_DefaultMode_from_RESET + 01000A66H PUBLIC CODE --- TIMER_SETUP_0_enter_DefaultMode_from_RESET + 01000A3BH PUBLIC CODE --- TIMER16_3_enter_DefaultMode_from_RESET + 01000A25H PUBLIC CODE --- TIMER01_0_enter_DefaultMode_from_RESET + 01000AA3H PUBLIC CODE --- CLOCK_0_enter_DefaultMode_from_RESET + 01000A5CH PUBLIC CODE --- PBCFG_0_enter_DefaultMode_from_RESET + 01000A87H PUBLIC CODE --- PORTS_1_enter_DefaultMode_from_RESET + 01000A80H PUBLIC CODE --- PORTS_0_enter_DefaultMode_from_RESET + 01000A79H PUBLIC CODE --- WDT_0_enter_DefaultMode_from_RESET + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 21 + + + 01000998H PUBLIC CODE --- enter_DefaultMode_from_RESET + 000000A2H SFRSYM DATA BYTE SPI0CKR + 00000080H SFRSYM DATA BYTE P0 + 000000D0H.2 SFRSYM DATA BIT PSW_OV + 00000090H SFRSYM DATA BYTE P1 + 00000097H SFRSYM DATA BYTE WDTCN + 000000A0H SFRSYM DATA BYTE P2 + 000000BCH SFRSYM DATA BYTE ADC0CF + 000000C8H SFRSYM DATA BIT TMR2CN0_T2XCLK + 000000C0H.7 SFRSYM DATA BIT SMB0CN0_MASTER + 000000F9H SFRSYM DATA WORD PCA0 + 000000E6H SFRSYM DATA BYTE EIE1 + 000000C0H.1 SFRSYM DATA BIT SMB0CN0_ACK + 0000008FH SFRSYM DATA BYTE PSCTL + 000000E4H SFRSYM DATA BYTE IT01CF + 000000C0H.6 SFRSYM DATA BIT SMB0CN0_TXMODE + 000000ADH SFRSYM DATA BYTE DERIVID + 000000A4H SFRSYM DATA BYTE P0MDOUT + 000000A5H SFRSYM DATA BYTE P1MDOUT + 000000E8H.5 SFRSYM DATA BIT ADC0CN0_ADINT + 000000CBH SFRSYM DATA BYTE TMR2RLH + 000000A6H SFRSYM DATA BYTE P2MDOUT + 000000A8H SFRSYM DATA BYTE IE + 00000093H SFRSYM DATA BYTE TMR3RLH + 000000F3H SFRSYM DATA BYTE EIP1 + 00000098H.2 SFRSYM DATA BIT SCON0_RB8 + 000000CAH SFRSYM DATA BYTE TMR2RLL + 000000FCH SFRSYM DATA BYTE PCA0CPH0 + 00000092H SFRSYM DATA BYTE TMR3RLL + 000000EAH SFRSYM DATA BYTE PCA0CPH1 + 00000098H.3 SFRSYM DATA BIT SCON0_TB8 + 000000F0H SFRSYM DATA BIT B_B0 + 00000082H SFRSYM DATA WORD DP + 000000ECH SFRSYM DATA BYTE PCA0CPH2 + 000000F0H.1 SFRSYM DATA BIT B_B1 + 000000C3H SFRSYM DATA WORD ADC0GT + 000000F0H.2 SFRSYM DATA BIT B_B2 + 000000FBH SFRSYM DATA BYTE PCA0CPL0 + 000000F0H.3 SFRSYM DATA BIT B_B3 + 000000D9H SFRSYM DATA BYTE PCA0MD + 000000DAH SFRSYM DATA BYTE PCA0CPM0 + 000000E9H SFRSYM DATA BYTE PCA0CPL1 + 000000F0H.4 SFRSYM DATA BIT B_B4 + 000000DBH SFRSYM DATA BYTE PCA0CPM1 + 000000EBH SFRSYM DATA BYTE PCA0CPL2 + 000000F0H.5 SFRSYM DATA BIT B_B5 + 000000DCH SFRSYM DATA BYTE PCA0CPM2 + 000000B8H SFRSYM DATA BYTE IP + 000000B9H SFRSYM DATA BYTE ADC0TK + 000000F0H.6 SFRSYM DATA BIT B_B6 + 000000C5H SFRSYM DATA WORD ADC0LT + 00000098H.5 SFRSYM DATA BIT SCON0_MCE + 000000F0H.7 SFRSYM DATA BIT B_B7 + 000000E1H SFRSYM DATA BYTE XBR0 + 000000C1H SFRSYM DATA BYTE SMB0CF + 000000E2H SFRSYM DATA BYTE XBR1 + 000000C0H.5 SFRSYM DATA BIT SMB0CN0_STA + 000000E3H SFRSYM DATA BYTE XBR2 + 000000BBH SFRSYM DATA BYTE ADC0MX + 000000E0H SFRSYM DATA BIT ACC_ACC0 + 000000D1H SFRSYM DATA BYTE REF0CN + 0000008EH SFRSYM DATA BYTE CKCON0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 22 + + + 000000E0H.1 SFRSYM DATA BIT ACC_ACC1 + 000000C9H SFRSYM DATA BYTE REG0CN + 000000DDH SFRSYM DATA BYTE CRC0IN + 000000C8H.2 SFRSYM DATA BIT TMR2CN0_TR2 + 000000E0H.2 SFRSYM DATA BIT ACC_ACC2 + 000000E0H.3 SFRSYM DATA BIT ACC_ACC3 + 00000081H SFRSYM DATA BYTE SP + 0000009DH SFRSYM DATA BYTE CMP0MD + 000000E0H.4 SFRSYM DATA BIT ACC_ACC4 + 000000B1H SFRSYM DATA BYTE LFO0CN + 000000ABH SFRSYM DATA BYTE CMP1MD + 000000D8H SFRSYM DATA BIT PCA0CN0_CCF0 + 000000E0H.5 SFRSYM DATA BIT ACC_ACC5 + 000000D8H.1 SFRSYM DATA BIT PCA0CN0_CCF1 + 000000E0H.6 SFRSYM DATA BIT ACC_ACC6 + 000000CCH SFRSYM DATA WORD TMR2 + 000000D8H.2 SFRSYM DATA BIT PCA0CN0_CCF2 + 000000E0H.7 SFRSYM DATA BIT ACC_ACC7 + 00000094H SFRSYM DATA WORD TMR3 + 000000C0H.3 SFRSYM DATA BIT SMB0CN0_ACKRQ + 000000FFH SFRSYM DATA BYTE VDM0CN + 000000F1H SFRSYM DATA BYTE P0MDIN + 00000098H.4 SFRSYM DATA BIT SCON0_REN + 000000ACH SFRSYM DATA BYTE SMB0TC + 000000F2H SFRSYM DATA BYTE P1MDIN + 000000C0H.4 SFRSYM DATA BIT SMB0CN0_STO + 000000FEH SFRSYM DATA BYTE P0MASK + 000000EEH SFRSYM DATA BYTE P1MASK + 000000D0H.3 SFRSYM DATA BIT PSW_RS0 + 000000D8H.7 SFRSYM DATA BIT PCA0CN0_CF + 0000009EH SFRSYM DATA BYTE PCA0CENT + 000000F8H.4 SFRSYM DATA BIT SPI0CN0_RXOVRN + 000000D0H.4 SFRSYM DATA BIT PSW_RS1 + 000000E8H.7 SFRSYM DATA BIT ADC0CN0_ADEN + 00000089H SFRSYM DATA BYTE TMOD + 00000088H SFRSYM DATA BYTE TCON + 000000CFH SFRSYM DATA BYTE CRC0FLIP + 000000D0H SFRSYM DATA BIT PSW_PARITY + 000000A8H.4 SFRSYM DATA BIT IE_ES0 + 0000009FH SFRSYM DATA BYTE CMP0MX + 000000A8H.1 SFRSYM DATA BIT IE_ET0 + 000000AAH SFRSYM DATA BYTE CMP1MX + 000000A8H.3 SFRSYM DATA BIT IE_ET1 + 000000D4H SFRSYM DATA BYTE P0SKIP + 000000A8H.5 SFRSYM DATA BIT IE_ET2 + 000000D5H SFRSYM DATA BYTE P1SKIP + 000000E8H SFRSYM DATA BYTE ADC0CN0 + 000000A8H SFRSYM DATA BIT IE_EX0 + 000000B2H SFRSYM DATA BYTE ADC0CN1 + 000000D8H.6 SFRSYM DATA BIT PCA0CN0_CR + 000000A8H.2 SFRSYM DATA BIT IE_EX1 + 00000098H.7 SFRSYM DATA BIT SCON0_SMODE + 000000B5H SFRSYM DATA BYTE DEVICEID + 000000A9H SFRSYM DATA BYTE CLKSEL + 000000F8H SFRSYM DATA BIT SPI0CN0_SPIEN + 000000F0H SFRSYM DATA BYTE B + 000000BEH SFRSYM DATA BYTE ADC0H + 000000D2H SFRSYM DATA BYTE CRC0AUTO + 000000E8H.6 SFRSYM DATA BIT ADC0CN0_ADBMEN + 000000CAH SFRSYM DATA WORD TMR2RL + 000000BDH SFRSYM DATA BYTE ADC0L + 00000092H SFRSYM DATA WORD TMR3RL + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 23 + + + 000000D8H SFRSYM DATA BYTE PCA0CN0 + 000000E0H SFRSYM DATA BYTE ACC + 000000FBH SFRSYM DATA WORD PCA0CP0 + 000000E9H SFRSYM DATA WORD PCA0CP1 + 000000EBH SFRSYM DATA WORD PCA0CP2 + 000000CEH SFRSYM DATA BYTE CRC0CN0 + 0000008CH SFRSYM DATA BYTE TH0 + 000000B8H.4 SFRSYM DATA BIT IP_PS0 + 0000008DH SFRSYM DATA BYTE TH1 + 000000FAH SFRSYM DATA BYTE PCA0H + 000000B8H.1 SFRSYM DATA BIT IP_PT0 + 000000B8H.3 SFRSYM DATA BIT IP_PT1 + 000000C0H.2 SFRSYM DATA BIT SMB0CN0_ARBLOST + 000000B8H.5 SFRSYM DATA BIT IP_PT2 + 0000008AH SFRSYM DATA BYTE TL0 + 000000F8H.1 SFRSYM DATA BIT SPI0CN0_TXBMT + 000000D0H.5 SFRSYM DATA BIT PSW_F0 + 000000A8H.6 SFRSYM DATA BIT IE_ESPI0 + 0000008BH SFRSYM DATA BYTE TL1 + 000000F9H SFRSYM DATA BYTE PCA0L + 000000C0H SFRSYM DATA BIT SMB0CN0_SI + 000000D0H.1 SFRSYM DATA BIT PSW_F1 + 00000080H SFRSYM DATA BIT P0_B0 + 000000B8H SFRSYM DATA BIT IP_PX0 + 00000090H SFRSYM DATA BIT P1_B0 + 00000080H.1 SFRSYM DATA BIT P0_B1 + 000000B8H.2 SFRSYM DATA BIT IP_PX1 + 0000009BH SFRSYM DATA BYTE CMP0CN0 + 00000088H.1 SFRSYM DATA BIT TCON_IE0 + 000000A0H SFRSYM DATA BIT P2_B0 + 00000090H.1 SFRSYM DATA BIT P1_B1 + 00000080H.2 SFRSYM DATA BIT P0_B2 + 000000BFH SFRSYM DATA BYTE CMP1CN0 + 00000088H.3 SFRSYM DATA BIT TCON_IE1 + 000000A0H.1 SFRSYM DATA BIT P2_B1 + 00000090H.2 SFRSYM DATA BIT P1_B2 + 00000080H.3 SFRSYM DATA BIT P0_B3 + 000000C0H SFRSYM DATA BYTE SMB0CN0 + 00000090H.3 SFRSYM DATA BIT P1_B3 + 00000080H.4 SFRSYM DATA BIT P0_B4 + 00000090H.4 SFRSYM DATA BIT P1_B4 + 00000080H.5 SFRSYM DATA BIT P0_B5 + 00000090H.5 SFRSYM DATA BIT P1_B5 + 00000080H.6 SFRSYM DATA BIT P0_B6 + 00000090H.6 SFRSYM DATA BIT P1_B6 + 00000080H.7 SFRSYM DATA BIT P0_B7 + 00000090H.7 SFRSYM DATA BIT P1_B7 + 00000083H SFRSYM DATA BYTE DPH + 000000C4H SFRSYM DATA BYTE ADC0GTH + 000000C8H.7 SFRSYM DATA BIT TMR2CN0_TF2H + 000000C8H.3 SFRSYM DATA BIT TMR2CN0_T2SPLIT + 000000D0H.6 SFRSYM DATA BIT PSW_AC + 000000F8H SFRSYM DATA BYTE SPI0CN0 + 000000C7H SFRSYM DATA BYTE HFO0CAL + 00000088H.5 SFRSYM DATA BIT TCON_TF0 + 00000098H SFRSYM DATA BIT SCON0_RI + 00000082H SFRSYM DATA BYTE DPL + 00000088H.7 SFRSYM DATA BIT TCON_TF1 + 00000099H SFRSYM DATA BYTE SBUF0 + 00000087H SFRSYM DATA BYTE PCON0 + 000000C3H SFRSYM DATA BYTE ADC0GTL + 000000C8H.6 SFRSYM DATA BIT TMR2CN0_TF2L + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 24 + + + 00000098H.1 SFRSYM DATA BIT SCON0_TI + 000000E8H SFRSYM DATA BIT ADC0CN0_ADCM0 + 000000C6H SFRSYM DATA BYTE ADC0LTH + 00000088H SFRSYM DATA BIT TCON_IT0 + 000000E8H.1 SFRSYM DATA BIT ADC0CN0_ADCM1 + 000000EFH SFRSYM DATA BYTE RSTSRC + 000000FDH SFRSYM DATA BYTE P0MAT + 000000DEH SFRSYM DATA BYTE CRC0DAT + 00000088H.2 SFRSYM DATA BIT TCON_IT1 + 000000E8H.2 SFRSYM DATA BIT ADC0CN0_ADCM2 + 00000098H SFRSYM DATA BYTE SCON0 + 000000F6H SFRSYM DATA BYTE PRTDRV + 000000EDH SFRSYM DATA BYTE P1MAT + 000000E8H.3 SFRSYM DATA BIT ADC0CN0_ADWINT + 000000E8H.4 SFRSYM DATA BIT ADC0CN0_ADBUSY + 000000D6H SFRSYM DATA BYTE SMB0ADM + 000000C5H SFRSYM DATA BYTE ADC0LTL + 000000F8H.5 SFRSYM DATA BIT SPI0CN0_MODF + 000000B8H.6 SFRSYM DATA BIT IP_PSPI0 + 0000009CH SFRSYM DATA BYTE PCA0CLR + 000000C8H SFRSYM DATA BYTE TMR2CN0 + 00000091H SFRSYM DATA BYTE TMR3CN0 + 000000D7H SFRSYM DATA BYTE SMB0ADR + 00000088H.4 SFRSYM DATA BIT TCON_TR0 + 000000C8H.4 SFRSYM DATA BIT TMR2CN0_TF2CEN + 00000088H.6 SFRSYM DATA BIT TCON_TR1 + 000000C2H SFRSYM DATA BYTE SMB0DAT + 000000CDH SFRSYM DATA BYTE TMR2H + 000000A1H SFRSYM DATA BYTE SPI0CFG + 00000095H SFRSYM DATA BYTE TMR3H + 000000D3H SFRSYM DATA BYTE CRC0CNT + 00000096H SFRSYM DATA BYTE PCA0POL + 000000CCH SFRSYM DATA BYTE TMR2L + 000000F8H.7 SFRSYM DATA BIT SPI0CN0_SPIF + 00000094H SFRSYM DATA BYTE TMR3L + 000000DFH SFRSYM DATA BYTE ADC0PWR + 000000A8H.7 SFRSYM DATA BIT IE_EA + 000000C8H.5 SFRSYM DATA BIT TMR2CN0_TF2LEN + 000000F8H.6 SFRSYM DATA BIT SPI0CN0_WCOL + 000000F8H.2 SFRSYM DATA BIT SPI0CN0_NSSMD0 + 000000D0H.7 SFRSYM DATA BIT PSW_CY + 000000A3H SFRSYM DATA BYTE SPI0DAT + 000000F8H.3 SFRSYM DATA BIT SPI0CN0_NSSMD1 + 000000BDH SFRSYM DATA WORD ADC0 + 000000D0H SFRSYM DATA BYTE PSW + 000000F7H SFRSYM DATA BYTE PCA0PWM + 000000B6H SFRSYM DATA BYTE REVID + 000000B7H SFRSYM DATA BYTE FLKEY + 000000B3H SFRSYM DATA BYTE ADC0AC + + 01000998H BLOCK CODE --- LVL=0 + 01000998H LINE CODE --- #22 + 01000998H LINE CODE --- #24 + 0100099BH LINE CODE --- #25 + 0100099EH LINE CODE --- #26 + 010009A1H LINE CODE --- #27 + 010009A4H LINE CODE --- #28 + 010009A7H LINE CODE --- #29 + 010009AAH LINE CODE --- #30 + 010009ADH LINE CODE --- #31 + 010009B0H LINE CODE --- #32 + 010009B3H LINE CODE --- #33 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 25 + + + 010009B6H LINE CODE --- #34 + 010009B9H LINE CODE --- #35 + 010009BCH LINE CODE --- #36 + --- BLOCKEND --- --- LVL=0 + + 01000A79H BLOCK CODE --- LVL=0 + 01000A79H LINE CODE --- #44 + 01000A79H LINE CODE --- #47 + 01000A7CH LINE CODE --- #48 + 01000A7FH LINE CODE --- #51 + --- BLOCKEND --- --- LVL=0 + + 01000A80H BLOCK CODE --- LVL=0 + 01000A80H LINE CODE --- #56 + 01000A80H LINE CODE --- #71 + 01000A83H LINE CODE --- #91 + 01000A86H LINE CODE --- #102 + --- BLOCKEND --- --- LVL=0 + + 01000A87H BLOCK CODE --- LVL=0 + 01000A87H LINE CODE --- #107 + 01000A87H LINE CODE --- #121 + 01000A8AH LINE CODE --- #140 + 01000A8DH LINE CODE --- #151 + --- BLOCKEND --- --- LVL=0 + + 01000A5CH BLOCK CODE --- LVL=0 + 01000A5CH LINE CODE --- #156 + 01000A5CH LINE CODE --- #162 + 01000A5FH LINE CODE --- #179 + 01000A62H LINE CODE --- #192 + 01000A65H LINE CODE --- #196 + --- BLOCKEND --- --- LVL=0 + + 01000AA3H BLOCK CODE --- LVL=0 + 01000AA3H LINE CODE --- #201 + 01000AA3H LINE CODE --- #207 + 01000AA6H LINE CODE --- #210 + --- BLOCKEND --- --- LVL=0 + + 01000A25H BLOCK CODE --- LVL=0 + 01000A25H BLOCK CODE NEAR LAB LVL=1 + 00000007H SYMBOL DATA BYTE TCON_save + --- BLOCKEND --- --- LVL=1 + 01000A25H LINE CODE --- #215 + 01000A25H LINE CODE --- #219 + 01000A27H LINE CODE --- #221 + 01000A2AH LINE CODE --- #229 + 01000A2DH LINE CODE --- #239 + 01000A30H LINE CODE --- #247 + 01000A3AH LINE CODE --- #251 + --- BLOCKEND --- --- LVL=0 + + 01000A3BH BLOCK CODE --- LVL=0 + 01000A3BH BLOCK CODE NEAR LAB LVL=1 + 00000007H SYMBOL DATA BYTE TMR3CN0_TR3_save + --- BLOCKEND --- --- LVL=1 + 01000A3BH LINE CODE --- #256 + 01000A3BH LINE CODE --- #260 + 01000A3FH LINE CODE --- #262 + 01000A42H LINE CODE --- #272 + 01000A45H LINE CODE --- #279 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 26 + + + 01000A48H LINE CODE --- #286 + 01000A4BH LINE CODE --- #293 + 01000A4EH LINE CODE --- #301 + 01000A50H LINE CODE --- #304 + --- BLOCKEND --- --- LVL=0 + + 01000A66H BLOCK CODE --- LVL=0 + 01000A66H LINE CODE --- #309 + 01000A66H LINE CODE --- #320 + 01000A69H LINE CODE --- #335 + 01000A6CH LINE CODE --- #344 + 01000A6FH LINE CODE --- #347 + --- BLOCKEND --- --- LVL=0 + + 0100005EH BLOCK CODE --- LVL=0 + 0100005EH LINE CODE --- #352 + 0100005EH LINE CODE --- #354 + 01000060H LINE CODE --- #364 + 01000063H LINE CODE --- #378 + 01000066H LINE CODE --- #390 + 01000069H LINE CODE --- #398 + 0100006CH LINE CODE --- #404 + --- BLOCKEND --- --- LVL=0 + + 01000A8EH BLOCK CODE --- LVL=0 + 01000A8EH LINE CODE --- #409 + 01000A8EH LINE CODE --- #412 + 01000A91H LINE CODE --- #426 + 01000A94H LINE CODE --- #444 + --- BLOCKEND --- --- LVL=0 + + 01000A95H BLOCK CODE --- LVL=0 + 01000A95H LINE CODE --- #449 + 01000A95H LINE CODE --- #452 + 01000A98H LINE CODE --- #466 + 01000A9BH LINE CODE --- #484 + --- BLOCKEND --- --- LVL=0 + + 01000AA7H BLOCK CODE --- LVL=0 + 01000AA7H LINE CODE --- #489 + 01000AA7H LINE CODE --- #494 + 01000AAAH LINE CODE --- #497 + --- BLOCKEND --- --- LVL=0 + + 01000A9CH BLOCK CODE --- LVL=0 + 01000A9CH LINE CODE --- #502 + 01000A9CH LINE CODE --- #514 + 01000A9FH LINE CODE --- #533 + 01000AA2H LINE CODE --- #541 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- RF_BRIDGE_MAIN + 0000001DH PUBLIC DATA BYTE uart_state + 00000020H.0 PUBLIC BIT BIT Sniffing + 0000001CH PUBLIC DATA BYTE uart_command + 0100025CH PUBLIC CODE --- main + 01000022H PUBLIC CODE --- SiLabs_Startup + 000000A2H SFRSYM DATA BYTE SPI0CKR + 00000080H SFRSYM DATA BYTE P0 + 000000D0H.2 SFRSYM DATA BIT PSW_OV + 00000090H SFRSYM DATA BYTE P1 + 00000097H SFRSYM DATA BYTE WDTCN + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 27 + + + 000000A0H SFRSYM DATA BYTE P2 + 000000BCH SFRSYM DATA BYTE ADC0CF + 000000C8H SFRSYM DATA BIT TMR2CN0_T2XCLK + 000000C0H.7 SFRSYM DATA BIT SMB0CN0_MASTER + 000000F9H SFRSYM DATA WORD PCA0 + 000000E6H SFRSYM DATA BYTE EIE1 + 000000C0H.1 SFRSYM DATA BIT SMB0CN0_ACK + 0000008FH SFRSYM DATA BYTE PSCTL + 000000E4H SFRSYM DATA BYTE IT01CF + 000000C0H.6 SFRSYM DATA BIT SMB0CN0_TXMODE + 000000ADH SFRSYM DATA BYTE DERIVID + 000000A4H SFRSYM DATA BYTE P0MDOUT + 000000A5H SFRSYM DATA BYTE P1MDOUT + 000000E8H.5 SFRSYM DATA BIT ADC0CN0_ADINT + 000000CBH SFRSYM DATA BYTE TMR2RLH + 000000A6H SFRSYM DATA BYTE P2MDOUT + 000000A8H SFRSYM DATA BYTE IE + 00000093H SFRSYM DATA BYTE TMR3RLH + 000000F3H SFRSYM DATA BYTE EIP1 + 00000098H.2 SFRSYM DATA BIT SCON0_RB8 + 000000CAH SFRSYM DATA BYTE TMR2RLL + 000000FCH SFRSYM DATA BYTE PCA0CPH0 + 00000092H SFRSYM DATA BYTE TMR3RLL + 000000EAH SFRSYM DATA BYTE PCA0CPH1 + 00000098H.3 SFRSYM DATA BIT SCON0_TB8 + 000000F0H SFRSYM DATA BIT B_B0 + 00000082H SFRSYM DATA WORD DP + 000000ECH SFRSYM DATA BYTE PCA0CPH2 + 000000F0H.1 SFRSYM DATA BIT B_B1 + 000000C3H SFRSYM DATA WORD ADC0GT + 000000F0H.2 SFRSYM DATA BIT B_B2 + 000000FBH SFRSYM DATA BYTE PCA0CPL0 + 000000F0H.3 SFRSYM DATA BIT B_B3 + 000000D9H SFRSYM DATA BYTE PCA0MD + 000000DAH SFRSYM DATA BYTE PCA0CPM0 + 000000E9H SFRSYM DATA BYTE PCA0CPL1 + 000000F0H.4 SFRSYM DATA BIT B_B4 + 000000DBH SFRSYM DATA BYTE PCA0CPM1 + 000000EBH SFRSYM DATA BYTE PCA0CPL2 + 000000F0H.5 SFRSYM DATA BIT B_B5 + 000000DCH SFRSYM DATA BYTE PCA0CPM2 + 000000B8H SFRSYM DATA BYTE IP + 000000B9H SFRSYM DATA BYTE ADC0TK + 000000F0H.6 SFRSYM DATA BIT B_B6 + 000000C5H SFRSYM DATA WORD ADC0LT + 00000098H.5 SFRSYM DATA BIT SCON0_MCE + 000000F0H.7 SFRSYM DATA BIT B_B7 + 000000E1H SFRSYM DATA BYTE XBR0 + 000000C1H SFRSYM DATA BYTE SMB0CF + 000000E2H SFRSYM DATA BYTE XBR1 + 000000C0H.5 SFRSYM DATA BIT SMB0CN0_STA + 000000E3H SFRSYM DATA BYTE XBR2 + 000000BBH SFRSYM DATA BYTE ADC0MX + 000000E0H SFRSYM DATA BIT ACC_ACC0 + 000000D1H SFRSYM DATA BYTE REF0CN + 0000008EH SFRSYM DATA BYTE CKCON0 + 000000E0H.1 SFRSYM DATA BIT ACC_ACC1 + 000000C9H SFRSYM DATA BYTE REG0CN + 000000DDH SFRSYM DATA BYTE CRC0IN + 000000C8H.2 SFRSYM DATA BIT TMR2CN0_TR2 + 000000E0H.2 SFRSYM DATA BIT ACC_ACC2 + 000000E0H.3 SFRSYM DATA BIT ACC_ACC3 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 28 + + + 00000081H SFRSYM DATA BYTE SP + 0000009DH SFRSYM DATA BYTE CMP0MD + 000000E0H.4 SFRSYM DATA BIT ACC_ACC4 + 000000B1H SFRSYM DATA BYTE LFO0CN + 000000ABH SFRSYM DATA BYTE CMP1MD + 000000D8H SFRSYM DATA BIT PCA0CN0_CCF0 + 000000E0H.5 SFRSYM DATA BIT ACC_ACC5 + 000000D8H.1 SFRSYM DATA BIT PCA0CN0_CCF1 + 000000E0H.6 SFRSYM DATA BIT ACC_ACC6 + 000000CCH SFRSYM DATA WORD TMR2 + 000000D8H.2 SFRSYM DATA BIT PCA0CN0_CCF2 + 000000E0H.7 SFRSYM DATA BIT ACC_ACC7 + 00000094H SFRSYM DATA WORD TMR3 + 000000C0H.3 SFRSYM DATA BIT SMB0CN0_ACKRQ + 000000FFH SFRSYM DATA BYTE VDM0CN + 000000F1H SFRSYM DATA BYTE P0MDIN + 00000098H.4 SFRSYM DATA BIT SCON0_REN + 000000ACH SFRSYM DATA BYTE SMB0TC + 000000F2H SFRSYM DATA BYTE P1MDIN + 000000C0H.4 SFRSYM DATA BIT SMB0CN0_STO + 000000FEH SFRSYM DATA BYTE P0MASK + 000000EEH SFRSYM DATA BYTE P1MASK + 000000D0H.3 SFRSYM DATA BIT PSW_RS0 + 000000D8H.7 SFRSYM DATA BIT PCA0CN0_CF + 0000009EH SFRSYM DATA BYTE PCA0CENT + 000000F8H.4 SFRSYM DATA BIT SPI0CN0_RXOVRN + 000000D0H.4 SFRSYM DATA BIT PSW_RS1 + 000000E8H.7 SFRSYM DATA BIT ADC0CN0_ADEN + 00000089H SFRSYM DATA BYTE TMOD + 00000088H SFRSYM DATA BYTE TCON + 000000CFH SFRSYM DATA BYTE CRC0FLIP + 000000D0H SFRSYM DATA BIT PSW_PARITY + 000000A8H.4 SFRSYM DATA BIT IE_ES0 + 0000009FH SFRSYM DATA BYTE CMP0MX + 000000A8H.1 SFRSYM DATA BIT IE_ET0 + 000000AAH SFRSYM DATA BYTE CMP1MX + 000000A8H.3 SFRSYM DATA BIT IE_ET1 + 000000D4H SFRSYM DATA BYTE P0SKIP + 000000A8H.5 SFRSYM DATA BIT IE_ET2 + 000000D5H SFRSYM DATA BYTE P1SKIP + 000000E8H SFRSYM DATA BYTE ADC0CN0 + 000000A8H SFRSYM DATA BIT IE_EX0 + 000000B2H SFRSYM DATA BYTE ADC0CN1 + 000000D8H.6 SFRSYM DATA BIT PCA0CN0_CR + 000000A8H.2 SFRSYM DATA BIT IE_EX1 + 00000098H.7 SFRSYM DATA BIT SCON0_SMODE + 000000B5H SFRSYM DATA BYTE DEVICEID + 000000A9H SFRSYM DATA BYTE CLKSEL + 000000F8H SFRSYM DATA BIT SPI0CN0_SPIEN + 000000F0H SFRSYM DATA BYTE B + 000000BEH SFRSYM DATA BYTE ADC0H + 000000D2H SFRSYM DATA BYTE CRC0AUTO + 000000E8H.6 SFRSYM DATA BIT ADC0CN0_ADBMEN + 000000CAH SFRSYM DATA WORD TMR2RL + 000000BDH SFRSYM DATA BYTE ADC0L + 00000092H SFRSYM DATA WORD TMR3RL + 000000D8H SFRSYM DATA BYTE PCA0CN0 + 000000E0H SFRSYM DATA BYTE ACC + 000000FBH SFRSYM DATA WORD PCA0CP0 + 000000E9H SFRSYM DATA WORD PCA0CP1 + 000000EBH SFRSYM DATA WORD PCA0CP2 + 000000CEH SFRSYM DATA BYTE CRC0CN0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 29 + + + 0000008CH SFRSYM DATA BYTE TH0 + 00000090H.3 SFRSYM DATA BIT R_DATA + 000000B8H.4 SFRSYM DATA BIT IP_PS0 + 0000008DH SFRSYM DATA BYTE TH1 + 000000FAH SFRSYM DATA BYTE PCA0H + 000000B8H.1 SFRSYM DATA BIT IP_PT0 + 00000080H SFRSYM DATA BIT T_DATA + 000000B8H.3 SFRSYM DATA BIT IP_PT1 + 000000C0H.2 SFRSYM DATA BIT SMB0CN0_ARBLOST + 000000B8H.5 SFRSYM DATA BIT IP_PT2 + 0000008AH SFRSYM DATA BYTE TL0 + 000000F8H.1 SFRSYM DATA BIT SPI0CN0_TXBMT + 000000D0H.5 SFRSYM DATA BIT PSW_F0 + 000000A8H.6 SFRSYM DATA BIT IE_ESPI0 + 0000008BH SFRSYM DATA BYTE TL1 + 000000F9H SFRSYM DATA BYTE PCA0L + 000000C0H SFRSYM DATA BIT SMB0CN0_SI + 000000D0H.1 SFRSYM DATA BIT PSW_F1 + 00000080H SFRSYM DATA BIT P0_B0 + 000000B8H SFRSYM DATA BIT IP_PX0 + 00000090H SFRSYM DATA BIT P1_B0 + 00000080H.1 SFRSYM DATA BIT P0_B1 + 000000B8H.2 SFRSYM DATA BIT IP_PX1 + 0000009BH SFRSYM DATA BYTE CMP0CN0 + 00000088H.1 SFRSYM DATA BIT TCON_IE0 + 000000A0H SFRSYM DATA BIT P2_B0 + 00000090H.1 SFRSYM DATA BIT P1_B1 + 00000080H.2 SFRSYM DATA BIT P0_B2 + 000000BFH SFRSYM DATA BYTE CMP1CN0 + 00000090H SFRSYM DATA BIT LED + 00000088H.3 SFRSYM DATA BIT TCON_IE1 + 000000A0H.1 SFRSYM DATA BIT P2_B1 + 00000090H.2 SFRSYM DATA BIT P1_B2 + 00000080H.3 SFRSYM DATA BIT P0_B3 + 000000C0H SFRSYM DATA BYTE SMB0CN0 + 00000090H.3 SFRSYM DATA BIT P1_B3 + 00000080H.4 SFRSYM DATA BIT P0_B4 + 00000090H.4 SFRSYM DATA BIT P1_B4 + 00000080H.5 SFRSYM DATA BIT P0_B5 + 00000090H.5 SFRSYM DATA BIT P1_B5 + 00000080H.6 SFRSYM DATA BIT P0_B6 + 00000090H.6 SFRSYM DATA BIT P1_B6 + 00000080H.7 SFRSYM DATA BIT P0_B7 + 00000090H.7 SFRSYM DATA BIT P1_B7 + 00000083H SFRSYM DATA BYTE DPH + 000000C4H SFRSYM DATA BYTE ADC0GTH + 000000C8H.7 SFRSYM DATA BIT TMR2CN0_TF2H + 000000C8H.3 SFRSYM DATA BIT TMR2CN0_T2SPLIT + 000000D0H.6 SFRSYM DATA BIT PSW_AC + 000000F8H SFRSYM DATA BYTE SPI0CN0 + 000000C7H SFRSYM DATA BYTE HFO0CAL + 00000088H.5 SFRSYM DATA BIT TCON_TF0 + 00000098H SFRSYM DATA BIT SCON0_RI + 00000082H SFRSYM DATA BYTE DPL + 00000088H.7 SFRSYM DATA BIT TCON_TF1 + 00000099H SFRSYM DATA BYTE SBUF0 + 00000087H SFRSYM DATA BYTE PCON0 + 000000C3H SFRSYM DATA BYTE ADC0GTL + 000000C8H.6 SFRSYM DATA BIT TMR2CN0_TF2L + 00000098H.1 SFRSYM DATA BIT SCON0_TI + 000000E8H SFRSYM DATA BIT ADC0CN0_ADCM0 + 000000C6H SFRSYM DATA BYTE ADC0LTH + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 30 + + + 00000088H SFRSYM DATA BIT TCON_IT0 + 000000E8H.1 SFRSYM DATA BIT ADC0CN0_ADCM1 + 000000EFH SFRSYM DATA BYTE RSTSRC + 000000FDH SFRSYM DATA BYTE P0MAT + 000000DEH SFRSYM DATA BYTE CRC0DAT + 00000090H.6 SFRSYM DATA BIT BUZZER + 00000088H.2 SFRSYM DATA BIT TCON_IT1 + 000000E8H.2 SFRSYM DATA BIT ADC0CN0_ADCM2 + 00000098H SFRSYM DATA BYTE SCON0 + 000000F6H SFRSYM DATA BYTE PRTDRV + 000000EDH SFRSYM DATA BYTE P1MAT + 000000E8H.3 SFRSYM DATA BIT ADC0CN0_ADWINT + 000000E8H.4 SFRSYM DATA BIT ADC0CN0_ADBUSY + 000000D6H SFRSYM DATA BYTE SMB0ADM + 000000C5H SFRSYM DATA BYTE ADC0LTL + 000000F8H.5 SFRSYM DATA BIT SPI0CN0_MODF + 000000B8H.6 SFRSYM DATA BIT IP_PSPI0 + 0000009CH SFRSYM DATA BYTE PCA0CLR + 000000C8H SFRSYM DATA BYTE TMR2CN0 + 00000091H SFRSYM DATA BYTE TMR3CN0 + 000000D7H SFRSYM DATA BYTE SMB0ADR + 00000088H.4 SFRSYM DATA BIT TCON_TR0 + 000000C8H.4 SFRSYM DATA BIT TMR2CN0_TF2CEN + 00000088H.6 SFRSYM DATA BIT TCON_TR1 + 000000C2H SFRSYM DATA BYTE SMB0DAT + 000000CDH SFRSYM DATA BYTE TMR2H + 000000A1H SFRSYM DATA BYTE SPI0CFG + 00000095H SFRSYM DATA BYTE TMR3H + 000000D3H SFRSYM DATA BYTE CRC0CNT + 00000096H SFRSYM DATA BYTE PCA0POL + 000000CCH SFRSYM DATA BYTE TMR2L + 000000F8H.7 SFRSYM DATA BIT SPI0CN0_SPIF + 00000094H SFRSYM DATA BYTE TMR3L + 000000DFH SFRSYM DATA BYTE ADC0PWR + 000000A8H.7 SFRSYM DATA BIT IE_EA + 000000C8H.5 SFRSYM DATA BIT TMR2CN0_TF2LEN + 000000F8H.6 SFRSYM DATA BIT SPI0CN0_WCOL + 000000F8H.2 SFRSYM DATA BIT SPI0CN0_NSSMD0 + 000000D0H.7 SFRSYM DATA BIT PSW_CY + 000000A3H SFRSYM DATA BYTE SPI0DAT + 000000F8H.3 SFRSYM DATA BIT SPI0CN0_NSSMD1 + 000000BDH SFRSYM DATA WORD ADC0 + 000000D0H SFRSYM DATA BYTE PSW + 000000F7H SFRSYM DATA BYTE PCA0PWM + 000000B6H SFRSYM DATA BYTE REVID + 000000B7H SFRSYM DATA BYTE FLKEY + 000000B3H SFRSYM DATA BYTE ADC0AC + + 01000022H BLOCK CODE --- LVL=0 + 01000022H LINE CODE --- #34 + 01000022H LINE CODE --- #35 + 01000022H LINE CODE --- #37 + --- BLOCKEND --- --- LVL=0 + + 0100025CH BLOCK CODE --- LVL=0 + 0100027AH BLOCK CODE NEAR LAB LVL=1 + 00000043H SYMBOL DATA WORD rxdata + 00000045H SYMBOL DATA BYTE len + 00000046H SYMBOL DATA BYTE position + 01000350H BLOCK CODE NEAR LAB LVL=2 + 00000047H SYMBOL DATA BYTE used_protocol + --- BLOCKEND --- --- LVL=2 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 31 + + + --- BLOCKEND --- --- LVL=1 + 0100025CH LINE CODE --- #42 + 0100025CH LINE CODE --- #43 + 0100025CH LINE CODE --- #45 + 0100025FH LINE CODE --- #48 + 01000261H LINE CODE --- #49 + 01000263H LINE CODE --- #51 + 01000265H LINE CODE --- #54 + 0100026DH LINE CODE --- #57 + 01000270H LINE CODE --- #58 + 01000275H LINE CODE --- #60 + 01000278H LINE CODE --- #63 + 0100027AH LINE CODE --- #65 + 0100027AH LINE CODE --- #66 + 0100027AH LINE CODE --- #74 + 01000281H LINE CODE --- #76 + 0100028EH LINE CODE --- #77 + 0100028EH LINE CODE --- #79 + 010002A6H LINE CODE --- #80 + 010002A6H LINE CODE --- #82 + 010002A6H LINE CODE --- #83 + 010002AFH LINE CODE --- #84 + 010002B2H LINE CODE --- #85 + 010002B5H LINE CODE --- #88 + 010002B5H LINE CODE --- #89 + 010002B9H LINE CODE --- #90 + 010002BCH LINE CODE --- #93 + 010002CCH LINE CODE --- #94 + 010002CCH LINE CODE --- #95 + 010002CCH LINE CODE --- #96 + 010002D6H LINE CODE --- #97 + 010002D8H LINE CODE --- #99 + 010002DBH LINE CODE --- #101 + 010002E0H LINE CODE --- #102 + 010002E2H LINE CODE --- #103 + 010002E4H LINE CODE --- #104 + 010002E4H LINE CODE --- #105 + 010002E7H LINE CODE --- #106 + 010002E9H LINE CODE --- #107 + 010002E9H LINE CODE --- #108 + 010002ECH LINE CODE --- #109 + 010002F1H LINE CODE --- #110 + 010002F3H LINE CODE --- #111 + 010002F3H LINE CODE --- #112 + 010002F6H LINE CODE --- #113 + 010002F8H LINE CODE --- #117 + 010002F8H LINE CODE --- #118 + 010002FBH LINE CODE --- #119 + 010002FDH LINE CODE --- #120 + 010002FFH LINE CODE --- #121 + 010002FFH LINE CODE --- #122 + 010002FFH LINE CODE --- #125 + 010002FFH LINE CODE --- #126 + 01000302H LINE CODE --- #127 + 01000306H LINE CODE --- #128 + 0100030DH LINE CODE --- #129 + 01000312H LINE CODE --- #135 + 01000312H LINE CODE --- #136 + 01000320H LINE CODE --- #137 + 01000322H LINE CODE --- #139 + 01000327H LINE CODE --- #140 + 0100032AH LINE CODE --- #141 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 32 + + + 0100032CH LINE CODE --- #144 + 0100032CH LINE CODE --- #145 + 01000332H LINE CODE --- #146 + 01000332H LINE CODE --- #147 + 01000334H LINE CODE --- #149 + 01000339H LINE CODE --- #150 + 01000339H LINE CODE --- #151 + 01000339H LINE CODE --- #152 + 01000339H LINE CODE --- #153 + 01000339H LINE CODE --- #158 + 01000346H LINE CODE --- #159 + 01000346H LINE CODE --- #160 + 01000346H LINE CODE --- #162 + 01000350H LINE CODE --- #163 + 01000350H LINE CODE --- #164 + 01000354H LINE CODE --- #165 + 0100035AH LINE CODE --- #168 + 0100035FH LINE CODE --- #169 + 0100035FH LINE CODE --- #170 + 01000362H LINE CODE --- #175 + 01000362H LINE CODE --- #177 + 01000369H LINE CODE --- #178 + 01000369H LINE CODE --- #180 + 0100036FH LINE CODE --- #181 + 01000372H LINE CODE --- #183 + 0100037FH LINE CODE --- #185 + 01000382H LINE CODE --- #186 + 01000382H LINE CODE --- #187 + 01000388H LINE CODE --- #188 + 0100038BH LINE CODE --- #189 + 01000391H LINE CODE --- #190 + 01000395H LINE CODE --- #192 + 010003B6H LINE CODE --- #193 + 010003B6H LINE CODE --- #195 + 010003B9H LINE CODE --- #196 + 010003BBH LINE CODE --- #198 + 010003BBH LINE CODE --- #200 + 010003C7H LINE CODE --- #201 + 010003C7H LINE CODE --- #203 + 010003CFH LINE CODE --- #204 + 010003D1H LINE CODE --- #205 + 010003D1H LINE CODE --- #207 + 010003D4H LINE CODE --- #208 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- RF_HANDLING + 020000D7H PUBLIC XDATA BYTE protocol_index + 020000D6H PUBLIC XDATA BYTE DUTY_CYLCE_LOW + 020000D5H PUBLIC XDATA BYTE actual_bit_of_byte + 020000D3H PUBLIC XDATA WORD Timer_3_Timeout + 020000D2H PUBLIC XDATA BYTE rf_state + 020000D1H PUBLIC XDATA BYTE RF_DATA_STATUS + 020000D0H PUBLIC XDATA BYTE sniffing_is_on + 020000CFH PUBLIC XDATA BYTE actual_bit + 020000CEH PUBLIC XDATA BYTE DUTY_CYCLE_HIGH + 020000CDH PUBLIC XDATA BYTE actual_byte + 0200008DH PUBLIC XDATA --- RF_DATA + 01000026H PUBLIC CODE --- TIMER3_ISR + 0100006DH PUBLIC CODE --- PCA0_StopSniffing + 010009BFH PUBLIC CODE --- PCA0_DoSniffing + 01000003H PUBLIC CODE --- PCA0_StopTransmit + 0100053EH PUBLIC CODE --- _PCA0_DoTransmit + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 33 + + + 010007D1H PUBLIC CODE --- _SendRF_SYNC + 01000AB2H PUBLIC CODE --- PCA0_channel2EventCb + 010003D7H PUBLIC CODE --- PCA0_channel1EventCb + 0100083BH PUBLIC CODE --- PCA0_channel0EventCb + 01000AB1H PUBLIC CODE --- PCA0_intermediateOverflowCb + 0100005AH PUBLIC CODE --- PCA0_overflowCb + 000000A2H SFRSYM DATA BYTE SPI0CKR + 00000080H SFRSYM DATA BYTE P0 + 000000D0H.2 SFRSYM DATA BIT PSW_OV + 00000090H SFRSYM DATA BYTE P1 + 00000097H SFRSYM DATA BYTE WDTCN + 000000A0H SFRSYM DATA BYTE P2 + 000000BCH SFRSYM DATA BYTE ADC0CF + 000000C8H SFRSYM DATA BIT TMR2CN0_T2XCLK + 000000C0H.7 SFRSYM DATA BIT SMB0CN0_MASTER + 000000F9H SFRSYM DATA WORD PCA0 + 000000E6H SFRSYM DATA BYTE EIE1 + 000000C0H.1 SFRSYM DATA BIT SMB0CN0_ACK + 0000008FH SFRSYM DATA BYTE PSCTL + 000000E4H SFRSYM DATA BYTE IT01CF + 000000C0H.6 SFRSYM DATA BIT SMB0CN0_TXMODE + 000000ADH SFRSYM DATA BYTE DERIVID + 000000A4H SFRSYM DATA BYTE P0MDOUT + 000000A5H SFRSYM DATA BYTE P1MDOUT + 000000E8H.5 SFRSYM DATA BIT ADC0CN0_ADINT + 000000CBH SFRSYM DATA BYTE TMR2RLH + 000000A6H SFRSYM DATA BYTE P2MDOUT + 000000A8H SFRSYM DATA BYTE IE + 00000093H SFRSYM DATA BYTE TMR3RLH + 000000F3H SFRSYM DATA BYTE EIP1 + 00000098H.2 SFRSYM DATA BIT SCON0_RB8 + 000000CAH SFRSYM DATA BYTE TMR2RLL + 000000FCH SFRSYM DATA BYTE PCA0CPH0 + 00000092H SFRSYM DATA BYTE TMR3RLL + 000000EAH SFRSYM DATA BYTE PCA0CPH1 + 00000098H.3 SFRSYM DATA BIT SCON0_TB8 + 000000F0H SFRSYM DATA BIT B_B0 + 00000082H SFRSYM DATA WORD DP + 000000ECH SFRSYM DATA BYTE PCA0CPH2 + 000000F0H.1 SFRSYM DATA BIT B_B1 + 000000C3H SFRSYM DATA WORD ADC0GT + 000000F0H.2 SFRSYM DATA BIT B_B2 + 000000FBH SFRSYM DATA BYTE PCA0CPL0 + 000000F0H.3 SFRSYM DATA BIT B_B3 + 000000D9H SFRSYM DATA BYTE PCA0MD + 000000DAH SFRSYM DATA BYTE PCA0CPM0 + 000000E9H SFRSYM DATA BYTE PCA0CPL1 + 000000F0H.4 SFRSYM DATA BIT B_B4 + 000000DBH SFRSYM DATA BYTE PCA0CPM1 + 000000EBH SFRSYM DATA BYTE PCA0CPL2 + 000000F0H.5 SFRSYM DATA BIT B_B5 + 000000DCH SFRSYM DATA BYTE PCA0CPM2 + 000000B8H SFRSYM DATA BYTE IP + 000000B9H SFRSYM DATA BYTE ADC0TK + 000000F0H.6 SFRSYM DATA BIT B_B6 + 000000C5H SFRSYM DATA WORD ADC0LT + 00000098H.5 SFRSYM DATA BIT SCON0_MCE + 000000F0H.7 SFRSYM DATA BIT B_B7 + 000000E1H SFRSYM DATA BYTE XBR0 + 000000C1H SFRSYM DATA BYTE SMB0CF + 000000E2H SFRSYM DATA BYTE XBR1 + 000000C0H.5 SFRSYM DATA BIT SMB0CN0_STA + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 34 + + + 000000E3H SFRSYM DATA BYTE XBR2 + 000000BBH SFRSYM DATA BYTE ADC0MX + 000000E0H SFRSYM DATA BIT ACC_ACC0 + 000000D1H SFRSYM DATA BYTE REF0CN + 0000008EH SFRSYM DATA BYTE CKCON0 + 000000E0H.1 SFRSYM DATA BIT ACC_ACC1 + 000000C9H SFRSYM DATA BYTE REG0CN + 000000DDH SFRSYM DATA BYTE CRC0IN + 000000C8H.2 SFRSYM DATA BIT TMR2CN0_TR2 + 000000E0H.2 SFRSYM DATA BIT ACC_ACC2 + 000000E0H.3 SFRSYM DATA BIT ACC_ACC3 + 00000081H SFRSYM DATA BYTE SP + 0000009DH SFRSYM DATA BYTE CMP0MD + 000000E0H.4 SFRSYM DATA BIT ACC_ACC4 + 000000B1H SFRSYM DATA BYTE LFO0CN + 000000ABH SFRSYM DATA BYTE CMP1MD + 000000D8H SFRSYM DATA BIT PCA0CN0_CCF0 + 000000E0H.5 SFRSYM DATA BIT ACC_ACC5 + 000000D8H.1 SFRSYM DATA BIT PCA0CN0_CCF1 + 000000E0H.6 SFRSYM DATA BIT ACC_ACC6 + 000000CCH SFRSYM DATA WORD TMR2 + 000000D8H.2 SFRSYM DATA BIT PCA0CN0_CCF2 + 000000E0H.7 SFRSYM DATA BIT ACC_ACC7 + 00000094H SFRSYM DATA WORD TMR3 + 000000C0H.3 SFRSYM DATA BIT SMB0CN0_ACKRQ + 000000FFH SFRSYM DATA BYTE VDM0CN + 000000F1H SFRSYM DATA BYTE P0MDIN + 00000098H.4 SFRSYM DATA BIT SCON0_REN + 000000ACH SFRSYM DATA BYTE SMB0TC + 000000F2H SFRSYM DATA BYTE P1MDIN + 000000C0H.4 SFRSYM DATA BIT SMB0CN0_STO + 000000FEH SFRSYM DATA BYTE P0MASK + 000000EEH SFRSYM DATA BYTE P1MASK + 000000D0H.3 SFRSYM DATA BIT PSW_RS0 + 000000D8H.7 SFRSYM DATA BIT PCA0CN0_CF + 0000009EH SFRSYM DATA BYTE PCA0CENT + 000000F8H.4 SFRSYM DATA BIT SPI0CN0_RXOVRN + 000000D0H.4 SFRSYM DATA BIT PSW_RS1 + 000000E8H.7 SFRSYM DATA BIT ADC0CN0_ADEN + 00000089H SFRSYM DATA BYTE TMOD + 00000088H SFRSYM DATA BYTE TCON + 000000CFH SFRSYM DATA BYTE CRC0FLIP + 000000D0H SFRSYM DATA BIT PSW_PARITY + 000000A8H.4 SFRSYM DATA BIT IE_ES0 + 0000009FH SFRSYM DATA BYTE CMP0MX + 000000A8H.1 SFRSYM DATA BIT IE_ET0 + 000000AAH SFRSYM DATA BYTE CMP1MX + 000000A8H.3 SFRSYM DATA BIT IE_ET1 + 000000D4H SFRSYM DATA BYTE P0SKIP + 000000A8H.5 SFRSYM DATA BIT IE_ET2 + 000000D5H SFRSYM DATA BYTE P1SKIP + 000000E8H SFRSYM DATA BYTE ADC0CN0 + 000000A8H SFRSYM DATA BIT IE_EX0 + 000000B2H SFRSYM DATA BYTE ADC0CN1 + 000000D8H.6 SFRSYM DATA BIT PCA0CN0_CR + 000000A8H.2 SFRSYM DATA BIT IE_EX1 + 00000098H.7 SFRSYM DATA BIT SCON0_SMODE + 000000B5H SFRSYM DATA BYTE DEVICEID + 000000A9H SFRSYM DATA BYTE CLKSEL + 000000F8H SFRSYM DATA BIT SPI0CN0_SPIEN + 000000F0H SFRSYM DATA BYTE B + 000000BEH SFRSYM DATA BYTE ADC0H + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 35 + + + 000000D2H SFRSYM DATA BYTE CRC0AUTO + 000000E8H.6 SFRSYM DATA BIT ADC0CN0_ADBMEN + 000000CAH SFRSYM DATA WORD TMR2RL + 000000BDH SFRSYM DATA BYTE ADC0L + 00000092H SFRSYM DATA WORD TMR3RL + 000000D8H SFRSYM DATA BYTE PCA0CN0 + 000000E0H SFRSYM DATA BYTE ACC + 000000FBH SFRSYM DATA WORD PCA0CP0 + 000000E9H SFRSYM DATA WORD PCA0CP1 + 000000EBH SFRSYM DATA WORD PCA0CP2 + 000000CEH SFRSYM DATA BYTE CRC0CN0 + 0000008CH SFRSYM DATA BYTE TH0 + 00000090H.3 SFRSYM DATA BIT R_DATA + 000000B8H.4 SFRSYM DATA BIT IP_PS0 + 0000008DH SFRSYM DATA BYTE TH1 + 000000FAH SFRSYM DATA BYTE PCA0H + 000000B8H.1 SFRSYM DATA BIT IP_PT0 + 00000080H SFRSYM DATA BIT T_DATA + 000000B8H.3 SFRSYM DATA BIT IP_PT1 + 000000C0H.2 SFRSYM DATA BIT SMB0CN0_ARBLOST + 000000B8H.5 SFRSYM DATA BIT IP_PT2 + 0000008AH SFRSYM DATA BYTE TL0 + 000000F8H.1 SFRSYM DATA BIT SPI0CN0_TXBMT + 000000D0H.5 SFRSYM DATA BIT PSW_F0 + 000000A8H.6 SFRSYM DATA BIT IE_ESPI0 + 0000008BH SFRSYM DATA BYTE TL1 + 000000F9H SFRSYM DATA BYTE PCA0L + 000000C0H SFRSYM DATA BIT SMB0CN0_SI + 000000D0H.1 SFRSYM DATA BIT PSW_F1 + 00000080H SFRSYM DATA BIT P0_B0 + 000000B8H SFRSYM DATA BIT IP_PX0 + 00000090H SFRSYM DATA BIT P1_B0 + 00000080H.1 SFRSYM DATA BIT P0_B1 + 000000B8H.2 SFRSYM DATA BIT IP_PX1 + 0000009BH SFRSYM DATA BYTE CMP0CN0 + 00000088H.1 SFRSYM DATA BIT TCON_IE0 + 000000A0H SFRSYM DATA BIT P2_B0 + 00000090H.1 SFRSYM DATA BIT P1_B1 + 00000080H.2 SFRSYM DATA BIT P0_B2 + 000000BFH SFRSYM DATA BYTE CMP1CN0 + 00000090H SFRSYM DATA BIT LED + 00000088H.3 SFRSYM DATA BIT TCON_IE1 + 000000A0H.1 SFRSYM DATA BIT P2_B1 + 00000090H.2 SFRSYM DATA BIT P1_B2 + 00000080H.3 SFRSYM DATA BIT P0_B3 + 000000C0H SFRSYM DATA BYTE SMB0CN0 + 00000090H.3 SFRSYM DATA BIT P1_B3 + 00000080H.4 SFRSYM DATA BIT P0_B4 + 00000090H.4 SFRSYM DATA BIT P1_B4 + 00000080H.5 SFRSYM DATA BIT P0_B5 + 00000090H.5 SFRSYM DATA BIT P1_B5 + 00000080H.6 SFRSYM DATA BIT P0_B6 + 00000090H.6 SFRSYM DATA BIT P1_B6 + 00000080H.7 SFRSYM DATA BIT P0_B7 + 00000090H.7 SFRSYM DATA BIT P1_B7 + 00000083H SFRSYM DATA BYTE DPH + 000000C4H SFRSYM DATA BYTE ADC0GTH + 000000C8H.7 SFRSYM DATA BIT TMR2CN0_TF2H + 000000C8H.3 SFRSYM DATA BIT TMR2CN0_T2SPLIT + 000000D0H.6 SFRSYM DATA BIT PSW_AC + 000000F8H SFRSYM DATA BYTE SPI0CN0 + 000000C7H SFRSYM DATA BYTE HFO0CAL + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 36 + + + 00000088H.5 SFRSYM DATA BIT TCON_TF0 + 00000098H SFRSYM DATA BIT SCON0_RI + 00000082H SFRSYM DATA BYTE DPL + 00000088H.7 SFRSYM DATA BIT TCON_TF1 + 00000099H SFRSYM DATA BYTE SBUF0 + 00000087H SFRSYM DATA BYTE PCON0 + 000000C3H SFRSYM DATA BYTE ADC0GTL + 000000C8H.6 SFRSYM DATA BIT TMR2CN0_TF2L + 00000098H.1 SFRSYM DATA BIT SCON0_TI + 000000E8H SFRSYM DATA BIT ADC0CN0_ADCM0 + 000000C6H SFRSYM DATA BYTE ADC0LTH + 00000088H SFRSYM DATA BIT TCON_IT0 + 000000E8H.1 SFRSYM DATA BIT ADC0CN0_ADCM1 + 000000EFH SFRSYM DATA BYTE RSTSRC + 000000FDH SFRSYM DATA BYTE P0MAT + 000000DEH SFRSYM DATA BYTE CRC0DAT + 00000090H.6 SFRSYM DATA BIT BUZZER + 00000088H.2 SFRSYM DATA BIT TCON_IT1 + 000000E8H.2 SFRSYM DATA BIT ADC0CN0_ADCM2 + 00000098H SFRSYM DATA BYTE SCON0 + 000000F6H SFRSYM DATA BYTE PRTDRV + 000000EDH SFRSYM DATA BYTE P1MAT + 000000E8H.3 SFRSYM DATA BIT ADC0CN0_ADWINT + 000000E8H.4 SFRSYM DATA BIT ADC0CN0_ADBUSY + 000000D6H SFRSYM DATA BYTE SMB0ADM + 000000C5H SFRSYM DATA BYTE ADC0LTL + 000000F8H.5 SFRSYM DATA BIT SPI0CN0_MODF + 000000B8H.6 SFRSYM DATA BIT IP_PSPI0 + 0000009CH SFRSYM DATA BYTE PCA0CLR + 000000C8H SFRSYM DATA BYTE TMR2CN0 + 00000091H SFRSYM DATA BYTE TMR3CN0 + 000000D7H SFRSYM DATA BYTE SMB0ADR + 00000088H.4 SFRSYM DATA BIT TCON_TR0 + 000000C8H.4 SFRSYM DATA BIT TMR2CN0_TF2CEN + 00000088H.6 SFRSYM DATA BIT TCON_TR1 + 000000C2H SFRSYM DATA BYTE SMB0DAT + 000000CDH SFRSYM DATA BYTE TMR2H + 000000A1H SFRSYM DATA BYTE SPI0CFG + 00000095H SFRSYM DATA BYTE TMR3H + 000000D3H SFRSYM DATA BYTE CRC0CNT + 00000096H SFRSYM DATA BYTE PCA0POL + 000000CCH SFRSYM DATA BYTE TMR2L + 000000F8H.7 SFRSYM DATA BIT SPI0CN0_SPIF + 00000094H SFRSYM DATA BYTE TMR3L + 000000DFH SFRSYM DATA BYTE ADC0PWR + 000000A8H.7 SFRSYM DATA BIT IE_EA + 000000C8H.5 SFRSYM DATA BIT TMR2CN0_TF2LEN + 000000F8H.6 SFRSYM DATA BIT SPI0CN0_WCOL + 000000F8H.2 SFRSYM DATA BIT SPI0CN0_NSSMD0 + 000000D0H.7 SFRSYM DATA BIT PSW_CY + 000000A3H SFRSYM DATA BYTE SPI0DAT + 000000F8H.3 SFRSYM DATA BIT SPI0CN0_NSSMD1 + 000000BDH SFRSYM DATA WORD ADC0 + 000000D0H SFRSYM DATA BYTE PSW + 000000F7H SFRSYM DATA BYTE PCA0PWM + 000000B6H SFRSYM DATA BYTE REVID + 000000B7H SFRSYM DATA BYTE FLKEY + 000000B3H SFRSYM DATA BYTE ADC0AC + 0000002EH SYMBOL DATA --- PROTOCOL_DATA + + 010008EFH BLOCK CODE --- LVL=0 + --- BLOCKEND --- --- LVL=0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 37 + + + + 0100005AH BLOCK CODE --- LVL=0 + 0100005AH LINE CODE --- #34 + 0100005AH LINE CODE --- #35 + 0100005AH LINE CODE --- #37 + --- BLOCKEND --- --- LVL=0 + + 01000AB1H BLOCK CODE --- LVL=0 + 01000AB1H LINE CODE --- #39 + 01000AB1H LINE CODE --- #40 + 01000AB1H LINE CODE --- #42 + --- BLOCKEND --- --- LVL=0 + + 0100083BH BLOCK CODE --- LVL=0 + 0100083BH LINE CODE --- #44 + 0100083BH LINE CODE --- #45 + 0100083BH LINE CODE --- #47 + 01000841H LINE CODE --- #48 + 01000841H LINE CODE --- #49 + 01000847H LINE CODE --- #50 + 0100084DH LINE CODE --- #51 + 0100084DH LINE CODE --- #53 + 0100085BH LINE CODE --- #54 + 0100085BH LINE CODE --- #55 + 0100085EH LINE CODE --- #57 + 0100085EH LINE CODE --- #59 + 01000864H LINE CODE --- #60 + 0100086AH LINE CODE --- #62 + 0100088BH LINE CODE --- #63 + 0100088BH LINE CODE --- #65 + 0100088EH LINE CODE --- #66 + 01000890H LINE CODE --- #68 + 01000890H LINE CODE --- #70 + 0100089CH LINE CODE --- #71 + 0100089CH LINE CODE --- #72 + --- BLOCKEND --- --- LVL=0 + + 010003D7H BLOCK CODE --- LVL=0 + 010003D7H BLOCK CODE NEAR LAB LVL=1 + 00000021H SYMBOL DATA WORD current_capture_value + 00000023H SYMBOL DATA WORD previous_capture_value_pos + 00000025H SYMBOL DATA WORD previous_capture_value_neg + 00000027H SYMBOL DATA WORD capture_period_pos + 00000029H SYMBOL DATA WORD capture_period_neg + 0000002BH SYMBOL DATA BYTE used_protocol + 0000002CH SYMBOL DATA WORD low_pulse_time + --- BLOCKEND --- --- LVL=1 + 010003D7H LINE CODE --- #74 + 010003D7H LINE CODE --- #75 + 010003D7H LINE CODE --- #84 + 010003E6H LINE CODE --- #87 + 010003ECH LINE CODE --- #88 + 010003ECH LINE CODE --- #90 + 010003F2H LINE CODE --- #93 + 010003FFH LINE CODE --- #95 + 0100040FH LINE CODE --- #96 + 0100040FH LINE CODE --- #98 + 0100040FH LINE CODE --- #100 + 01000418H LINE CODE --- #101 + 01000418H LINE CODE --- #103 + 0100041BH LINE CODE --- #104 + 0100041BH LINE CODE --- #105 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 38 + + + 01000461H LINE CODE --- #111 + 01000461H LINE CODE --- #112 + 01000467H LINE CODE --- #113 + 0100046CH LINE CODE --- #114 + 01000470H LINE CODE --- #115 + 01000474H LINE CODE --- #116 + 01000481H LINE CODE --- #117 + 01000487H LINE CODE --- #118 + 01000488H LINE CODE --- #119 + 01000488H LINE CODE --- #120 + 01000491H LINE CODE --- #121 + 01000491H LINE CODE --- #124 + 01000491H LINE CODE --- #125 + 01000497H LINE CODE --- #126 + 0100049DH LINE CODE --- #131 + 010004BFH LINE CODE --- #135 + 010004BFH LINE CODE --- #136 + 010004C1H LINE CODE --- #137 + 010004F9H LINE CODE --- #138 + 010004FBH LINE CODE --- #140 + 010004FBH LINE CODE --- #141 + 010004FDH LINE CODE --- #143 + 01000502H LINE CODE --- #144 + 01000508H LINE CODE --- #145 + 01000508H LINE CODE --- #147 + 0100050EH LINE CODE --- #148 + 01000511H LINE CODE --- #151 + 0100051BH LINE CODE --- #152 + 0100051BH LINE CODE --- #153 + 01000521H LINE CODE --- #154 + 01000524H LINE CODE --- #155 + 01000526H LINE CODE --- #156 + 01000529H LINE CODE --- #157 + 01000529H LINE CODE --- #158 + 0100052AH LINE CODE --- #159 + 0100052AH LINE CODE --- #160 + 0100052AH LINE CODE --- #163 + 0100052AH LINE CODE --- #165 + 01000530H LINE CODE --- #168 + 0100053DH LINE CODE --- #169 + 0100053DH LINE CODE --- #170 + --- BLOCKEND --- --- LVL=0 + + 01000AB2H BLOCK CODE --- LVL=0 + 01000AB2H LINE CODE --- #172 + 01000AB2H LINE CODE --- #173 + 01000AB2H LINE CODE --- #175 + --- BLOCKEND --- --- LVL=0 + + 010007D1H BLOCK CODE --- LVL=0 + 00000007H SYMBOL DATA BYTE used_protocol + 010007D1H LINE CODE --- #180 + 010007D1H LINE CODE --- #181 + 010007D1H LINE CODE --- #183 + 010007D4H LINE CODE --- #185 + 010007DEH LINE CODE --- #187 + 010007E0H LINE CODE --- #189 + 010007E3H LINE CODE --- #191 + 010007E8H LINE CODE --- #193 + 010007EAH LINE CODE --- #195 + 010007F3H LINE CODE --- #197 + 010007F6H LINE CODE --- #199 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 39 + + + 010007FBH LINE CODE --- #201 + 010007FDH LINE CODE --- #203 + 01000811H LINE CODE --- #205 + 01000814H LINE CODE --- #207 + 01000819H LINE CODE --- #209 + 0100081BH LINE CODE --- #212 + 0100082FH LINE CODE --- #214 + 01000832H LINE CODE --- #216 + 01000837H LINE CODE --- #218 + 0100083AH LINE CODE --- #219 + --- BLOCKEND --- --- LVL=0 + + 0100053EH BLOCK CODE --- LVL=0 + 00000007H SYMBOL DATA BYTE identifier + 0100053EH BLOCK CODE NEAR LAB LVL=1 + 00000006H SYMBOL DATA BYTE i + 00000048H SYMBOL DATA BYTE protocol_index + 00000007H SYMBOL DATA BYTE TCON_save + --- BLOCKEND --- --- LVL=1 + 0100053EH LINE CODE --- #221 + 0100053EH LINE CODE --- #222 + 0100053EH LINE CODE --- #224 + 01000541H LINE CODE --- #228 + 01000552H LINE CODE --- #229 + 01000552H LINE CODE --- #231 + 01000554H LINE CODE --- #232 + 01000554H LINE CODE --- #233 + 01000560H LINE CODE --- #234 + 01000560H LINE CODE --- #235 + 01000562H LINE CODE --- #236 + 01000564H LINE CODE --- #237 + 01000564H LINE CODE --- #238 + 01000568H LINE CODE --- #241 + 0100056DH LINE CODE --- #242 + 0100056DH LINE CODE --- #244 + 010005A6H LINE CODE --- #247 + 010005A8H LINE CODE --- #249 + 010005ABH LINE CODE --- #254 + 010005ADH LINE CODE --- #257 + 010005B2H LINE CODE --- #260 + 010005C1H LINE CODE --- #261 + 010005CEH LINE CODE --- #264 + 010005D1H LINE CODE --- #267 + 010005D4H LINE CODE --- #272 + 010005D7H LINE CODE --- #273 + 010005D7H LINE CODE --- #274 + 010005D7H LINE CODE --- #276 + 010005D9H LINE CODE --- #277 + --- BLOCKEND --- --- LVL=0 + + 01000003H BLOCK CODE --- LVL=0 + 01000003H LINE CODE --- #279 + 01000003H LINE CODE --- #280 + 01000003H LINE CODE --- #282 + 0100000AH LINE CODE --- #284 + 0100000DH LINE CODE --- #285 + 01000010H LINE CODE --- #288 + 01000013H LINE CODE --- #290 + 01000015H LINE CODE --- #292 + 01000018H LINE CODE --- #295 + 0100001EH LINE CODE --- #296 + 01000021H LINE CODE --- #297 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 40 + + + --- BLOCKEND --- --- LVL=0 + + 010009BFH BLOCK CODE --- LVL=0 + 010009BFH BLOCK CODE NEAR LAB LVL=1 + 00000007H SYMBOL DATA BYTE TCON_save + --- BLOCKEND --- --- LVL=1 + 010009BFH LINE CODE --- #299 + 010009BFH LINE CODE --- #300 + 010009BFH LINE CODE --- #304 + 010009C1H LINE CODE --- #306 + 010009C4H LINE CODE --- #311 + 010009C7H LINE CODE --- #314 + 010009CCH LINE CODE --- #317 + 010009CEH LINE CODE --- #320 + 010009D1H LINE CODE --- #323 + 010009D4H LINE CODE --- #326 + 010009D6H LINE CODE --- #328 + 010009DBH LINE CODE --- #329 + 010009DFH LINE CODE --- #330 + 010009E4H LINE CODE --- #331 + --- BLOCKEND --- --- LVL=0 + + 0100006DH BLOCK CODE --- LVL=0 + 0100006DH LINE CODE --- #333 + 0100006DH LINE CODE --- #334 + 0100006DH LINE CODE --- #336 + 0100006FH LINE CODE --- #339 + 01000072H LINE CODE --- #340 + --- BLOCKEND --- --- LVL=0 + + 01000026H BLOCK CODE --- LVL=0 + 01000026H LINE CODE --- #351 + 0100002EH LINE CODE --- #354 + 01000031H LINE CODE --- #357 + 01000040H LINE CODE --- #358 + 01000040H LINE CODE --- #360 + 01000043H LINE CODE --- #361 + 01000043H LINE CODE --- #363 + 01000051H LINE CODE --- #364 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- ?C_STARTUP + 01000000H PUBLIC CODE NEAR LAB ?C_STARTUP + 000000E0H SFRSYM DATA BYTE ACC + 000000F0H SFRSYM DATA BYTE B + 00000083H SFRSYM DATA BYTE DPH + 00000082H SFRSYM DATA BYTE DPL + 000000A0H SFRSYM DATA BYTE PPAGE_SFR + 00000081H SFRSYM DATA BYTE SP + 00000000H SYMBOL NUMBER --- IBPSTACK + 00000100H SYMBOL NUMBER --- IBPSTACKTOP + 00000080H SYMBOL NUMBER --- IDATALEN + 010005E0H SYMBOL CODE NEAR LAB IDATALOOP + 00000000H SYMBOL NUMBER --- PBPSTACK + 00000100H SYMBOL NUMBER --- PBPSTACKTOP + 00000000H SYMBOL NUMBER --- PDATALEN + 00000000H SYMBOL NUMBER --- PDATASTART + 00000000H SYMBOL NUMBER --- PPAGE + 00000000H SYMBOL NUMBER --- PPAGEENABLE + 010005DAH SYMBOL CODE NEAR LAB STARTUP1 + 00000000H SYMBOL NUMBER --- XBPSTACK + 00010000H SYMBOL NUMBER --- XBPSTACKTOP + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 41 + + + 00000000H SYMBOL NUMBER --- XDATALEN + 00000000H SYMBOL NUMBER --- XDATASTART + + 01000000H BLOCK CODE NEAR LAB LVL=0 + 01000000H LINE CODE --- #126 + --- BLOCKEND --- --- LVL=0 + + 010005DAH BLOCK CODE NEAR LAB LVL=0 + 010005DAH LINE CODE --- #134 + 010005DDH LINE CODE --- #138 + 010005DFH LINE CODE --- #139 + 010005E0H LINE CODE --- #140 + 010005E1H LINE CODE --- #141 + 010005E3H LINE CODE --- #190 + 010005E6H LINE CODE --- #201 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- UART + 02000044H PUBLIC XDATA --- UART_TX_Buffer + 02000000H PUBLIC XDATA --- UART_RX_Buffer + 0100089DH PUBLIC CODE --- _uart_put_RF_Data + 01000A51H PUBLIC CODE --- _uart_put_command + 010009EEH PUBLIC CODE --- _uart_putc + 01000931H PUBLIC CODE --- uart_getc + 01000760H PUBLIC CODE --- UART0_ISR + 000000A2H SFRSYM DATA BYTE SPI0CKR + 00000080H SFRSYM DATA BYTE P0 + 000000D0H.2 SFRSYM DATA BIT PSW_OV + 00000090H SFRSYM DATA BYTE P1 + 00000097H SFRSYM DATA BYTE WDTCN + 000000A0H SFRSYM DATA BYTE P2 + 000000BCH SFRSYM DATA BYTE ADC0CF + 000000C8H SFRSYM DATA BIT TMR2CN0_T2XCLK + 000000C0H.7 SFRSYM DATA BIT SMB0CN0_MASTER + 000000F9H SFRSYM DATA WORD PCA0 + 000000E6H SFRSYM DATA BYTE EIE1 + 000000C0H.1 SFRSYM DATA BIT SMB0CN0_ACK + 0000008FH SFRSYM DATA BYTE PSCTL + 000000E4H SFRSYM DATA BYTE IT01CF + 000000C0H.6 SFRSYM DATA BIT SMB0CN0_TXMODE + 000000ADH SFRSYM DATA BYTE DERIVID + 000000A4H SFRSYM DATA BYTE P0MDOUT + 000000A5H SFRSYM DATA BYTE P1MDOUT + 000000E8H.5 SFRSYM DATA BIT ADC0CN0_ADINT + 000000CBH SFRSYM DATA BYTE TMR2RLH + 000000A6H SFRSYM DATA BYTE P2MDOUT + 000000A8H SFRSYM DATA BYTE IE + 00000093H SFRSYM DATA BYTE TMR3RLH + 000000F3H SFRSYM DATA BYTE EIP1 + 00000098H.2 SFRSYM DATA BIT SCON0_RB8 + 000000CAH SFRSYM DATA BYTE TMR2RLL + 000000FCH SFRSYM DATA BYTE PCA0CPH0 + 00000092H SFRSYM DATA BYTE TMR3RLL + 000000EAH SFRSYM DATA BYTE PCA0CPH1 + 00000098H.3 SFRSYM DATA BIT SCON0_TB8 + 000000F0H SFRSYM DATA BIT B_B0 + 00000082H SFRSYM DATA WORD DP + 000000ECH SFRSYM DATA BYTE PCA0CPH2 + 000000F0H.1 SFRSYM DATA BIT B_B1 + 000000C3H SFRSYM DATA WORD ADC0GT + 000000F0H.2 SFRSYM DATA BIT B_B2 + 000000FBH SFRSYM DATA BYTE PCA0CPL0 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 42 + + + 000000F0H.3 SFRSYM DATA BIT B_B3 + 000000D9H SFRSYM DATA BYTE PCA0MD + 000000DAH SFRSYM DATA BYTE PCA0CPM0 + 000000E9H SFRSYM DATA BYTE PCA0CPL1 + 000000F0H.4 SFRSYM DATA BIT B_B4 + 000000DBH SFRSYM DATA BYTE PCA0CPM1 + 000000EBH SFRSYM DATA BYTE PCA0CPL2 + 000000F0H.5 SFRSYM DATA BIT B_B5 + 000000DCH SFRSYM DATA BYTE PCA0CPM2 + 000000B8H SFRSYM DATA BYTE IP + 000000B9H SFRSYM DATA BYTE ADC0TK + 000000F0H.6 SFRSYM DATA BIT B_B6 + 000000C5H SFRSYM DATA WORD ADC0LT + 00000098H.5 SFRSYM DATA BIT SCON0_MCE + 000000F0H.7 SFRSYM DATA BIT B_B7 + 000000E1H SFRSYM DATA BYTE XBR0 + 000000C1H SFRSYM DATA BYTE SMB0CF + 000000E2H SFRSYM DATA BYTE XBR1 + 000000C0H.5 SFRSYM DATA BIT SMB0CN0_STA + 000000E3H SFRSYM DATA BYTE XBR2 + 000000BBH SFRSYM DATA BYTE ADC0MX + 000000E0H SFRSYM DATA BIT ACC_ACC0 + 000000D1H SFRSYM DATA BYTE REF0CN + 0000008EH SFRSYM DATA BYTE CKCON0 + 000000E0H.1 SFRSYM DATA BIT ACC_ACC1 + 000000C9H SFRSYM DATA BYTE REG0CN + 000000DDH SFRSYM DATA BYTE CRC0IN + 000000C8H.2 SFRSYM DATA BIT TMR2CN0_TR2 + 000000E0H.2 SFRSYM DATA BIT ACC_ACC2 + 000000E0H.3 SFRSYM DATA BIT ACC_ACC3 + 00000081H SFRSYM DATA BYTE SP + 0000009DH SFRSYM DATA BYTE CMP0MD + 000000E0H.4 SFRSYM DATA BIT ACC_ACC4 + 000000B1H SFRSYM DATA BYTE LFO0CN + 000000ABH SFRSYM DATA BYTE CMP1MD + 000000D8H SFRSYM DATA BIT PCA0CN0_CCF0 + 000000E0H.5 SFRSYM DATA BIT ACC_ACC5 + 000000D8H.1 SFRSYM DATA BIT PCA0CN0_CCF1 + 000000E0H.6 SFRSYM DATA BIT ACC_ACC6 + 000000CCH SFRSYM DATA WORD TMR2 + 000000D8H.2 SFRSYM DATA BIT PCA0CN0_CCF2 + 000000E0H.7 SFRSYM DATA BIT ACC_ACC7 + 00000094H SFRSYM DATA WORD TMR3 + 000000C0H.3 SFRSYM DATA BIT SMB0CN0_ACKRQ + 000000FFH SFRSYM DATA BYTE VDM0CN + 000000F1H SFRSYM DATA BYTE P0MDIN + 00000098H.4 SFRSYM DATA BIT SCON0_REN + 000000ACH SFRSYM DATA BYTE SMB0TC + 000000F2H SFRSYM DATA BYTE P1MDIN + 000000C0H.4 SFRSYM DATA BIT SMB0CN0_STO + 000000FEH SFRSYM DATA BYTE P0MASK + 000000EEH SFRSYM DATA BYTE P1MASK + 000000D0H.3 SFRSYM DATA BIT PSW_RS0 + 000000D8H.7 SFRSYM DATA BIT PCA0CN0_CF + 0000009EH SFRSYM DATA BYTE PCA0CENT + 000000F8H.4 SFRSYM DATA BIT SPI0CN0_RXOVRN + 000000D0H.4 SFRSYM DATA BIT PSW_RS1 + 000000E8H.7 SFRSYM DATA BIT ADC0CN0_ADEN + 00000089H SFRSYM DATA BYTE TMOD + 00000088H SFRSYM DATA BYTE TCON + 000000CFH SFRSYM DATA BYTE CRC0FLIP + 000000D0H SFRSYM DATA BIT PSW_PARITY + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 43 + + + 000000A8H.4 SFRSYM DATA BIT IE_ES0 + 0000009FH SFRSYM DATA BYTE CMP0MX + 000000A8H.1 SFRSYM DATA BIT IE_ET0 + 000000AAH SFRSYM DATA BYTE CMP1MX + 000000A8H.3 SFRSYM DATA BIT IE_ET1 + 000000D4H SFRSYM DATA BYTE P0SKIP + 000000A8H.5 SFRSYM DATA BIT IE_ET2 + 000000D5H SFRSYM DATA BYTE P1SKIP + 000000E8H SFRSYM DATA BYTE ADC0CN0 + 000000A8H SFRSYM DATA BIT IE_EX0 + 000000B2H SFRSYM DATA BYTE ADC0CN1 + 000000D8H.6 SFRSYM DATA BIT PCA0CN0_CR + 000000A8H.2 SFRSYM DATA BIT IE_EX1 + 00000098H.7 SFRSYM DATA BIT SCON0_SMODE + 000000B5H SFRSYM DATA BYTE DEVICEID + 000000A9H SFRSYM DATA BYTE CLKSEL + 000000F8H SFRSYM DATA BIT SPI0CN0_SPIEN + 000000F0H SFRSYM DATA BYTE B + 000000BEH SFRSYM DATA BYTE ADC0H + 000000D2H SFRSYM DATA BYTE CRC0AUTO + 000000E8H.6 SFRSYM DATA BIT ADC0CN0_ADBMEN + 000000CAH SFRSYM DATA WORD TMR2RL + 000000BDH SFRSYM DATA BYTE ADC0L + 00000092H SFRSYM DATA WORD TMR3RL + 000000D8H SFRSYM DATA BYTE PCA0CN0 + 000000E0H SFRSYM DATA BYTE ACC + 000000FBH SFRSYM DATA WORD PCA0CP0 + 000000E9H SFRSYM DATA WORD PCA0CP1 + 000000EBH SFRSYM DATA WORD PCA0CP2 + 000000CEH SFRSYM DATA BYTE CRC0CN0 + 0000008CH SFRSYM DATA BYTE TH0 + 00000090H.3 SFRSYM DATA BIT R_DATA + 000000B8H.4 SFRSYM DATA BIT IP_PS0 + 0000008DH SFRSYM DATA BYTE TH1 + 000000FAH SFRSYM DATA BYTE PCA0H + 000000B8H.1 SFRSYM DATA BIT IP_PT0 + 00000080H SFRSYM DATA BIT T_DATA + 000000B8H.3 SFRSYM DATA BIT IP_PT1 + 000000C0H.2 SFRSYM DATA BIT SMB0CN0_ARBLOST + 000000B8H.5 SFRSYM DATA BIT IP_PT2 + 0000008AH SFRSYM DATA BYTE TL0 + 000000F8H.1 SFRSYM DATA BIT SPI0CN0_TXBMT + 000000D0H.5 SFRSYM DATA BIT PSW_F0 + 000000A8H.6 SFRSYM DATA BIT IE_ESPI0 + 0000008BH SFRSYM DATA BYTE TL1 + 000000F9H SFRSYM DATA BYTE PCA0L + 000000C0H SFRSYM DATA BIT SMB0CN0_SI + 000000D0H.1 SFRSYM DATA BIT PSW_F1 + 00000080H SFRSYM DATA BIT P0_B0 + 000000B8H SFRSYM DATA BIT IP_PX0 + 00000090H SFRSYM DATA BIT P1_B0 + 00000080H.1 SFRSYM DATA BIT P0_B1 + 000000B8H.2 SFRSYM DATA BIT IP_PX1 + 0000009BH SFRSYM DATA BYTE CMP0CN0 + 00000088H.1 SFRSYM DATA BIT TCON_IE0 + 000000A0H SFRSYM DATA BIT P2_B0 + 00000090H.1 SFRSYM DATA BIT P1_B1 + 00000080H.2 SFRSYM DATA BIT P0_B2 + 000000BFH SFRSYM DATA BYTE CMP1CN0 + 00000090H SFRSYM DATA BIT LED + 00000088H.3 SFRSYM DATA BIT TCON_IE1 + 000000A0H.1 SFRSYM DATA BIT P2_B1 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 44 + + + 00000090H.2 SFRSYM DATA BIT P1_B2 + 00000080H.3 SFRSYM DATA BIT P0_B3 + 000000C0H SFRSYM DATA BYTE SMB0CN0 + 00000090H.3 SFRSYM DATA BIT P1_B3 + 00000080H.4 SFRSYM DATA BIT P0_B4 + 00000090H.4 SFRSYM DATA BIT P1_B4 + 00000080H.5 SFRSYM DATA BIT P0_B5 + 00000090H.5 SFRSYM DATA BIT P1_B5 + 00000080H.6 SFRSYM DATA BIT P0_B6 + 00000090H.6 SFRSYM DATA BIT P1_B6 + 00000080H.7 SFRSYM DATA BIT P0_B7 + 00000090H.7 SFRSYM DATA BIT P1_B7 + 00000083H SFRSYM DATA BYTE DPH + 000000C4H SFRSYM DATA BYTE ADC0GTH + 000000C8H.7 SFRSYM DATA BIT TMR2CN0_TF2H + 000000C8H.3 SFRSYM DATA BIT TMR2CN0_T2SPLIT + 000000D0H.6 SFRSYM DATA BIT PSW_AC + 000000F8H SFRSYM DATA BYTE SPI0CN0 + 000000C7H SFRSYM DATA BYTE HFO0CAL + 00000088H.5 SFRSYM DATA BIT TCON_TF0 + 00000098H SFRSYM DATA BIT SCON0_RI + 00000082H SFRSYM DATA BYTE DPL + 00000088H.7 SFRSYM DATA BIT TCON_TF1 + 00000099H SFRSYM DATA BYTE SBUF0 + 00000087H SFRSYM DATA BYTE PCON0 + 000000C3H SFRSYM DATA BYTE ADC0GTL + 000000C8H.6 SFRSYM DATA BIT TMR2CN0_TF2L + 00000098H.1 SFRSYM DATA BIT SCON0_TI + 000000E8H SFRSYM DATA BIT ADC0CN0_ADCM0 + 000000C6H SFRSYM DATA BYTE ADC0LTH + 00000088H SFRSYM DATA BIT TCON_IT0 + 000000E8H.1 SFRSYM DATA BIT ADC0CN0_ADCM1 + 000000EFH SFRSYM DATA BYTE RSTSRC + 000000FDH SFRSYM DATA BYTE P0MAT + 000000DEH SFRSYM DATA BYTE CRC0DAT + 00000090H.6 SFRSYM DATA BIT BUZZER + 00000088H.2 SFRSYM DATA BIT TCON_IT1 + 000000E8H.2 SFRSYM DATA BIT ADC0CN0_ADCM2 + 00000098H SFRSYM DATA BYTE SCON0 + 000000F6H SFRSYM DATA BYTE PRTDRV + 000000EDH SFRSYM DATA BYTE P1MAT + 000000E8H.3 SFRSYM DATA BIT ADC0CN0_ADWINT + 000000E8H.4 SFRSYM DATA BIT ADC0CN0_ADBUSY + 000000D6H SFRSYM DATA BYTE SMB0ADM + 000000C5H SFRSYM DATA BYTE ADC0LTL + 000000F8H.5 SFRSYM DATA BIT SPI0CN0_MODF + 000000B8H.6 SFRSYM DATA BIT IP_PSPI0 + 0000009CH SFRSYM DATA BYTE PCA0CLR + 000000C8H SFRSYM DATA BYTE TMR2CN0 + 00000091H SFRSYM DATA BYTE TMR3CN0 + 000000D7H SFRSYM DATA BYTE SMB0ADR + 00000088H.4 SFRSYM DATA BIT TCON_TR0 + 000000C8H.4 SFRSYM DATA BIT TMR2CN0_TF2CEN + 00000088H.6 SFRSYM DATA BIT TCON_TR1 + 000000C2H SFRSYM DATA BYTE SMB0DAT + 000000CDH SFRSYM DATA BYTE TMR2H + 000000A1H SFRSYM DATA BYTE SPI0CFG + 00000095H SFRSYM DATA BYTE TMR3H + 000000D3H SFRSYM DATA BYTE CRC0CNT + 00000096H SFRSYM DATA BYTE PCA0POL + 000000CCH SFRSYM DATA BYTE TMR2L + 000000F8H.7 SFRSYM DATA BIT SPI0CN0_SPIF + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 45 + + + 00000094H SFRSYM DATA BYTE TMR3L + 000000DFH SFRSYM DATA BYTE ADC0PWR + 000000A8H.7 SFRSYM DATA BIT IE_EA + 000000C8H.5 SFRSYM DATA BIT TMR2CN0_TF2LEN + 000000F8H.6 SFRSYM DATA BIT SPI0CN0_WCOL + 000000F8H.2 SFRSYM DATA BIT SPI0CN0_NSSMD0 + 000000D0H.7 SFRSYM DATA BIT PSW_CY + 000000A3H SFRSYM DATA BYTE SPI0DAT + 000000F8H.3 SFRSYM DATA BIT SPI0CN0_NSSMD1 + 000000BDH SFRSYM DATA WORD ADC0 + 000000D0H SFRSYM DATA BYTE PSW + 000000F7H SFRSYM DATA BYTE PCA0PWM + 000000B6H SFRSYM DATA BYTE REVID + 000000B7H SFRSYM DATA BYTE FLKEY + 000000B3H SFRSYM DATA BYTE ADC0AC + 02000088H SYMBOL XDATA BYTE lastRxError + 02000089H SYMBOL XDATA BYTE UART_Buffer_Read_Position + 0200008AH SYMBOL XDATA BYTE UART_Buffer_Write_Position + 0200008BH SYMBOL XDATA BYTE UART_RX_Buffer_Position + 0200008CH SYMBOL XDATA BYTE UART_TX_Buffer_Position + 00000008H SYMBOL DATA --- PROTOCOL_DATA + + 01000967H BLOCK CODE --- LVL=0 + --- BLOCKEND --- --- LVL=0 + + 01000760H BLOCK CODE --- LVL=0 + 0100076DH BLOCK CODE NEAR LAB LVL=1 + 00000007H SYMBOL DATA BYTE flags + --- BLOCKEND --- --- LVL=1 + 01000760H LINE CODE --- #109 + 0100076DH LINE CODE --- #112 + 01000772H LINE CODE --- #113 + 01000775H LINE CODE --- #116 + 01000779H LINE CODE --- #117 + 01000779H LINE CODE --- #118 + 01000780H LINE CODE --- #119 + 01000780H LINE CODE --- #121 + 01000783H LINE CODE --- #122 + 01000785H LINE CODE --- #124 + 01000785H LINE CODE --- #126 + 0100078EH LINE CODE --- #127 + 01000794H LINE CODE --- #128 + 01000794H LINE CODE --- #129 + 01000794H LINE CODE --- #132 + 01000798H LINE CODE --- #133 + 01000798H LINE CODE --- #134 + 0100079FH LINE CODE --- #135 + 0100079FH LINE CODE --- #137 + 010007A2H LINE CODE --- #138 + 010007A4H LINE CODE --- #140 + 010007A4H LINE CODE --- #141 + 010007ABH LINE CODE --- #142 + 010007ABH LINE CODE --- #143 + 010007B1H LINE CODE --- #144 + 010007B7H LINE CODE --- #145 + 010007B7H LINE CODE --- #147 + 010007BDH LINE CODE --- #148 + 010007BDH LINE CODE --- #149 + 010007C2H LINE CODE --- #150 + 010007C6H LINE CODE --- #151 + 010007C6H LINE CODE --- #152 + 010007C6H LINE CODE --- #153 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 46 + + + 010007C6H LINE CODE --- #154 + --- BLOCKEND --- --- LVL=0 + + 01000931H BLOCK CODE --- LVL=0 + 01000931H BLOCK CODE NEAR LAB LVL=1 + 00000004H SYMBOL DATA WORD rxdata + --- BLOCKEND --- --- LVL=1 + 01000931H LINE CODE --- #180 + 01000931H LINE CODE --- #181 + 01000931H LINE CODE --- #184 + 01000937H LINE CODE --- #185 + 0100093CH LINE CODE --- #186 + 0100093CH LINE CODE --- #189 + 01000946H LINE CODE --- #190 + 0100094CH LINE CODE --- #193 + 01000952H LINE CODE --- #194 + 01000952H LINE CODE --- #195 + 01000954H LINE CODE --- #196 + 01000958H LINE CODE --- #197 + 01000958H LINE CODE --- #199 + 01000960H LINE CODE --- #200 + 01000962H LINE CODE --- #201 + 01000966H LINE CODE --- #202 + --- BLOCKEND --- --- LVL=0 + + 010009E5H BLOCK CODE VOID LVL=0 + --- BLOCKEND --- --- LVL=0 + + 010009EEH BLOCK CODE --- LVL=0 + 00000007H SYMBOL DATA BYTE txdata + 010009EEH LINE CODE --- #210 + 010009EEH LINE CODE --- #211 + 010009EEH LINE CODE --- #212 + 010009F5H LINE CODE --- #213 + 010009F8H LINE CODE --- #215 + 01000A00H LINE CODE --- #216 + 01000A06H LINE CODE --- #217 + --- BLOCKEND --- --- LVL=0 + + 01000A51H BLOCK CODE --- LVL=0 + 00000006H SYMBOL DATA BYTE command + 01000A51H LINE CODE --- #219 + 01000A51H LINE CODE --- #220 + 01000A51H LINE CODE --- #221 + 01000A51H LINE CODE --- #222 + 01000A54H LINE CODE --- #223 + 01000A59H LINE CODE --- #224 + --- BLOCKEND --- --- LVL=0 + 00000006H SYMBOL DATA BYTE command + 00000004H SYMBOL DATA WORD value + + 0100089DH BLOCK CODE --- LVL=0 + 00000006H SYMBOL DATA BYTE Command + 00000005H SYMBOL DATA BYTE used_protocol + 0100089FH BLOCK CODE NEAR LAB LVL=1 + 00000004H SYMBOL DATA BYTE i + 00000003H SYMBOL DATA BYTE b + --- BLOCKEND --- --- LVL=1 + 0100089DH LINE CODE --- #237 + 0100089FH LINE CODE --- #238 + 0100089FH LINE CODE --- #239 + 010008A1H LINE CODE --- #240 + LX51 LINKER/LOCATER V4.66.30.0 11/30/2017 14:29:25 PAGE 47 + + + 010008A2H LINE CODE --- #242 + 010008A2H LINE CODE --- #243 + 010008A5H LINE CODE --- #245 + 010008B4H LINE CODE --- #246 + 010008B4H LINE CODE --- #247 + 010008B8H LINE CODE --- #248 + 010008B9H LINE CODE --- #249 + 010008BBH LINE CODE --- #250 + 010008C1H LINE CODE --- #253 + 010008CEH LINE CODE --- #256 + 010008D0H LINE CODE --- #257 + 010008D5H LINE CODE --- #258 + 010008D5H LINE CODE --- #259 + 010008E4H LINE CODE --- #260 + 010008E5H LINE CODE --- #261 + 010008E7H LINE CODE --- #262 + 010008ECH LINE CODE --- #264 + --- BLOCKEND --- --- LVL=0 + + --- MODULE --- --- ?C_INIT + 01000624H PUBLIC CODE --- ?C_START + + --- MODULE --- --- ?C?IMUL + 01000076H PUBLIC CODE --- ?C?IMUL + + --- MODULE --- --- ?C?UIDIV + 01000088H PUBLIC CODE --- ?C?UIDIV + + --- MODULE --- --- ?C?SIDIV + 010000DDH PUBLIC CODE --- ?C?SIDIV + + --- MODULE --- --- ?C?LMUL + 01000113H PUBLIC CODE --- ?C?LMUL + + --- MODULE --- --- ?C?ULDIV + 0100019EH PUBLIC CODE --- ?C?ULDIV + + --- MODULE --- --- ?C?MEMSET + 01000230H PUBLIC CODE --- ?C?MEMSET + +Program Size: data=71.1 xdata=216 const=0 code=2739 +LX51 RUN COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil 8051 v9.53 - Release/RF_Bridge.omf b/Keil 8051 v9.53 - Release/RF_Bridge.omf new file mode 100644 index 0000000000000000000000000000000000000000..810e91ca47ea02b11f14c86beb6d51271993673b GIT binary patch literal 64264 zcmeHQ34D`Pw!dH6bYqX8s30X4DF|)af`H4=Hc3mQOH5Lh+Gkp5fM`o=+u$(5u*rZsa`O<>CN>4>)L1jYa%sDp{RopzI$mgjjaC%G2OT06^ zRW~`Se8t|ff_Y=yH6)$FoPb6ImNv5wsA z_^dQXrgcQ@)HFwqEhjU}I>nk5pFAQqBP%z}m64a9KRrHWL~O3zWy`kZTjM8;a@ws{ z%Lquzu;p0ebGXzil19YZa$Hj&IoAn7giN&6Io{}<@Ok!p6b(M+ZO=FWlPB0}*NKCYN=6Pp&5-aBv zRd|XME4}17qo~r;O>(Un+2hmGlM=fxrK-e0MZ1f6O;a2rVjb4Z3|p2pUTYl*xeoJ) zSi1xD5uecIrczQ_H6qrWi#B0T%d}3lSzMFilaf)1WWs&PSTqFQe13*t1Q@~C zbCI$6qr09O1X9?{5rgu*r`lq=+*Ne!-DjJoU)MdY>x6YCJLeo7yFY1g{#B=%L$m@u z7`V|RW_f2PKrZE^w0mzM`A zGYhEmVUVMqSs*%QfsCP`LxdL3EFR4^WNlXWWbL>iprF$0t|}`lnK`G(JD2iAkrke{ z$f}CHbF0*7icVuRGms~W=fgu^O?RTXb-j|b(x@!B&f_g{^ZJ^QFgB$C1A0MGB_=VR z1Cs3MM#+^Zo3eyC|0-V;(Z&v*sY%mUR8bY0HAAyzSLP|%R!+mTDJ6?}^HI#32|pt} z+QfP7sZJ{=pE%X-BIcWt?is*NJaft@LsMsH>O7NE=QHJZ=-b%i-7^nW;`7Wl*IOml zJE3p1&^KC#7V)#^ln&toGe`e~g5&)ZcCHeeZ$H)fp@ZO=p|6gAbK~Kc{?*Yft&P40 zg9gnx7nFaD?X*94--xVjpSVlu<1e&x_Wyq8j0U(4t>WJrnLEe`jLrka=zP4t!dB{I z^IhFBLU#}z8m0f;?crbgD1G;)A^F*-+Tv)G&MYaLQB=bB>Q2kZ|BL(DJhNNQcm82W z{*~QP&-5uyn~IlXG1)D9*chrN70oR!@y^8__O$Z9V19qHTjzI8dT4SFP3~fH*P6t? zJF{y70@L~cZCVfZRG1Rp4IM=;N;Ju#2|YBS2Xxp4(3_ktWlv>Q1s|Dp>~t&@PR}f& zW3^2~@<}muO6C@{tikMLuPCc3n^`8-HoqKYaW}6BEaji++L&9HHmy4>U1+>>+OpEp zoo=Tq&Ed+kC!~!{GR9gRj$8+~afo$VUGdz&WmJ1cvPlspFWG5kM{aBmEKw{-Q^*wM z-!_^#p>if*bJ9tr1?E@h^z8K9EN55EOgfQ8Q*Ep;DUqMh?JGV33ssE>Cmz?v@FGN$J;`nzjVh zbl5DJ)&$r^Czu`SdA2M|7^{O{uXX{#rNwF@%wQ6wsdZw&0#}+^Ct@&66sFb~cEg#l z*6BhR8k1pZrUmMsz(oaVxHPYU!b?k?&`)XJ12k`KPeAjNL62V@iInyhLDl&ooQ+8B zna}M5ZCN&$0@JD+i|=eZTsGHqrz_85%Pp8Procir;<%;46%9w;pE=fo+C76tF z>KXnNQ^WZzjz!b&c7J--1Ma>j@Lj;_8Y0+GOm^(01_O&_kqDq;Vfb(OtdgSHwI>L> zh%IY~VncQ8Hny0V8qRJPI;zTB>LEk%cN@-u2c=VpjrJCoc$`&5Ri61jDO=B$vgIOO zx3fPt3}`1g685HZ=Xy#qe=<0we&A2~_F&7|LN(!aY(&FZ5FgIdN2%1$D=P7MqD~Ne z1*>j|VMD{%O16sK$!dNweN>)-jE9$&6?+yo^aGI+C`u!&ysYH2pNxwFpZ$}*J=ops zW>HG_u*Y~dB06Lv;sk+Lvm4Y>Si=T4^hdhrFPtg(Z-i%V(Toz$Mr8Ct1?f!%?T4Qf z7LIn-^Cx}7*!^lc*RkI<43rUx0*LVzd*)VoXL&sp#}L^tB?dA5j-mPuY-l8VkgaDA zv4`33*(2;x_JkIg@iL6DS*$rOTZYZ*Naf9pl8!3Gzi8+59J70pEpyT=-ZH7kg-;as z$;zEt&pn7)dZgQ2Zk*e&{s~zTJwZg%i#$k_+mh#+epbVI@QvcZNNP{=g*fh+&XXZ} zB6&uWr#Uw-$CW3F@&QylV-0G#THyHZCreI2x%R0U1s)a|gL=6DKlE(SM7v|68v}&N zJ=I}zSuvvIC*i54!vQcAn&IF$+>_c%ER6S zgyh&aT!+iqbtxl-l*OG&N$P4^j6zBQNueI3XCf`>=8Vj)r{z{5Wj#ru5m8Dp zXXTnFcU{UQHC8H@VI<{jE@dp03-v6ADXHsn;)R^cI+K%hi94mMWfNUvqx8%Ql+6S! zJ#I9MJbTyER3O^THPqbu@VxPM!@FKr({r{cY1r3+69ZZ&oQ|6FNakJ| zA1m-f&tfK;`FQ2DW*!vdA|Lm3Tnrx<+o$R)&ct(}P)@=zc&6JrB&bhKBD`3BAiF~- z>3p!xonm$1P~lW_It9WIZ=q50eKG3&k&0Rr5Fhn;2wvXVR*NmoW$irl=QU#}zRRKz zb_RavS)3N1oJCAntme4dM><&q`ydR#X7dt0E?810!Je!cLa_~1|D$7lsJMf2^SluJ zOdvPM2~O@raFUo3-;P9juI1SfQ=$`RG$Ebl_uyFSYfO}cU+KYqFK3UXT)TOpS#n*D zv>a!)tzE)eMUY7pj*3~wVkzk-3bIr*UCefx@W%_3S*#KOc`%_)H#DC6|jz zTTXeN3}y^-6Q@~%lQ39t?4w3RgNGg*5EmrlPojfVQfRRzFa&$k%3xf|z?#7b%s!-A zxr2-8g)Tv#=CU>UQW#&vbi6vDlF=1qaB)+6_^Fh*{C%N3Bl&_+; zOkZ8Hlr=7_0<*Kxi@C^V!F(T;p`$Zql%^%kmByK`s2K&21a@Jd1bgrxR58gZzZSmp$ag32?L8)%C*r#l zIj~qi6YD(+&)2{@*3*bHwXx}GIg?{e#(RY~wF~(v*^_6)o$1KMJZo)KKW*P$QwjMj zQl7k?ajL3^lb^q#^Ra(e<3k~;vCb(z6NhkU!|YFMuBM*Qi?&9zgQu2L%`+)l=}hcL zYi^*)`}`9eIE7NTJC1>?8ZC;M^7ZwaYtgV+zo3}K$mjDl0b3l2HodTf&)4)(t7p|LN-T<;G``a3 zFwvqpZB9{16^&1vSj!AzTEC&fTjeo}y`^zYGx~w!LHwg_ib$v3W-?DEN!601vtv=A zEI@mtb!UX#In|vz1%4|ue;Rb}kuE(xEX_G^JRk`=doq5#C|wb07PHBm0fDJfU~gBp zBiWo|a=VhJnX@nvE0L;?GdtZxKG|tbtgj*A5SOB7;gmW2-YKPqTWwY(LQ!PM9%@KT zqF|v(molffJI$^vI9enj!saq1@zg|gjMFuZKB>X?q~wjXSRJ-0HVd2&sU*88+mf5- zg7aaGlq5-t72SzStQXHRvXN%Nx)pr?PW2hvMTXWNz&OU6?du(2$Leh zd?!iByqz+?Fs?ZZ9PZ z@hA&}cv9g1PstNOjU$`t>BIJ+vMF`D+S9TqTQxzF#=w6^d!B4c9D;l% z1&2>dcThGrNOuJ92^nyG9>hVJ)_3eHSaO2pUqNh?{=Z5$PfzwV1f*$#+I3W#+3dzY zitcTd%VEtxmxZfNrI;sEb3{0$LpUncH&iYxtVFnvRf^eRHrXIaNmmo94HOP4d|d}| zL<{Rcqh@id6sU7j1>C2J&!*0cFyS4-Py_g*%9WLoE0XnuN-<~K(Zdn0Q6{S=H8&ci z%;pTrroMwbGz?`!C%jY#5gmA`0c_?mVT_~ff@fnVVTm5uAuP3m`k=7LyAmeD_6iyg z9an*=jWgmyV~QnPWbhl6LdC+%{pI%U&S9l${cn|xB)ZISeXCNaTzJ568LKu55iiInUO`kTB+8Oh*aCt zuv0x9REu6DC&FfRTPZ7SoeUd+Mr7iBDJ_`CMLdrO@g#8`b2}cSoxQ8_*iFvKJO$Qv zJZK*5J&h+x@USl>B~s=XNlXn6HjScxracpt)T>(V)Q0W=HN9O>;(JZDmmXsNamxAg zIVmwpY)A76^f5_`z=ZF#VzyBlWp(sY>ki24!!KEtbo}_6bm%DyG;eN`1YR3ydDPC7 z47C{qYBoKa%Mz0z##S-$BJ4}S0+9|m5egPegrIDfERnMP!PzWHVHo}JQ%p{JCOBxd zBxf0oM3p8c5RF82v=#sOqKn!Rh7dSwB`M5B^Rn`?R?2p_owp(SET%AEAgMn}Cuvcs zM3fD|A*e+uo7z#RrgXAK`)I?0BRwnENqy**cFdH>+qDS!th=FOMY*P>XH&>UQYc>_ z@{uq@%8KG00P9LfS{9H-$rlScTA3mF)DGyghbEU8HEB*8sJFJ0O`GRC3EYJi&G6X4M8Ud1Nf@@SI%OV5MLX8K3 zXd(#L2naL=gc^+i4kG9^0yt>STBH%cL4*j601nJl%553}97KrJ2;jhcq%775;GhX= zp-gL-#ZKM#Wi{#4RdJCRf@I37?y1f88OcO9OL`xTp6rDE0kyo_f?G!#^~i&&TsfM+ z`I<_aL{oYiwKc0uov2wCZ?lamO)jF*`s9KZUCv^sV3{flZxF5wYB#H;biFe@kL18i zKy*_yY`*%DYg~L_iL8>Kj83vj^bKkRA`LF;0jX-Y3k+&zzMg$mM#SZ2@ghuB!;2Qn z2Z6NC!c)rk$?y>lr_1S}!aFJ{=vvunC|~x8Bt+6Mg}pi?C%r=y)Kb$si-MYdgDQ~c z2afM0A;Ru(SsYW~+M}{y5y2xcOJThO`JKwYo)pXRKIwT*Ot|cQDI}6QLYgHT&R0|t ziOHgGKjjq}zNb3VV4lhV{Z-lXqHHwOiqVSp(D?w($Nnq_oUf}S*$&}c8AM7E!}td( zNhAdU6-&D!bI~eYvB(w>_y*2MHq%t4WOU%Bs@fPVl-C2>B1w8m4fUwsX*~2DpOFdY zT|qo4#Pg2IBc>gy;=5H6WfW>^I5$fY7fl8CTE~JzA)(;pq7!2{(vU(SKb0YQleABz z%x9{@8chZG%uuYIEyG!eJZu8KTDF{0S&taj=!jcjI7C4O2D5a zfqylnnJu+_L10J%Z%$z_yfM`F3npn*7t%W`lEfLCnDF>kvoP6(IBvlS_AjQ ze@KqLr0fPyMST55G7#}R9sYIy!k+yLd&lX@doMqH#}VW5U3YwCT>kYPyPsWwyqu4) zx%E9|h&Y5W_Fi>6cVY;lXi=;r$SNR%u^w<`!bk{!MofTlk>E<0KmqVUaUK9o<$M6D zi2x01FaXQKApkpLv4E=tpj{f_axzBoqZbh53AmdQc>xlcCGskYUoD`Ny0ekgYIyVQ zw!l_f-}>G>4}!k&6JzVDp`0*BP`m=J6>uFkmk{MAxl zk1s#Cuqb&9a7X|a?*9!Jz8wfK=l&UROaQ*lUw{k$BhV>q6Cg}LxWZnAOD`Z&VNGyF z35Zr0WhF+yos`i<$Y^V06pP?0Jk#toRiv_ul4hne&yX@|(3*LyXCT@$r;Qo{ZB(z* zrj6PLZB+07h&JjoXlpPpoEdFYZ)l@1f1OEfl!E+WempbUs0wJKFr%FzZB*~h)H&nO zO}QnY9?FUyZtAQiw-UT>n~?U#=x7A5*0I2o`5dzGlf zGqV>Pg}qobl{2{)dl>mU=S=OzmS8V-;2GPCjY5k&w|$G8bIL7}PK;2C+|k)a?}OBL z>G&w^=*9=18^zrKcr^`YN{W0XRoS>e!9A;@tW+H5Mwmxrm$9)oZIxI_3#6h8t zv$jbmI|V1Auw_Zod}_$PN5SaayhLJoe07BD9;~- zPK01R4I4gru*U7mNd5(%2&o%^z3^)E1AedL2{&XeuTQ3ZbIEFmxycYyZHQTHh$%3{ ztT)6AGsIkGh?!+z*BD~z3^8{ZVjj`O+&gmBY#s=k#kA{#Jyim1cCH1ShXd3AoWl4W zU=VJ!01U<^BLJr!9tRA;;RHY|)DnQ9IMMTDVP-13Xk{Ty% zoyDnFQl4mo>m@B#3gUaHpYPqR#_2NF@r++{nJECr9u|UU7EJyDuXGYCZScuhPrSMJ zoE9qu@jaa8d+!G04Kh|71tIE90%~#U7Os16H!R@uPGY5P$hfX-L7r1TK$b8C@%<~+ z_nG4RTxYC=I)@4wC)~*6K>>ea%ner~V>19RGv)z2M)A|>pTa;{)3#|`SGG)Ft?wh_ zrywl{9y1B7u}1S0Hb+ z#ofj2?I!|xqfks&iw+yeTVL9zBgLxAk>aK-_SUjU?5!(Z;m(zZeRs9_>f3yGw)s}w zmcDZ9@maKk*VwemB66%S3X3Br1Q80G2YrYiFS7-4pHJX>$jft}Pj#aqCQ~|jP^MY-f!b$*FE36Dq zPN@*hR~w#4d(j2W#UJZMQ)P?-Z2ZLcPrdI@o9}ML{6ng7yKD!A3iq8MphRJX;JsO4 zGXb|DU4S~I3s8@A0eVq_`k*YX4)iBdzerWhiMRZ})J72s;{0L0@53vNBjqTvT46-J zSHR{zczGG2y;VU<1#sP>{7ToY_EWC6!th6{)?g#L&sP(s(V52vXZS> z%OnN!?Ofq|bOn05n2f&1g_@x1bQ}ig*gCid>)3;UVl9)6eOYhZXDD70;8(W(xaJy$ z*|slHE4;}&Wzq$f!-VA-I>&T???Wy z7&#3uSoEHzOD$i-Rh@AdoW%v9XD(MO*SOd)90um^d~{DO(K|CcP*@kCu;`jx z?b+ULX<(Pbs^a?2tSU+|o6_*W6*4jWaBC&KyMfsj|HG_+k8I~$@2pukG6yb%o8C6dFaYSEEu25?f=PJ7S#(jBhvHo^XUTo(7lU{?2+lY z04y$7svqD|^#Lc8GN?d$#(-Y|NktaAcM%O*|Nrye#cy$wA$H&KNAH^{gOj1k6K+4; zxPegh{)W5XySt=l3XbcB+HC{w7iO_xUsmXst7JCr{E6T5`F?OLpr0%%PPH9 z-mB{_!Zq&o8*mR3u7c&oWsDG$?yO=un5ztGs9evay2IJ19YWn6e6r(232 z=RbUd6=Jg-7~~tQYaJAq5B9>i{)HFEMV60R!QQFbN9_iww~yfVCXW$fpNH{M;H zM_I8WD=jNnlfOE{H#n?1t>wU=1B0tCZ8?wuVb)gbJM}E}Jm28(>fu$(hh-dC&@zS{ zSlDXu>oZz2p0gSdTXnBiOL1O#Rvsb0JmH3bwqt&7l9)3iiQ1|Ng?<73{sLD1UQ*{|dIHO2L2MqF>E% z%VoBj+rZI$Y~Q01QPsLlXKg=XYSyn{TdTuXu=ksP!;ZAH8Db(K3_>H{-u4NK3Xy(C z$)N`U_pbU_M~TKglGJuC7J##wv175Ts~YI4VWk323+e7*NwOi834PCHo(mSek0(w z0_LNuq3)}(kq)>O8{dG%j2Qq+1T1AN7OrLJ`~X;Y3~8@7gIloye--c|o=Je~C0y?g_#0+sKqGD* z25f-I5MYylmr>zxy^4250Iv&p1GjU-^$!7?@x}sNTkxm|;4J}7c=Q0SX04$&_F_Fq z!5|-t+zp+>@D4hM?m1hmgvaKugN`-+KcZuO4LZmXXG+JqA39cy9A{F;`UUcbQR>X- zSf@e9I_iw+Soh=AvC%wh70@~*%<1lD!ES*L7su~UgAVs8bf&}(ovC}&gO@{rHwUk! znb6A6d+lA>FbseCUOEw|RP&*-CH1!{NFVNLDGTxnJ1(57qG)bqDZlTPUhmc8 zp{l;}4c@XKKY9pQ&u(Qs-A>QkVkD1V07gRSU15r=KaWdZ?4E3$2Qygn4EWQ7#>e?5 z1^nrq?CMK} z-wK^5HkMI>kFj2MN3JUu4>0mQxTR2tL(77{@1YRypKz#th;$z${kfr0|54bN7i7fi zdOUw&y#AweCl9;>ci@T;J+X6@#@_A+Ex91{0f8Ac|GwORTTjjZEb_lV^Y0I5I-WPv zl5h_BvvW0ubGd*fy(VA~F$~cB2Xp_eVVZv|2vh#5`48p(@Bg6r$AR#~49$NS_kVA{ z<{u9Ni`M){aR0Zy*ZfD3zh3hn&Hc9o!kfrn(fpIR{|7s@@MFmTXdN!K6@UA%M;B=> zD>a!?F1evTJBZqPvCkj#P~5nKJKKy0cl!Ko54AnzzlHs#*ua)-s%l$D)MHUQ+v3I_ z-8-i3$UDY&TI25;-8%fPQO4Fu6x4VYDb}FjW$|@`P(RfqoHp}1Zsfh8rH*`!FT%)y zYSSpVFBC9Lz%wKhRRkl4cvU9tBc5mv(Wl8LPUF>5KH?xZbZ`XFQ4v%J`Xq zJy3NIb7FldPbp)>LOS;Ho}_pWhx(l~@}yEXM12E&eDiaWVc3_UU))pZ>VKw&-gw!n z1|A>uO%&m10nnjz(PQV15K!)ow0Z`8u!}Tl1 zt_46#zYLHj0CiXgmxZwv0BkxEWa6AZV3L4cRBp5>995^48|@FbD>rp-_z~Dl3>O9_ z#KWf7evFWG#E*ZC44CPwsK6$(duCC2m9N6%=GRoi6HS3LoL64qnddF@Rkr7F!|nte zXelS;n(LVj4r*ca>0?kMDfd)(%V4U(Wk5aJsjmnNqOs5~YXy}EDjB%SYzY7t79>Xo&9D8h>Bw@OxA9_r<;5*7B=kn_A=7 zwGO}Eex+ndB9@W&wT`$qb)3dBa$W0)`|ZO;D~0jN7H%_gVAO%p$L6OV{WWY7Zdz{8 znUDgQlNj}gu2@&T%t$Sqj7+EzQ*R%M-aaBV$`G}$dDFVoK8EPn)C@R8d%t|!3i=V( z*48qn?HDo~WndpyEl)hKpo;zKz(RV;Q`)6eDZ(%%W&4p_dLPqY-D~3t5*D#&_^3tk zqj|>)Lx0j_BPDOQUhKD2`!}v=S?@P48aix|@ggd{xC8Mhy$cTve~237EQ}O^vH1$< zK#cFMTF&d@N>Le;1;Cz!S|SuqI{~mK*$u#GL;ypQZvn6%X#*6(Mh8d#(9{Wv1wa)w z5H7SUf;rIY1H1ytU>XBgxq$2OA}d@KjFkY;T+0DaS5*OgFn_|^wN2SsoP3{U_o&{$C< zE755IcM7P778S00U>^X0UC8+W*o6?RK_3OI#dEfRd!fJr+{f4m0BlAGU^6lj@PL5z z0v;CdC~mHR-(!qXO*}5(3#zBts3%=u;2_0QyMaShI=!roQCU;|@c0yZ)B72p+EA^~2*!V2&PsvhtUR6Sq|suzRz zTa5JwKrMPM;9b-*0J_*jz;>7m0X}4G9AF2o8v%Sqg?cR&W!+$u4eFjTQY{{*R-9LR z4*97C8{;j;fbN~;^;E9`Quv{Mg@q@EhMP3jFr%52xE*_8q9j ztuE_!3rEaP1QC6=Q{PeJx-&reV1DU^)lv74QvXbKv?G z%4NWQ0YAW$4z5FtJqkF6=c56N!kz?#E9@Bn9t7S1z)Qee0X-D(>aGroc{55f9FbwVC7pt(o0HcCiJ8&Nf*6e`c z3Oxg$#N!hHFhZdfhtfo89fAZ-4y;m1%idALzC6%w$(vpG)7Jo*WR{4JHxyh0#9PY7 zPs}?M6Vug{cQ37xi4!M$1Ie>96 z&;?wou-5=rC~Pwz6*UGhqs9Oks4>7Kg}o23DQpMeN`-w2n5;00ia(%!5mI0Y)L1D> zCs1RmrNKA#{bcsYf8!@;-nh1g7UNiCD%^S@M}S>`6IbSd)1@%Xddk(5Rs5e7Yac0? z1r;5;Xl>m&5K;{E_B0}6@ zlpAr&x3fLCE=xULg`t9Pz~i@)zZ z1}VFQULTogCc_bjE6;xRnnDJ$!D-7%OLwZ>W0qr+ha7-NiC&*r5Ek))?7X^s^38 zlvGwlBoq+SbCI$68>;(Z-cFk~HYs*WN zTGf*iek&+XQ@6vQ$!6D$RE1M+29t2Nd2Eu*k&v1!r53?nT}UNf12f(@zvcVwM}4$?fpW_EyrHDAu{YQkV!j%$FuQ zy(Qk6Wpn8^4*V`Hhs#@ale5ZK>@7>2Hzu*zGtW~}hVR3~%Hr!P6UUpzCV`ADHX$+5 zf)CM|oTQ*lnHW$ZRmNz3hyc*tWvN7Mmf++UYT|Erp3K zR=lUd#C9ESGWr!#&M%-bC7iiCfA+vkb>e9=Q+)t~L#jGBbdOCh-6+(EM5moLgXAeN zNX9&Rx(t%bTJ7l!TFDH9ULrqFc%!V-M=V*Q3m7Yv@fN z-XuZ>oT6)l3^+puoahiC15Qj8hxv37GT_7}R>*)8uY%jGCfZ@s(?|)hCyU#ZpjMOw zT(3l1o?Ur2C}hCdVH5Oaxi*WW2k0|h*cVkYv6Dq5-BVs5L+^_a-7M*SGo)1dAFxU@L*_wME-cFE8FM&aQ%RFDa!uwm?71pdS%>mrmkg@tMwP~&ym32h2-be9 zR>@RZ_%j8r4BE0>Ev4(7>3JlFEmjG?%x8o`2Am-SPAI}7WnY!u%pEe|?79KxMvM?_ z2?~&utvyPLDytkfS}Q8bXk%%qB%jN-oWy<;Hrk7d-FA5q5SXAI;9<`TW|~^zt?~qO zL3_Zt&f#3z9#t?4Gz&p2+6GrJOBCWe-q17yR-RBY;BPFpqWVWQ!O&E=$HA?1VrZHQ zrHbH~430FmEE?)rLC67ty{q}>a{tk7@q- zL}CLf1iw@Yj(4%Ki-kL-Z}p2Ub&t!(oas`?<(y zFts4e?f%;+XVVdLzk13D{k@9#nj$qlv1`?L+ykm@%1JpaB>>msni@bAZZHDCOzS4V zJOMXAcL~=`0&a%p6s}tsTLggajbJ{kWdPNT)dQd=C8!aw2v2Cib(;Xp!|UKehay0i zc@TgG{}2GGG=e(VX#nmJumV=AaIIwQF94Wu5!5sG65uWYcQdvTu6smY8w6klKskp& z7r{0v7i5wh;uVbWVh=a4f4d@3i?q4RzN&>;g?Jey=t{87^{KL0iOCRM_gtj@x5z#k z*HYA6^U+(Ns$a_M1zr(UDa-J0N%OJ2>ESK@r^27sH&9Z>LiAXzsn3EeW5X&R7yYbA z*>eJ(7w`gXl)&^qj9m_RNdR)#^L>0eO?Tz|4S%SnaS~pBz7ULJ%^*$6aHDz z|7sRsYE&R$?TXm-OwTQVlX#lZabWKVjYUwJrM4oqb~JfvX@*_9e1t&{G7UHFEp|WF zW(1P=ROHq`D_;i!`%UfnBu}IQwx3=&!lWc+#;@zImUTtUEk_O;qQBU~4bA$&v~M@Y zqR6VKQAc`IfAw{E8wyGIMZph_mLt12t+gAfmXFfzXalup^)9tM-=Na5BeL^g4M=sp zN91}h#s);UPkUD+}-=j>iLz!blW= z|7``p_Nxhi+4Vg@n1FED2f+nPuvS2X!oC2&AZ$0_FO)_H(l)R$nnl8nz?NfkonJkW zDFa{u6Pp;D=FA4BRaSaRXOws<#w{5DW)_EY9aJGvsvXUX^_chh-!7O3=yU}wcdkE( zf2m>LS1aE}eY(GT1W{a(aXnw(l=8Bxk0ti?g{k5Dr&KE$-+$Ut-2>mVQGH`mVZ6V$ z<+sY6g)gpeb4@h0M!SX_L%>3%_gk*UVau(gDI zd{Osc{JUDV9yRVcc)-86CU)DPV^8`8=bn_KsgVu# zi1+;88aFi@1>;x71u}_FO5)y=CJ|j;OCk?4z8-2;{zqOL-`j2aBKn#4S~lHxwB_C- zdre;qAji74miv#<$&waMuEsToOHA)YZffBk#?`VCvQPmxt-&l5&#n`tjo0A)GHtxlDaiHp7@PUu40xd$ zd<&SUvn?rGHm7WUWkJd-3)b#gvwL;xf`-(d2NvvIdu-2|qq|ohLG8TXvh{GwmLFR- zA9{3w@p-o41vdSE*y!EM{55ZF-EySW|BpjA4iv&rvuFcfryTD4LD=fl@UK@N?z6qM z<NywUdq{n}k?QX_Y-J+f=fp+4K2Ti!qfhmAgeUriL!^?J(deLsj?yL-)- zt5ak4tUbDW&55<3$#=jmr@}2nA K|5Y7h&1 >/dev/null + +# Other Targets +clean: + -$(RM) $(EXECUTABLES)$(OBJS) RF_Bridge.omf + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets +# echo the path +echo_path: + @echo PATH=$$PATH + @echo ' ' + diff --git a/Keil 8051 v9.53 - Release/objects.mk b/Keil 8051 v9.53 - Release/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/Keil 8051 v9.53 - Release/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Keil 8051 v9.53 - Release/sources.mk b/Keil 8051 v9.53 - Release/sources.mk new file mode 100644 index 0000000..9ed08b2 --- /dev/null +++ b/Keil 8051 v9.53 - Release/sources.mk @@ -0,0 +1,18 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +A51_UPPER_SRCS := +OBJ_UPPER_SRCS := +SRC_UPPER_SRCS := +ASM_SRCS := +C_SRCS := +S_UPPER_SRCS := +EXECUTABLES := +OBJS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +lib/efm8bb1/peripheralDrivers/src \ +src \ + diff --git a/README.md b/README.md new file mode 100644 index 0000000..91a48af --- /dev/null +++ b/README.md @@ -0,0 +1,58 @@ +# RF-Bridge-EFM8BB1 +RF-Bridge-EFM8BB1 + +The Sonoff RF Bridge is only supporting one protocol with 24 bits.
+The Idea is to write a alternative firmware for the onboard EFM8BB1 chip. + +# Hardware +There are the pins C2 & C2CK on the board. With a Arduino you can build a programmer to read/erase and program the flash. +Software for the Arduino: https://github.com/conorpp/efm8-arduino-programmer + +# Software +The project is written with Simplicity Studio 4. The resulting *.hex file can be programmed on the EFM8BB1. + +# First results +The reading of RF signals is already working:
+Sending start sniffing: 0xAA 0xA6 0x55
+Receiving AKN: 0xAA 0xA0 0x55
+ +Sending stop sniffing: 0xAA 0xA7 0x55
+Receiving AKN: 0xAA 0xA0 0x55
+ +## RF decode from Rohrmotor24.de remote (40 bit of data): +0xAA: uart sync init
+0xA6: sniffing active
+0x06: data len
+0x01: protocol identifier
+0xD0-0x55: data
+0x55: uart sync end + +STOP:
+Binary: 10101010 10100110 00000110 00000001 11010000 11111001 00110010 00010001 01010101 01010101
+Hex: AA A6 06 01 D0 F9 32 11 55 55
+DOWN:
+Binary: 10101010 10100110 00000110 00000001 11010000 11111001 00110010 00010001 00110011 01010101
+Hex: AA A6 06 01 D0 F9 32 11 33 55
+ +## RF decode from Seamaid_PAR_56_RGB remote (24 bit of data): +Light ON:
+Binary: 10101010 10100110 00000100 00000010 00110010 11111010 10001111 01010101
+Hex: AA A6 04 02 32 FA 8F 55
+ +## Transmiting by command 0xA8 +There is already a new command in the firmware to be able to send RF data.
+The original command isn't supported yet!
+ +Hex: AA A8 06 01 D0 F9 32 11 33 55
+ +0xAA: uart sync init
+0xA8: transmit RF data
+0x06: data len
+0x01: protocol identifier (ROHRMOTOR24)
+0xD0-0x55: data
+0x55: uart sync end + +# Next Steps +Add full support for the original firmware
+Add ESPurna support:
+A new protocol have to be implemented to support more RF signals -> have to be defined! \ No newline at end of file diff --git a/RF_Bridge.hwconf b/RF_Bridge.hwconf new file mode 100644 index 0000000..600a3c0 --- /dev/null +++ b/RF_Bridge.hwconf @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/inc/Globals.h b/inc/Globals.h new file mode 100644 index 0000000..957e80f --- /dev/null +++ b/inc/Globals.h @@ -0,0 +1,27 @@ +/* + * Globals.h + * + * Created on: 27.11.2017 + * Author: + */ + +#ifndef INC_GLOBALS_H_ +#define INC_GLOBALS_H_ + +// USER CONSTANTS +#define LED_ON 1 +#define LED_OFF 0 + +#define BUZZER_ON 1 +#define BUZZER_OFF 0 + +#define TDATA_ON 1 +#define TDATA_OFF 0 + +// USER PROTOTYPES +SI_SBIT(LED, SFR_P1, 0); // LED +SI_SBIT(T_DATA, SFR_P0, 0); // T_DATA +SI_SBIT(R_DATA, SFR_P1, 3); // R_DATA +SI_SBIT(BUZZER, SFR_P1, 6); // BUZZER + +#endif /* INC_GLOBALS_H_ */ diff --git a/inc/InitDevice.h b/inc/InitDevice.h new file mode 100644 index 0000000..cd3d075 --- /dev/null +++ b/inc/InitDevice.h @@ -0,0 +1,35 @@ +//========================================================= +// inc/InitDevice.h: generated by Hardware Configurator +// +// This file will be regenerated when saving a document. +// leave the sections inside the "$[...]" comment tags alone +// or they will be overwritten! +//========================================================= +#ifndef __INIT_DEVICE_H__ +#define __INIT_DEVICE_H__ + +// USER CONSTANTS +// USER PROTOTYPES + +// $[Mode Transition Prototypes] +extern void enter_DefaultMode_from_RESET(void); +// [Mode Transition Prototypes]$ + +// $[Config(Per-Module Mode)Transition Prototypes] +extern void WDT_0_enter_DefaultMode_from_RESET(void); +extern void PORTS_0_enter_DefaultMode_from_RESET(void); +extern void PORTS_1_enter_DefaultMode_from_RESET(void); +extern void PBCFG_0_enter_DefaultMode_from_RESET(void); +extern void CLOCK_0_enter_DefaultMode_from_RESET(void); +extern void TIMER01_0_enter_DefaultMode_from_RESET(void); +extern void TIMER16_3_enter_DefaultMode_from_RESET(void); +extern void TIMER_SETUP_0_enter_DefaultMode_from_RESET(void); +extern void PCA_0_enter_DefaultMode_from_RESET(void); +extern void PCACH_0_enter_DefaultMode_from_RESET(void); +extern void PCACH_1_enter_DefaultMode_from_RESET(void); +extern void UART_0_enter_DefaultMode_from_RESET(void); +extern void INTERRUPT_0_enter_DefaultMode_from_RESET(void); +// [Config(Per-Module Mode)Transition Prototypes]$ + +#endif + diff --git a/inc/RF_Handling.h b/inc/RF_Handling.h new file mode 100644 index 0000000..660bfc3 --- /dev/null +++ b/inc/RF_Handling.h @@ -0,0 +1,48 @@ +/* + * RF_Handling.h + * + * Created on: 28.11.2017 + * Author: + */ + +#ifndef INC_RF_HANDLING_H_ +#define INC_RF_HANDLING_H_ + +extern void SendRF_SYNC(uint8_t used_protocol); +extern uint8_t PCA0_DoTransmit(uint8_t identifier); +extern void PCA0_StopTransmit(void); +extern void PCA0_DoSniffing(void); +extern void PCA0_StopSniffing(void); + +#define SYSCLK 24500000 +// 64 byte == 512 bits, so a RF signal with maximum of 512 bits is possible +#define RF_DATA_BUFFERSIZE 64 + +typedef enum +{ + RF_IDLE, + RF_IN_SYNC +} rf_state_t; + +#define RF_DATA_RECEIVED_MASK 0x80 + +extern SI_SEGMENT_VARIABLE(RF_DATA[RF_DATA_BUFFERSIZE], uint8_t, SI_SEG_XDATA); +// RF_DATA_STATUS +// Bit 7: 1 Data received, 0 nothing received +// Bit 6-0: Protocol identifier +extern SI_SEGMENT_VARIABLE(RF_DATA_STATUS, uint8_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(Timer_3_Timeout, uint16_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(sniffing_is_on, uint8_t, SI_SEG_XDATA); + +extern SI_SEGMENT_VARIABLE(DUTY_CYCLE_HIGH, uint8_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(DUTY_CYLCE_LOW, uint8_t, SI_SEG_XDATA); + +extern SI_SEGMENT_VARIABLE(actual_bit_of_byte, uint8_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(actual_bit, uint8_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(actual_byte, uint8_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(protocol_index, uint8_t, SI_SEG_XDATA); + +extern uint8_t testbyte; + + +#endif /* INC_RF_HANDLING_H_ */ diff --git a/inc/RF_Protocols.h b/inc/RF_Protocols.h new file mode 100644 index 0000000..793f289 --- /dev/null +++ b/inc/RF_Protocols.h @@ -0,0 +1,60 @@ +/* + * RF_Protocols.h + * + * Created on: 28.11.2017 + * Author: + */ + +#ifndef INC_RF_PROTOCOLS_H_ +#define INC_RF_PROTOCOLS_H_ + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include + +typedef struct +{ + // Protocol specific identifier + uint8_t IDENTIFIER; + // normal high signal time on sync pulse + uint16_t SYNC_HIGH; + // normal low signal time on sync pulse + uint16_t SYNC_LOW; + // time in µs for one bit. This is the sum of the high and low time of on bit + // example bit 1: high time 700µs, low time 300µs: sum is 1000µs == 1kHz + uint16_t BIT_TIME; + // duty cycle for logic bit 1 + uint8_t BIT_HIGH_DUTY; + // duty cycle for logic bit 0 + uint8_t BIT_LOW_DUTY; + // bit count for this protocol + uint8_t BIT_COUNT; +} PROTOCOL_DATA_t; + +#define SYNC_TOLERANCE 200 + +/* + * Rohrmotor24 + * https://github.com/bjwelker/Raspi-Rollo/tree/master/Arduino/Rollo_Code_Receiver + */ +#define ROHRMOTOR24_IDENTIFIER 0x01 +#define ROHRMOTOR24 {ROHRMOTOR24_IDENTIFIER, 4800, 1500, 1000, 30, 70, 40} + +/* + * UNDERWATER PAR56 LED LAMP, 502266 + * http://www.seamaid-lighting.com/de/produit/lampe-par56/ + */ +#define Seamaid_PAR_56_RGB_IDENTIFIER 0x02 +#define Seamaid_PAR_56_RGB {Seamaid_PAR_56_RGB_IDENTIFIER, 3000, 9000, 1500, 25, 75, 24} + + +/* + * Protocol array + */ +static const PROTOCOL_DATA_t PROTOCOL_DATA[2] = { ROHRMOTOR24, Seamaid_PAR_56_RGB}; +#define PROTOCOLCOUNT sizeof PROTOCOL_DATA / sizeof PROTOCOL_DATA[0] + + + +#endif /* INC_RF_PROTOCOLS_H_ */ diff --git a/inc/efm8_config.h b/inc/efm8_config.h new file mode 100644 index 0000000..e297c77 --- /dev/null +++ b/inc/efm8_config.h @@ -0,0 +1,15 @@ +/****************************************************************************** + * Copyright (c) 2014 by Silicon Laboratories Inc. All rights reserved. + * + * http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt + *****************************************************************************/ + +#ifndef __EFM8_CONFIG_H__ +#define __EFM8_CONFIG_H__ + +#define EFM8PDL_PCA0_USE_ISR 1 +#define EFM8PDL_UART0_USE_STDIO 0 +#define EFM8PDL_UART0_USE_BUFFER 0 + +#endif // __EFM8_CONFIG_H__ + diff --git a/inc/uart.h b/inc/uart.h new file mode 100644 index 0000000..fa8bbe8 --- /dev/null +++ b/inc/uart.h @@ -0,0 +1,74 @@ +/* + * uart.h + * + * Created on: 28.11.2017 + * Author: + */ + +#ifndef INC_UART_H_ +#define INC_UART_H_ + +//----------------------------------------------------------------------------- +// Global Constants +//----------------------------------------------------------------------------- +//#define UART_BUFFER_LENGTH 64 + 4 +#define UART_SYNC_INIT 0xAA +#define UART_SYNC_END 0x55 + +#define UART_BUFFER_SIZE 64 + 4 + +/* +** high byte error return code of uart_getc() +*/ +#define UART_FRAME_ERROR 0x1000 /* Framing Error by UART */ +#define UART_OVERRUN_ERROR 0x0800 /* Overrun condition by UART */ +#define UART_PARITY_ERROR 0x0400 /* Parity Error by UART */ +#define UART_BUFFER_OVERFLOW 0x0200 /* receive ringbuffer overflow */ +#define UART_NO_DATA 0x0100 /* no receive data available */ +//----------------------------------------------------------------------------- +// Global Enums +//----------------------------------------------------------------------------- +typedef enum +{ + IDLE, + SYNC_INIT, + SYNC_FINISH, + RECEIVE_LEN, + RECEIVING, + TRANSMIT, + COMMAND +} uart_state_t; + +typedef enum +{ + NONE = 0x00, + COMMAND_AK = 0xA0, + LEARNING = 0xA1, + TIMEOUT_EXITS = 0xA2, + LEARNING_SUCCESS = 0xA3, + FORWARD_RF_KEY = 0xA4, + TRANSMIT_KEY = 0xA5, + SNIFFING_ON = 0xA6, + SNIFFING_OFF = 0xA7, + TRANSMIT_DATA = 0xA8 +} uart_command_t; + + +//----------------------------------------------------------------------------- +// Global Variables +//----------------------------------------------------------------------------- +extern SI_SEGMENT_VARIABLE(UART_RX_Buffer[UART_BUFFER_SIZE], uint8_t, SI_SEG_XDATA); +extern SI_SEGMENT_VARIABLE(UART_TX_Buffer[UART_BUFFER_SIZE], uint8_t, SI_SEG_XDATA); +extern uart_state_t uart_state; + +extern void uart_buffer_reset(void); +extern uint8_t uart_getlen(void); +extern bool uart_transfer_finished(void); +extern unsigned int uart_getc(void); +extern void uart_putc(uint8_t txdata); +extern void uart_put_command(uint8_t command); +extern void uart_put_uint16_t(uint8_t command, uint16_t value); +extern void uart_put_RF_Data(uint8_t Command, uint8_t used_protocol); + + +#endif /* INC_UART_H_ */ diff --git a/lib/efm8bb1/peripheralDrivers/inc/pca_0.h b/lib/efm8bb1/peripheralDrivers/inc/pca_0.h new file mode 100644 index 0000000..a45de9c --- /dev/null +++ b/lib/efm8bb1/peripheralDrivers/inc/pca_0.h @@ -0,0 +1,601 @@ +/****************************************************************************** + * Copyright (c) 2014 by Silicon Laboratories Inc. All rights reserved. + * + * http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt + *****************************************************************************/ + +#ifndef __PCA_0_H__ +#define __PCA_0_H__ + + +#include "efm8_config.h" +#include "SI_EFM8BB1_Register_Enums.h" + +/**************************************************************************//** + * @addtogroup pca_0 PCA0 Driver + * @{ + * + * @brief Peripheral driver for PCA0 + * + * # Introduction # + * + * This module contains all the driver content for PCA0 + * + * @warning The WDT0 module on this device interacts with the PCA. + * + * ### Memory Usage ### + * + * The table below shows the memory consumption of the library with various + * options. The 'default' entry shows the consumption when most or all available + * functions are called. Typical consumption is expected to be less than this + * since there are normally many uncalled functions that will consume no + * resources. + * + * @note It is possible for memory usage to exceed the listed values in rare cases + * + * | condition | CODE | XRAM | IRAM | RAM | + * |--------------------|------|------|------|-----| + * |default | 504 | 0 | 0 | 0 | + * + * # Theory of Operation # + * + * The Programable counter array provides 3 main catagories of functionality. + * + * - PWM + * - Counter/capture + * - Timer + * + * It consists of a single counter/timer and several channels which all operate + * using the single counter. + * + * ### Timer operations ### + * + * The PCA can be used to provide basic timer operations. The timer period + * is determined by the timer configuration. Each PCA channel may fire an + * interrupt at an independent point in the period. For example We may set up + * the timer to overflow (and provide an interrupt) every 100 cycles. We can + * then configure on channel to provide an interrupt at 90 cycles and another + * at 50 cycles. This would generate a 'half-way' and 'early-warning' + * interrupts. + * + * ### PWM operations ### + * + * The PCA can be configured to output PWM waveforms (or square waveforms). + * The period of the PWM is controlled by the time an thus the same for all + * channels. The duty cycle and polarity is controlled by each channel + * independently. + * + * A related mode is high frequency output mode where each PCA channel can be + * configured to toggle it's output ever N ticks of the timer. This allows + * each module to independently generate a digital frequency. + * + * ### Capture operations ### + * + * The state of the timer can be captured by a PCA channel based on several + * triggers. The captured value can then be used for various operations. + * + * For example if channel 0 captures on the rising edge of a signal and + * channel 0 captures on the falling edge of that same signal then the + * high pulse with time can be calculated by the equation. + * time = (ch1_value - ch0_value) * period_of_timer + * + * Another mode of operation is to + * + * ### Watch Dog Timer ### + * + * While the Peripheral Driver Library defines a separate module for interacting with the + * watch-dog timer the WDT is physically located in channel 4 of the PCA on this device. + * Any changes to the counter in the WDT or PCA block will effect the other block. In + * addition when the WDT is in used PCA channel 4 is unavailable. + * + * Runtime asserts have been placed in this module to help highlight cases where the + * WDT and PCA interfere with one another. However it is not possible to catch all + * issues and the user needs to be aware of this interaction. + * + * ### Hardware Configuration ### + * + * This driver provides basic facilities for configuring the PCA. + * it is recommended that Simplicity Hardware Configurator be for more + * advanced configuration as it provides more comprehensive validation + * of user selections. + * + *****************************************************************************/ + +//Option macro documentation +/**************************************************************************//** + * @addtogroup pca0_config Driver Configuration + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @def EFM8PDL_PCA0_USE_ISR + * @brief Controls inclusion of PCA0 ISR and associated callbacks. + * + * When '1' the PCA0 ISR in the driver is used and callbacks are functional. + * + * Default setting is '1' and may be overridden by defining in 'efm8_config.h'. + * + *****************************************************************************/ +/** @} (end addtogroup pca0_config Driver Configuration) */ + +//Configuration defaults +#ifndef IS_DOXYGEN + #define IS_DOXYGEN 0 +#endif + +#ifndef EFM8PDL_PCA0_USE_ISR + #define EFM8PDL_PCA0_USE_ISR 1 +#endif + +// Runtime API +/**************************************************************************//** + * @addtogroup pca0_runtime PCA0 Runtime API + * @{ + *****************************************************************************/ + +/// PCA Channel Enumeration +typedef enum +{ + PCA0_CHAN0 = 0x0, //!< PCA Channel 0 + PCA0_CHAN1 = 0x1, //!< PCA Channel 1 + PCA0_CHAN2 = 0x2, //!< PCA Channel 2 + +#if IS_DOXYGEN + PCA0_CHAN3 = -1, //!< NOT SUPPORTED ON THIS DEVICE + PCA0_CHAN4 = -1, //!< NOT SUPPORTED ON THIS DEVICE + PCA0_CHAN5 = -1, //!< NOT SUPPORTED ON THIS DEVICE +#endif +} PCA0_Channel_t; + +/**************************************************************************//** + * @addtogroup pca0_if Interrupt Flag Enums + * @{ + ******************************************************************************/ +#define PCA0_OVERFLOW_IF PCA0CN0_CF__BMASK //!< Counter overflow flag +#define PCA0_IOVERFLOW_IF PCA0PWM_COVF__BMASK //!< Intermediate overflow flag +#define PCA0_CHAN0_IF PCA0CN0_CCF0__BMASK //!< Channel 0 +#define PCA0_CHAN1_IF PCA0CN0_CCF1__BMASK //!< Channel 1 +#define PCA0_CHAN2_IF PCA0CN0_CCF2__BMASK //!< Channel 2 + +#if IS_DOXYGEN + #define PCA0_CHAN3_IF -1 //!< @warning NOT SUPPORTED ON THIS DEVICE + #define PCA0_CHAN4_IF -1 //!< @warning NOT SUPPORTED ON THIS DEVICE + #define PCA0_CHAN5_IF -1 //!< @warning NOT SUPPORTED ON THIS DEVICE +#endif +/** @} (end addtogroup pca0_if Interrupt Flag Enums) */ + +/***************************************************************************//** + * @brief + * Return the value of the interrupt flags + * + * @return + * The state of the flags. This value is the OR of all flags which are set. + * + * Valid enums can be fond in the Interrupt Flag Enums group. + * + ******************************************************************************/ +uint8_t PCA0_getIntFlags(); + +/***************************************************************************//** + * @brief + * Clear the specified status flag + * + * @param flag: + * Flag to clear. Multiple flags can be cleared by OR-ing the flags. + * + * Valid enums can be found in the Interrupt Flag Enums group. + ******************************************************************************/ +void PCA0_clearIntFlag(uint8_t flag); + +/***************************************************************************//** + * @brief + * Enable or disable the PCA interrupts + * + * @param flag: + * Interrupt to be enabled/disabled + * @param enable: + * New target status (true to enable) + * + * Multiple interrupts may be enabled/disabled at a time by or-ing their flags + * + * Valid enums can be found in the Interrupt Flag Enums group. + * + ******************************************************************************/ +void PCA0_enableInt(uint8_t flag, bool enable); + +/***************************************************************************//** + * @brief + * Read the channel capture/compare register + * + * @param channel: + * Channel to read. + * + * @return + * Current value of capture/compare register for the specified channel. + * + ******************************************************************************/ +uint16_t PCA0_readChannel(PCA0_Channel_t channel); + +/***************************************************************************//** + * @brief + * Write the channel capture.compare register + * + * @param channel: + * Channel to read. + * @param value: + * Value to write to capture/compare register. + * + ******************************************************************************/ +void PCA0_writeChannel(PCA0_Channel_t channel, uint16_t value); + +/***************************************************************************//** + * @brief + * Read the PCA counter. + * + * @return + * Current value of the PCA counter. + ******************************************************************************/ +uint16_t PCA0_readCounter(); + +/***************************************************************************//** + * @brief + * Write to the PCA counter. + * + * @param value: + * Value to write to PCA counter. + * + ******************************************************************************/ +void PCA0_writeCounter(uint16_t value); + +/***************************************************************************//** + * @brief + * Start the PCA Counter. + * + ******************************************************************************/ +void PCA0_run(); + +/***************************************************************************//** + * @brief + * Stop the PCA Counter. + * + ******************************************************************************/ +void PCA0_halt(); + +/** @} (end addtogroup pca0_runtime PCA0 Runtime API) */ + +// Initialization API +/**************************************************************************//** + * @addtogroup pca0_init PCA0 Initialization API + * @{ + *****************************************************************************/ + +/// @brief Clock Selection Enum. +typedef enum +{ + PCA0_SYSCLK_DIV12 = PCA0MD_CPS__SYSCLK_DIV_12, //!< Select SystemClock/12 + PCA0_SYSCLK_DIV4 = PCA0MD_CPS__SYSCLK_DIV_4, //!< Select SystemClock/4 + PCA0_TIMER0 = PCA0MD_CPS__T0_OVERFLOW, //!< Select Timer0 Overflow + PCA0_ECI = PCA0MD_CPS__ECI, //!< Select ECI falling edge + PCA0_SYSCLK = PCA0MD_CPS__SYSCLK, //!< Select SystemClock + PCA0_EXTOSC_DIV8 = PCA0MD_CPS__EXTOSC_DIV_8, //!< Select ExternalOsc/8 + PCA0_LFOSC_DIV8 = PCA0MD_CPS__LFOSC_DIV_8, //!< Select LowFrequencyOsc/8 +} PCA0_Timebase_t; + +/// @brief Channel mode enum. +typedef enum +{ + //xx10 000* (CPM) 0x20 + //0x*0 0xxx (PWM) + PCA0_CAPTURE_POS_CEX = PCA0CPM0_PWM16__8_BIT //!< Capture mode triggered by CEX rising + | PCA0CPM0_ECOM__DISABLED + | PCA0CPM0_CAPP__ENABLED + | PCA0CPM0_CAPN__DISABLED + | PCA0CPM0_MAT__DISABLED + | PCA0CPM0_TOG__DISABLED + | PCA0CPM0_PWM__DISABLED, + + //xx01 000* (CPM) 0x10 + //0x*0 0xxx (PWM) + PCA0_CAPTURE_NEG_CEX = PCA0CPM0_PWM16__8_BIT //!< Capture mode triggered by CEX falling + | PCA0CPM0_ECOM__DISABLED + | PCA0CPM0_CAPP__DISABLED + | PCA0CPM0_CAPN__ENABLED + | PCA0CPM0_MAT__DISABLED + | PCA0CPM0_TOG__DISABLED + | PCA0CPM0_PWM__DISABLED, + + //xx11 000* (CPM) 0x30 + //0x*0 0xxx (PWM) + PCA0_CAPTUE_TOGGLE_CEX = PCA0CPM0_PWM16__8_BIT //!< Capture Mode triggered by CEX rising or falling + | PCA0CPM0_ECOM__DISABLED + | PCA0CPM0_CAPP__ENABLED + | PCA0CPM0_CAPN__ENABLED + | PCA0CPM0_MAT__DISABLED + | PCA0CPM0_TOG__DISABLED + | PCA0CPM0_PWM__DISABLED, + + //x100 100* (CPM) 0x48 + //0x*0 0xxx (PWM) + PCA0_TIMER = PCA0CPM0_PWM16__8_BIT //!< Timer mode + | PCA0CPM0_ECOM__ENABLED + | PCA0CPM0_CAPP__DISABLED + | PCA0CPM0_CAPN__DISABLED + | PCA0CPM0_MAT__ENABLED + | PCA0CPM0_TOG__DISABLED + | PCA0CPM0_PWM__DISABLED, + + //x100 110* (CPM) 0x4C + //0x*0 0xxx (PWM) + PCA0_HIGH_SPEED_OUT = PCA0CPM0_PWM16__8_BIT //!< High speed output mode + | PCA0CPM0_ECOM__ENABLED + | PCA0CPM0_CAPP__DISABLED + | PCA0CPM0_CAPN__DISABLED + | PCA0CPM0_MAT__ENABLED + | PCA0CPM0_TOG__ENABLED + | PCA0CPM0_PWM__DISABLED, + + //x100 011* (CPM) 0x46 + //0x*0 0xxx (PWM) + PCA0_FREQUENCY_OUT = PCA0CPM0_PWM16__8_BIT //!< High frequency output mode + | PCA0CPM0_ECOM__ENABLED + | PCA0CPM0_CAPP__DISABLED + | PCA0CPM0_CAPN__DISABLED + | PCA0CPM0_MAT__DISABLED + | PCA0CPM0_TOG__ENABLED + | PCA0CPM0_PWM__ENABLED, + + //0111 101* (CPM) 0x4A + //10*0 0000 (PWM) 0x80 + PCA0_PWM8 = PCA0CPM0_PWM16__8_BIT //!< 8-bit PWM (edge aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__8_BITS, + + PCA0_PWM8_CENTER = PCA0CPM0_PWM16__8_BIT //!< 8-bit PWM (center aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__8_BITS + | 0x08, //center alignment + + //0111 101* (CPM) 0x4A + //10*0 0001 (PWM) 0x81 + PCA0_PWM9 = PCA0CPM0_PWM16__8_BIT //!< 9-bit PWM (edge aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__9_BITS, + + PCA0_PWM9_CENTER = PCA0CPM0_PWM16__8_BIT //!< 9-bit PWM (center aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__9_BITS + | 0x08, //center alignment + + //0111 101* (CPM) 0x4A + //10*0 0010 (PWM) 0x82 + PCA0_PWM10 = PCA0CPM0_PWM16__8_BIT //!< 10-bit PWM (edge aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__10_BITS, + + PCA0_PWM10_CENTER = PCA0CPM0_PWM16__8_BIT //!< 10-bit PWM (center aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__10_BITS + | 0x08, //center alignment + + //0111 101* (CPM) 0x4A + //10*0 0011 (PWM) 0x83 + PCA0_PWM11 = PCA0CPM0_PWM16__8_BIT //!< 11-bit PWM (edge aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__11_BITS, + + PCA0_PWM11_CENTER = PCA0CPM0_PWM16__8_BIT //!< 11-bit PWM (center aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__11_BITS + | 0x08, //center alignment + + //1111 101* (CPM) 0xCA + //00*0 0xxx (PWM) 0x00 + PCA0_PWM16 = PCA0CPM0_PWM16__16_BIT //!< 16-bit PWM (edge aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__11_BITS, + //1111 101* (CPM) 0xCA + //00*0 0xxx (PWM) 0x00 + + PCA0_PWM16_CENTER = PCA0CPM0_PWM16__16_BIT //!< 16-bit PWM (center aligned) + | PCA0CPM0_ECOM__ENABLED + | 0x30 //Code for n-bit PWM + | PCA0PWM_CLSEL__11_BITS + | 0x08, //center alignment +} PCA0_ChannelMode_t; + + +/// @brief Output Polarity enum. +typedef enum +{ + PCA0_NORMAL_POLARITY = 0x0, //!< normal channel out + PCA0_INVERT_POLARITY = 0x1, //!< normal channel out +} PCA0_ChannelOutPolatiry_t; + +/// @brief Idle state of PCA Counter +typedef enum +{ + PCA0_IDLE_RUN = PCA0MD_CIDL__NORMAL, //!< PCA runs when idle + PCA0_IDLE_SUSPEND = PCA0MD_CIDL__SUSPEND, //!< PCA suspended when idle +} PCA0_IdleState_t; + + +/***************************************************************************//** + * @brief Initialize the PCA + * + * @param timebase: + * Timebase selection. + * @param idleState: + * Idle state selection. + * + ******************************************************************************/ +void PCA0_init(PCA0_Timebase_t timebase, PCA0_IdleState_t idleState); + +/**************************************************************************//** + * @brief + * Initialize the PCA Channel. + * + * @param channel: + * The channel to initialize. + * @param mode: + * The desired mode for this channel. + * @param pol: + * Desired output polarity for this channel. + * + * This function initialized the PCA channel including setting up + * the shared PCA0PWM register. + * + * @warning + * All channels in 8-11 bit PWM mode must be in the same + * mode. You can not use 8-bit PWM for one channel and 11-bit PWM + * for another. The N-bit PWM mode will be set to whatever was + * specified in the last call to PCA0_init Channel. + * + *****************************************************************************/ +void PCA0_initChannel(PCA0_Channel_t channel, + PCA0_ChannelMode_t mode, + PCA0_ChannelOutPolatiry_t pol + ); +/***************************************************************************//** + * @brief + * Restore the PCA to it's uninitialized (reset) state. + * + * This function restores the entire PCA INCLUDING ALL CHANNELS to default values. + ******************************************************************************/ +void PCA0_reset(); + +/***************************************************************************//** + * @brief + * Restore the PCA Channel to it's uninitialized (reset) state. + * + * @param channel: + * Channel to reset; + * + * This function restores only the specified channels to the reset state. + ******************************************************************************/ +void PCA0_resetChannel(PCA0_Channel_t channel); + +/** @} (end addtogroup pca0_init PCA0 Initialization API) */ + +//========================================================= +// ISR API +//========================================================= +#if (EFM8PDL_PCA0_USE_ISR == 1) || IS_DOXYGEN +/**************************************************************************//** + * @def void PCA0_ISR() + * @brief PCA Interrupt handler (not a callback). + * + * This ISR is provided by the library when EFM8PDL_PCA0_USE_ISR = "1". + * + *****************************************************************************/ +#endif //EFM8PDL_PCA0_USE_ISR + +// Callbacks +/**************************************************************************//** + * @addtogroup pca0_callback User Callbacks + * @{ + *****************************************************************************/ +#if (EFM8PDL_PCA0_USE_ISR == 1) || IS_DOXYGEN + +/***************************************************************************//** + * @addtogroup pca0_callbacks_isr ISR API + * @{ + * + * These callbacks will be called by the library when + * EFM8PDL_PCA0_USE_ISR. If the ISR Api is disabled + * the callbacks do not need to be provided by the user. + * + *****************************************************************************/ + +/***************************************************************************//** + * @brief + * Callback for overflow of PCA. + * + * This function is defined by the user and called by the peripheral driver the PCA counter overflows. + * + * @warning + * This function is called from an ISR and should be as short as possible. + * + ******************************************************************************/ +extern void PCA0_overflowCb(); + +/***************************************************************************//** + * @brief + * Callback for intermediate overflow of PCA. + * + * This function is defined by the user and called by the peripheral driver the + * PCA counter half way point is reached as defined by the N-bit PWM settings. + * + * @warning + * This function is called from an ISR and should be as short as possible + * + ******************************************************************************/ +extern void PCA0_intermediateOverflowCb(); + +/***************************************************************************//** + * @brief + * Callback for channel 0 events. + * + * This function is defined by the user and called when there is a capture + * or compare event on channel 0 + * + * @warning + * This function is called from an ISR and should be as short as possible. + * + ******************************************************************************/ +extern void PCA0_channel0EventCb(); + +/***************************************************************************//** + * @brief + * Callback for channel 1 events. + * + * This function is defined by the user and called when there is a capture + * or compare event on channel 1 + * + * @warning + * This function is called from an ISR and should be as short as possible. + * + ******************************************************************************/ +extern void PCA0_channel1EventCb(); + +/***************************************************************************//** + * @brief + * Callback for channel 2 events. + * + * This function is defined by the user and called when there is a capture + * or compare event on channel 2 + * + * @warning + * This function is called from an ISR and should be as short as possible. + * + ******************************************************************************/ +extern void PCA0_channel2EventCb(); + +/**************************************************************************//** + * @def void PCA0_channel3EventCb() + * @warning NOT SUPPORTED ON THIS DEVICE + *****************************************************************************/ + +/**************************************************************************//** + * @def void PCA0_channel4EventCb() + * @warning NOT SUPPORTED ON THIS DEVICE + *****************************************************************************/ + +/**************************************************************************//** + * @def void PCA0_channel5EventCb() + * @warning NOT SUPPORTED ON THIS DEVICE + *****************************************************************************/ + +#endif //EFM8PDL_PCA0_USE_ISR +/** @} (end addtogroup pca0_callbacks_isr ISR API) */ +/** @} (end addtogroup pca0_callback User Callbacks) */ +/** @} (end addtogroup PCA0 Driver) */ +#endif //__PCA_0_H__ diff --git a/lib/efm8bb1/peripheralDrivers/inc/uart_0.h b/lib/efm8bb1/peripheralDrivers/inc/uart_0.h new file mode 100644 index 0000000..f520a22 --- /dev/null +++ b/lib/efm8bb1/peripheralDrivers/inc/uart_0.h @@ -0,0 +1,632 @@ +/****************************************************************************** + * Copyright (c) 2014 by Silicon Laboratories Inc. All rights reserved. + * + * http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt + *****************************************************************************/ + +#ifndef __UART_0_H__ +#define __UART_0_H__ + + +#include "efm8_config.h" +#include "SI_EFM8BB1_Register_Enums.h" + +/**************************************************************************//** + *@addtogroup uart_0 UART0 Driver + *@{ + * + *@brief Peripheral driver for uart0 + * + * # Introduction # + * + * This module contains all the driver content for UART0 + * + * ### Memory Usage ### + * + * The table below shows the memory consumption of the library with various + * options. The 'default' entry shows the consumption when most or all available + * functions are called. Typical consumption is expected to be less than this + * since there are normally many uncalled functions that will consume no + * resources. + * + * @note It is possible for memory usage to exceed the listed values in rare cases + * + * | condition | CODE | XRAM | IRAM | RAM | + * |--------------------|------|------|------|-----| + * |USE | 295 | 6 | 0 | 0 | + * |STDIO | 20 | 0 | 0 | 0 | + * + * # Theory of Operation # + * + * The UART driver provides several levels of functionality. Higher level + * functionality is more user friendly but also less broadly applicable. + * + * ### Buffered Api ### + * + * The driver provides high level functions for transferring a buffer of data. + * This functionality is made available by setting EFM8PDL_UART0_USE_BUFFER + * to 1. + * + * This functionality relies on the UART0 interrupt to function and the + * library provides the ISR for that interrupt. + * + * For data transmission the user provides a data buffer and the length of that + * buffer. The driver will then transmit the entire buffer before issuing an + * end-of-transfer callback. + * + * In the following example we implement a ping-pong transmission. + * + * ~~~~~.c + * + * SI_SEGMENT_VARIABLE(bufferA[32], uint8_t, SI_SEG_XDATA); + * SI_SEGMENT_VARIABLE(bufferB[32], uint8_t, SI_SEG_XDATA); + * SI_VARIABLE_SEGMENT_POINTER(curBuffer, uint8_t, SI_SEG_XDATA); + * bool targetA; + * + * // Some other code pushes data to curBuffer and handles + * // kicking the transfer with an initial call to writeBuffer + * + * //when current transfer is complete send switch ping-pong + * // and send all data accumulated in the other buffer. + * // If no data is ready in other buffer we will write + * void UART0_transmitCompleteCb() + * { + * if(targetA) + * { + * //Don't transmit if no data is available + * if(curBuffer == bufferA) + * { + * //Some code to mark that the transfer is stalled + * return; + * } + * + * // Send all data in A and start accumulating in B + * UART0_writeBuffer(bufferA, curBuffer - bufferA); + * curBuffer = bufferB; + * targetA = false; + * } + * else + * { + * //Don't transmit if no data is available + * if(curBuffer == bufferA) + * { + * //Some code to mark that the transfer is stalled + * return; + * } + * + * //send all data in B and start accumulating in A + * UART0_writeBuffer(bufferA, curBuffer - bufferA); + * curBuffer = bufferA; + * targetA = true; + * } + * } + * + * ~~~~~ + * + * For reception the user provides a buffer and it's size. The library will + * receive data into the buffer until it is full and then call the user + * back. The user may query the number of bytes remaining in the buffer at + * any time if they wish to process data before the buffer is full. + * + * This example provides ping-pong reception. + * + * ~~~~~.c + * + * SI_SEGMENT_VARIABLE(bufferA[32], uint8_t, SI_SEG_XDATA); + * SI_SEGMENT_VARIABLE(bufferB[32], uint8_t, SI_SEG_XDATA); + * SI_VARIABLE_SEGMENT_POINTER(curBuffer, uint8_t, SI_SEG_XDATA); + * SI_VARIABLE_SEGMENT_POINTER(dataReady, uint8_t, SI_SEG_XDATA); + * bool targetA; + * + * //Here the main loop handles stuff + * void main() + * { + * //other initialization + * UART0_readBuffer(bufferA, 32); + * targetA = true; + * + * while(1) + * { + * if(dataReady != NULL) + * { + * //process data + * dataReady = NULL; + * } + * } + * } + * + * // When the current buffer is full inform the main loop it's + * //ready for processing and switch to the other buffer + * void UART0_receiveCompleteCb() + * { + * if(targetA) + * { + * datReady = bufferA; + * UART0_readBuffer(bufferB, 32); + * targetA = false; + * } + * else + * { + * datReady = bufferB; + * UART0_readBuffer(bufferA, 32); + * targetA = true; + * } + * } + * + * ~~~~~ + * + * ### STDIO Api ### + * + * One of the simplest use cases is using UART 0 to stdio data. The driver + * provides a standard blocking implementation accessed by setting + * EFM8PDL_UART0_USE_STDIO. + * + * When this is in use no other functions are available. + * + * When this is in use calls to printf will block until the entire string + * has been transmitted on the uart. + * + * ### Runtime & Initialization API ### + * + * The final option is to use the runtime and initialization api to implement + * a custom uart driver. + * + * The reference manual should be consulted for a full understanding of how + * the block operates in order to use the Runtime api correctly. + * + * ### Hardware Configuration ### + * + * This Driver provides a basic level of configuration through the API. However + * use of the Simplicity Hardware Configuration tool is highly recommended. + * + *****************************************************************************/ + +// Option macro documentation +/**************************************************************************//** + * @addtogroup uart0_config Driver Configuration + * @{ + *****************************************************************************/ + +/***************************************************************************//** + * @def EFM8PDL_UART0_USE + * @brief Controls inclusion of UART0 Peripheral Driver. + * + * + * When '1' the UART0 driver is available. + * + * Default setting is '0' and may be overridden by defining in 'efm8_config.h'. + * + *****************************************************************************/ + +/**************************************************************************//** + * @def EFM8PDL_UART0_USE_STDIO + * @brief Controls the inclusion of putchar and setchar for use with printf/scanf. + * + * When '1' blocking implementations of putchar and set char are defined. This option + * is intended to be use in place of all other options. If EFM8PDL_UART0_USE_STDIO + * is '1' then EFM8PDL_UART0_USE should be 0 and the UART 0 peripheral driver should + * not be called by the user directly accept for the initial setup. + * + * The putchar implementation provides an initialization function to prime the TX transfer + * and configure the UART for receive and transmit. This function should be called immediately + * after device configuration and before any printf or scanf calls. + * + * Default setting is '0' and may be overridden by defining in 'efm8_config.h'. + * + *****************************************************************************/ + +/**************************************************************************//** + * @def EFM8PDL_UART0_USE_INIT + * @brief Controls inclusion of UART0 Initialization API. + * + * When '1' the UART0 Initialization API is included in the driver. + * + * Default setting is '1' and may be overridden by defining in 'efm8_config.h'. + * + *****************************************************************************/ + +/**************************************************************************//** + * @def EFM8PDL_UART0_USE_BUFFER + * @brief Controls inclusion of UART0 Buffer Access API. + * + * When '1' the UART0 Buffered Access API is included in the driver. + * + * Default setting is '1' and may be overridden by defining in 'efm8_config.h'. + * + *****************************************************************************/ + +/**************************************************************************//** + * @addtogroup uart0_config_buffered Buffered API Options + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @def EFM8PDL_UART0_RX_BUFTYPE + * @brief Controls the type of pointer used for buffered receives. + * + * Sets the memory segment for the rx data buffer pointer when EFM8PDL_UART0_USE_BUFFER is '1' + * valid values are: + * + * - SI_SEG_XDATA (default) + * - SI_SEG_PDATA + * - SI_SEG_IDATA + * - SI_SEG_CODE + * - SI_SEG_GENERIC + * + * @warning: Use of generic pointers will adversely effect the size and performance + * of the buffering functions. + * + *****************************************************************************/ + +/**************************************************************************//** + * @def EFM8PDL_UART0_TX_BUFTYPE + * @brief Controls the type of pointer used for buffered transmits. + * + * Sets the memory segment for the tx data buffer pointer when EFM8PDL_UART0_USE_BUFFER is '1' + * valid values are: + * + * - SI_SEG_XDATA (default) + * - SI_SEG_PDATA + * - SI_SEG_IDATA + * - SI_SEG_CODE + * - SI_SEG_GENERIC + * + *****************************************************************************/ + +/** @} (end addtogroup uart0_config_buffered Buffered API Optionsn) */ +/** @} (end addtogroup uart0_config Driver Configuration) */ + +// Option macro default values +#ifndef IS_DOXYGEN + #define IS_DOXYGEN 0 +#endif + +#ifndef EFM8PDL_UART0_USE_STDIO +#define EFM8PDL_UART0_USE_STDIO 0 +#endif +#ifndef EFM8PDL_UART0_USE_BUFFER + #if (!EFM8PDL_UART0_USE_STDIO) + #define EFM8PDL_UART0_USE_BUFFER 1 // buffer mode by default unless user has already selected one of the others + #else + #define EFM8PDL_UART0_USE_BUFFER 0 // buffer mode by default unless user has already selected one of the others + #endif +#endif +#ifndef EFM8PDL_UART0_TX_BUFTYPE +#define EFM8PDL_UART0_TX_BUFTYPE SI_SEG_XDATA +#endif +#ifndef EFM8PDL_UART0_RX_BUFTYPE +#define EFM8PDL_UART0_RX_BUFTYPE SI_SEG_XDATA +#endif + +// Runtime API +/**************************************************************************//** + * @addtogroup uart0_runtime UART0 Runtime API + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @addtogroup uart0_if Interrupt Flag Enums + * @{ + *****************************************************************************/ +#define UART0_TX_IF SCON0_TI__BMASK /**< UART0 TX Interrupt */ +#define UART0_RX_IF SCON0_RI__BMASK /**< UART0 RX Interrupt */ +/** @} (end addtogroup uart0_if Interrupt Flag Enums) */ + +/***************************************************************************//** + * @brief + * Return the value of the specified interrupt flag. + * + * @param flag: + * Flag to check. If OR'd together will return >0 if either flag is set. + * + * @return + * The state of the flags. This value is the OR of all flags which are set. + * + * ~~~~~.c + * if(UART0_getIntFlags() & UART_TX_IF) + * { + * //do something + * } + * + * uint8_t value = UART0_getIntFlags(); + * if(value) + * { + * //do some stuff that needs to be done for RX and TX + * if (value & UART_RX_IF) + * { + * //Do stuff that only needs to be done for RX + * } + * } + * ~~~~~ + * + * Valid flags can be found in the Interrupt Flag Enums group. + * + *****************************************************************************/ +uint8_t UART0_getIntFlags(); + +/***************************************************************************//** + * @brief + * Clear the specified interrupt flag. + * + * @param flag: + * Flag to clear. Multiple flags can be cleared by OR-ing the flags. + * + * Valid flags can be found in the Interrupt Flag Enums group. + * + ******************************************************************************/ +void UART0_clearIntFlag(uint8_t flag); + +/***************************************************************************//** + * @brief + * Sets the TX complete interrupt flag. + * + * It is common to operate the UART in polling mode where the procedure for + * transmitting a byte is to block till TX is complete and then clear the flag + * and write to SBUF. For these cases it is necessary to manually set the TX bit + * to initialize the UART. + * + ******************************************************************************/ +void UART0_initTxPolling(); + +/***************************************************************************//** + * @brief + * Write 8 bits to the UART to be transmitted. + * + * @param value: + * Data to be transmitted. + * + * If the UART already has data pending transmission it will be overwritten. + * + ******************************************************************************/ +void UART0_write(uint8_t value); + +/***************************************************************************//** + * @brief + * Read the last received byte from UART. + * + * @return + * The most recent byte read by the UART. + * + ******************************************************************************/ +uint8_t UART0_read(void); + +/***************************************************************************//** + * @brief + * Write the a byte to the UART with an extra bit. + * + * @param value: + * Data to transmit. + * + * Data[9] should contain the value of the extra bit. + * + ******************************************************************************/ +void UART0_writeWithExtraBit(uint16_t value); + +/***************************************************************************//** + * @brief + * Read a byte from the UART with an extra bit. + * + * @return + * The last byte received with data[9] set to the value of the extra bit. + * + ******************************************************************************/ +uint16_t UART0_readWithExtraBit(void); +/** @} (end addtogroup uart0_runtime UART0 Runtime API) */ + +// Initialization API +/***************************************************************************//** + * @addtogroup uart0_init UART0 Initialization API + * @{ + ******************************************************************************/ + +/// UART transfer width enums. +typedef enum +{ + UART0_WIDTH_8 = SCON0_SMODE__8_BIT, //!< UART in 8-bit mode. + UART0_WIDTH_9 = SCON0_SMODE__9_BIT, //!< UART in 9-bit mode. +} UART0_Width_t; + +/// UART Multiprocessor support enums. +typedef enum +{ + UART0_MULTIPROC_DISABLE = SCON0_MCE__MULTI_DISABLED, //!< UART Multiprocessor communication Disabled. + UART0_MULTIPROC_ENABLE = SCON0_MCE__MULTI_ENABLED, //!< UART Multiprocessor communication Enabled. +} UART0_Multiproc_t; + +/// UART RX support enums +typedef enum +{ + UART0_RX_ENABLE = SCON0_REN__RECEIVE_ENABLED, //!< UART Receive Enabled. + UART0_RX_DISABLE = SCON0_REN__RECEIVE_DISABLED, //!< UART Receive Disabled. +} UART0_RxEnable_t; + +/***************************************************************************//** + * @brief + * Initialize the UART + * + * @param rxen: + * Receive enable status. + * @param width: + * Data word width. + * @param mce: + * Multiprocessor mode status. + * + ******************************************************************************/ +void UART0_init(UART0_RxEnable_t rxen, UART0_Width_t width, UART0_Multiproc_t mce); + +/***************************************************************************//** + * @brief + * Restore the UART to it's uninitialized (reset) state. + * + ******************************************************************************/ +void UART0_reset(); + +/** @} (end uart0_init UART0 Initialization API) */ + +// Buffer API +/**************************************************************************//** + * @addtogroup uart0_buffer UART0 Buffer Access API + * @{ + *****************************************************************************/ +#if (EFM8PDL_UART0_USE_BUFFER == 1) || IS_DOXYGEN + +/***************************************************************************//** + * @brief + * Transmit a buffer of data via UART. + * + * @param[in] buffer: + * Pointer to buffer of data to be transmitted. + * @param length: + * Number of bytes in transfer to be transmitted. + * + * Buffer transfers support only 8-bit wide transfers. + * + ******************************************************************************/ +void UART0_writeBuffer(SI_VARIABLE_SEGMENT_POINTER(buffer, + uint8_t, + EFM8PDL_UART0_TX_BUFTYPE), + uint8_t length); + +/***************************************************************************//** + * @brief + * Receive a buffer of data via UART. + * + * @param[out] buffer: + * Pointer to buffer of data to be transmitted. + * @param length: + * Number of bytes in transfer to be transmitted. + * + * Buffered transfers support only 8-bit words. + * + ******************************************************************************/ +void UART0_readBuffer(SI_VARIABLE_SEGMENT_POINTER(buffer, + uint8_t, + EFM8PDL_UART0_RX_BUFTYPE), + uint8_t length); + +/***************************************************************************//** + * @brief + * Abort current buffer transmission. + * + * Data already moved into the UART will finish transmission. No more + * data will be pulled out of the TX buffer. + * + ******************************************************************************/ +void UART0_abortWrite(); + +/***************************************************************************//** + * @brief + * Abort current buffer reception. + * + * No more data will be written to the RX buffer. + * + ******************************************************************************/ +void UART0_abortRead(); + +/***************************************************************************//** + * @brief + * Return the number of bytes remaining in the TX buffer. + * + * @return + * number of btyes remaining in TX buffer. 0 if no transfer is in progress. + * + * @returns 0 if transfer is not in progress. + ******************************************************************************/ +uint8_t UART0_txBytesRemaining(); + +/***************************************************************************//** + * @brief + * Return the number of bytes remaining in the RX buffer. + * + * @return + * number of btyes remaining in RX buffer. 0 if no transfer is in progress. + * + ******************************************************************************/ +uint8_t UART0_rxBytesRemaining(); +/** @} (end uart0_buffer UART0 Buffer Access API) */ + +/**************************************************************************//** + * @def void UART0_ISR() + * @brief UART0 Interrupt handler. + * + * This callback is implemented inside the driver if EFM8PDL_UART0_USE_BUFFER is set + * otherwise the user must implement the ISR. + * + *****************************************************************************/ +#endif // EFM8PDL_UART0_USE_BUFFER + +// Callbacks +/**************************************************************************//** + * @addtogroup uart0_callbacks User Callbacks + * @{ + *****************************************************************************/ + +/**************************************************************************//** + *@addtogroup uart0_callbacks_buffer Buffer Access API + *@{ + * + * These callbacks will be called by the library when + * EFM8PDL_UART0_USE_BUFFER. If the Buffered Access API is disabled + * the callbacks do not need to be provided by the user. + * + *****************************************************************************/ +#if (EFM8PDL_UART0_USE_BUFFER == 1) || IS_DOXYGEN + +/***************************************************************************//** + * @brief + * Callback for reception of byte. + * + * This function is called when all expected bytes have been received. + * + * @warning + * This function is called from an ISR and should be as short as possible. + * + ******************************************************************************/ +void UART0_receiveCompleteCb(); + +/***************************************************************************//** + * @brief + * Callback for transmission of a byte. + * + * This function is called when all bytes in the buffer have been transferred. + * + * @warning + * This function is called from an ISR and should be as short as possible. + * + ******************************************************************************/ +void UART0_transmitCompleteCb(); + +#endif //EFM8PDL_UART0_USE_BUFFER +/** @} (end uart0_callbacks_buffer Buffer Access API) */ +/** @} (end uart0_callbacks User Callbacks) */ + + +// STIDO API +/**************************************************************************//** + * @addtogroup uart0_stdio UART0 STDIO API + * @{ + * + * This API is intended to be used in place of all other uart driver + * API's and will assume control of the uart. + * + * @warning + * This implementation is blocking and may hang the MCU under certain + * conditions. + * + ******************************************************************************/ +#if (EFM8PDL_UART0_USE_STDIO == 1) || IS_DOXYGEN + +/***************************************************************************//** + * @brief + * Initializes uart for STDIO operation. + * + * This function sets up the uart for use by printf/scanif. It must be called + * once durring device initialization **before** using STDIO. + * + ******************************************************************************/ +void UART0_initStdio(); + +#endif //EFM8PDL_UART0_USE_STDIO +/** @} (end uart0_stdio UART0 STDIO API) */ +/** @} (end uart_0 UART0 Driver) */ +#endif //__UART_0_H__ diff --git a/lib/efm8bb1/peripheralDrivers/src/pca_0.c b/lib/efm8bb1/peripheralDrivers/src/pca_0.c new file mode 100644 index 0000000..77e00eb --- /dev/null +++ b/lib/efm8bb1/peripheralDrivers/src/pca_0.c @@ -0,0 +1,269 @@ +/**************************************************************************//** + * Copyright (c) 2015 by Silicon Laboratories Inc. All rights reserved. + * + * http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt + *****************************************************************************/ + +#include "pca_0.h" + +#include "assert.h" + +uint8_t PCA0_getIntFlags() +{ + uint8_t val; + val = PCA0CN0 & (PCA0_OVERFLOW_IF + | PCA0_CHAN0_IF + | PCA0_CHAN1_IF + | PCA0_CHAN2_IF); + return val | (PCA0PWM & PCA0_IOVERFLOW_IF); +} + +void PCA0_clearIntFlag(uint8_t flag) +{ + PCA0CN0 &= ~(flag & ~PCA0_IOVERFLOW_IF); + PCA0PWM &= ~(flag & PCA0_IOVERFLOW_IF); +} + +void PCA0_enableInt(uint8_t flag, bool enable) +{ + uint8_t en = (uint8_t) enable; + + if(flag & PCA0_CHAN0_IF){ + PCA0CPM0 &= ~PCA0CPM0_ECCF__BMASK; + PCA0CPM0 |= en << PCA0CPM0_ECCF__SHIFT; + } + if(flag & PCA0_CHAN1_IF){ + PCA0CPM1 &= ~PCA0CPM1_ECCF__BMASK; + PCA0CPM1 |= en << PCA0CPM1_ECCF__SHIFT; + } + if(flag & PCA0_CHAN2_IF){ + PCA0CPM2 &= ~PCA0CPM2_ECCF__BMASK; + PCA0CPM2 |= en << PCA0CPM2_ECCF__SHIFT; + } + if(flag & PCA0_OVERFLOW_IF){ + PCA0MD &= ~PCA0MD_ECF__BMASK; + PCA0MD |= en << PCA0MD_ECF__SHIFT; + } + if(flag & PCA0_IOVERFLOW_IF){ + PCA0PWM &= ~PCA0PWM_ECOV__BMASK; + PCA0PWM |= en << PCA0PWM_ECOV__SHIFT; + } +} + +uint16_t PCA0_readChannel(PCA0_Channel_t channel) +{ + switch(channel) + { + case 0: + return PCA0CP0; + case 1: + return PCA0CP1; + case 2: + return PCA0CP2; + } + return 0x0; +} + +void PCA0_writeChannel(PCA0_Channel_t channel, uint16_t value) +{ + uint8_t lower = value >> 8; + switch(channel) + { + case 0: + PCA0CPL0 = value; + PCA0CPH0 = lower; + break; + case 1: + PCA0CPL1 = value; + PCA0CPH1 = lower; + break; + case 2: + PCA0CPL2 = value; + PCA0CPH2 = lower; + break; + } +} + +uint16_t PCA0_readCounter() +{ + //PCA0L must be read first for accurate results. If PCA0 + // is returned then PCA0H will be read first (compiler specific). + return PCA0L + (PCA0H << 8); +} + +void PCA0_writeCounter(uint16_t value) +{ + PCA0 = value; +} + +void PCA0_run() +{ + PCA0CN0_CR = 1; +} + +void PCA0_halt() +{ + PCA0CN0_CR = 0; +} + +void PCA0_init(PCA0_Timebase_t timebase, PCA0_IdleState_t idleState) +{ + PCA0MD &= ~(PCA0MD_CPS__FMASK | PCA0MD_CIDL__BMASK); + PCA0MD |= timebase + idleState; +} + +void PCA0_initChannel(PCA0_Channel_t channel, + PCA0_ChannelMode_t mode, + PCA0_ChannelOutPolatiry_t pol + ) +{ + #define MODE_MASK ~(PCA0CPM0_PWM16__BMASK \ + | PCA0CPM0_ECOM__BMASK \ + | PCA0CPM0_CAPP__BMASK \ + | PCA0CPM0_CAPN__BMASK \ + | PCA0CPM0_MAT__BMASK \ + | PCA0CPM0_TOG__BMASK \ + | PCA0CPM0_PWM__BMASK) + #define PWM_MASK ~(PCA0PWM_ARSEL__BMASK \ + | PCA0PWM_CLSEL__FMASK) + + #define NBIT_VALUE_MASK 0x07 + #define NBIT_MASK 0x70 + #define NBIT_PCM PCA0CPM0_PWM16__8_BIT \ + | PCA0CPM0_ECOM__ENABLED \ + | PCA0CPM0_CAPP__DISABLED \ + | PCA0CPM0_CAPN__DISABLED \ + | PCA0CPM0_MAT__ENABLED \ + | PCA0CPM0_TOG__DISABLED \ + | PCA0CPM0_PWM__ENABLED + # define IS_16BIT 0x80 + + uint8_t pwmValue = (uint8_t) mode; + + //Set channel polarity + PCA0POL &= ~(0x01 << channel); + PCA0POL |= (pol << channel); + + //UPDATE PWM if we are a PWM mode + if( (mode & NBIT_MASK) == NBIT_MASK) + { + PCA0PWM &= PWM_MASK; + + + if(mode & IS_16BIT) + { + pwmValue = NBIT_PCM | IS_16BIT; + } + else + { + PCA0PWM |= (mode & NBIT_VALUE_MASK) | PCA0PWM_ARSEL__AUTORELOAD; + pwmValue = NBIT_PCM; + } + + //Update center/edge selection + PCA0CENT &= ~(0x01 << channel); + PCA0CENT |= ((mode & 0x08) >> 3) << channel; + } + + //Set channel mode + switch (channel) + { + case 0: + PCA0CPM0 &= MODE_MASK; + PCA0CPM0 |= pwmValue; + break; + + case 1: + PCA0CPM1 &= MODE_MASK; + PCA0CPM1 |= pwmValue; + break; + + case 2: + PCA0CPM2 &= MODE_MASK; + PCA0CPM2 |= pwmValue; + break; + } +} + +void PCA0_reset() +{ + //Reset channels + uint8_t i; + for (i=0; i<=2; i++) + { + PCA0_resetChannel(i); + } + + //Reset PCA regs + PCA0MD = 0x0; + PCA0CN0 = 0x0; + PCA0 = 0x0; + PCA0PWM = 0x0; +} + +void PCA0_resetChannel(PCA0_Channel_t channel) +{ + //Clear polarity and center align + PCA0POL &= ~(0x01 << channel); + PCA0CENT &= ~(0x01 << channel); + + + switch (channel) + { + case 0: + PCA0CP0 = 0x00; + PCA0CPM0 = 0x0; + return; + case 1: + PCA0CP1 = 0x00; + PCA0CPM1 = 0x0; + return; + case 2: + PCA0CP2 = 0x00; + PCA0CPM2 = 0x0; + return; + } +} + +#if EFM8PDL_PCA0_USE_ISR == 1 + +SI_INTERRUPT(PCA0_ISR, PCA0_IRQn) +{ + //Save and clear flags + uint8_t flags = PCA0CN0 & (PCA0CN0_CF__BMASK + | PCA0CN0_CCF0__BMASK + | PCA0CN0_CCF1__BMASK + | PCA0CN0_CCF2__BMASK); + PCA0CN0 &= ~flags; + + if( (PCA0PWM & PCA0PWM_COVF__BMASK) + && (PCA0PWM & PCA0PWM_ECOV__BMASK)) + { + PCA0_intermediateOverflowCb(); + } + PCA0PWM &= ~PCA0PWM_COVF__BMASK; + + if((flags & PCA0CN0_CF__BMASK) + && (PCA0MD & PCA0MD_ECF__BMASK)) + { + PCA0_overflowCb(); + } + if((flags & PCA0CN0_CCF0__BMASK) + && (PCA0CPM0 & PCA0CPM0_ECCF__BMASK)) + { + PCA0_channel0EventCb(); + } + if((flags & PCA0CN0_CCF1__BMASK) + && (PCA0CPM1 & PCA0CPM1_ECCF__BMASK)) + { + PCA0_channel1EventCb(); + } + if((flags & PCA0CN0_CCF2__BMASK) + && (PCA0CPM2 & PCA0CPM2_ECCF__BMASK)) + { + PCA0_channel2EventCb(); + } +} + + +#endif //EFM8PDL_PCA0_USE_ISR diff --git a/lib/efm8bb1/peripheralDrivers/src/uart_0.c b/lib/efm8bb1/peripheralDrivers/src/uart_0.c new file mode 100644 index 0000000..274e379 --- /dev/null +++ b/lib/efm8bb1/peripheralDrivers/src/uart_0.c @@ -0,0 +1,193 @@ +/**************************************************************************//** + * Copyright (c) 2015 by Silicon Laboratories Inc. All rights reserved. + * + * http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt + *****************************************************************************/ + +#include "uart_0.h" + +uint8_t UART0_getIntFlags() +{ + return SCON0 & (UART0_TX_IF | UART0_RX_IF); +} + +void UART0_clearIntFlag(uint8_t flag) +{ + SCON0 &= ~(flag); +} + +void UART0_initTxPolling() +{ + SCON0_TI = 1; +} + +void UART0_write(uint8_t value) +{ + SBUF0 = value; +} + +uint8_t UART0_read(void) +{ + return SBUF0; +} +void UART0_writeWithExtraBit(uint16_t value) +{ + SCON0_TB8 = value >> 8; + SBUF0 = value; +} + +uint16_t UART0_readWithExtraBit(void) +{ + return (SBUF0 | ((SCON0 & SCON0_RB8__BMASK) << 6) ); +} + +void UART0_init(UART0_RxEnable_t rxen, UART0_Width_t width, UART0_Multiproc_t mce) +{ + SCON0 &= ~(SCON0_SMODE__BMASK + | SCON0_MCE__BMASK + | SCON0_REN__BMASK); + SCON0 = mce | rxen | width; +} + +void UART0_reset() +{ + SCON0 = SCON0_SMODE__8_BIT + | SCON0_MCE__MULTI_DISABLED + | SCON0_REN__RECEIVE_DISABLED + | SCON0_TB8__CLEARED_TO_0 + | SCON0_RB8__CLEARED_TO_0 + | SCON0_TI__NOT_SET + | SCON0_RI__NOT_SET; +} + +//========================================================= +// Interrupt API +//========================================================= +#if EFM8PDL_UART0_USE_BUFFER == 1 + +/** + * Internal variable fort tracking buffer transfers. transferLenth[UART0_TX_TRANSFER] = bytes remaining in transfer. + */ +SI_SEGMENT_VARIABLE(txRemaining, static uint8_t, SI_SEG_XDATA)=0; +SI_SEGMENT_VARIABLE(rxRemaining, static uint8_t, SI_SEG_XDATA)=0; +SI_SEGMENT_VARIABLE_SEGMENT_POINTER(txBuffer, static uint8_t, EFM8PDL_UART0_TX_BUFTYPE, SI_SEG_XDATA); +SI_SEGMENT_VARIABLE_SEGMENT_POINTER(rxBuffer, static uint8_t, EFM8PDL_UART0_RX_BUFTYPE, SI_SEG_XDATA); + + +SI_INTERRUPT(UART0_ISR, UART0_IRQn) +{ + //Buffer and clear flags immediately so we don't miss an interrupt while processing + uint8_t flags = SCON0 & (UART0_RX_IF | UART0_TX_IF); + SCON0 &= ~flags; + + if (rxRemaining && (flags & SCON0_RI__SET)) + { + *rxBuffer = SBUF0; + ++rxBuffer; + --rxRemaining; + if (!rxRemaining) + { + UART0_receiveCompleteCb(); + } + } + + if ((flags & SCON0_TI__SET)) + { + if (txRemaining){ + SBUF0 = *txBuffer; + ++txBuffer; + --txRemaining; + } + else + { + UART0_transmitCompleteCb(); + } + } +} + +void UART0_writeBuffer(SI_VARIABLE_SEGMENT_POINTER(buffer, + uint8_t, + EFM8PDL_UART0_TX_BUFTYPE), + uint8_t length) +{ + //Init internal data + txBuffer = buffer+1; + txRemaining = length-1; + + //Send initial byte + SBUF0 = *buffer; +} + +void UART0_readBuffer(SI_VARIABLE_SEGMENT_POINTER(buffer, + uint8_t, + EFM8PDL_UART0_RX_BUFTYPE), + uint8_t length) +{ + //Init internal data + rxBuffer = buffer; + rxRemaining = length; +} + +void UART0_abortWrite() +{ + txRemaining = 0; +} + +void UART0_abortRead() +{ + rxRemaining = 0; +} + +uint8_t UART0_txBytesRemaining() +{ + return txRemaining; +} + +uint8_t UART0_rxBytesRemaining() +{ + return rxRemaining; +} + +#endif //EFM8PDL_UART0_USE_BUFFER + +#if EFM8PDL_UART0_USE_STDIO == 1 + +#if defined __C51__ + +char putchar(char c){ + while(!SCON0_TI); + SBUF0 = c; + SCON0_TI = 0; + return c; +} + +char _getkey(){ + while(!SCON0_RI); + SCON0_RI = 0; + return SBUF0; +} + +#elif defined __ICC8051__ + +int putchar(int c){ + while(!SCON0_TI); + SBUF0 = c; + SCON0_TI = 0; + return c; +} + +int getchar(void){ + while(!SCON0_RI); + SCON0_RI = 0; + return SBUF0; +} + +#endif + +void UART0_initStdio() +{ + SCON0 |= SCON0_REN__RECEIVE_ENABLED | SCON0_TI__SET; +} +#endif //EFM8PDL_UART0_USE_STDIO + + diff --git a/src/InitDevice.c b/src/InitDevice.c new file mode 100644 index 0000000..e93dd40 --- /dev/null +++ b/src/InitDevice.c @@ -0,0 +1,542 @@ +//========================================================= +// src/InitDevice.c: generated by Hardware Configurator +// +// This file will be regenerated when saving a document. +// leave the sections inside the "$[...]" comment tags alone +// or they will be overwritten! +//========================================================= + +// USER INCLUDES +#include +#include "InitDevice.h" + +// USER PROTOTYPES +// USER FUNCTIONS + +// $[Library Includes] +// [Library Includes]$ + +//============================================================================== +// enter_DefaultMode_from_RESET +//============================================================================== +extern void enter_DefaultMode_from_RESET(void) { + // $[Config Calls] + WDT_0_enter_DefaultMode_from_RESET(); + PORTS_0_enter_DefaultMode_from_RESET(); + PORTS_1_enter_DefaultMode_from_RESET(); + PBCFG_0_enter_DefaultMode_from_RESET(); + CLOCK_0_enter_DefaultMode_from_RESET(); + TIMER01_0_enter_DefaultMode_from_RESET(); + TIMER16_3_enter_DefaultMode_from_RESET(); + TIMER_SETUP_0_enter_DefaultMode_from_RESET(); + PCA_0_enter_DefaultMode_from_RESET(); + PCACH_0_enter_DefaultMode_from_RESET(); + PCACH_1_enter_DefaultMode_from_RESET(); + UART_0_enter_DefaultMode_from_RESET(); + INTERRUPT_0_enter_DefaultMode_from_RESET(); + // [Config Calls]$ + +} + +//================================================================================ +// WDT_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void WDT_0_enter_DefaultMode_from_RESET(void) { + // $[WDTCN - Watchdog Timer Control] + //Disable Watchdog with key sequence + WDTCN = 0xDE; //First key + WDTCN = 0xAD; //Second key + // [WDTCN - Watchdog Timer Control]$ + +} + +//================================================================================ +// PORTS_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void PORTS_0_enter_DefaultMode_from_RESET(void) { + // $[P0 - Port 0 Pin Latch] + // [P0 - Port 0 Pin Latch]$ + + // $[P0MDOUT - Port 0 Output Mode] + /*********************************************************************** + - P0.0 output is push-pull + - P0.1 output is open-drain + - P0.2 output is open-drain + - P0.3 output is open-drain + - P0.4 output is push-pull + - P0.5 output is open-drain + - P0.6 output is open-drain + - P0.7 output is open-drain + ***********************************************************************/ + P0MDOUT = P0MDOUT_B0__PUSH_PULL | P0MDOUT_B1__OPEN_DRAIN + | P0MDOUT_B2__OPEN_DRAIN | P0MDOUT_B3__OPEN_DRAIN + | P0MDOUT_B4__PUSH_PULL | P0MDOUT_B5__OPEN_DRAIN + | P0MDOUT_B6__OPEN_DRAIN | P0MDOUT_B7__OPEN_DRAIN; + // [P0MDOUT - Port 0 Output Mode]$ + + // $[P0MDIN - Port 0 Input Mode] + // [P0MDIN - Port 0 Input Mode]$ + + // $[P0SKIP - Port 0 Skip] + /*********************************************************************** + - P0.0 pin is not skipped by the crossbar + - P0.1 pin is skipped by the crossbar + - P0.2 pin is skipped by the crossbar + - P0.3 pin is skipped by the crossbar + - P0.4 pin is not skipped by the crossbar + - P0.5 pin is not skipped by the crossbar + - P0.6 pin is skipped by the crossbar + - P0.7 pin is skipped by the crossbar + ***********************************************************************/ + P0SKIP = P0SKIP_B0__NOT_SKIPPED | P0SKIP_B1__SKIPPED | P0SKIP_B2__SKIPPED + | P0SKIP_B3__SKIPPED | P0SKIP_B4__NOT_SKIPPED + | P0SKIP_B5__NOT_SKIPPED | P0SKIP_B6__SKIPPED | P0SKIP_B7__SKIPPED; + // [P0SKIP - Port 0 Skip]$ + + // $[P0MASK - Port 0 Mask] + // [P0MASK - Port 0 Mask]$ + + // $[P0MAT - Port 0 Match] + // [P0MAT - Port 0 Match]$ + +} + +//================================================================================ +// PORTS_1_enter_DefaultMode_from_RESET +//================================================================================ +extern void PORTS_1_enter_DefaultMode_from_RESET(void) { + // $[P1 - Port 1 Pin Latch] + // [P1 - Port 1 Pin Latch]$ + + // $[P1MDOUT - Port 1 Output Mode] + /*********************************************************************** + - P1.0 output is push-pull + - P1.1 output is open-drain + - P1.2 output is open-drain + - P1.3 output is open-drain + - P1.4 output is open-drain + - P1.5 output is open-drain + - P1.6 output is push-pull + ***********************************************************************/ + P1MDOUT = P1MDOUT_B0__PUSH_PULL | P1MDOUT_B1__OPEN_DRAIN + | P1MDOUT_B2__OPEN_DRAIN | P1MDOUT_B3__OPEN_DRAIN + | P1MDOUT_B4__OPEN_DRAIN | P1MDOUT_B5__OPEN_DRAIN + | P1MDOUT_B6__PUSH_PULL; + // [P1MDOUT - Port 1 Output Mode]$ + + // $[P1MDIN - Port 1 Input Mode] + // [P1MDIN - Port 1 Input Mode]$ + + // $[P1SKIP - Port 1 Skip] + /*********************************************************************** + - P1.0 pin is skipped by the crossbar + - P1.1 pin is skipped by the crossbar + - P1.2 pin is skipped by the crossbar + - P1.3 pin is not skipped by the crossbar + - P1.4 pin is skipped by the crossbar + - P1.5 pin is skipped by the crossbar + - P1.6 pin is skipped by the crossbar + ***********************************************************************/ + P1SKIP = P1SKIP_B0__SKIPPED | P1SKIP_B1__SKIPPED | P1SKIP_B2__SKIPPED + | P1SKIP_B3__NOT_SKIPPED | P1SKIP_B4__SKIPPED | P1SKIP_B5__SKIPPED + | P1SKIP_B6__SKIPPED; + // [P1SKIP - Port 1 Skip]$ + + // $[P1MASK - Port 1 Mask] + // [P1MASK - Port 1 Mask]$ + + // $[P1MAT - Port 1 Match] + // [P1MAT - Port 1 Match]$ + +} + +//================================================================================ +// PBCFG_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void PBCFG_0_enter_DefaultMode_from_RESET(void) { + // $[XBR2 - Port I/O Crossbar 2] + /*********************************************************************** + - Weak Pullups enabled + - Crossbar enabled + ***********************************************************************/ + XBR2 = XBR2_WEAKPUD__PULL_UPS_ENABLED | XBR2_XBARE__ENABLED; + // [XBR2 - Port I/O Crossbar 2]$ + + // $[PRTDRV - Port Drive Strength] + // [PRTDRV - Port Drive Strength]$ + + // $[XBR0 - Port I/O Crossbar 0] + /*********************************************************************** + - UART TX, RX routed to Port pins P0.4 and P0.5 + - SPI I/O unavailable at Port pins + - SMBus 0 I/O unavailable at Port pins + - CP0 unavailable at Port pin + - Asynchronous CP0 unavailable at Port pin + - CP1 unavailable at Port pin + - Asynchronous CP1 unavailable at Port pin + - SYSCLK unavailable at Port pin + ***********************************************************************/ + XBR0 = XBR0_URT0E__ENABLED | XBR0_SPI0E__DISABLED | XBR0_SMB0E__DISABLED + | XBR0_CP0E__DISABLED | XBR0_CP0AE__DISABLED | XBR0_CP1E__DISABLED + | XBR0_CP1AE__DISABLED | XBR0_SYSCKE__DISABLED; + // [XBR0 - Port I/O Crossbar 0]$ + + // $[XBR1 - Port I/O Crossbar 1] + /*********************************************************************** + - CEX0, CEX1 routed to Port pins + - ECI unavailable at Port pin + - T0 unavailable at Port pin + - T1 unavailable at Port pin + - T2 unavailable at Port pin + ***********************************************************************/ + XBR1 = XBR1_PCA0ME__CEX0_CEX1 | XBR1_ECIE__DISABLED | XBR1_T0E__DISABLED + | XBR1_T1E__DISABLED | XBR1_T2E__DISABLED; + // [XBR1 - Port I/O Crossbar 1]$ + +} + +//================================================================================ +// CLOCK_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void CLOCK_0_enter_DefaultMode_from_RESET(void) { + // $[CLKSEL - Clock Select] + /*********************************************************************** + - Clock derived from the Internal High-Frequency Oscillator + - SYSCLK is equal to selected clock source divided by 1 + ***********************************************************************/ + CLKSEL = CLKSEL_CLKSL__HFOSC | CLKSEL_CLKDIV__SYSCLK_DIV_1; + // [CLKSEL - Clock Select]$ + +} + +//================================================================================ +// TIMER01_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void TIMER01_0_enter_DefaultMode_from_RESET(void) { + // $[Timer Initialization] + //Save Timer Configuration + uint8_t TCON_save; + TCON_save = TCON; + //Stop Timers + TCON &= ~TCON_TR0__BMASK & ~TCON_TR1__BMASK; + + // [Timer Initialization]$ + + // $[TH0 - Timer 0 High Byte] + /*********************************************************************** + - Timer 0 High Byte = 0x0B + ***********************************************************************/ + TH0 = (0x0B << TH0_TH0__SHIFT); + // [TH0 - Timer 0 High Byte]$ + + // $[TL0 - Timer 0 Low Byte] + // [TL0 - Timer 0 Low Byte]$ + + // $[TH1 - Timer 1 High Byte] + /*********************************************************************** + - Timer 1 High Byte = 0x96 + ***********************************************************************/ + TH1 = (0x96 << TH1_TH1__SHIFT); + // [TH1 - Timer 1 High Byte]$ + + // $[TL1 - Timer 1 Low Byte] + // [TL1 - Timer 1 Low Byte]$ + + // $[Timer Restoration] + //Restore Timer Configuration + TCON |= (TCON_save & TCON_TR0__BMASK) | (TCON_save & TCON_TR1__BMASK); + + // [Timer Restoration]$ + +} + +//================================================================================ +// TIMER16_3_enter_DefaultMode_from_RESET +//================================================================================ +extern void TIMER16_3_enter_DefaultMode_from_RESET(void) { + // $[Timer Initialization] + // Save Timer Configuration + uint8_t TMR3CN0_TR3_save; + TMR3CN0_TR3_save = TMR3CN0 & TMR3CN0_TR3__BMASK; + // Stop Timer + TMR3CN0 &= ~(TMR3CN0_TR3__BMASK); + // [Timer Initialization]$ + + // $[TMR3CN0 - Timer 3 Control] + // [TMR3CN0 - Timer 3 Control]$ + + // $[TMR3H - Timer 3 High Byte] + /*********************************************************************** + - Timer 3 High Byte = 0xFF + ***********************************************************************/ + TMR3H = (0xFF << TMR3H_TMR3H__SHIFT); + // [TMR3H - Timer 3 High Byte]$ + + // $[TMR3L - Timer 3 Low Byte] + /*********************************************************************** + - Timer 3 Low Byte = 0xFF + ***********************************************************************/ + TMR3L = (0xFF << TMR3L_TMR3L__SHIFT); + // [TMR3L - Timer 3 Low Byte]$ + + // $[TMR3RLH - Timer 3 Reload High Byte] + /*********************************************************************** + - Timer 3 Reload High Byte = 0xFF + ***********************************************************************/ + TMR3RLH = (0xFF << TMR3RLH_TMR3RLH__SHIFT); + // [TMR3RLH - Timer 3 Reload High Byte]$ + + // $[TMR3RLL - Timer 3 Reload Low Byte] + /*********************************************************************** + - Timer 3 Reload Low Byte = 0x86 + ***********************************************************************/ + TMR3RLL = (0x86 << TMR3RLL_TMR3RLL__SHIFT); + // [TMR3RLL - Timer 3 Reload Low Byte]$ + + // $[TMR3CN0] + // [TMR3CN0]$ + + // $[Timer Restoration] + // Restore Timer Configuration + TMR3CN0 |= TMR3CN0_TR3_save; + // [Timer Restoration]$ + +} + +//================================================================================ +// TIMER_SETUP_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void TIMER_SETUP_0_enter_DefaultMode_from_RESET(void) { + // $[CKCON0 - Clock Control 0] + /*********************************************************************** + - System clock divided by 12 + - Counter/Timer 0 uses the system clock + - Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0 + - Timer 2 low byte uses the clock defined by T2XCLK in TMR2CN0 + - Timer 3 high byte uses the clock defined by T3XCLK in TMR3CN0 + - Timer 3 low byte uses the system clock + - Timer 1 uses the clock defined by the prescale field, SCA + ***********************************************************************/ + CKCON0 = CKCON0_SCA__SYSCLK_DIV_12 | CKCON0_T0M__SYSCLK + | CKCON0_T2MH__EXTERNAL_CLOCK | CKCON0_T2ML__EXTERNAL_CLOCK + | CKCON0_T3MH__EXTERNAL_CLOCK | CKCON0_T3ML__SYSCLK + | CKCON0_T1M__PRESCALE; + // [CKCON0 - Clock Control 0]$ + + // $[TMOD - Timer 0/1 Mode] + /*********************************************************************** + - Mode 2, 8-bit Counter/Timer with Auto-Reload + - Mode 2, 8-bit Counter/Timer with Auto-Reload + - Timer Mode + - Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level + - Timer Mode + - Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level + ***********************************************************************/ + TMOD = TMOD_T0M__MODE2 | TMOD_T1M__MODE2 | TMOD_CT0__TIMER + | TMOD_GATE0__DISABLED | TMOD_CT1__TIMER | TMOD_GATE1__DISABLED; + // [TMOD - Timer 0/1 Mode]$ + + // $[TCON - Timer 0/1 Control] + /*********************************************************************** + - Start Timer 0 running + - Start Timer 1 running + ***********************************************************************/ + TCON |= TCON_TR0__RUN | TCON_TR1__RUN; + // [TCON - Timer 0/1 Control]$ + +} + +//================================================================================ +// PCA_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void PCA_0_enter_DefaultMode_from_RESET(void) { + // $[PCA Off] + PCA0CN0_CR = PCA0CN0_CR__STOP; + // [PCA Off]$ + + // $[PCA0MD - PCA Mode] + /*********************************************************************** + - PCA continues to function normally while the system controller is in + Idle Mode + - Enable a PCA Counter/Timer Overflow interrupt request when CF is set + - Timer 0 overflow + ***********************************************************************/ + PCA0MD = PCA0MD_CIDL__NORMAL | PCA0MD_ECF__OVF_INT_ENABLED + | PCA0MD_CPS__T0_OVERFLOW; + // [PCA0MD - PCA Mode]$ + + // $[PCA0CENT - PCA Center Alignment Enable] + // [PCA0CENT - PCA Center Alignment Enable]$ + + // $[PCA0CLR - PCA Comparator Clear Control] + // [PCA0CLR - PCA Comparator Clear Control]$ + + // $[PCA0L - PCA Counter/Timer Low Byte] + /*********************************************************************** + - PCA Counter/Timer Low Byte = 0xFF + ***********************************************************************/ + PCA0L = (0xFF << PCA0L_PCA0L__SHIFT); + // [PCA0L - PCA Counter/Timer Low Byte]$ + + // $[PCA0H - PCA Counter/Timer High Byte] + // [PCA0H - PCA Counter/Timer High Byte]$ + + // $[PCA0POL - PCA Output Polarity] + /*********************************************************************** + - Invert polarity + - Use default polarity + - Use default polarity + ***********************************************************************/ + PCA0POL = PCA0POL_CEX0POL__INVERT | PCA0POL_CEX1POL__DEFAULT + | PCA0POL_CEX2POL__DEFAULT; + // [PCA0POL - PCA Output Polarity]$ + + // $[PCA0PWM - PCA PWM Configuration] + /*********************************************************************** + - A PCA interrupt will be generated when COVF is set + ***********************************************************************/ + PCA0PWM |= PCA0PWM_ECOV__COVF_MASK_ENABLED; + // [PCA0PWM - PCA PWM Configuration]$ + + // $[PCA On] + // [PCA On]$ + +} + +//================================================================================ +// PCACH_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void PCACH_0_enter_DefaultMode_from_RESET(void) { + // $[PCA0 Settings Save] + // Select Capture/Compare register) + PCA0PWM &= ~PCA0PWM_ARSEL__BMASK; + // [PCA0 Settings Save]$ + + // $[PCA0CPM0 - PCA Channel 0 Capture/Compare Mode] + /*********************************************************************** + - Disable negative edge capture + - Disable CCF0 interrupts + - Enable match function + - 8 to 11-bit PWM selected + - Disable positive edge capture + - Enable comparator function + - Enable PWM function + - Disable toggle function + ***********************************************************************/ + PCA0CPM0 = PCA0CPM0_CAPN__DISABLED | PCA0CPM0_ECCF__DISABLED + | PCA0CPM0_MAT__ENABLED | PCA0CPM0_PWM16__8_BIT + | PCA0CPM0_CAPP__DISABLED | PCA0CPM0_ECOM__ENABLED + | PCA0CPM0_PWM__ENABLED | PCA0CPM0_TOG__DISABLED; + // [PCA0CPM0 - PCA Channel 0 Capture/Compare Mode]$ + + // $[PCA0CPL0 - PCA Channel 0 Capture Module Low Byte] + // [PCA0CPL0 - PCA Channel 0 Capture Module Low Byte]$ + + // $[PCA0CPH0 - PCA Channel 0 Capture Module High Byte] + // [PCA0CPH0 - PCA Channel 0 Capture Module High Byte]$ + + // $[Auto-reload] + // [Auto-reload]$ + + // $[PCA0 Settings Restore] + // [PCA0 Settings Restore]$ + +} + +//================================================================================ +// PCACH_1_enter_DefaultMode_from_RESET +//================================================================================ +extern void PCACH_1_enter_DefaultMode_from_RESET(void) { + // $[PCA0 Settings Save] + // Select Capture/Compare register) + PCA0PWM &= ~PCA0PWM_ARSEL__BMASK; + // [PCA0 Settings Save]$ + + // $[PCA0CPM1 - PCA Channel 1 Capture/Compare Mode] + /*********************************************************************** + - Enable negative edge capture + - Disable CCF1 interrupts + - Disable match function + - 8 to 11-bit PWM selected + - Enable positive edge capture + - Disable comparator function + - Disable PWM function + - Disable toggle function + ***********************************************************************/ + PCA0CPM1 = PCA0CPM1_CAPN__ENABLED | PCA0CPM1_ECCF__DISABLED + | PCA0CPM1_MAT__DISABLED | PCA0CPM1_PWM16__8_BIT + | PCA0CPM1_CAPP__ENABLED | PCA0CPM1_ECOM__DISABLED + | PCA0CPM1_PWM__DISABLED | PCA0CPM1_TOG__DISABLED; + // [PCA0CPM1 - PCA Channel 1 Capture/Compare Mode]$ + + // $[PCA0CPL1 - PCA Channel 1 Capture Module Low Byte] + // [PCA0CPL1 - PCA Channel 1 Capture Module Low Byte]$ + + // $[PCA0CPH1 - PCA Channel 1 Capture Module High Byte] + // [PCA0CPH1 - PCA Channel 1 Capture Module High Byte]$ + + // $[Auto-reload] + // [Auto-reload]$ + + // $[PCA0 Settings Restore] + // [PCA0 Settings Restore]$ + +} + +//================================================================================ +// UART_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void UART_0_enter_DefaultMode_from_RESET(void) { + // $[SCON0 - UART0 Serial Port Control] + /*********************************************************************** + - UART0 reception enabled + ***********************************************************************/ + SCON0 |= SCON0_REN__RECEIVE_ENABLED; + // [SCON0 - UART0 Serial Port Control]$ + +} + +//================================================================================ +// INTERRUPT_0_enter_DefaultMode_from_RESET +//================================================================================ +extern void INTERRUPT_0_enter_DefaultMode_from_RESET(void) { + // $[EIE1 - Extended Interrupt Enable 1] + /*********************************************************************** + - Disable ADC0 Conversion Complete interrupt + - Disable ADC0 Window Comparison interrupt + - Disable CP0 interrupts + - Disable CP1 interrupts + - Disable all Port Match interrupts + - Enable interrupt requests generated by PCA0 + - Disable all SMB0 interrupts + - Enable interrupt requests generated by the TF3L or TF3H flags + ***********************************************************************/ + EIE1 = EIE1_EADC0__DISABLED | EIE1_EWADC0__DISABLED | EIE1_ECP0__DISABLED + | EIE1_ECP1__DISABLED | EIE1_EMAT__DISABLED | EIE1_EPCA0__ENABLED + | EIE1_ESMB0__DISABLED | EIE1_ET3__ENABLED; + // [EIE1 - Extended Interrupt Enable 1]$ + + // $[EIP1 - Extended Interrupt Priority 1] + // [EIP1 - Extended Interrupt Priority 1]$ + + // $[IE - Interrupt Enable] + /*********************************************************************** + - Enable each interrupt according to its individual mask setting + - Disable external interrupt 0 + - Disable external interrupt 1 + - Disable all SPI0 interrupts + - Disable all Timer 0 interrupt + - Disable all Timer 1 interrupt + - Disable Timer 2 interrupt + - Enable UART0 interrupt + ***********************************************************************/ + IE = IE_EA__ENABLED | IE_EX0__DISABLED | IE_EX1__DISABLED + | IE_ESPI0__DISABLED | IE_ET0__DISABLED | IE_ET1__DISABLED + | IE_ET2__DISABLED | IE_ES0__ENABLED; + // [IE - Interrupt Enable]$ + + // $[IP - Interrupt Priority] + // [IP - Interrupt Priority]$ + +} + diff --git a/src/RF_Bridge_main.c b/src/RF_Bridge_main.c new file mode 100644 index 0000000..b7e4d05 --- /dev/null +++ b/src/RF_Bridge_main.c @@ -0,0 +1,211 @@ +//========================================================= +// src/RF_Bridge_2_main.c: generated by Hardware Configurator +// +// This file will be updated when saving a document. +// leave the sections inside the "$[...]" comment tags alone +// or they will be overwritten!! +//========================================================= + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include // SFR declarations +#include "Globals.h" +#include "InitDevice.h" +#include "uart_0.h" +#include "pca_0.h" +#include "uart.h" +#include "RF_Handling.h" +// $[Generated Includes] +// [Generated Includes]$ + +uart_state_t uart_state = IDLE; +uart_command_t uart_command = NONE; +bool Sniffing = false; + +//----------------------------------------------------------------------------- +// SiLabs_Startup() Routine +// ---------------------------------------------------------------------------- +// This function is called immediately after reset, before the initialization +// code is run in SILABS_STARTUP.A51 (which runs before main() ). This is a +// useful place to disable the watchdog timer, which is enable by default +// and may trigger before main() in some instances. +//----------------------------------------------------------------------------- +void SiLabs_Startup (void) +{ + +} + +//----------------------------------------------------------------------------- +// main() Routine +// ---------------------------------------------------------------------------- +int main (void) +{ + // Call hardware initialization routine + enter_DefaultMode_from_RESET(); + + // enter default state + LED = LED_OFF; + BUZZER = BUZZER_OFF; + + T_DATA = 1; + + // enable UART + UART0_init(UART0_RX_ENABLE, UART0_WIDTH_8, UART0_MULTIPROC_DISABLE); + + // start sniffing if enabled by default + if (Sniffing) + PCA0_DoSniffing(); + else + PCA0_StopSniffing(); + + // enable global interrupts + IE_EA = 1; + + while (1) + { + /*------------------------------------------ + * check if something got received by UART + ------------------------------------------*/ + unsigned int rxdata; + uint8_t len; + uint8_t position; + + rxdata = uart_getc(); + + if (rxdata != UART_NO_DATA) + { + // state machine for UART + switch(uart_state) + { + // check if UART_SYNC_INIT got received + case IDLE: + if ((rxdata & 0xFF) == UART_SYNC_INIT) + uart_state = SYNC_INIT; + break; + + // sync byte got received, read command + case SYNC_INIT: + uart_command = rxdata & 0xFF; + uart_state = SYNC_FINISH; + + // check if some data needs to be received + switch(uart_command) + { + case LEARNING: + Timer_3_Timeout = 50000; + BUZZER = BUZZER_ON; + // start 5µs timer + TMR3CN0 |= TMR3CN0_TR3__RUN; + // wait until timer has finished + while((TMR3CN0 & TMR3CN0_TR3__BMASK) == TMR3CN0_TR3__RUN); + BUZZER = BUZZER_OFF; + break; + case SNIFFING_ON: + PCA0_DoSniffing(); + break; + case SNIFFING_OFF: + PCA0_StopSniffing(); + sniffing_is_on = false; + break; + case TRANSMIT_DATA: + uart_state = RECEIVE_LEN; + break; + + + // unknown command + default: + uart_command = NONE; + uart_state = IDLE; + break; + } + break; + + // Receiving UART data len + case RECEIVE_LEN: + position = 0; + len = rxdata & 0xFF; + if (len > 0) + uart_state = RECEIVING; + else + uart_state = SYNC_FINISH; + break; + + // Receiving UART data + case RECEIVING: + RF_DATA[position] = rxdata & 0xFF; + position++; + + if (position == len) + uart_state = SYNC_FINISH; + break; + + // wait and check for UART_SYNC_END + case SYNC_FINISH: + if ((rxdata & 0xFF) == UART_SYNC_END) + { + uart_state = IDLE; + // send acknowledge + uart_put_command(COMMAND_AK); + } + break; + } + } + + /*------------------------------------------ + * check command byte + ------------------------------------------*/ + switch(uart_command) + { + case SNIFFING_ON: + // check if a RF signal got decoded + if ((RF_DATA_STATUS & RF_DATA_RECEIVED_MASK) != 0) + { + uint8_t used_protocol = RF_DATA_STATUS & 0x7F; + uart_put_RF_Data(SNIFFING_ON, used_protocol); + + // clear RF status + RF_DATA_STATUS = 0; + } + break; + + // transmit data on RF + // byte 0: Protocol identifier + // byte 1..N: data to be transmitted + case TRANSMIT_DATA: + // only do the job if all data got received by UART + if (uart_state != IDLE) + break; + + if (sniffing_is_on) + PCA0_StopSniffing(); + + protocol_index = PCA0_DoTransmit(RF_DATA[0]); + + if (protocol_index != 0xFF) + { + actual_bit_of_byte = 0x08; + actual_bit_of_byte--; + actual_byte = 1; + actual_bit = 1; + + if(((RF_DATA[actual_byte] >> actual_bit_of_byte) & 0x01) == 0x01) + { + // bit 1 + PCA0_writeChannel(PCA0_CHAN0, DUTY_CYCLE_HIGH << 8); + } + else + { + // bit 0 + PCA0_writeChannel(PCA0_CHAN0, DUTY_CYLCE_LOW << 8); + } + + SendRF_SYNC(protocol_index); + PCA0CN0_CR = PCA0CN0_CR__RUN; + } + + uart_command = NONE; + break; + } + } +} diff --git a/src/RF_Handling.c b/src/RF_Handling.c new file mode 100644 index 0000000..c140fc5 --- /dev/null +++ b/src/RF_Handling.c @@ -0,0 +1,364 @@ +/* + * RF_Handling.c + * + * Created on: 27.11.2017 + * Author: + */ + +#include +#include +#include "Globals.h" +#include "RF_Handling.h" +#include "RF_Protocols.h" +#include "pca_0.h" +#include "uart.h" + +SI_SEGMENT_VARIABLE(RF_DATA[RF_DATA_BUFFERSIZE], uint8_t, SI_SEG_XDATA); +SI_SEGMENT_VARIABLE(RF_DATA_STATUS, uint8_t, SI_SEG_XDATA) = 0; +SI_SEGMENT_VARIABLE(rf_state, rf_state_t, SI_SEG_XDATA) = RF_IDLE; + +SI_SEGMENT_VARIABLE(Timer_3_Timeout, uint16_t, SI_SEG_XDATA) = 0x0000; +SI_SEGMENT_VARIABLE(sniffing_is_on, uint8_t, SI_SEG_XDATA) = false; + +SI_SEGMENT_VARIABLE(DUTY_CYCLE_HIGH, uint8_t, SI_SEG_XDATA) = 0x56; +SI_SEGMENT_VARIABLE(DUTY_CYLCE_LOW, uint8_t, SI_SEG_XDATA) = 0xAB; + +SI_SEGMENT_VARIABLE(actual_bit_of_byte, uint8_t, SI_SEG_XDATA) = 0; +SI_SEGMENT_VARIABLE(actual_bit, uint8_t, SI_SEG_XDATA) = 0; +SI_SEGMENT_VARIABLE(actual_byte, uint8_t, SI_SEG_XDATA) = 0; +SI_SEGMENT_VARIABLE(protocol_index, uint8_t, SI_SEG_XDATA) = 0; + +//----------------------------------------------------------------------------- +// Callbacks +//----------------------------------------------------------------------------- +void PCA0_overflowCb() +{ + +} + +void PCA0_intermediateOverflowCb() +{ + +} + +void PCA0_channel0EventCb() +{ + // stop transfer if all bits are transmitted + if (actual_bit_of_byte == 0) + { + actual_byte++; + actual_bit_of_byte = 8; + } + + if (actual_bit == PROTOCOL_DATA[protocol_index].BIT_COUNT) + { + PCA0_StopTransmit(); + return; + } + + actual_bit++; + actual_bit_of_byte--; + + if(((RF_DATA[actual_byte] >> actual_bit_of_byte) & 0x01) == 0x01) + { + // bit 1 + PCA0_writeChannel(PCA0_CHAN0, DUTY_CYCLE_HIGH << 8); + } + else + { + // bit 0 + PCA0_writeChannel(PCA0_CHAN0, DUTY_CYLCE_LOW << 8); + } +} + +void PCA0_channel1EventCb() +{ + static uint16_t current_capture_value; + static uint16_t previous_capture_value_pos, previous_capture_value_neg; + static uint16_t capture_period_pos, capture_period_neg; + + static uint8_t used_protocol; + static uint16_t low_pulse_time; + + // Store most recent capture value + current_capture_value = PCA0CP1 * 10; + + // positive edge + if (R_DATA) + { + // Update previous capture value with most recent info. + previous_capture_value_pos = current_capture_value; + + // Calculate capture period from last two values. + capture_period_neg = current_capture_value - previous_capture_value_neg; + + switch (rf_state) + { + // check if we receive a sync + case RF_IDLE: + // check first if last decoded RF signal was cleared + if (RF_DATA_STATUS != 0) + break; + + for ( used_protocol = 0; used_protocol < PROTOCOLCOUNT; used_protocol++) + { + if ( + (capture_period_pos > (PROTOCOL_DATA[used_protocol].SYNC_HIGH - SYNC_TOLERANCE)) && + (capture_period_pos < (PROTOCOL_DATA[used_protocol].SYNC_HIGH + SYNC_TOLERANCE)) && + (capture_period_neg > (PROTOCOL_DATA[used_protocol].SYNC_LOW - SYNC_TOLERANCE)) && + (capture_period_neg < (PROTOCOL_DATA[used_protocol].SYNC_LOW + SYNC_TOLERANCE)) + ) + { + actual_bit_of_byte = 8; + actual_byte = 0; + actual_bit = 0; + low_pulse_time = 0; + memset(RF_DATA, 0, sizeof(RF_DATA)); + rf_state = RF_IN_SYNC; + break; + } + } + break; + + // one matching sync got received + case RF_IN_SYNC: + actual_bit_of_byte--; + actual_bit++; + + // if high time is longer than low time: logic 1 + // if high time is shorter than low time: logic 0 + // the high time of bit 0 is getting measured to be able to determine the last bit + if ( + ((capture_period_pos > capture_period_neg) && (actual_bit < PROTOCOL_DATA[used_protocol].BIT_COUNT)) || + ((capture_period_pos > low_pulse_time) && (actual_bit == PROTOCOL_DATA[used_protocol].BIT_COUNT)) + ) + { + LED = LED_ON; + RF_DATA[(actual_bit - 1) / 8] |= (1 << actual_bit_of_byte); + } + else + { + LED = LED_OFF; + // backup low bit pulse time to be able to determine the last bit + if (capture_period_pos > low_pulse_time) + low_pulse_time = capture_period_pos; + } + + if (actual_bit_of_byte == 0) + actual_bit_of_byte = 8; + + // check if all bits for this protocol got received + if (actual_bit == PROTOCOL_DATA[used_protocol].BIT_COUNT) + { + RF_DATA_STATUS = used_protocol; + RF_DATA_STATUS |= RF_DATA_RECEIVED_MASK; + LED = LED_OFF; + rf_state = RF_IDLE; + } + break; + } + } + // negative edge + else + { + // Update previous capture value with most recent info. + previous_capture_value_neg = current_capture_value; + + // Calculate capture period from last two values. + capture_period_pos = current_capture_value - previous_capture_value_pos; + } +} + +void PCA0_channel2EventCb() +{ + +} + +//----------------------------------------------------------------------------- +// Send RF SYNC HIGH/LOW Routine +//----------------------------------------------------------------------------- +void SendRF_SYNC(uint8_t used_protocol) +{ + // enable P0.0 for I/O control + XBR1 &= ~XBR1_PCA0ME__CEX0_CEX1; + // do activate the SYN115 chip + Timer_3_Timeout = 3000; + // switch to high + T_DATA = 1; + // start 5µs timer + TMR3CN0 |= TMR3CN0_TR3__RUN; + // wait until timer has finished + while((TMR3CN0 & TMR3CN0_TR3__BMASK) == TMR3CN0_TR3__RUN); + // switch to low + T_DATA = 0; + + Timer_3_Timeout = 100; + // start 5µs timer + TMR3CN0 |= TMR3CN0_TR3__RUN; + // wait until timer has finished + while((TMR3CN0 & TMR3CN0_TR3__BMASK) == TMR3CN0_TR3__RUN); + // switch to high + T_DATA = 1; + // do high time + Timer_3_Timeout = PROTOCOL_DATA[used_protocol].SYNC_HIGH; + // start 5µs timer + TMR3CN0 |= TMR3CN0_TR3__RUN; + // wait until timer has finished + while((TMR3CN0 & TMR3CN0_TR3__BMASK) == TMR3CN0_TR3__RUN); + // switch to low + T_DATA = 0; + + // do low time + Timer_3_Timeout = PROTOCOL_DATA[used_protocol].SYNC_LOW; + // start 5µs timer + TMR3CN0 |= TMR3CN0_TR3__RUN; + // wait until timer has finished + while((TMR3CN0 & TMR3CN0_TR3__BMASK) == TMR3CN0_TR3__RUN); + // disable P0.0 for I/O control, enter PCA mode + XBR1 |= XBR1_PCA0ME__CEX0_CEX1; +} + +uint8_t PCA0_DoTransmit(uint8_t identifier) +{ + uint8_t i; + uint8_t protocol_index = 0xFF; + uint8_t TCON_save; + + // check first for valid identifier + if ((identifier > 0x00) && (identifier < 0x80)) + { + // find protocol index by identifier + for(i = 0; i < PROTOCOLCOUNT; i++) + { + if (PROTOCOL_DATA[i].IDENTIFIER == identifier) + { + protocol_index = i; + break; + } + } + + // check if protocol got found + if (protocol_index != 0xFF) + { + // calculate T0_Overflow + i = (uint8_t)(0x100 - ((uint32_t)SYSCLK / (0xFF * (1000000 / (uint32_t)PROTOCOL_DATA[protocol_index].BIT_TIME)))); + + //Save Timer Configuration + TCON_save = TCON; + //Stop Timer 0 + TCON &= ~TCON_TR0__BMASK; + + /*********************************************************************** + - Timer 0 High Byte = i (T0_Overflow) + ***********************************************************************/ + TH0 = (i << TH0_TH0__SHIFT); + + //Restore Timer Configuration + TCON |= (TCON_save & TCON_TR0__BMASK); + + // calculate high and low duty cycle + DUTY_CYCLE_HIGH = (uint16_t)(0xFF - ((PROTOCOL_DATA[protocol_index].BIT_HIGH_DUTY * 0xFF) / 100)); + DUTY_CYLCE_LOW = (uint16_t)(0xFF - ((PROTOCOL_DATA[protocol_index].BIT_LOW_DUTY * 0xFF) / 100)); + + // enable interrupt for RF transmitting + PCA0CPM0 |= PCA0CPM0_ECCF__ENABLED; + + // disable interrupt for RF receiving + PCA0CPM1 &= ~PCA0CPM1_ECCF__ENABLED; + + /*********************************************************************** + - PCA Counter/Timer Low Byte = 0xFF + ***********************************************************************/ + PCA0L = (0xFF << PCA0L_PCA0L__SHIFT); + } + } + + return protocol_index; +} + +void PCA0_StopTransmit(void) +{ + // set duty cycle to zero + PCA0_writeChannel(PCA0_CHAN0, 0x0000); + // disable interrupt for RF transmitting + PCA0CPM0 &= ~PCA0CPM0_ECCF__ENABLED; + PCA0_halt(); + + // enable P0.0 for I/O control + XBR1 &= ~XBR1_PCA0ME__CEX0_CEX1; + // switch to low + T_DATA = 0; + // disable P0.0 for I/O control, enter PCA mode + XBR1 |= XBR1_PCA0ME__CEX0_CEX1; + + // restart sniffing it was active + if(sniffing_is_on) + PCA0_DoSniffing(); +} + +void PCA0_DoSniffing(void) +{ + // restore timer to 100000Hz, 10µs interval + //Save Timer Configuration + uint8_t TCON_save; + TCON_save = TCON; + //Stop Timer 0 + TCON &= ~TCON_TR0__BMASK; + + /*********************************************************************** + - Timer 0 High Byte = 0x0B + ***********************************************************************/ + TH0 = (0x0B << TH0_TH0__SHIFT); + + //Restore Timer Configuration + TCON |= (TCON_save & TCON_TR0__BMASK); + + // stop PCA + PCA0CN0_CR = PCA0CN0_CR__STOP; + + // enable interrupt for RF receiving + PCA0CPM1 |= PCA0CPM1_ECCF__ENABLED; + + // disable interrupt for RF transmitting + PCA0CPM0 &= ~PCA0CPM0_ECCF__ENABLED; + + // start PCA + PCA0CN0_CR = PCA0CN0_CR__RUN; + + rf_state = RF_IDLE; + RF_DATA_STATUS = 0; + sniffing_is_on = true; +} + +void PCA0_StopSniffing(void) +{ + // stop PCA + PCA0CN0_CR = PCA0CN0_CR__STOP; + + // disable interrupt for RF receiving + PCA0CPM1 &= ~PCA0CPM1_ECCF__ENABLED; +} + +//----------------------------------------------------------------------------- +// TIMER3_ISR +//----------------------------------------------------------------------------- +// +// TIMER3 ISR Content goes here. Remember to clear flag bits: +// TMR3CN0::TF3H (Timer # High Byte Overflow Flag) +// TMR3CN0::TF3L (Timer # Low Byte Overflow Flag) +// +//----------------------------------------------------------------------------- +SI_INTERRUPT (TIMER3_ISR, TIMER3_IRQn) +{ + // Clear Timer 3 high overflow flag + TMR3CN0 &= ~TMR3CN0_TF3H__SET; + + // check if pulse time is over + if(Timer_3_Timeout <= 0) + { + // stop timer + TMR3CN0 &= ~TMR3CN0_TR3__RUN; + } + + Timer_3_Timeout -= 5; +} diff --git a/src/SILABS_STARTUP.A51 b/src/SILABS_STARTUP.A51 new file mode 100644 index 0000000..bef2e8d --- /dev/null +++ b/src/SILABS_STARTUP.A51 @@ -0,0 +1,203 @@ +$NOMOD51 +;------------------------------------------------------------------------------ +; This file is part of the C51 Compiler package +; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. +; Version 8.01 +; +; *** <<< Use Configuration Wizard in Context Menu >>> *** +;------------------------------------------------------------------------------ +; STARTUP.A51: This code is executed after processor reset. +; +; To translate this file use A51 with the following invocation: +; +; A51 STARTUP.A51 +; +; To link the modified STARTUP.OBJ file to your application use the following +; Lx51 invocation: +; +; Lx51 your object file list, STARTUP.OBJ controls +; +;------------------------------------------------------------------------------ +; +; User-defined Power-On Initialization of Memory +; +; With the following EQU statements the initialization of memory +; at processor reset can be defined: +; +; IDATALEN: IDATA memory size <0x0-0x100> +; Note: The absolute start-address of IDATA memory is always 0 +; The IDATA space overlaps physically the DATA and BIT areas. +IDATALEN EQU 80H +; +; XDATASTART: XDATA memory start address <0x0-0xFFFF> +; The absolute start address of XDATA memory +XDATASTART EQU 0 +; +; XDATALEN: XDATA memory size <0x0-0xFFFF> +; The length of XDATA memory in bytes. +XDATALEN EQU 0 +; +; PDATASTART: PDATA memory start address <0x0-0xFFFF> +; The absolute start address of PDATA memory +PDATASTART EQU 0H +; +; PDATALEN: PDATA memory size <0x0-0xFF> +; The length of PDATA memory in bytes. +PDATALEN EQU 0H +; +; +;------------------------------------------------------------------------------ +; +; Reentrant Stack Initialization +; +; The following EQU statements define the stack pointer for reentrant +; functions and initialized it: +; +; Stack Space for reentrant functions in the SMALL model. +; IBPSTACK: Enable SMALL model reentrant stack +; Stack space for reentrant functions in the SMALL model. +IBPSTACK EQU 0 ; set to 1 if small reentrant is used. +; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> +; Set the top of the stack to the highest location. +IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +; Stack Space for reentrant functions in the LARGE model. +; XBPSTACK: Enable LARGE model reentrant stack +; Stack space for reentrant functions in the LARGE model. +XBPSTACK EQU 0 ; set to 1 if large reentrant is used. +; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 +; +; +; Stack Space for reentrant functions in the COMPACT model. +; PBPSTACK: Enable COMPACT model reentrant stack +; Stack space for reentrant functions in the COMPACT model. +PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. +; +; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +;------------------------------------------------------------------------------ +; +; Memory Page for Using the Compact Model with 64 KByte xdata RAM +; Compact Model Page Definition +; +; Define the XDATA page used for PDATA variables. +; PPAGE must conform with the PPAGE set in the linker invocation. +; +; Enable pdata memory page initalization +PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. +; +; PPAGE number <0x0-0xFF> +; uppermost 256-byte address of the page used for PDATA variables. +PPAGE EQU 0 +; +; SFR address which supplies uppermost address byte <0x0-0xFF> +; most 8051 variants use P2 as uppermost address byte +PPAGE_SFR DATA 0A0H +; +; +;------------------------------------------------------------------------------ + +; Standard SFR Symbols +ACC DATA 0E0H +B DATA 0F0H +SP DATA 81H +DPL DATA 82H +DPH DATA 83H + + NAME ?C_STARTUP + + +?C_C51STARTUP SEGMENT CODE +?STACK SEGMENT IDATA + + RSEG ?STACK + DS 1 + + EXTRN CODE (?C_START) + PUBLIC ?C_STARTUP + + CSEG AT 0 +?C_STARTUP: LJMP STARTUP1 + + RSEG ?C_C51STARTUP + +STARTUP1: + +$IF (SILABS_STARTUP = 1) +EXTRN CODE (SiLabs_Startup) + LCALL SiLabs_Startup +$ENDIF + +IF IDATALEN <> 0 + MOV R0,#IDATALEN - 1 + CLR A +IDATALOOP: MOV @R0,A + DJNZ R0,IDATALOOP +ENDIF + +IF XDATALEN <> 0 + MOV DPTR,#XDATASTART + MOV R7,#LOW (XDATALEN) + IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE + MOV R6,#HIGH (XDATALEN) + ENDIF + CLR A +XDATALOOP: MOVX @DPTR,A + INC DPTR + DJNZ R7,XDATALOOP + DJNZ R6,XDATALOOP +ENDIF + +IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE +ENDIF + +IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A +PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP +ENDIF + +IF IBPSTACK <> 0 +EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP +ENDIF + +IF XBPSTACK <> 0 +EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP +ENDIF + +IF PBPSTACK <> 0 +EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP +ENDIF + + MOV SP,#?STACK-1 + +; This code is required if you use L51_BANK.A51 with Banking Mode 4 +; Code Banking +; Select Bank 0 for L51_BANK.A51 Mode 4 +$IF (USE_BANKING = 1) +; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4. +EXTRN CODE (?B_SWITCH0) + CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 +$ENDIF +; + LJMP ?C_START + + END diff --git a/src/uart.c b/src/uart.c new file mode 100644 index 0000000..777cd58 --- /dev/null +++ b/src/uart.c @@ -0,0 +1,266 @@ +/* + * uart.c + * + * Created on: 27.11.2017 + * Author: + */ + +#include +#include +#include "Globals.h" +#include "uart_0.h" +#include "uart.h" +#include "RF_Handling.h" +#include "RF_Protocols.h" + +//----------------------------------------------------------------------------- +// Global Variables +//----------------------------------------------------------------------------- +SI_SEGMENT_VARIABLE(UART_RX_Buffer[UART_BUFFER_SIZE], uint8_t, SI_SEG_XDATA); +SI_SEGMENT_VARIABLE(UART_TX_Buffer[UART_BUFFER_SIZE], uint8_t, SI_SEG_XDATA); +SI_SEGMENT_VARIABLE(UART_RX_Buffer_Position, static volatile uint8_t, SI_SEG_XDATA)=0; +SI_SEGMENT_VARIABLE(UART_TX_Buffer_Position, static volatile uint8_t, SI_SEG_XDATA)=0; +SI_SEGMENT_VARIABLE(UART_Buffer_Read_Position, static volatile uint8_t, SI_SEG_XDATA)=0; +SI_SEGMENT_VARIABLE(UART_Buffer_Write_Position, static volatile uint8_t, SI_SEG_XDATA)=0; +SI_SEGMENT_VARIABLE(lastRxError, static volatile uint8_t, SI_SEG_XDATA)=0; + +/* +uint8_t SendCommand(uint8_t command) +{ + uart_buffer[0] = UART_SYNC_INIT; + uart_buffer[1] = command; + uart_buffer[2] = UART_SYNC_END; + + return 3; +} +*/ +/* +void SendData(SI_VARIABLE_SEGMENT_POINTER(buffer, uint8_t, EFM8PDL_UART0_TX_BUFTYPE), uint8_t len) +{ + uart_buffer[0] = UART_SYNC_INIT; + memcpy(&uart_buffer[1], buffer, len); +} +*/ +//----------------------------------------------------------------------------- +// UART ISR Callbacks +//----------------------------------------------------------------------------- +void UART0_receiveCompleteCb() +{ + //UART0_writeBuffer(uart_buffer, 1); + /* + static uint8_t len; + static uart_command_t uart_command; + + switch(uart_state) + { + // check if byte was got received is sync byte + case SYNC_INIT: + len = 0; + + if (uart_buffer[0] == UART_SYNC_INIT) + uart_state = COMMAND; + + // start reading the next byte + UART0_readBuffer(uart_buffer, 1); + break; + + // check which command should be handled + case COMMAND: + uart_command = uart_buffer[0]; + + // check which command got received + switch(uart_command) + { + case LEARNING: + uart_state = SYNC_FINISH; + break; + + default: + uart_state = SYNC_INIT; + break; + } + + // start reading the next byte and data if available + UART0_readBuffer(uart_buffer, 1 + len); + break; + + // check if byte was got received is sync byte + case SYNC_FINISH: + if (uart_buffer[len] == UART_SYNC_END) + { + // send acknowledge + len = SendCommand(COMMAND_AK); + UART0_writeBuffer(uart_buffer, len); + uart_state = TRANSMIT; + } + + break; + } + */ +} + +void UART0_transmitCompleteCb() +{ +} + +//========================================================= +// Interrupt API +//========================================================= +SI_INTERRUPT(UART0_ISR, UART0_IRQn) +{ + //Buffer and clear flags immediately so we don't miss an interrupt while processing + uint8_t flags = SCON0 & (UART0_RX_IF | UART0_TX_IF); + SCON0 &= ~flags; + + // receiving byte + if ((flags & SCON0_RI__SET)) + { + if ( UART_RX_Buffer_Position == UART_BUFFER_SIZE ) + { + /* error: receive buffer overflow */ + lastRxError = UART_BUFFER_OVERFLOW >> 8; + } + else + { + /* store received data in buffer */ + UART_RX_Buffer[UART_RX_Buffer_Position] = SBUF0; + UART_RX_Buffer_Position++; + } + } + + // transmit byte + if ((flags & SCON0_TI__SET)) + { + if ( UART_TX_Buffer_Position == UART_BUFFER_SIZE ) + { + /* error: receive buffer overflow */ + lastRxError = UART_BUFFER_OVERFLOW >> 8; + } + else + { + if (UART_Buffer_Write_Position < UART_TX_Buffer_Position) + { + SBUF0 = UART_TX_Buffer[UART_Buffer_Write_Position]; + UART_Buffer_Write_Position++; + } + + if (UART_Buffer_Write_Position == UART_TX_Buffer_Position) + { + UART_TX_Buffer_Position = 0; + UART_Buffer_Write_Position = 0; + } + } + } +} + +void uart_buffer_reset(void) +{ + UART_RX_Buffer_Position = 0; + UART_Buffer_Read_Position = 0; + UART_TX_Buffer_Position = 0; + UART_Buffer_Write_Position = 0; +} + +uint8_t uart_getlen(void) +{ + return UART_RX_Buffer_Position - UART_Buffer_Read_Position; +} + +bool uart_transfer_finished(void) +{ + return UART_Buffer_Write_Position == UART_TX_Buffer_Position; +} + +/************************************************************************* +Function: uart_getc() +Purpose: return byte from ringbuffer +Returns: lower byte: received byte from ringbuffer + higher byte: last receive error +**************************************************************************/ +unsigned int uart_getc(void) +{ + unsigned int rxdata; + + if ( UART_Buffer_Read_Position == UART_RX_Buffer_Position ) { + return UART_NO_DATA; /* no data available */ + } + + /* get data from receive buffer */ + rxdata = UART_RX_Buffer[UART_Buffer_Read_Position]; + UART_Buffer_Read_Position++; + + /* all got read of the received data, reset to 0 */ + if (UART_Buffer_Read_Position == UART_RX_Buffer_Position) + { + UART_Buffer_Read_Position = 0; + UART_RX_Buffer_Position = 0; + } + + rxdata |= (lastRxError << 8); + lastRxError = 0; + return rxdata; +} + +/************************************************************************* +Function: uart_putc() +Purpose: write byte to ringbuffer for transmitting via UART +Input: byte to be transmitted +Returns: none +**************************************************************************/ +void uart_putc(uint8_t txdata) +{ + if (UART_TX_Buffer_Position == UART_BUFFER_SIZE) + lastRxError = UART_BUFFER_OVERFLOW >> 8; + + UART_TX_Buffer[UART_TX_Buffer_Position] = txdata; + UART_TX_Buffer_Position++; +} + +void uart_put_command(uint8_t command) +{ + uart_putc(UART_SYNC_INIT); + uart_putc(command); + uart_putc(UART_SYNC_END); + UART0_initTxPolling(); +} + +void uart_put_uint16_t(uint8_t command, uint16_t value) +{ + uart_putc(UART_SYNC_INIT); + uart_putc(command); + uart_putc((value >> 8) & 0xFF); + uart_putc(value & 0xFF); + uart_putc(UART_SYNC_END); + UART0_initTxPolling(); +} + +void uart_put_RF_Data(uint8_t Command, uint8_t used_protocol) +{ + uint8_t i = 0; + uint8_t b = 0; + + uart_putc(UART_SYNC_INIT); + uart_putc(Command); + + while(i < PROTOCOL_DATA[used_protocol].BIT_COUNT) + { + i += 8; + b++; + } + uart_putc(b+1); + + // set identifier for this protocol + uart_putc(PROTOCOL_DATA[used_protocol].IDENTIFIER); + + // copy data to UART buffer + i = 0; + while(i < b) + { + uart_putc(RF_DATA[i]); + i++; + } + uart_putc(UART_SYNC_END); + + UART0_initTxPolling(); +} +