diff --git a/Data_Selection_includePID_RTL_Schematic.png b/Data_Selection_includePID_RTL_Schematic.png
deleted file mode 100644
index cca9cfe..0000000
Binary files a/Data_Selection_includePID_RTL_Schematic.png and /dev/null differ
diff --git a/Final_I2C.vhd b/Final_I2C.vhd
deleted file mode 100644
index 3aa35f0..0000000
--- a/Final_I2C.vhd
+++ /dev/null
@@ -1,153 +0,0 @@
---Author: Manas Ranjan Swain
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_arith.ALL;
-use IEEE.STD_LOGIC_unsigned.ALL;
-
---To write data to a address 50 
-
-entity I2C_master_simple is
-    Port ( sys_clk: in STD_LOGIC;
-			  clk : inout STD_LOGIC;
-           reset : in  STD_LOGIC;
-           i2c_scl : inout  STD_LOGIC:='1';
-           i2c_sda : out  STD_LOGIC;
-			  
-			  Sensor1: inout STD_LOGIC_VECTOR(15 downto 0);
-			  Sensor2: inout STD_LOGIC_VECTOR(15 downto 0);
-		     Sensor3: inout STD_LOGIC_VECTOR(15 downto 0);
-		     Sensor4: inout STD_LOGIC_VECTOR(15 downto 0);
-			  Sensor_input1: in INTEGER range 0 to 4303;
-			  Sensor_input2: in INTEGER range 0 to 4303;
-		     Sensor_input3: in INTEGER range 0 to 4303;
-		     Sensor_input4: in INTEGER range 0 to 4303
-			  );
-end I2C_master_simple;
-
---Hot coding is done for implementing Finite State machine
- 
-architecture code_starts of I2C_master_simple is
-signal state:STD_LOGIC_VECTOR(7 downto 0):="00000001";
-constant initial_idle_state:STD_LOGIC_VECTOR(7 downto 0):="00000001";
-constant initial_start_state:STD_LOGIC_VECTOR(7 downto 0):="00000010";
-constant address_state:STD_LOGIC_VECTOR(7 downto 0):="00000100";
-constant acknowledge_state:STD_LOGIC_VECTOR(7 downto 0):="00001000";
-constant acknowledge_state_2:STD_LOGIC_VECTOR(7 downto 0):="00010000";
-constant stop_state:STD_LOGIC_VECTOR(7 downto 0):="00100000";
-constant address:STD_LOGIC_VECTOR(6 downto 0):="1010000";
-constant data_state:STD_LOGIC_VECTOR(7 downto 0):="01000000";
-signal I2C_enable:STD_LOGIC:='0';
-shared variable count:INTEGER range 0 to 15;
-shared variable start:STD_LOGIC:='0';
-shared variable data:STD_LOGIC_VECTOR(15 downto 0);
-shared variable cal:INTEGER range 0 to 65535;
-
-COMPONENT I2C_clock_divider	--Lowers the frequency from the default system frequency to the frequency ideal for I2c i.e, 100Khz
-	PORT(sys_clk : IN std_logic;       
-		  i2c_clk : INOUT std_logic);
-end component;
-
-COMPONENT Tem_sensor_sampleblock
-	PORT(
-		Sensor : IN INTEGER range 0 to 4303;          
-		output_vector : OUT std_logic_vector(15 downto 0)
-		);
-	END COMPONENT;
-begin
-block1: Tem_sensor_sampleblock PORT MAP(
-		Sensor => Sensor_input1,
-		output_vector => Sensor1
-	);
-block2: Tem_sensor_sampleblock PORT MAP(
-		Sensor => Sensor_input2,
-		output_vector => Sensor2
-	);
-block3: Tem_sensor_sampleblock PORT MAP(
-		Sensor => Sensor_input3,
-		output_vector => Sensor3
-	);
-block4: Tem_sensor_sampleblock PORT MAP(
-		Sensor => Sensor_input4,
-		output_vector => Sensor4
-	);
-divider: I2C_clock_divider PORT MAP(
-		sys_clk =>sys_clk ,
-		i2c_clk => clk
-	);
-process(Sensor1,Sensor2,Sensor3,Sensor4)
-begin
-	cal:=conv_integer(unsigned(Sensor1))+conv_integer(unsigned(Sensor2))+conv_integer(unsigned(Sensor3))+conv_integer(unsigned(Sensor4));
-	data:=conv_std_logic_vector(cal,16);
-	start:='1';
-end process;
-	
-process(clk,i2c_enable) --Implemented for clock synchronization
- begin
-	if(i2c_enable='0') then
-		i2c_scl<='1';
-	else
-		i2c_scl<=not clk;
-	end if;
-end process;
-
-process(clk,reset,state)-- Chnage of i2c_enable which is later used for clock synchronization
-	begin
-	if(clk'event and clk='1')then
-		if(reset='1') then
-			i2c_enable<='0';
-		else
-			if(state=initial_idle_state or state=initial_start_state or state=stop_state) then
-				i2c_enable<='0';
-			else
-				i2c_enable<='1';
-			end if;
-		end if;
-		end if;
-	end process;
-process(reset,clk,state)
-begin
-if(clk'event and clk='1') then
-	if(reset='1') then
-		state<=initial_idle_state;
-		i2c_sda<='1';
-	else
-		case state is
-		  when initial_idle_state=>
-				i2c_sda<='1';
-				if(start='1') then
-				state<=initial_start_state;
-				end if;
-		  when initial_start_state=>
-				i2c_sda<='1';
-				state<=address_state;
-				count:=6;
-		  when address_state=> --Address reach state
-				i2c_sda<=address(count);
-				if (count=0) then
-					state<=acknowledge_state;
-				else
-					count:=count-1;
-				end if;
-			when acknowledge_state=>	--This state is left blank , Will be modified later when needed
-				state<=data_state;
-				count:=15;
-			when data_state=>	--In this state data transfer takes place
-				i2c_sda<=data(count);
-				if(count=0) then
-					state<=acknowledge_state_2;
-				else
-					count:=count-1;
-				end if;
-			when acknowledge_state_2=> --This state is left blank , Will be modified later when needed
-				state<=stop_state;
-			when stop_state=> 
-				i2c_sda<='1';
-				state<=initial_idle_state;
-			when others=>
-				state<=initial_idle_state;
-		end case;
-	end if;
-	end if;
-	end process;
-end code_starts;
diff --git a/Final_Test_bench.vhd b/Final_Test_bench.vhd
deleted file mode 100644
index ef0b95d..0000000
--- a/Final_Test_bench.vhd
+++ /dev/null
@@ -1,127 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   20:00:02 12/31/2017
--- Design Name:   
--- Module Name:   /home/ise/Documents/Temperature_block/Test_bench.vhd
--- Project Name:  Temperature_block
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: I2C_master_simple
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
-ENTITY Test_bench IS
-END Test_bench;
- 
-ARCHITECTURE behavior OF Test_bench IS 
- 
-    -- Component Declaration for the Unit Under Test (UUT)
- 
-    COMPONENT I2C_master_simple
-    PORT(
-         sys_clk : IN  std_logic;
-         clk : INOUT  std_logic;
-         reset : IN  std_logic;
-         i2c_scl : INOUT  std_logic;
-         i2c_sda : OUT  std_logic;
-         Sensor1 : INOUT  std_logic_vector(15 downto 0);
-         Sensor2 : INOUT  std_logic_vector(15 downto 0);
-         Sensor3 : INOUT  std_logic_vector(15 downto 0);
-         Sensor4 : INOUT  std_logic_vector(15 downto 0);
-         Sensor_input1 : IN  integer range 0 to 4303;
-			Sensor_input2 : IN  integer range 0 to 4303;
-			Sensor_input3 : IN  integer range 0 to 4303;
-			Sensor_input4 : IN  integer range 0 to 4303
-        );
-    END COMPONENT;
-    
-
-   --Inputs
-   signal sys_clk : std_logic := '0';
-   signal reset : std_logic := '0';
-   signal Sensor_input1 : integer range 0 to 4303:=0;
-   signal Sensor_input2 : integer range 0 to 4303:=0;
-   signal Sensor_input3 : integer range 0 to 4303:=0;
-   signal Sensor_input4 : integer range 0 to 4303:=0;
-
-	--BiDirs
-   signal clk : std_logic;
-   signal i2c_scl : std_logic;
-   signal Sensor1 : std_logic_vector(15 downto 0);
-   signal Sensor2 : std_logic_vector(15 downto 0);
-   signal Sensor3 : std_logic_vector(15 downto 0);
-   signal Sensor4 : std_logic_vector(15 downto 0);
-
- 	--Outputs
-   signal i2c_sda : std_logic;
-
-   -- Clock period definitions
-   constant sys_clk_period : time := 10 ns;
- 
-BEGIN
- 
-	-- Instantiate the Unit Under Test (UUT)
-   uut: I2C_master_simple PORT MAP (
-          sys_clk => sys_clk,
-          clk => clk,
-          reset => reset,
-          i2c_scl => i2c_scl,
-          i2c_sda => i2c_sda,
-          Sensor1 => Sensor1,
-          Sensor2 => Sensor2,
-          Sensor3 => Sensor3,
-          Sensor4 => Sensor4,
-          Sensor_input1 => Sensor_input1,
-          Sensor_input2 => Sensor_input2,
-          Sensor_input3 => Sensor_input3,
-          Sensor_input4 => Sensor_input4
-        );
-
-   -- Clock process definitions
-   sys_clk_process :process
-   begin
-		sys_clk <= '0';
-		wait for sys_clk_period/2;
-		sys_clk <= '1';
-		wait for sys_clk_period/2;
-   end process;
- 
- 
-
-   -- Stimulus process
-   stim_proc: process
-   begin		
-		reset<='1';
-		Sensor_input1<=40;
-		Sensor_input2<=30;
-		Sensor_input3<=20;
-		Sensor_input4<=10;
-		wait for 10 us;
-		reset<='0';
-		wait for 10 us;
-      wait;
-   end process;
-
-END;
diff --git a/I2C_Final.png b/I2C_Final.png
deleted file mode 100644
index d24b770..0000000
Binary files a/I2C_Final.png and /dev/null differ
diff --git a/I2C_RTL_Schematic.png b/I2C_RTL_Schematic.png
deleted file mode 100644
index 7969ac8..0000000
Binary files a/I2C_RTL_Schematic.png and /dev/null differ
diff --git a/I2C_Technology_Schematic.png b/I2C_Technology_Schematic.png
deleted file mode 100644
index a65d005..0000000
Binary files a/I2C_Technology_Schematic.png and /dev/null differ
diff --git a/I2C_clock_divider.vhd b/I2C_clock_divider.vhd
deleted file mode 100644
index cef2464..0000000
--- a/I2C_clock_divider.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
---Author: Manas Ranjan Swain
---To make a clock divider that converts the default clock speed to 100KHz i.e., the clock frequency for I2C (although max is 400KHz)
-
-library IEEE;			
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-entity I2C_clock_divider is
-port(sys_clk: in STD_LOGIC;				
-		i2c_clk: inout STD_LOGIC:='0');
-end I2C_clock_divider;
-
-architecture clock_divider of I2C_clock_divider is
-shared variable count:INTEGER range 1 to 1001:=1;
-begin
-	process(sys_clk)
-	begin
-		if(count=1001) then		
-			count:=1;
-			i2c_clk<=not i2c_clk;
-		else
-			count:= count+1;
-		end if;
-	end process;
-end clock_divider;
-
diff --git a/I2C_test_bench.png b/I2C_test_bench.png
deleted file mode 100644
index cc89c43..0000000
Binary files a/I2C_test_bench.png and /dev/null differ