Relationship between high-level logic and low-level representation

[MasterInQuestion]

    Arbitrary complex logic high-level may be represented as gate array abstraction low-level.
    Ideally the CPU, GPU, NPU etc. (General Purpose Instruction Set Architecture) abstraction (that expects architecture-specific Assembly) may be dropped: replaceable with FPGA [1].

[ [1]
    FPGA (Field-Programmable Gate Array) [1]: Gate array [2] abstraction reprogrammable on need.
[1] Maybe also called CPLD (Complex Programmable Logic Device). ]

[ [2]
    Combination of the basic logic gates.
    Namely 4: "NOT", "AND", "OR", "XOR".

    Note all gate types may be simulated solely with "NAND" or "NOR":
[[
    NAND( 1, 2 )
    = NOT( AND( 1, 2 ) )
    = OR( NOT( 1 ), NOT( 2 ) )

    NOR( 1, 2 )
    = NOT( OR( 1, 2 ) )
    = AND( NOT( 1 ), NOT( 2 ) )

    OR( 1, 2 )
    = NAND( NAND( 1, 1 ), NAND( 2, 2 ) )
    = NAND( NOT( 1 ), NOT( 2 ) )

    AND( 1, 2 )
    = NOR( NOR( 1, 1 ), NOR( 2, 2 ) )
    = NOR( NOT( 1 ), NOT( 2 ) )

    XOR( 1, 2 )
    = AND( OR( 1, 2 ), NAND( 1, 2 ) )
    = NOR( NOR( 1, 2 ), NOR( NOT( 1 ), NOT( 2 ) ) )
    = NOR( NOR( 1, 2 ), AND( 1, 2 ) )
    = NOR( AND( NOT( 1 ), NOT( 2 ) ), AND( 1, 2 ) )
    = OR( AND( 1, NOT( 2 ) ), AND( NOT( 1 ), 2 ) )

    NXOR( 1, 2 )
    = NOT( XOR( 1, 2 ) )
    = XOR( NOT( 1 ), 2 )
    = XOR( 1, NOT( 2 ) )

    OR( NOT( 1 ), 2 ) = NAND( 1, NOT( 2 ) )
    OR( 1, NOT( 2 ) ) = NAND( NOT( 1 ), 2 )
]]
    Or "NOT" + ( "AND" | "OR" ), more appropriately.

    Order doesn't matter for serial "AND", "OR", "XOR", "NXOR" same kind. (otherwise does)
    I.e. "AND( 1, 2, 3 ) = AND( 1, 3, 2 )" etc. ]

[ [3]
    "¬" "~" "Negation".
    "∧" "∨" "Conjunction" "Disjunction"?

    More indicative perhaps: "_∧_" "←∨→" ]


=== Basic adder logic ===

    XOR by bit, NXOR on carry; carry when both 1, break on both 0.

    |1| Starting from the least significant bit, XOR by bit (1 bit each time) and save to the output.
    |2| If the current working bit of input matches "both 1": switch to "carry" mode.
    |3| Shift next the current working bit.
    |4| XOR/NXOR the bit.
    |5| Go to |2| if not in "carry" mode.
    |6| If the current working bit of input matches "both 0": break from "carry" mode.
    |7| Go to |3|.

[[

	add {
	for (
	${ /@1\.(\d+)/ },
	${ /@2\.\d+/ }
	) {
# >>>> (0)
	${Out.${1.1}} = XOR( ${@1}, ${@2} );
	( ${carry} ) && { ${Out.${1.1}} = NOT( .. ); };

	if ( ${ /@[12]/ } == 1 ) {
	${carry} = true;

	} else if ( ${ /@[12]/ } == 0 ) {
	${carry} = false;
	};
# <<<< (0)
	};

	return ${ /Out\.\d+/ };
	};

]]