dump.vcd

$date
	Sat Nov 18 19:56:58 2023
$end

$version
	Synopsys VCS version S-2021.09
$end

$timescale
	1ps
$end

$comment Csum: 1 f7d1087b00f34db5 $end


$scope module uvm_pkg $end
$var reg 32 ! UVM_UNBOUNDED_CONNECTIONS [31:0] $end
$var reg 1 " uvm_start_uvm_declarations $end
$var time 64 # setting_offset $end
$var reg 32 $ setting_verbosity [31:0] $end
$var reg 1 % is_verdi_set_verbosity_called $end
$var reg 32 & uvm_global_random_seed [31:0] $end
$upscope $end


$scope module $unit $end
$upscope $end


$scope module tb $end

$scope begin unnamed$$_vcs_2 $end
$upscope $end


$scope begin unnamed$$_vcs_0 $end
$upscope $end


$scope begin unnamed$$_vcs_1 $end
$upscope $end


$scope begin unnamed$$_vcs_3 $end
$upscope $end


$scope module dif $end
$var reg 1 ' din $end
$var reg 1 ( dout $end
$var reg 1 ) rst $end
$var reg 1 * clk $end
$upscope $end


$scope module dut $end
$var wire 1 + clk $end
$var wire 1 , rst $end
$var wire 1 - din $end
$var reg 1 . dout $end
$upscope $end

$upscope $end

$enddefinitions $end

#0
$dumpvars
0%
1"
bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx #
b11111111111111111111111111111111 !
b00000000000000000000000000000000 $
b01000010000001111100110001000111 &
x.
0*
0'
x(
1)
0+
0-
1,
$end
#10000
1*
1+
0.
0(
#20000
0*
0+
#30000
1*
1+
#40000
0*
0+
#50000
1*
1+
#60000
0*
0+
#70000
1*
1+
#80000
0*
0+
#90000
1*
1+
0)
0,
1'
1-
#100000
0*
0+
#110000
1*
1+
1.
1(
#120000
0*
0+
#130000
1*
1+
#140000
0*
0+
#150000
1*
1+
#160000
0*
0+
#170000
1*
1+
#180000
0*
0+
#190000
1*
1+
#200000
0*
0+
#210000
1*
1+
#220000
0*
0+
#230000
1*
1+
#240000
0*
0+
#250000
1*
1+
#260000
0*
0+
#270000
1*
1+
#280000
0*
0+
#290000
1*
1+
#300000
0*
0+
#310000
1*
1+
#320000
0*
0+
#330000
1*
1+
0'
0-
#340000
0*
0+
#350000
1*
1+
0.
0(
#360000
0*
0+
#370000
1*
1+
#380000
0*
0+
#390000
1*
1+
#400000
0*
0+
#410000
1*
1+
1'
1-
#420000
0*
0+
#430000
1*
1+
1.
1(
#440000
0*
0+
#450000
1*
1+
#460000
0*
0+
#470000
1*
1+
#480000
0*
0+
#490000
1*
1+
#500000
0*
0+
#510000
1*
1+