-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathmealy1.map.rpt
209 lines (185 loc) · 14.7 KB
/
mealy1.map.rpt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
Analysis & Synthesis report for mealy1
Tue Mar 01 15:16:44 2022
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Parameter Settings for User Entity Instance: Top-level Entity: |mealy1
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 01 15:16:44 2022 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name ; mealy1 ;
; Top-level Entity Name ; mealy1 ;
; Family ; FLEX10KE ;
; Total logic elements ; 3 ;
; Total pins ; 4 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+-----------------------------------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------+--------------+---------------+
; Top-level entity name ; mealy1 ; mealy1 ;
; Family name ; FLEX10KE ; Stratix II ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Use Generated Physical Constraints File ; On ; ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique ; Area ; Area ;
; Carry Chain Length ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+--------------+---------------+
+--------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+--------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+--------------------------------------+
; mealy1.v ; yes ; User Verilog HDL File ; C:/altera/81/quartus/mealy1/mealy1.v ;
+----------------------------------+-----------------+------------------------+--------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource ; Usage ;
+--------------------------------+------------+
; Total logic elements ; 3 ;
; Total combinational functions ; 2 ;
; -- Total 4-input functions ; 0 ;
; -- Total 3-input functions ; 0 ;
; -- Total 2-input functions ; 1 ;
; -- Total 1-input functions ; 1 ;
; -- Total 0-input functions ; 0 ;
; Total registers ; 2 ;
; I/O pins ; 4 ;
; Maximum fan-out node ; w ;
; Maximum fan-out ; 2 ;
; Total fan-out ; 9 ;
; Average fan-out ; 1.29 ;
+--------------------------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |mealy1 ; 3 (3) ; 2 ; 0 ; 4 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |mealy1 ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 2 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 1 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 1 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |mealy1 ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------+
; S0 ; 0 ; Unsigned Binary ;
; S1 ; 1 ; Unsigned Binary ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Tue Mar 01 15:16:44 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mealy1 -c mealy1
Info: Found 1 design units, including 1 entities, in source file mealy1.v
Info: Found entity 1: mealy1
Warning: EDA synthesis tool is specified as "Custom", but Library Mapping File is not specified
Warning: EDA synthesis tool is specified as "Custom", but VCC is not specified
Warning: EDA synthesis tool is specified as "Custom", but GND is not specified
Info: Elaborating entity "mealy1" for the top level hierarchy
Info: Implemented 7 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 1 output pins
Info: Implemented 3 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 217 megabytes
Info: Processing ended: Tue Mar 01 15:16:44 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00