diff --git a/Documentation/Module-Docs/02_ID_EX_Latch.md b/Documentation/Module-Docs/02_ID_EX_Latch.md
index 1a67cb3a..81fe2f03 100644
--- a/Documentation/Module-Docs/02_ID_EX_Latch.md
+++ b/Documentation/Module-Docs/02_ID_EX_Latch.md
@@ -14,7 +14,7 @@ Note: The inputs and outputs for this module should be made into an interface
 |:---|:---:|
 |```clk```|1-bit|
 |```rstn```|1-bit|
-|```a_sel```|1-bit|
+|```a_sel```|2-bit|
 |```b_sel```|2-bit|
 |```nranch_taken_in```|1-bit|
 |```imm```|32-bits|
@@ -59,6 +59,7 @@ Note: The inputs and outputs for this module should be made into an interface
     |---|---|
     |```a_sel == 0```|```a = rs1d```|
     |```a_sel == 1```|```a = pc```|
+    |```a_sel == 2```|```a = imm```|
   - ```b_sel```
 
     |State|Output|
@@ -66,6 +67,7 @@ Note: The inputs and outputs for this module should be made into an interface
     |```b_sel == 0```|```b = rs2d_in```|
     |```b_sel == 1```|```b = imm```|
     |```b_sel == 2```|```b = 4```|
+    |```b_sel == 3```|```b = 12```|
 
 ### Asynchronous active low reset
   - Register values reset to 0