diff --git a/CMakeLists.txt b/CMakeLists.txt
index 444cceff..53c100a3 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,6 +1,6 @@
-cmake_minimum_required(VERSION 3.27)
+cmake_minimum_required(VERSION 3.24)
 
-if(NOT SKIP_VCPKG AND NOT DEFINED CMAKE_TOOLCHAIN_FILE)
+if(NOT DEFINED CMAKE_TOOLCHAIN_FILE)
   include(FetchContent)
   FetchContent_Declare(
     vcpkg
@@ -16,11 +16,9 @@ if(NOT SKIP_VCPKG AND NOT DEFINED CMAKE_TOOLCHAIN_FILE)
   set(VCPKG_ROOT_DIR ${vcpkg_SOURCE_DIR} CACHE PATH "Vcpkg Root Directory")
 endif()
 
-if(DEFINED VCPKG_ROOT_DIR)
-  add_custom_target(UpdateVcpkgBaseline
-    ${VCPKG_ROOT_DIR}/vcpkg x-update-baseline
-  )
-endif()
+add_custom_target(UpdateVcpkgBaseline
+  ${VCPKG_ROOT_DIR}/vcpkg x-update-baseline
+)
 
 project(nyu-core VERSION 1.0.0)
 
diff --git a/rtl/Alu.sv b/rtl/Alu.sv
index 42d67011..50b1428d 100644
--- a/rtl/Alu.sv
+++ b/rtl/Alu.sv
@@ -13,26 +13,37 @@ parameter USLT = 6'h03;
 
 
 module Alu #(
-    WordSize = 32
-) (
-    input [WordSize - 1:0] a,
-    input [WordSize - 1:0] b,
+  WordSize = 32
+)(
+    input [WordSize - 1:0] a, b,
     input [5:0] alu_mode,
     output logic [WordSize - 1:0] alu_out
 );
-  always_comb begin
-    case (alu_mode)
-      ADD: alu_out = a + b;
-      SUB: alu_out = a - b;
-      XOR: alu_out = a ^ b;
-      OR: alu_out = a | b;
-      AND: alu_out = a & b;
-      LLS: alu_out = a << b[4:0];
-      LRS: alu_out = a >> b[4:0];
-      ARS: alu_out = $signed(a) >>> b[4:0];
-      SSLT: alu_out = WordSize'($signed(a) < $signed(b));
-      USLT: alu_out = WordSize'(a < b);
-      default: alu_out = 0;
+
+    logic[WordSize - 1:0] adder_result;
+    logic do_sub, carry;
+
+assign do_sub = alu_mode[5] | (alu_mode == SSLT) | (alu_mode == USLT);
+
+assign {carry, adder_result} = {1'b0, a} + {1'b0, ((b^({WordSize{do_sub}})) + {{WordSize - 1{1'b0}}, do_sub})};
+
+always_comb begin 
+    case(alu_mode)
+    ADD: alu_out = adder_result;
+    SUB: alu_out = adder_result;
+    XOR: alu_out = a ^ b;
+    OR: alu_out = a | b;
+    AND: alu_out = a & b;
+    LLS: alu_out = a << b[4:0];
+    LRS: alu_out = a >> b[4:0];
+    ARS: alu_out = a >>> b[4:0];
+    SSLT: alu_out = (a[WordSize - 1] & !(b[WordSize - 1])) ? 1 : (!(a[WordSize - 1]) & b[WordSize - 1]) ? 0 : {{WordSize - 1{1'b0}}, carry^(!b[WordSize - 1])};
+    USLT: alu_out = {{WordSize - 1{1'b0}}, !carry};
+    default: alu_out = 0;
     endcase
-  end
+
+
+end
+
+
 endmodule
diff --git a/rtl/Branch_Addr_Calc.sv b/rtl/Branch_Addr_Calc.sv
index afc1801c..02632771 100644
--- a/rtl/Branch_Addr_Calc.sv
+++ b/rtl/Branch_Addr_Calc.sv
@@ -1,48 +1,44 @@
 //Branch Address Conditions
-parameter PC = 0;  //Case when branch_addr = pc + imm
-parameter RD = 1;  //Case when branch_addr = imm + rs1d
+parameter PC = 0;   //Case when branch_addr = pc + imm
+parameter RD = 1;   //Case when branch_addr = imm + rs1d
 
-module Branch_Addr_Calc #(
+module Branch_Addr_Calc # (
     WordSize = 32
-) (
-    input addr_mode,
-    input branch_taken,
-    input [WordSize - 1:0] imm,
-    input [WordSize - 1:0] rs1d,
-    input [WordSize - 1:0] pc_in,
-    output logic [WordSize - 1:0] branch_addr,
-    output logic [WordSize - 1:0] npc
+)(
+    input addr_mode, branch_taken,
+    input [WordSize - 1:0] imm, rs1d, pc_in,
+    output logic [WordSize - 1:0] branch_addr, npc
 );
 
-  always_comb begin
-    case (addr_mode)
-      PC:
-      case (branch_taken)
-        1'b0: begin
-          branch_addr = pc_in + imm;
-          npc = pc_in;
+always_comb begin
+    case(addr_mode)
+        PC:
+            case (branch_taken)
+                1'b0: begin
+                    branch_addr = pc_in + imm;
+                    npc = pc_in;
+                end
+                1'b1: begin
+                    branch_addr = pc_in + imm;
+                    npc = branch_addr; 
+                end 
+            endcase
+        RD:
+            case (branch_taken)
+                1'b0: begin
+                    branch_addr = imm + rs1d;
+                    npc = pc_in;
+                end
+                1'b1: begin
+                    branch_addr = imm + rs1d;
+                    npc = branch_addr;
+                end
+            endcase
+        default: begin
+            branch_addr = pc_in + imm;
+            npc = pc_in;
         end
-        1'b1: begin
-          branch_addr = pc_in + imm;
-          npc = branch_addr;
-        end
-      endcase
-      RD:
-      case (branch_taken)
-        1'b0: begin
-          branch_addr = imm + rs1d;
-          npc = pc_in;
-        end
-        1'b1: begin
-          branch_addr = imm + rs1d;
-          npc = branch_addr;
-        end
-      endcase
-      default: begin
-        branch_addr = pc_in + imm;
-        npc = pc_in;
-      end
     endcase
-  end
+end
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/rtl/Branch_Eval.sv b/rtl/Branch_Eval.sv
index 17cb6ea9..c791552e 100644
--- a/rtl/Branch_Eval.sv
+++ b/rtl/Branch_Eval.sv
@@ -1,28 +1,28 @@
 
 //Branch condition definitions
-parameter NE = 2'h0;    //Non branching instruction
-parameter ALU = 2'h1;   //Branch condition is < or !=
-parameter NALU = 2'h2;  //Branch condition is >= or =
-parameter AL = 2'h3;    //Jump instruction
+parameter NE = 2'h0; //Non branching instruction
+parameter ALU = 2'h1; //Branch condition is < or !=
+parameter NALU = 2'h2; //Branch condition is >= or =
+parameter AL = 2'h3; //Jump instruction
 
 
 
 module Branch_Eval #(
-    WordSize = 32
-) (
+  WordSize = 32
+)(
     input [WordSize - 1:0] alu_out,
     input [1:0] branch_cond,
     output logic act_taken
 );
 
-  always_comb begin
-    case (branch_cond)
-      NE:   act_taken = 0;
-      ALU:  act_taken = |alu_out;
-      NALU: act_taken = ~(|alu_out);
-      AL:   act_taken = 1;
+always_comb begin 
+    case(branch_cond)
+        NE: act_taken = 0;  
+        ALU: act_taken = |alu_out;
+        NALU: act_taken = ~(|alu_out);
+        AL: act_taken = 1;
     endcase
-  end
+end
 
 
 endmodule
diff --git a/rtl/Branch_Manager.sv b/rtl/Branch_Manager.sv
index 269ebecb..312328a3 100644
--- a/rtl/Branch_Manager.sv
+++ b/rtl/Branch_Manager.sv
@@ -1,39 +1,36 @@
 module Branch_Manager #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input pred_taken,
-    input act_taken,
-    input [WordSize - 1:0] pred_pc,
-    input [WordSize - 1:0] pred_addr,
+  WordSize = 32
+)(
+    input clk, rstn, pred_taken, act_taken,
+    input [WordSize - 1:0] pred_pc, pred_addr,
     output logic flush,
     output logic [WordSize - 1:0] npc
 );
 
-  logic restart;
+logic restart;
 
-  always_ff @(posedge clk or negedge rstn) begin
+always @ (posedge clk or negedge rstn) begin
     if (!rstn) begin
       restart <= 1;
       flush <= 0;
       npc <= 0;
-    end else begin
-      restart <= 0;
-
+    end
+    else begin
       if ((pred_taken != act_taken) && !restart) begin
         flush <= 1;
-        case (act_taken)
-          0: npc <= pred_pc + 4;
-          1: npc <= pred_addr;
+        case(act_taken)
+        0: npc <= pred_pc + 4;
+        1: npc <= pred_addr;
         endcase
-      end else begin
+      end
+      else begin
         flush <= 0;
-        case (pred_taken)
-          0: npc <= pred_pc + 4;
-          1: npc <= pred_addr;
+        case(pred_taken)
+        0: npc <= pred_pc + 4;
+        1: npc <= pred_addr;
         endcase
       end
+      if (restart) restart <= 0;
     end
-  end
-endmodule
+end
+endmodule
\ No newline at end of file
diff --git a/rtl/Branch_Predictor.sv b/rtl/Branch_Predictor.sv
index fe35c3c3..1dceab64 100644
--- a/rtl/Branch_Predictor.sv
+++ b/rtl/Branch_Predictor.sv
@@ -1,40 +1,38 @@
 module Branch_Predictor (
-    input clk,
-    input rstn_h,
-    input act_taken,
-    input pred_taken,
-    input [1:0] branch_occr,
-    input [1:0] branch_cond,
+    input clk, rstn_h, act_taken, pred_taken,
+    input [1:0] branch_occr, branch_cond,
     output logic branch_taken
 );
-  logic curr_pred, incorrect_pred;
+logic curr_pred, incorrect_pred;
 
-  always_ff @(posedge clk or negedge rstn_h) begin
+always @ (posedge clk or negedge rstn_h) begin
     if (!rstn_h) begin
       curr_pred <= 0;
       incorrect_pred <= 0;
-    end else begin
+    end
+    else begin
       if (^branch_cond == 0) begin
         curr_pred <= curr_pred;
         incorrect_pred <= incorrect_pred;
-      end else if (act_taken ^ pred_taken == 0) begin
+      end
+      else if (act_taken ^ pred_taken == 0) begin
         curr_pred <= curr_pred;
         incorrect_pred <= 0;
-      end else if (incorrect_pred) begin
+      end
+      else if (incorrect_pred) begin
         curr_pred <= ~curr_pred;
         incorrect_pred <= 1;
-      end else begin
+      end
+      else begin
         curr_pred <= curr_pred;
         incorrect_pred <= 1;
       end
     end
-  end
-
-  always_comb begin
-    case (branch_occr[1])
-      0: branch_taken = branch_occr[0];
-      1: branch_taken = curr_pred;
+end
+always_comb begin 
+    case(branch_occr[1]) 
+    0: branch_taken = branch_occr[0];
+    1: branch_taken = curr_pred;
     endcase
-  end
-
+end
 endmodule
diff --git a/rtl/Con_EX.sv b/rtl/Con_EX.sv
index e7f484f3..4b3d6be4 100644
--- a/rtl/Con_EX.sv
+++ b/rtl/Con_EX.sv
@@ -1,54 +1,20 @@
 module Con_EX #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input branch_taken_in,
-    input [1:0] a_sel,
-    input [1:0] b_sel,
-    input [WordSize - 1:0] imm,
-    input [WordSize - 1:0] pc_in,
-    input [WordSize - 1:0] rs1d,
-    input [WordSize - 1:0] rs2d_in,
-    input [WordSize - 1:0] branch_addr_in,
-    input [4:0] rdn_in,
-    input [5:0] alu_mode,
-    output logic branch_taken,
-    output logic [4:0] rdn,
-    output logic [WordSize - 1:0] pc,
-    output logic [WordSize - 1:0] branch_addr,
-    output logic [WordSize - 1:0] rs2d,
-    output logic [WordSize - 1:0] alu_out
+  WordSize = 32
+)(
+  input clk, rstn, branch_taken_in,
+  input[1:0] a_sel, b_sel,
+  input[WordSize - 1:0] imm, pc_in, rs1d, rs2d_in, branch_addr_in,
+  input[4:0] rdn_in,
+  input[5:0] alu_mode,
+  output logic branch_taken,
+  output logic [4:0] rdn,
+  output logic [WordSize - 1:0] pc, branch_addr, rs2d, alu_out
 );
+  
+logic [WordSize - 1:0] a, b;
 
-  logic [WordSize - 1:0] a, b;
+IDEX #(WordSize) id_ex_latch(.clk(clk), .rstn(rstn), .branch_taken_in(branch_taken_in), .a_sel(a_sel), .b_sel(b_sel), .imm(imm), .pc_in(pc_in), .rs1d(rs1d), .rs2d_in(rs2d_in), .branch_addr_in(branch_addr_in), .rdn_in(rdn_in), .branch_taken(branch_taken), .rdn(rdn), .pc(pc), .branch_addr(branch_addr), .rs2d(rs2d), .a(a), .b(b));
 
-  IDEX #(WordSize) id_ex_latch (
-      .clk(clk),
-      .rstn(rstn),
-      .branch_taken_in(branch_taken_in),
-      .a_sel(a_sel),
-      .b_sel(b_sel),
-      .imm(imm),
-      .pc_in(pc_in),
-      .rs1d(rs1d),
-      .rs2d_in(rs2d_in),
-      .branch_addr_in(branch_addr_in),
-      .rdn_in(rdn_in),
-      .branch_taken(branch_taken),
-      .rdn(rdn),
-      .pc(pc),
-      .branch_addr(branch_addr),
-      .rs2d(rs2d),
-      .a(a),
-      .b(b)
-  );
+Alu #(WordSize) alu_modulemake(.a(a), .b(b), .alu_mode(alu_mode), .alu_out(alu_out));
 
-  Alu #(WordSize) alu_modulemake (
-      .a(a),
-      .b(b),
-      .alu_mode(alu_mode),
-      .alu_out(alu_out)
-  );
-
-endmodule
+endmodule
\ No newline at end of file
diff --git a/rtl/Con_ID.sv b/rtl/Con_ID.sv
index f1488bb5..22366bb5 100644
--- a/rtl/Con_ID.sv
+++ b/rtl/Con_ID.sv
@@ -1,61 +1,20 @@
 module Con_ID #(
-    WordSize = 32
-) (
-    input clk,
-    input cache_clk,
-    input rstn,
-    input wbe,
-    input addr_mode,
-    input branch_taken,
-    input [2:0] immode,
-    input [4:0] rdn_in,
-    input [WordSize - 1:0] ins,
-    input [WordSize - 1:0] pc_in,
-    input [WordSize - 1:0] rdd,
-    output logic [4:0] rdn,
-    output logic [WordSize - 1:0] imm,
-    output logic [WordSize - 1:0] pc,
-    output logic [WordSize - 1:0] rs1d,
-    output logic [WordSize - 1:0] rs2d,
-    output logic [WordSize - 1:0] npc,
-    output logic [WordSize - 1:0] branch_addr
+  WordSize = 32
+)(
+  input clk, cache_clk, rstn, wbe, addr_mode, branch_taken,
+  input [2:0] immode,
+  input [4:0] rdn_in;
+  input[WordSize - 1:0] ins, pc_in, rdd,
+  output logic [4:0] rdn,
+  output logic [WordSize - 1:0] imm, pc, rs1d, rs2d, npc, branch_addr
 );
+  
+logic [4:0] rs1n, rs2n;
 
-  logic [4:0] rs1n, rs2n;
+IFID if_id_latch(.clk(clk), .rstn(rstn), .immode(immode), .ins(ins), .pc_in(pc_in), .rdn(rdn), .rs1n(rs1n), .rs2n(rs2n), .imm(imm), .pc(pc));
 
-  IFID if_id_latch (
-      .clk(clk),
-      .rstn(rstn),
-      .immode(immode),
-      .ins(ins),
-      .pc_in(pc_in),
-      .rdn(rdn),
-      .rs1n(rs1n),
-      .rs2n(rs2n),
-      .imm(imm),
-      .pc(pc)
-  );
+GPR registers(.clk(cache_clk), .rstn(rstn), .wbe(wbe), .rs1n(rs1n), .rs2n(rs2n), .rdn(rdn_in), .rdd(rdd), .rs1d(rs1d), .rs2d(rs2d));
 
-  GPR registers (
-      .clk (cache_clk),
-      .rstn(rstn),
-      .wbe (wbe),
-      .rs1n(rs1n),
-      .rs2n(rs2n),
-      .rdn (rdn_in),
-      .rdd (rdd),
-      .rs1d(rs1d),
-      .rs2d(rs2d)
-  );
+Branch_Addr_Calc branch_address(.addr_mode(addr_mode), .branch_taken(branch_taken), .imm(imm), .rs1d(rs1d), .pc_in(pc), .branch_addr(branch_addr), .npc(npc));
 
-  Branch_Addr_Calc branch_address (
-      .addr_mode(addr_mode),
-      .branch_taken(branch_taken),
-      .imm(imm),
-      .rs1d(rs1d),
-      .pc_in(pc),
-      .branch_addr(branch_addr),
-      .npc(npc)
-  );
-
-endmodule
+endmodule
\ No newline at end of file
diff --git a/rtl/EXMEM.sv b/rtl/EXMEM.sv
index e46154b5..3bad749f 100644
--- a/rtl/EXMEM.sv
+++ b/rtl/EXMEM.sv
@@ -1,22 +1,20 @@
 module EXMEM #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input [4:0] rdn_in,
-    input [WordSize - 1:0] alu_out_in,
-    input [WordSize - 1:0] rs2d,
-    output logic [4:0] rdn,
-    output logic [WordSize - 1:0] alu_out,
-    output logic [WordSize - 1:0] mem_data
+  WordSize = 32
+)(
+  input clk, rstn,
+  input [4:0] rdn_in,
+  input [WordSize - 1:0] alu_out_in, rs2d,
+  output logic [4:0] rdn,
+  output logic [WordSize - 1:0] alu_out, mem_data
 );
 
-  always_ff @(posedge clk, negedge rstn) begin
+  always @ (posedge clk or negedge rstn) begin
     if (!rstn) begin
       rdn <= 0;
       alu_out <= 0;
       mem_data <= 0;
-    end else begin
+    end
+    else begin
       rdn <= rdn_in;
       alu_out <= alu_out_in;
       mem_data <= rs2d;
diff --git a/rtl/GPR.sv b/rtl/GPR.sv
index c12289d8..a9353069 100644
--- a/rtl/GPR.sv
+++ b/rtl/GPR.sv
@@ -1,30 +1,30 @@
 module GPR #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input wbe,
-    input [4:0] rs1n,
-    input [4:0] rs2n,
-    input [4:0] rdn,
-    input [WordSize - 1:0] rdd,
-    output logic [WordSize - 1:0] rs1d,
-    output logic [WordSize - 1:0] rs2d
+  WordSize = 32
+)(
+  input clk, rstn, wbe,
+  input [4:0] rs1n, rs2n, rdn,
+  input [WordSize - 1:0] rdd,
+  output logic [WordSize - 1:0] rs1d, rs2d
 );
+  
+  logic [31:0] registers [31:1]; 
+  
+  integer i;
 
-  logic [31:0] registers[31:1];
+  //if this doesn't work, try setting regs to 0 outside of always 
 
-  //if this doesn't work, try setting regs to 0 outside of always
-
-  always_ff @(posedge clk, negedge rstn) begin
-    if (rstn == 0) begin
-      for (int i = 1; i < 32; i = i + 1) begin
-        registers[i] <= 32'd0;
+  always @ (posedge clk or negedge rstn) begin
+    if (rstn == 0)
+      begin
+        for (i = 1; i < 32; i = i+1) begin
+          registers[i] <= 32'd0;
+        end
       end
-    end else begin
+    else begin
       //rs1d <= registers[rs1n];
       //rs2d <= registers[rs2n];
-      if (wbe && rdn != 0) registers[rdn] <= rdd;
+      if (wbe && rdn != 0)
+        registers[rdn] <= rdd;
     end
   end
 
diff --git a/rtl/IDEX.sv b/rtl/IDEX.sv
index 01f8ba72..865565a4 100644
--- a/rtl/IDEX.sv
+++ b/rtl/IDEX.sv
@@ -1,27 +1,16 @@
 module IDEX #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input branch_taken_in,
-    input [1:0] a_sel,
-    input [1:0] b_sel,
-    input [WordSize - 1:0] pc_in,
-    input [WordSize - 1:0] imm,
-    input [WordSize - 1:0] rs1d,
-    input [WordSize - 1:0] rs2d_in,
-    input [WordSize - 1:0] branch_addr_in,
-    input [4:0] rdn_in,
-    output logic branch_taken,
-    output logic [4:0] rdn,
-    output logic [WordSize - 1:0] pc,
-    output logic [WordSize - 1:0] branch_addr,
-    output logic [WordSize - 1:0] a,
-    output logic [WordSize - 1:0] b,
-    output logic [WordSize - 1:0] rs2d
+  WordSize = 32
+)(
+  input clk, rstn, branch_taken_in,
+  input[1:0] a_sel, b_sel,
+  input[WordSize - 1:0] pc_in, imm, rs1d, rs2d_in, branch_addr_in,
+  input[4:0] rdn_in,
+  output logic branch_taken,
+  output logic [4:0] rdn,
+  output logic [WordSize - 1:0] pc, branch_addr, a, b, rs2d
 );
-
-  always @(posedge clk or negedge rstn) begin
+  
+  always @ (posedge clk or negedge rstn) begin
     if (!rstn) begin
       rdn <= 0;
       a <= 0;
@@ -30,19 +19,20 @@ module IDEX #(
       pc <= 0;
       rs2d <= 0;
       branch_taken <= 0;
-    end else begin
+    end
+    else begin
       rdn <= rdn_in;
       branch_taken <= branch_taken_in;
       rs2d <= rs2d_in;
       branch_addr <= branch_addr_in;
       pc <= pc_in;
-      case (a_sel)
+      case(a_sel)
         0: a <= rs1d;
         1: a <= pc_in;
         3: a <= 0;
-        default a <= 0;
+      default a <= 0;
       endcase
-      case (b_sel)
+      case(b_sel)
         0: b <= rs2d_in;
         1: b <= imm;
         2: b <= 4;
diff --git a/rtl/IFID.sv b/rtl/IFID.sv
index 225d98dc..46b70a9a 100644
--- a/rtl/IFID.sv
+++ b/rtl/IFID.sv
@@ -1,40 +1,38 @@
 module IFID #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input [2:0] immode,
-    input [31:0] ins,
-    input [WordSize - 1:0] pc_in,
-    output logic [4:0] rdn,
-    output logic [4:0] rs1n,
-    output logic [4:0] rs2n,
-    output logic [31:0] imm,
-    output logic [WordSize - 1:0] pc
+  WordSize = 32
+)(
+  input clk, rstn,
+  input[2:0] immode,
+  input[31:0] ins,
+  input[WordSize - 1:0] pc_in,
+  output logic [4:0] rdn, rs1n, rs2n,
+  output logic [31:0] imm,
+  output logic [WordSize - 1:0] pc
 );
-
-  always @(posedge clk or negedge rstn) begin
+  
+  always @ (posedge clk or negedge rstn) begin
     if (!rstn) begin
-      rdn  <= 0;
+      rdn <= 0;
       rs1n <= 0;
       rs2n <= 0;
-      pc   <= 0;
-      imm  <= 0;
-    end else begin
-      pc   <= pc_in;
-      rdn  <= ins[11:7];
+      pc <= 0;
+      imm = 0;
+    end
+    else begin
+      pc <= pc_in;
+      rdn <= ins[11:7];
       rs1n <= ins[19:15];
       rs2n <= ins[24:20];
-      case (immode)
-        1: imm <= {{20{ins[31]}}, ins[31:20]};
-        2: imm <= {{20{ins[31]}}, ins[31:25], ins[11:7]};
-        3: imm <= {{19{ins[31]}}, ins[31], ins[7], ins[30:25], ins[11:8], 1'b0};
-        4: imm <= {ins[31:12], 12'b0};
-        5: imm <= {11'b0, ins[31], ins[19:12], ins[20], ins[30:21], 1'b0};
-        default imm <= 0;
+      case(immode)
+        1: imm = {{20{ins[31]}}, ins[31:20]};
+        2: imm = {{20{ins[31]}}, ins[31:25], ins[11:7]};
+        3: imm = {{19{ins[31]}}, ins[31], ins[7], ins[30:25], ins[11:8], 1'b0};
+        4: imm = {ins[31:12], 12'b0};
+        5: imm = {11'b0, ins[31], ins[19:12], ins[20], ins[30:21], 1'b0};
+      default imm = 0;
       endcase
     end
-
+      
   end
-
+  
 endmodule
diff --git a/rtl/MEMWB.sv b/rtl/MEMWB.sv
index 17d696ca..d6c20939 100644
--- a/rtl/MEMWB.sv
+++ b/rtl/MEMWB.sv
@@ -1,30 +1,29 @@
 module MEMWB #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input [2:0] wbs,
-    input [4:0] rdn_in,
-    input [WordSize - 1:0] alu_out,
-    input [WordSize - 1:0] mrd,
-    output logic [4:0] rdn,
-    output logic [WordSize - 1:0] rdd
+  WordSize = 32
+)(
+  input clk, rstn,
+  input[2:0] wbs,
+  input[4:0] rdn_in,
+  input[WordSize - 1:0] alu_out, mrd,
+  output logic [4:0] rdn,
+  output logic [WordSize - 1:0] rdd
 );
-
-  always_ff @(posedge clk, negedge rstn) begin
+  
+  always @ (posedge clk or negedge rstn) begin
     if (!rstn) begin
       rdn <= 0;
-      rdd <= 0;
-    end else begin
-      rdn <= rdn_in;
-      case (wbs)
-        0: rdd <= {{{WordSize - 8{mrd[7]}}}, mrd[7:0]};
-        1: rdd <= {{{WordSize - 16{mrd[15]}}}, mrd[15:0]};
-        2: rdd <= mrd;
-        3: rdd <= alu_out;
-        4: rdd <= {{{WordSize - 8{1'b0}}}, mrd[7:0]};
-        5: rdd <= {{{WordSize - 16{1'b0}}}, mrd[15:0]};
-        default rdd <= 0;
+      rdd = 0;
+    end
+    else begin
+    rdn <= rdn_in;
+      case(wbs)
+        0: rdd = {{{WordSize - 8{mrd[7]}}}, mrd[7:0]};
+        1: rdd = {{{WordSize - 16{mrd[15]}}}, mrd[15:0]};
+        2: rdd = mrd;
+        3: rdd = alu_out;
+        4: rdd = {{{WordSize - 8{1'b0}}}, mrd[7:0]};
+        5: rdd = {{{WordSize - 16{1'b0}}}, mrd[15:0]};
+      default rdd = 0;
       endcase
     end
   end
diff --git a/rtl/PC.sv b/rtl/PC.sv
index 2f8b4531..f8985235 100644
--- a/rtl/PC.sv
+++ b/rtl/PC.sv
@@ -1,18 +1,20 @@
 
 module PC #(
-    WordSize = 32
-) (
-    input clk,
-    input rstn,
-    input pc_en,
-    input [WordSize - 1:0] npc,
-    output logic [WordSize - 1:0] pc
+  WordSize = 32
+)(
+  input clk,
+  input rstn,
+  input pc_en,
+  input [WordSize - 1:0] npc,
+  output logic [WordSize - 1:0] pc
 );
-
-  always_ff @(posedge clk, negedge rstn) begin
-    if (rstn == 0) pc <= 0;
+  
+  always @ (posedge clk or negedge rstn) begin
+    if (rstn == 0)
+      pc <= 0;
     else begin
-      if (pc_en) pc <= npc;
+      if (pc_en)
+        pc <= npc;
     end
   end
 endmodule
diff --git a/rtl/Pipeline_Reset.sv b/rtl/Pipeline_Reset.sv
index 8a45bf4c..fcffb997 100644
--- a/rtl/Pipeline_Reset.sv
+++ b/rtl/Pipeline_Reset.sv
@@ -1,23 +1,22 @@
 module Pipeline_Reset #(
-    WordSize = 32
-) (
-    input [WordSize - 1:0] npc_in,
-    input [WordSize - 1:0] npc_corr,
-    input flush,
-    output logic [WordSize - 1:0] npc,
-    output logic rstn_out
+  WordSize = 32
+)(
+  input [WordSize - 1:0] npc_in, npc_corr,
+  input flush,
+  output logic [WordSize - 1:0] npc,
+  output logic rstn_out
 );
 
-  always_comb begin
-    case (flush)
-      0: begin
-        npc = npc_in;
-        rstn_out = 1'bZ;
-      end
-      1: begin
-        npc = npc_corr;
-        rstn_out = 0;
-      end
-    endcase
-  end
+always_comb begin
+case(flush)
+0: begin
+    npc = npc_in;
+    rstn_out = 1'bZ;
+end
+1: begin
+    npc = npc_corr;
+    rstn_out = 0;
+end
+endcase
+end
 endmodule
diff --git a/vcpkg-configuration.json b/vcpkg-configuration.json
new file mode 100644
index 00000000..0679c033
--- /dev/null
+++ b/vcpkg-configuration.json
@@ -0,0 +1,17 @@
+{
+  "default-registry": {
+    "kind": "git",
+    "baseline": "36fb23307e10cc6ffcec566c46c4bb3f567c82c6",
+    "repository": "https://github.com/microsoft/vcpkg.git"
+  },
+  "registries": [
+    {
+      "kind": "git",
+      "baseline": "7b0b898fee86b45451f19bee2b7147695acf09e2",
+      "repository": "https://github.com/NYU-Processor-Design/nyu-registry.git",
+      "packages": [
+        "nyu-*"
+      ]
+    }
+  ]
+}
diff --git a/vcpkg.json b/vcpkg.json
index 56023ee6..8ed40e00 100644
--- a/vcpkg.json
+++ b/vcpkg.json
@@ -9,22 +9,5 @@
     "nyu-cmake",
     "nyu-util",
     "catch2"
-  ],
-  "vcpkg-configuration": {
-    "default-registry": {
-      "kind": "git",
-      "baseline": "66b4b34d99ab272fcf21f2bd12b616e371c6bb31",
-      "repository": "https://github.com/microsoft/vcpkg.git"
-    },
-    "registries": [
-      {
-        "kind": "git",
-        "baseline": "b6a23db783c5c5c2da5b9dbdcd3f852df94b83d4",
-        "repository": "https://github.com/NYU-Processor-Design/nyu-registry.git",
-        "packages": [
-          "nyu-*"
-        ]
-      }
-    ]
-  }
+  ]
 }