From 662d409c2d45a37192b0f603e68110d13eceb95d Mon Sep 17 00:00:00 2001 From: ShinyMiraidon Date: Mon, 11 Sep 2023 12:46:52 -0400 Subject: [PATCH] FInished Tests for MEMWB --- dv/ifid.cpp | 20 ++-- dv/memwb.cpp | 256 ++++++++++++++++++++++++++++++++++++++++++++++++++- rtl/MEMWB.sv | 4 +- 3 files changed, 263 insertions(+), 17 deletions(-) diff --git a/dv/ifid.cpp b/dv/ifid.cpp index 981c6ccf..a9dca6b4 100644 --- a/dv/ifid.cpp +++ b/dv/ifid.cpp @@ -18,7 +18,7 @@ TEST_CASE("PC Passthrough") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = rand() % (int) (7); - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -37,7 +37,7 @@ TEST_CASE("PC Passthrough") { } } -TEST_CASE("Decypher Register Numbers") { +TEST_CASE("Decipher Register Numbers") { VIFID model; bool clk; bool rstn; @@ -50,7 +50,7 @@ TEST_CASE("Decypher Register Numbers") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = rand() % (int) (7); - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -58,7 +58,7 @@ TEST_CASE("Decypher Register Numbers") { model.eval(); - //Test Decyphering of Register Numbers + //Test Deciphering of Register Numbers model.clk = 1; model.rstn = 1; model.immode = immode; @@ -85,7 +85,7 @@ TEST_CASE("Imm Mode 0") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = 0; - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -119,7 +119,7 @@ TEST_CASE("Imm Mode 1") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = 1; - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -152,7 +152,7 @@ TEST_CASE("Imm Mode 2") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = 2; - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -184,7 +184,7 @@ TEST_CASE("Imm Mode 3") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = 3; - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -217,7 +217,7 @@ TEST_CASE("Imm Mode 4") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = 4; - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); @@ -250,7 +250,7 @@ TEST_CASE("Imm Mode 5") { pc_in = rand() % (int) (pow(2, 32) - 1); immode = 5; - //Initalize Module + //Initialize Module model.rstn = 1; model.clk = 0; model.eval(); diff --git a/dv/memwb.cpp b/dv/memwb.cpp index 641ba86b..22c202ef 100644 --- a/dv/memwb.cpp +++ b/dv/memwb.cpp @@ -4,11 +4,257 @@ #include #include -VMEMWB model; -bool clk; -bool rstn; +//This function takes an input and sign extends the number of bits specified by old_size to the number of bits specified by new_size +uint32_t sign_extend(uint32_t input, uint32_t old_size, uint32_t new_size = 32) { + return (uint32_t) ((input & ((int) pow(2, old_size) - 1)) | (((input & ((int) pow(2, old_size - 1))) >> (old_size - 1)) * (((int) pow(2, new_size - old_size) - 1) << (old_size)))); +} + +TEST_CASE("rdn Passthrough") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = rand() % (int) (pow(2, 3) - 1); + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); + + + //Test PC Passthrough + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint8_t) model.rdn == (uint8_t) rdn_in); + } + +} + +TEST_CASE("Write Back State 0") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = 0; + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); + + + //Test RDD Output (rdd = alu_out) + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint32_t) model.rdd == (uint32_t) alu_out); + } + +} + +TEST_CASE("Write Back State 1") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = 1; + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); + + + //Test RDD Output (rdd = sign extend mrd[7:0]) + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint32_t) model.rdd == sign_extend(mrd, 8)); + } + +} + + +TEST_CASE("Write Back State 2") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = 2; + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); + + + //Test RDD Output (rdd = sign extend mrd[15:0]) + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint32_t) model.rdd == sign_extend(mrd, 16)); + } + +} + +TEST_CASE("Write Back State 3") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = 3; + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); + + + //Test RDD Output (rdd = mrd[7:0]) + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint32_t) model.rdd == (uint32_t) (mrd & ((int) (pow(2, 8) - 1)))); + } +} + +TEST_CASE("Write Back State 4") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = 4; + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); + + + //Test RDD Output (rdd = mrd[15:0]) + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint32_t) model.rdd == (uint32_t) (mrd & ((int) (pow(2, 16) - 1)))); + } +} + +TEST_CASE("Write Back State 5") { + VMEMWB model; + bool clk; + bool rstn; + uint8_t wbs; + uint8_t rdn_in; + uint32_t alu_out; + uint32_t mrd; + for (int i = 0; i < 1000; i++) { + rdn_in = rand() % (int) (pow(2, 5) - 1); + wbs = 5; + alu_out = rand() % (int) (pow(2, 32) - 1); + mrd = rand() % (int) (pow(2, 32) - 1); + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn = 0; + model.eval(); -TEST_CASE() { - + + //Test RDD Output (rdd = mrd) + model.clk = 1; + model.rstn = 1; + model.wbs = wbs; + model.rdn_in = rdn_in; + model.mrd = mrd; + model.alu_out = alu_out; + model.eval(); + REQUIRE((uint32_t) model.rdd == (uint32_t) mrd); + } } diff --git a/rtl/MEMWB.sv b/rtl/MEMWB.sv index 21de52a5..959826c0 100644 --- a/rtl/MEMWB.sv +++ b/rtl/MEMWB.sv @@ -4,7 +4,7 @@ module MEMWB #( input clk, rstn, input[2:0] wbs, input[4:0] rdn_in, - input[WordSize - 1:0] alu_out, mrd + input[WordSize - 1:0] alu_out, mrd, output logic [4:0] rdn, output logic [WordSize - 1:0] rdd ); @@ -12,7 +12,7 @@ module MEMWB #( always @ (posedge clk or negedge rstn) begin if (!rstn) begin rdn <= 0; - rdd <= 0; + rdd = 0; end else begin rdn <= rdn_in;